1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 #include "qla_gbl.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 13 #include "qla_devtbl.h" 14 15 #ifdef CONFIG_SPARC 16 #include <asm/prom.h> 17 #endif 18 19 #include "qla_target.h" 20 21 /* 22 * QLogic ISP2x00 Hardware Support Function Prototypes. 23 */ 24 static int qla2x00_isp_firmware(scsi_qla_host_t *); 25 static int qla2x00_setup_chip(scsi_qla_host_t *); 26 static int qla2x00_fw_ready(scsi_qla_host_t *); 27 static int qla2x00_configure_hba(scsi_qla_host_t *); 28 static int qla2x00_configure_loop(scsi_qla_host_t *); 29 static int qla2x00_configure_local_loop(scsi_qla_host_t *); 30 static int qla2x00_configure_fabric(scsi_qla_host_t *); 31 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *); 32 static int qla2x00_restart_isp(scsi_qla_host_t *); 33 34 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); 35 static int qla84xx_init_chip(scsi_qla_host_t *); 36 static int qla25xx_init_queues(struct qla_hw_data *); 37 static void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, 38 struct event_arg *ea); 39 static void qla24xx_handle_prli_done_event(struct scsi_qla_host *, 40 struct event_arg *); 41 static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *); 42 43 /* SRB Extensions ---------------------------------------------------------- */ 44 45 void 46 qla2x00_sp_timeout(struct timer_list *t) 47 { 48 srb_t *sp = timer_container_of(sp, t, u.iocb_cmd.timer); 49 struct srb_iocb *iocb; 50 scsi_qla_host_t *vha = sp->vha; 51 52 WARN_ON(irqs_disabled()); 53 iocb = &sp->u.iocb_cmd; 54 iocb->timeout(sp); 55 56 /* ref: TMR */ 57 kref_put(&sp->cmd_kref, qla2x00_sp_release); 58 59 if (vha && qla2x00_isp_reg_stat(vha->hw)) { 60 ql_log(ql_log_info, vha, 0x9008, 61 "PCI/Register disconnect.\n"); 62 qla_pci_set_eeh_busy(vha); 63 } 64 } 65 66 void qla2x00_sp_free(srb_t *sp) 67 { 68 struct srb_iocb *iocb = &sp->u.iocb_cmd; 69 70 timer_delete(&iocb->timer); 71 qla2x00_rel_sp(sp); 72 } 73 74 void qla2xxx_rel_done_warning(srb_t *sp, int res) 75 { 76 WARN_ONCE(1, "Calling done() of an already freed srb %p object\n", sp); 77 } 78 79 void qla2xxx_rel_free_warning(srb_t *sp) 80 { 81 WARN_ONCE(1, "Calling free() of an already freed srb %p object\n", sp); 82 } 83 84 /* Asynchronous Login/Logout Routines -------------------------------------- */ 85 86 unsigned long 87 qla2x00_get_async_timeout(struct scsi_qla_host *vha) 88 { 89 unsigned long tmo; 90 struct qla_hw_data *ha = vha->hw; 91 92 /* Firmware should use switch negotiated r_a_tov for timeout. */ 93 tmo = ha->r_a_tov / 10 * 2; 94 if (IS_QLAFX00(ha)) { 95 tmo = FX00_DEF_RATOV * 2; 96 } else if (!IS_FWI2_CAPABLE(ha)) { 97 /* 98 * Except for earlier ISPs where the timeout is seeded from the 99 * initialization control block. 100 */ 101 tmo = ha->login_timeout; 102 } 103 return tmo; 104 } 105 106 static void qla24xx_abort_iocb_timeout(void *data) 107 { 108 srb_t *sp = data; 109 struct srb_iocb *abt = &sp->u.iocb_cmd; 110 struct qla_qpair *qpair = sp->qpair; 111 u32 handle; 112 unsigned long flags; 113 int sp_found = 0, cmdsp_found = 0; 114 115 if (sp->cmd_sp) 116 ql_dbg(ql_dbg_async, sp->vha, 0x507c, 117 "Abort timeout - cmd hdl=%x, cmd type=%x hdl=%x, type=%x\n", 118 sp->cmd_sp->handle, sp->cmd_sp->type, 119 sp->handle, sp->type); 120 else 121 ql_dbg(ql_dbg_async, sp->vha, 0x507c, 122 "Abort timeout 2 - hdl=%x, type=%x\n", 123 sp->handle, sp->type); 124 125 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 126 for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) { 127 if (sp->cmd_sp && (qpair->req->outstanding_cmds[handle] == 128 sp->cmd_sp)) { 129 qpair->req->outstanding_cmds[handle] = NULL; 130 cmdsp_found = 1; 131 qla_put_fw_resources(qpair, &sp->cmd_sp->iores); 132 } 133 134 /* removing the abort */ 135 if (qpair->req->outstanding_cmds[handle] == sp) { 136 qpair->req->outstanding_cmds[handle] = NULL; 137 sp_found = 1; 138 qla_put_fw_resources(qpair, &sp->iores); 139 break; 140 } 141 } 142 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 143 144 if (cmdsp_found && sp->cmd_sp) { 145 /* 146 * This done function should take care of 147 * original command ref: INIT 148 */ 149 sp->cmd_sp->done(sp->cmd_sp, QLA_OS_TIMER_EXPIRED); 150 } 151 152 if (sp_found) { 153 abt->u.abt.comp_status = cpu_to_le16(CS_TIMEOUT); 154 sp->done(sp, QLA_OS_TIMER_EXPIRED); 155 } 156 } 157 158 static void qla24xx_abort_sp_done(srb_t *sp, int res) 159 { 160 struct srb_iocb *abt = &sp->u.iocb_cmd; 161 srb_t *orig_sp = sp->cmd_sp; 162 163 if (orig_sp) 164 qla_wait_nvme_release_cmd_kref(orig_sp); 165 166 if (sp->flags & SRB_WAKEUP_ON_COMP) 167 complete(&abt->u.abt.comp); 168 else 169 /* ref: INIT */ 170 kref_put(&sp->cmd_kref, qla2x00_sp_release); 171 } 172 173 int qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait) 174 { 175 scsi_qla_host_t *vha = cmd_sp->vha; 176 struct srb_iocb *abt_iocb; 177 srb_t *sp; 178 int rval = QLA_FUNCTION_FAILED; 179 180 /* ref: INIT for ABTS command */ 181 sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport, 182 GFP_ATOMIC); 183 if (!sp) 184 return QLA_MEMORY_ALLOC_FAILED; 185 186 qla_vha_mark_busy(vha); 187 abt_iocb = &sp->u.iocb_cmd; 188 sp->type = SRB_ABT_CMD; 189 sp->name = "abort"; 190 sp->qpair = cmd_sp->qpair; 191 sp->cmd_sp = cmd_sp; 192 if (wait) 193 sp->flags = SRB_WAKEUP_ON_COMP; 194 195 init_completion(&abt_iocb->u.abt.comp); 196 /* FW can send 2 x ABTS's timeout/20s */ 197 qla2x00_init_async_sp(sp, 42, qla24xx_abort_sp_done); 198 sp->u.iocb_cmd.timeout = qla24xx_abort_iocb_timeout; 199 200 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle; 201 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id); 202 203 ql_dbg(ql_dbg_async, vha, 0x507c, 204 "Abort command issued - hdl=%x, type=%x\n", cmd_sp->handle, 205 cmd_sp->type); 206 207 rval = qla2x00_start_sp(sp); 208 if (rval != QLA_SUCCESS) { 209 /* ref: INIT */ 210 kref_put(&sp->cmd_kref, qla2x00_sp_release); 211 return rval; 212 } 213 214 if (wait) { 215 wait_for_completion(&abt_iocb->u.abt.comp); 216 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ? 217 QLA_SUCCESS : QLA_ERR_FROM_FW; 218 /* ref: INIT */ 219 kref_put(&sp->cmd_kref, qla2x00_sp_release); 220 } 221 222 return rval; 223 } 224 225 void 226 qla2x00_async_iocb_timeout(void *data) 227 { 228 srb_t *sp = data; 229 fc_port_t *fcport = sp->fcport; 230 struct srb_iocb *lio = &sp->u.iocb_cmd; 231 int rc, h, found; 232 unsigned long flags; 233 234 if (fcport) { 235 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, 236 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n", 237 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name); 238 239 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 240 } else { 241 pr_info("Async-%s timeout - hdl=%x.\n", 242 sp->name, sp->handle); 243 } 244 245 switch (sp->type) { 246 case SRB_LOGIN_CMD: 247 rc = qla24xx_async_abort_cmd(sp, false); 248 if (rc) { 249 /* Retry as needed. */ 250 lio->u.logio.data[0] = MBS_COMMAND_ERROR; 251 lio->u.logio.data[1] = 252 lio->u.logio.flags & SRB_LOGIN_RETRIED ? 253 QLA_LOGIO_LOGIN_RETRIED : 0; 254 found = 0; 255 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 256 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; 257 h++) { 258 if (sp->qpair->req->outstanding_cmds[h] == 259 sp) { 260 sp->qpair->req->outstanding_cmds[h] = 261 NULL; 262 found = 1; 263 break; 264 } 265 } 266 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 267 /* 268 * Only complete the command if this path removed it 269 * from outstanding_cmds. Otherwise the ISR already 270 * completed it and a second sp->done() would race the 271 * submitter's freeing of the on-stack completion. 272 */ 273 if (found) 274 sp->done(sp, QLA_FUNCTION_TIMEOUT); 275 } 276 break; 277 case SRB_LOGOUT_CMD: 278 case SRB_CT_PTHRU_CMD: 279 case SRB_MB_IOCB: 280 case SRB_NACK_PLOGI: 281 case SRB_NACK_PRLI: 282 case SRB_NACK_LOGO: 283 case SRB_CTRL_VP: 284 default: 285 rc = qla24xx_async_abort_cmd(sp, false); 286 if (rc) { 287 found = 0; 288 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 289 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; 290 h++) { 291 if (sp->qpair->req->outstanding_cmds[h] == 292 sp) { 293 sp->qpair->req->outstanding_cmds[h] = 294 NULL; 295 found = 1; 296 break; 297 } 298 } 299 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 300 /* 301 * Only complete the command if this path removed it 302 * from outstanding_cmds. Otherwise the ISR already 303 * completed it and a second sp->done() would race the 304 * submitter's freeing of the on-stack completion. 305 */ 306 if (found) 307 sp->done(sp, QLA_FUNCTION_TIMEOUT); 308 } 309 break; 310 } 311 } 312 313 static void qla2x00_async_login_sp_done(srb_t *sp, int res) 314 { 315 struct scsi_qla_host *vha = sp->vha; 316 struct srb_iocb *lio = &sp->u.iocb_cmd; 317 struct event_arg ea; 318 319 ql_dbg(ql_dbg_disc, vha, 0x20dd, 320 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res); 321 322 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 323 324 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 325 memset(&ea, 0, sizeof(ea)); 326 ea.fcport = sp->fcport; 327 ea.data[0] = lio->u.logio.data[0]; 328 ea.data[1] = lio->u.logio.data[1]; 329 ea.iop[0] = lio->u.logio.iop[0]; 330 ea.iop[1] = lio->u.logio.iop[1]; 331 ea.sp = sp; 332 if (res) 333 ea.data[0] = MBS_COMMAND_ERROR; 334 qla24xx_handle_plogi_done_event(vha, &ea); 335 } 336 337 /* ref: INIT */ 338 kref_put(&sp->cmd_kref, qla2x00_sp_release); 339 } 340 341 int 342 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, 343 uint16_t *data) 344 { 345 srb_t *sp; 346 struct srb_iocb *lio; 347 int rval = QLA_FUNCTION_FAILED; 348 349 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) || 350 fcport->loop_id == FC_NO_LOOP_ID) { 351 ql_log(ql_log_warn, vha, 0xffff, 352 "%s: %8phC - not sending command.\n", 353 __func__, fcport->port_name); 354 return rval; 355 } 356 357 /* ref: INIT */ 358 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 359 if (!sp) 360 goto done; 361 362 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND); 363 fcport->flags |= FCF_ASYNC_SENT; 364 fcport->logout_completed = 0; 365 366 sp->type = SRB_LOGIN_CMD; 367 sp->name = "login"; 368 sp->gen1 = fcport->rscn_gen; 369 sp->gen2 = fcport->login_gen; 370 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 371 qla2x00_async_login_sp_done); 372 373 lio = &sp->u.iocb_cmd; 374 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport)) { 375 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY; 376 } else { 377 if (vha->hw->flags.edif_enabled && 378 DBELL_ACTIVE(vha)) { 379 lio->u.logio.flags |= 380 (SRB_LOGIN_FCSP | SRB_LOGIN_SKIP_PRLI); 381 } else { 382 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; 383 } 384 } 385 386 if (NVME_TARGET(vha->hw, fcport)) 387 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI; 388 389 rval = qla2x00_start_sp(sp); 390 391 ql_dbg(ql_dbg_disc, vha, 0x2072, 392 "Async-login - %8phC hdl=%x, loopid=%x portid=%06x retries=%d %s.\n", 393 fcport->port_name, sp->handle, fcport->loop_id, 394 fcport->d_id.b24, fcport->login_retry, 395 lio->u.logio.flags & SRB_LOGIN_FCSP ? "FCSP" : ""); 396 397 if (rval != QLA_SUCCESS) { 398 fcport->flags |= FCF_LOGIN_NEEDED; 399 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 400 goto done_free_sp; 401 } 402 403 return rval; 404 405 done_free_sp: 406 /* ref: INIT */ 407 kref_put(&sp->cmd_kref, qla2x00_sp_release); 408 fcport->flags &= ~FCF_ASYNC_SENT; 409 done: 410 fcport->flags &= ~FCF_ASYNC_ACTIVE; 411 412 /* 413 * async login failed. Could be due to iocb/exchange resource 414 * being low. Set state DELETED for re-login process to start again. 415 */ 416 qla2x00_set_fcport_disc_state(fcport, DSC_DELETED); 417 return rval; 418 } 419 420 static void qla2x00_async_logout_sp_done(srb_t *sp, int res) 421 { 422 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 423 sp->fcport->login_gen++; 424 qlt_logo_completion_handler(sp->fcport, sp->u.iocb_cmd.u.logio.data[0]); 425 /* ref: INIT */ 426 kref_put(&sp->cmd_kref, qla2x00_sp_release); 427 } 428 429 int 430 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) 431 { 432 srb_t *sp; 433 int rval = QLA_FUNCTION_FAILED; 434 435 fcport->flags |= FCF_ASYNC_SENT; 436 /* ref: INIT */ 437 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 438 if (!sp) 439 goto done; 440 441 sp->type = SRB_LOGOUT_CMD; 442 sp->name = "logout"; 443 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 444 qla2x00_async_logout_sp_done); 445 446 ql_dbg(ql_dbg_disc, vha, 0x2070, 447 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC explicit %d.\n", 448 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 449 fcport->d_id.b.area, fcport->d_id.b.al_pa, 450 fcport->port_name, fcport->explicit_logout); 451 452 rval = qla2x00_start_sp(sp); 453 if (rval != QLA_SUCCESS) 454 goto done_free_sp; 455 return rval; 456 457 done_free_sp: 458 /* ref: INIT */ 459 kref_put(&sp->cmd_kref, qla2x00_sp_release); 460 done: 461 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 462 return rval; 463 } 464 465 void 466 qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport, 467 uint16_t *data) 468 { 469 fcport->flags &= ~FCF_ASYNC_ACTIVE; 470 /* Don't re-login in target mode */ 471 if (!fcport->tgt_session) 472 qla2x00_mark_device_lost(vha, fcport, 1); 473 qlt_logo_completion_handler(fcport, data[0]); 474 } 475 476 static void qla2x00_async_prlo_sp_done(srb_t *sp, int res) 477 { 478 struct srb_iocb *lio = &sp->u.iocb_cmd; 479 struct scsi_qla_host *vha = sp->vha; 480 481 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE; 482 if (!test_bit(UNLOADING, &vha->dpc_flags)) 483 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport, 484 lio->u.logio.data); 485 /* ref: INIT */ 486 kref_put(&sp->cmd_kref, qla2x00_sp_release); 487 } 488 489 int 490 qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport) 491 { 492 srb_t *sp; 493 int rval; 494 495 rval = QLA_FUNCTION_FAILED; 496 /* ref: INIT */ 497 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 498 if (!sp) 499 goto done; 500 501 sp->type = SRB_PRLO_CMD; 502 sp->name = "prlo"; 503 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 504 qla2x00_async_prlo_sp_done); 505 506 ql_dbg(ql_dbg_disc, vha, 0x2070, 507 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 508 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 509 fcport->d_id.b.area, fcport->d_id.b.al_pa); 510 511 rval = qla2x00_start_sp(sp); 512 if (rval != QLA_SUCCESS) 513 goto done_free_sp; 514 515 return rval; 516 517 done_free_sp: 518 /* ref: INIT */ 519 kref_put(&sp->cmd_kref, qla2x00_sp_release); 520 done: 521 fcport->flags &= ~FCF_ASYNC_ACTIVE; 522 return rval; 523 } 524 525 static 526 void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea) 527 { 528 struct fc_port *fcport = ea->fcport; 529 unsigned long flags; 530 531 ql_dbg(ql_dbg_disc, vha, 0x20d2, 532 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n", 533 __func__, fcport->port_name, fcport->disc_state, 534 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2, 535 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id); 536 537 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 538 ea->data[0]); 539 540 if (ea->data[0] != MBS_COMMAND_COMPLETE) { 541 ql_dbg(ql_dbg_disc, vha, 0x2066, 542 "%s %8phC: adisc fail: post delete\n", 543 __func__, ea->fcport->port_name); 544 545 spin_lock_irqsave(&vha->work_lock, flags); 546 /* deleted = 0 & logout_on_delete = force fw cleanup */ 547 if (fcport->deleted == QLA_SESS_DELETED) 548 fcport->deleted = 0; 549 550 fcport->logout_on_delete = 1; 551 spin_unlock_irqrestore(&vha->work_lock, flags); 552 553 qlt_schedule_sess_for_deletion(ea->fcport); 554 return; 555 } 556 557 if (ea->fcport->disc_state == DSC_DELETE_PEND) 558 return; 559 560 if (ea->sp->gen2 != ea->fcport->login_gen) { 561 /* target side must have changed it. */ 562 ql_dbg(ql_dbg_disc, vha, 0x20d3, 563 "%s %8phC generation changed\n", 564 __func__, ea->fcport->port_name); 565 return; 566 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) { 567 qla_rscn_replay(fcport); 568 qlt_schedule_sess_for_deletion(fcport); 569 return; 570 } 571 572 __qla24xx_handle_gpdb_event(vha, ea); 573 } 574 575 static int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport) 576 { 577 struct qla_work_evt *e; 578 579 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI); 580 if (!e) 581 return QLA_FUNCTION_FAILED; 582 583 e->u.fcport.fcport = fcport; 584 fcport->flags |= FCF_ASYNC_ACTIVE; 585 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND); 586 return qla2x00_post_work(vha, e); 587 } 588 589 static void qla2x00_async_adisc_sp_done(srb_t *sp, int res) 590 { 591 struct scsi_qla_host *vha = sp->vha; 592 struct event_arg ea; 593 struct srb_iocb *lio = &sp->u.iocb_cmd; 594 595 ql_dbg(ql_dbg_disc, vha, 0x2066, 596 "Async done-%s res %x %8phC\n", 597 sp->name, res, sp->fcport->port_name); 598 599 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 600 601 memset(&ea, 0, sizeof(ea)); 602 ea.rc = res; 603 ea.data[0] = lio->u.logio.data[0]; 604 ea.data[1] = lio->u.logio.data[1]; 605 ea.iop[0] = lio->u.logio.iop[0]; 606 ea.iop[1] = lio->u.logio.iop[1]; 607 ea.fcport = sp->fcport; 608 ea.sp = sp; 609 if (res) 610 ea.data[0] = MBS_COMMAND_ERROR; 611 612 qla24xx_handle_adisc_event(vha, &ea); 613 /* ref: INIT */ 614 kref_put(&sp->cmd_kref, qla2x00_sp_release); 615 } 616 617 int 618 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, 619 uint16_t *data) 620 { 621 srb_t *sp; 622 struct srb_iocb *lio; 623 int rval = QLA_FUNCTION_FAILED; 624 625 if (IS_SESSION_DELETED(fcport)) { 626 ql_log(ql_log_warn, vha, 0xffff, 627 "%s: %8phC is being delete - not sending command.\n", 628 __func__, fcport->port_name); 629 fcport->flags &= ~FCF_ASYNC_ACTIVE; 630 return rval; 631 } 632 633 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT)) 634 return rval; 635 636 fcport->flags |= FCF_ASYNC_SENT; 637 /* ref: INIT */ 638 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 639 if (!sp) 640 goto done; 641 642 sp->type = SRB_ADISC_CMD; 643 sp->name = "adisc"; 644 sp->gen1 = fcport->rscn_gen; 645 sp->gen2 = fcport->login_gen; 646 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 647 qla2x00_async_adisc_sp_done); 648 649 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) { 650 lio = &sp->u.iocb_cmd; 651 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 652 } 653 654 ql_dbg(ql_dbg_disc, vha, 0x206f, 655 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n", 656 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name); 657 658 rval = qla2x00_start_sp(sp); 659 if (rval != QLA_SUCCESS) 660 goto done_free_sp; 661 662 return rval; 663 664 done_free_sp: 665 /* ref: INIT */ 666 kref_put(&sp->cmd_kref, qla2x00_sp_release); 667 done: 668 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 669 qla2x00_post_async_adisc_work(vha, fcport, data); 670 return rval; 671 } 672 673 static bool qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id) 674 { 675 struct qla_hw_data *ha = vha->hw; 676 677 if (IS_FWI2_CAPABLE(ha)) 678 return loop_id > NPH_LAST_HANDLE; 679 680 return (loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) || 681 loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST; 682 } 683 684 /** 685 * qla2x00_find_new_loop_id - scan through our port list and find a new usable loop ID 686 * @vha: adapter state pointer. 687 * @dev: port structure pointer. 688 * 689 * Returns: 690 * qla2x00 local function return status code. 691 * 692 * Context: 693 * Kernel context. 694 */ 695 static int qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) 696 { 697 int rval; 698 struct qla_hw_data *ha = vha->hw; 699 unsigned long flags = 0; 700 701 rval = QLA_SUCCESS; 702 703 spin_lock_irqsave(&ha->vport_slock, flags); 704 705 dev->loop_id = find_first_zero_bit(ha->loop_id_map, LOOPID_MAP_SIZE); 706 if (dev->loop_id >= LOOPID_MAP_SIZE || 707 qla2x00_is_reserved_id(vha, dev->loop_id)) { 708 dev->loop_id = FC_NO_LOOP_ID; 709 rval = QLA_FUNCTION_FAILED; 710 } else { 711 set_bit(dev->loop_id, ha->loop_id_map); 712 } 713 spin_unlock_irqrestore(&ha->vport_slock, flags); 714 715 if (rval == QLA_SUCCESS) 716 ql_dbg(ql_dbg_disc, dev->vha, 0x2086, 717 "Assigning new loopid=%x, portid=%x.\n", 718 dev->loop_id, dev->d_id.b24); 719 else 720 ql_log(ql_log_warn, dev->vha, 0x2087, 721 "No loop_id's available, portid=%x.\n", 722 dev->d_id.b24); 723 724 return rval; 725 } 726 727 void qla2x00_clear_loop_id(fc_port_t *fcport) 728 { 729 struct qla_hw_data *ha = fcport->vha->hw; 730 731 if (fcport->loop_id == FC_NO_LOOP_ID || 732 qla2x00_is_reserved_id(fcport->vha, fcport->loop_id)) 733 return; 734 735 clear_bit(fcport->loop_id, ha->loop_id_map); 736 fcport->loop_id = FC_NO_LOOP_ID; 737 } 738 739 static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha, 740 struct event_arg *ea) 741 { 742 fc_port_t *fcport, *conflict_fcport; 743 struct get_name_list_extended *e; 744 u16 i, n, found = 0, loop_id; 745 port_id_t id; 746 u64 wwn; 747 u16 data[2]; 748 u8 current_login_state, nvme_cls; 749 750 fcport = ea->fcport; 751 ql_dbg(ql_dbg_disc, vha, 0xffff, 752 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d edif %d\n", 753 __func__, fcport->port_name, fcport->disc_state, 754 fcport->fw_login_state, ea->rc, 755 fcport->login_gen, fcport->last_login_gen, 756 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id, fcport->edif.enable); 757 758 if (fcport->disc_state == DSC_DELETE_PEND) 759 return; 760 761 if (ea->rc) { /* rval */ 762 if (fcport->login_retry == 0) { 763 ql_dbg(ql_dbg_disc, vha, 0x20de, 764 "GNL failed Port login retry %8phN, retry cnt=%d.\n", 765 fcport->port_name, fcport->login_retry); 766 } 767 return; 768 } 769 770 if (fcport->last_rscn_gen != fcport->rscn_gen) { 771 qla_rscn_replay(fcport); 772 qlt_schedule_sess_for_deletion(fcport); 773 return; 774 } else if (fcport->last_login_gen != fcport->login_gen) { 775 ql_dbg(ql_dbg_disc, vha, 0x20e0, 776 "%s %8phC login gen changed\n", 777 __func__, fcport->port_name); 778 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 779 return; 780 } 781 782 n = ea->data[0] / sizeof(struct get_name_list_extended); 783 784 ql_dbg(ql_dbg_disc, vha, 0x20e1, 785 "%s %d %8phC n %d %02x%02x%02x lid %d \n", 786 __func__, __LINE__, fcport->port_name, n, 787 fcport->d_id.b.domain, fcport->d_id.b.area, 788 fcport->d_id.b.al_pa, fcport->loop_id); 789 790 for (i = 0; i < n; i++) { 791 e = &vha->gnl.l[i]; 792 wwn = wwn_to_u64(e->port_name); 793 id.b.domain = e->port_id[2]; 794 id.b.area = e->port_id[1]; 795 id.b.al_pa = e->port_id[0]; 796 id.b.rsvd_1 = 0; 797 798 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE)) 799 continue; 800 801 if (IS_SW_RESV_ADDR(id)) 802 continue; 803 804 found = 1; 805 806 loop_id = le16_to_cpu(e->nport_handle); 807 loop_id = (loop_id & 0x7fff); 808 nvme_cls = e->current_login_state >> 4; 809 current_login_state = e->current_login_state & 0xf; 810 811 if (PRLI_PHASE(nvme_cls)) { 812 current_login_state = nvme_cls; 813 fcport->fc4_type &= ~FS_FC4TYPE_FCP; 814 fcport->fc4_type |= FS_FC4TYPE_NVME; 815 } else if (PRLI_PHASE(current_login_state)) { 816 fcport->fc4_type |= FS_FC4TYPE_FCP; 817 fcport->fc4_type &= ~FS_FC4TYPE_NVME; 818 } 819 820 ql_dbg(ql_dbg_disc, vha, 0x20e2, 821 "%s found %8phC CLS [%x|%x] fc4_type %d ID[%06x|%06x] lid[%d|%d]\n", 822 __func__, fcport->port_name, 823 e->current_login_state, fcport->fw_login_state, 824 fcport->fc4_type, id.b24, fcport->d_id.b24, 825 loop_id, fcport->loop_id); 826 827 switch (fcport->disc_state) { 828 case DSC_DELETE_PEND: 829 case DSC_DELETED: 830 break; 831 default: 832 if ((id.b24 != fcport->d_id.b24 && 833 fcport->d_id.b24 && 834 fcport->loop_id != FC_NO_LOOP_ID) || 835 (fcport->loop_id != FC_NO_LOOP_ID && 836 fcport->loop_id != loop_id)) { 837 ql_dbg(ql_dbg_disc, vha, 0x20e3, 838 "%s %d %8phC post del sess\n", 839 __func__, __LINE__, fcport->port_name); 840 if (fcport->n2n_flag) 841 fcport->d_id.b24 = 0; 842 qlt_schedule_sess_for_deletion(fcport); 843 return; 844 } 845 break; 846 } 847 848 fcport->loop_id = loop_id; 849 if (fcport->n2n_flag) 850 fcport->d_id.b24 = id.b24; 851 852 wwn = wwn_to_u64(fcport->port_name); 853 qlt_find_sess_invalidate_other(vha, wwn, 854 id, loop_id, &conflict_fcport); 855 856 if (conflict_fcport) { 857 /* 858 * Another share fcport share the same loop_id & 859 * nport id. Conflict fcport needs to finish 860 * cleanup before this fcport can proceed to login. 861 */ 862 conflict_fcport->conflict = fcport; 863 fcport->login_pause = 1; 864 } 865 866 switch (vha->hw->current_topology) { 867 default: 868 switch (current_login_state) { 869 case DSC_LS_PRLI_COMP: 870 ql_dbg(ql_dbg_disc, 871 vha, 0x20e4, "%s %d %8phC post gpdb\n", 872 __func__, __LINE__, fcport->port_name); 873 874 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0) 875 fcport->port_type = FCT_INITIATOR; 876 else 877 fcport->port_type = FCT_TARGET; 878 data[0] = data[1] = 0; 879 qla2x00_post_async_adisc_work(vha, fcport, 880 data); 881 break; 882 case DSC_LS_PLOGI_COMP: 883 if (vha->hw->flags.edif_enabled) { 884 /* check to see if App support Secure */ 885 qla24xx_post_gpdb_work(vha, fcport, 0); 886 break; 887 } 888 fallthrough; 889 case DSC_LS_PORT_UNAVAIL: 890 default: 891 if (fcport->loop_id == FC_NO_LOOP_ID) { 892 qla2x00_find_new_loop_id(vha, fcport); 893 fcport->fw_login_state = 894 DSC_LS_PORT_UNAVAIL; 895 } 896 ql_dbg(ql_dbg_disc, vha, 0x20e5, 897 "%s %d %8phC\n", __func__, __LINE__, 898 fcport->port_name); 899 qla24xx_fcport_handle_login(vha, fcport); 900 break; 901 } 902 break; 903 case ISP_CFG_N: 904 fcport->fw_login_state = current_login_state; 905 fcport->d_id = id; 906 switch (current_login_state) { 907 case DSC_LS_PRLI_PEND: 908 /* 909 * In the middle of PRLI. Let it finish. 910 * Allow relogin code to recheck state again 911 * with GNL. Push disc_state back to DELETED 912 * so GNL can go out again 913 */ 914 qla2x00_set_fcport_disc_state(fcport, 915 DSC_DELETED); 916 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 917 break; 918 case DSC_LS_PRLI_COMP: 919 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0) 920 fcport->port_type = FCT_INITIATOR; 921 else 922 fcport->port_type = FCT_TARGET; 923 924 data[0] = data[1] = 0; 925 qla2x00_post_async_adisc_work(vha, fcport, 926 data); 927 break; 928 case DSC_LS_PLOGI_COMP: 929 if (vha->hw->flags.edif_enabled && 930 DBELL_ACTIVE(vha)) { 931 /* check to see if App support secure or not */ 932 qla24xx_post_gpdb_work(vha, fcport, 0); 933 break; 934 } 935 if (fcport_is_bigger(fcport)) { 936 /* local adapter is smaller */ 937 if (fcport->loop_id != FC_NO_LOOP_ID) 938 qla2x00_clear_loop_id(fcport); 939 940 fcport->loop_id = loop_id; 941 qla24xx_fcport_handle_login(vha, 942 fcport); 943 break; 944 } 945 fallthrough; 946 default: 947 if (fcport_is_smaller(fcport)) { 948 /* local adapter is bigger */ 949 if (fcport->loop_id != FC_NO_LOOP_ID) 950 qla2x00_clear_loop_id(fcport); 951 952 fcport->loop_id = loop_id; 953 qla24xx_fcport_handle_login(vha, 954 fcport); 955 } 956 break; 957 } 958 break; 959 } /* switch (ha->current_topology) */ 960 } 961 962 if (!found) { 963 switch (vha->hw->current_topology) { 964 case ISP_CFG_F: 965 case ISP_CFG_FL: 966 for (i = 0; i < n; i++) { 967 e = &vha->gnl.l[i]; 968 id.b.domain = e->port_id[0]; 969 id.b.area = e->port_id[1]; 970 id.b.al_pa = e->port_id[2]; 971 id.b.rsvd_1 = 0; 972 loop_id = le16_to_cpu(e->nport_handle); 973 974 if (fcport->d_id.b24 == id.b24) { 975 conflict_fcport = 976 qla2x00_find_fcport_by_wwpn(vha, 977 e->port_name, 0); 978 if (conflict_fcport) { 979 ql_dbg(ql_dbg_disc + ql_dbg_verbose, 980 vha, 0x20e5, 981 "%s %d %8phC post del sess\n", 982 __func__, __LINE__, 983 conflict_fcport->port_name); 984 qlt_schedule_sess_for_deletion 985 (conflict_fcport); 986 } 987 } 988 /* 989 * FW already picked this loop id for 990 * another fcport 991 */ 992 if (fcport->loop_id == loop_id) 993 fcport->loop_id = FC_NO_LOOP_ID; 994 } 995 qla24xx_fcport_handle_login(vha, fcport); 996 break; 997 case ISP_CFG_N: 998 qla2x00_set_fcport_disc_state(fcport, DSC_DELETED); 999 if (time_after_eq(jiffies, fcport->dm_login_expire)) { 1000 if (fcport->n2n_link_reset_cnt < 2) { 1001 fcport->n2n_link_reset_cnt++; 1002 /* 1003 * remote port is not sending PLOGI. 1004 * Reset link to kick start his state 1005 * machine 1006 */ 1007 set_bit(N2N_LINK_RESET, 1008 &vha->dpc_flags); 1009 } else { 1010 if (fcport->n2n_chip_reset < 1) { 1011 ql_log(ql_log_info, vha, 0x705d, 1012 "Chip reset to bring laser down"); 1013 set_bit(ISP_ABORT_NEEDED, 1014 &vha->dpc_flags); 1015 fcport->n2n_chip_reset++; 1016 } else { 1017 ql_log(ql_log_info, vha, 0x705d, 1018 "Remote port %8ph is not coming back\n", 1019 fcport->port_name); 1020 fcport->scan_state = 0; 1021 } 1022 } 1023 qla2xxx_wake_dpc(vha); 1024 } else { 1025 /* 1026 * report port suppose to do PLOGI. Give him 1027 * more time. FW will catch it. 1028 */ 1029 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1030 } 1031 break; 1032 case ISP_CFG_NL: 1033 qla24xx_fcport_handle_login(vha, fcport); 1034 break; 1035 default: 1036 break; 1037 } 1038 } 1039 } /* gnl_event */ 1040 1041 static void qla24xx_async_gnl_sp_done(srb_t *sp, int res) 1042 { 1043 struct scsi_qla_host *vha = sp->vha; 1044 unsigned long flags; 1045 struct fc_port *fcport = NULL, *tf; 1046 u16 i, n = 0, loop_id; 1047 struct event_arg ea; 1048 struct get_name_list_extended *e; 1049 u64 wwn; 1050 struct list_head h; 1051 bool found = false; 1052 1053 ql_dbg(ql_dbg_disc, vha, 0x20e7, 1054 "Async done-%s res %x mb[1]=%x mb[2]=%x \n", 1055 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1], 1056 sp->u.iocb_cmd.u.mbx.in_mb[2]); 1057 1058 1059 sp->fcport->flags &= ~(FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE); 1060 memset(&ea, 0, sizeof(ea)); 1061 ea.sp = sp; 1062 ea.rc = res; 1063 1064 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >= 1065 sizeof(struct get_name_list_extended)) { 1066 n = sp->u.iocb_cmd.u.mbx.in_mb[1] / 1067 sizeof(struct get_name_list_extended); 1068 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */ 1069 } 1070 1071 for (i = 0; i < n; i++) { 1072 e = &vha->gnl.l[i]; 1073 loop_id = le16_to_cpu(e->nport_handle); 1074 /* mask out reserve bit */ 1075 loop_id = (loop_id & 0x7fff); 1076 set_bit(loop_id, vha->hw->loop_id_map); 1077 wwn = wwn_to_u64(e->port_name); 1078 1079 ql_dbg(ql_dbg_disc, vha, 0x20e8, 1080 "%s %8phC %02x:%02x:%02x CLS %x/%x lid %x \n", 1081 __func__, &wwn, e->port_id[2], e->port_id[1], 1082 e->port_id[0], e->current_login_state, e->last_login_state, 1083 (loop_id & 0x7fff)); 1084 } 1085 1086 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1087 1088 INIT_LIST_HEAD(&h); 1089 fcport = tf = NULL; 1090 if (!list_empty(&vha->gnl.fcports)) 1091 list_splice_init(&vha->gnl.fcports, &h); 1092 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1093 1094 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) { 1095 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1096 list_del_init(&fcport->gnl_entry); 1097 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1098 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1099 ea.fcport = fcport; 1100 1101 qla24xx_handle_gnl_done_event(vha, &ea); 1102 } 1103 1104 /* create new fcport if fw has knowledge of new sessions */ 1105 for (i = 0; i < n; i++) { 1106 port_id_t id; 1107 u64 wwnn; 1108 1109 e = &vha->gnl.l[i]; 1110 wwn = wwn_to_u64(e->port_name); 1111 1112 found = false; 1113 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) { 1114 if (!memcmp((u8 *)&wwn, fcport->port_name, 1115 WWN_SIZE)) { 1116 found = true; 1117 break; 1118 } 1119 } 1120 1121 id.b.domain = e->port_id[2]; 1122 id.b.area = e->port_id[1]; 1123 id.b.al_pa = e->port_id[0]; 1124 id.b.rsvd_1 = 0; 1125 1126 if (!found && wwn && !IS_SW_RESV_ADDR(id)) { 1127 ql_dbg(ql_dbg_disc, vha, 0x2065, 1128 "%s %d %8phC %06x post new sess\n", 1129 __func__, __LINE__, (u8 *)&wwn, id.b24); 1130 wwnn = wwn_to_u64(e->node_name); 1131 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn, 1132 (u8 *)&wwnn, NULL, 0); 1133 } 1134 } 1135 1136 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1137 vha->gnl.sent = 0; 1138 if (!list_empty(&vha->gnl.fcports)) { 1139 /* retrigger gnl */ 1140 list_for_each_entry_safe(fcport, tf, &vha->gnl.fcports, 1141 gnl_entry) { 1142 list_del_init(&fcport->gnl_entry); 1143 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1144 if (qla24xx_post_gnl_work(vha, fcport) == QLA_SUCCESS) 1145 break; 1146 } 1147 } 1148 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1149 1150 /* ref: INIT */ 1151 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1152 } 1153 1154 int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport) 1155 { 1156 srb_t *sp; 1157 int rval = QLA_FUNCTION_FAILED; 1158 unsigned long flags; 1159 u16 *mb; 1160 1161 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT)) 1162 goto done; 1163 1164 ql_dbg(ql_dbg_disc, vha, 0x20d9, 1165 "Async-gnlist WWPN %8phC \n", fcport->port_name); 1166 1167 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1168 fcport->flags |= FCF_ASYNC_SENT; 1169 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 1170 fcport->last_rscn_gen = fcport->rscn_gen; 1171 fcport->last_login_gen = fcport->login_gen; 1172 1173 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports); 1174 if (vha->gnl.sent) { 1175 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1176 return QLA_SUCCESS; 1177 } 1178 vha->gnl.sent = 1; 1179 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1180 1181 /* ref: INIT */ 1182 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1183 if (!sp) 1184 goto done; 1185 1186 sp->type = SRB_MB_IOCB; 1187 sp->name = "gnlist"; 1188 sp->gen1 = fcport->rscn_gen; 1189 sp->gen2 = fcport->login_gen; 1190 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 1191 qla24xx_async_gnl_sp_done); 1192 1193 mb = sp->u.iocb_cmd.u.mbx.out_mb; 1194 mb[0] = MBC_PORT_NODE_NAME_LIST; 1195 mb[1] = BIT_2 | BIT_3; 1196 mb[2] = MSW(vha->gnl.ldma); 1197 mb[3] = LSW(vha->gnl.ldma); 1198 mb[6] = MSW(MSD(vha->gnl.ldma)); 1199 mb[7] = LSW(MSD(vha->gnl.ldma)); 1200 mb[8] = vha->gnl.size; 1201 mb[9] = vha->vp_idx; 1202 1203 ql_dbg(ql_dbg_disc, vha, 0x20da, 1204 "Async-%s - OUT WWPN %8phC hndl %x\n", 1205 sp->name, fcport->port_name, sp->handle); 1206 1207 rval = qla2x00_start_sp(sp); 1208 if (rval != QLA_SUCCESS) 1209 goto done_free_sp; 1210 1211 return rval; 1212 1213 done_free_sp: 1214 /* 1215 * use qla24xx_async_gnl_sp_done to purge all pending gnl request. 1216 * kref_put is call behind the scene. 1217 */ 1218 sp->u.iocb_cmd.u.mbx.in_mb[0] = MBS_COMMAND_ERROR; 1219 qla24xx_async_gnl_sp_done(sp, QLA_COMMAND_ERROR); 1220 fcport->flags &= ~(FCF_ASYNC_SENT); 1221 done: 1222 fcport->flags &= ~(FCF_ASYNC_ACTIVE); 1223 return rval; 1224 } 1225 1226 int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport) 1227 { 1228 struct qla_work_evt *e; 1229 1230 e = qla2x00_alloc_work(vha, QLA_EVT_GNL); 1231 if (!e) 1232 return QLA_FUNCTION_FAILED; 1233 1234 e->u.fcport.fcport = fcport; 1235 fcport->flags |= FCF_ASYNC_ACTIVE; 1236 return qla2x00_post_work(vha, e); 1237 } 1238 1239 static void qla24xx_async_gpdb_sp_done(srb_t *sp, int res) 1240 { 1241 struct scsi_qla_host *vha = sp->vha; 1242 struct qla_hw_data *ha = vha->hw; 1243 fc_port_t *fcport = sp->fcport; 1244 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb; 1245 struct event_arg ea; 1246 1247 ql_dbg(ql_dbg_disc, vha, 0x20db, 1248 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n", 1249 sp->name, res, fcport->port_name, mb[1], mb[2]); 1250 1251 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1252 1253 if (res == QLA_FUNCTION_TIMEOUT) 1254 goto done; 1255 1256 memset(&ea, 0, sizeof(ea)); 1257 ea.fcport = fcport; 1258 ea.sp = sp; 1259 1260 qla24xx_handle_gpdb_event(vha, &ea); 1261 1262 done: 1263 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in, 1264 sp->u.iocb_cmd.u.mbx.in_dma); 1265 1266 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1267 } 1268 1269 int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport) 1270 { 1271 struct qla_work_evt *e; 1272 1273 if (vha->host->active_mode == MODE_TARGET) 1274 return QLA_FUNCTION_FAILED; 1275 1276 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI); 1277 if (!e) 1278 return QLA_FUNCTION_FAILED; 1279 1280 e->u.fcport.fcport = fcport; 1281 1282 return qla2x00_post_work(vha, e); 1283 } 1284 1285 static void qla2x00_async_prli_sp_done(srb_t *sp, int res) 1286 { 1287 struct scsi_qla_host *vha = sp->vha; 1288 struct srb_iocb *lio = &sp->u.iocb_cmd; 1289 struct event_arg ea; 1290 1291 ql_dbg(ql_dbg_disc, vha, 0x2129, 1292 "%s %8phC res %x\n", __func__, 1293 sp->fcport->port_name, res); 1294 1295 sp->fcport->flags &= ~FCF_ASYNC_SENT; 1296 1297 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 1298 memset(&ea, 0, sizeof(ea)); 1299 ea.fcport = sp->fcport; 1300 ea.data[0] = lio->u.logio.data[0]; 1301 ea.data[1] = lio->u.logio.data[1]; 1302 ea.iop[0] = lio->u.logio.iop[0]; 1303 ea.iop[1] = lio->u.logio.iop[1]; 1304 ea.sp = sp; 1305 if (res == QLA_OS_TIMER_EXPIRED) 1306 ea.data[0] = QLA_OS_TIMER_EXPIRED; 1307 else if (res) 1308 ea.data[0] = MBS_COMMAND_ERROR; 1309 1310 qla24xx_handle_prli_done_event(vha, &ea); 1311 } 1312 1313 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1314 } 1315 1316 int 1317 qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport) 1318 { 1319 srb_t *sp; 1320 struct srb_iocb *lio; 1321 int rval = QLA_FUNCTION_FAILED; 1322 1323 if (!vha->flags.online) { 1324 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n", 1325 __func__, __LINE__, fcport->port_name); 1326 return rval; 1327 } 1328 1329 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND || 1330 fcport->fw_login_state == DSC_LS_PRLI_PEND) && 1331 qla_dual_mode_enabled(vha)) { 1332 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n", 1333 __func__, __LINE__, fcport->port_name); 1334 return rval; 1335 } 1336 1337 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1338 if (!sp) 1339 return rval; 1340 1341 fcport->flags |= FCF_ASYNC_SENT; 1342 fcport->logout_completed = 0; 1343 1344 sp->type = SRB_PRLI_CMD; 1345 sp->name = "prli"; 1346 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 1347 qla2x00_async_prli_sp_done); 1348 1349 lio = &sp->u.iocb_cmd; 1350 lio->u.logio.flags = 0; 1351 1352 if (NVME_TARGET(vha->hw, fcport)) 1353 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI; 1354 1355 ql_dbg(ql_dbg_disc, vha, 0x211b, 1356 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d fc4type %x priority %x %s.\n", 1357 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24, 1358 fcport->login_retry, fcport->fc4_type, vha->hw->fc4_type_priority, 1359 NVME_TARGET(vha->hw, fcport) ? "nvme" : "fcp"); 1360 1361 rval = qla2x00_start_sp(sp); 1362 if (rval != QLA_SUCCESS) { 1363 fcport->flags |= FCF_LOGIN_NEEDED; 1364 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1365 goto done_free_sp; 1366 } 1367 1368 return rval; 1369 1370 done_free_sp: 1371 /* ref: INIT */ 1372 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1373 fcport->flags &= ~FCF_ASYNC_SENT; 1374 return rval; 1375 } 1376 1377 int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 1378 { 1379 struct qla_work_evt *e; 1380 1381 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB); 1382 if (!e) 1383 return QLA_FUNCTION_FAILED; 1384 1385 e->u.fcport.fcport = fcport; 1386 e->u.fcport.opt = opt; 1387 fcport->flags |= FCF_ASYNC_ACTIVE; 1388 return qla2x00_post_work(vha, e); 1389 } 1390 1391 int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 1392 { 1393 srb_t *sp; 1394 struct srb_iocb *mbx; 1395 int rval = QLA_FUNCTION_FAILED; 1396 u16 *mb; 1397 dma_addr_t pd_dma; 1398 struct port_database_24xx *pd; 1399 struct qla_hw_data *ha = vha->hw; 1400 1401 if (IS_SESSION_DELETED(fcport)) { 1402 ql_log(ql_log_warn, vha, 0xffff, 1403 "%s: %8phC is being delete - not sending command.\n", 1404 __func__, fcport->port_name); 1405 fcport->flags &= ~FCF_ASYNC_ACTIVE; 1406 return rval; 1407 } 1408 1409 if (!vha->flags.online || fcport->flags & FCF_ASYNC_SENT) { 1410 ql_log(ql_log_warn, vha, 0xffff, 1411 "%s: %8phC online %d flags %x - not sending command.\n", 1412 __func__, fcport->port_name, vha->flags.online, fcport->flags); 1413 goto done; 1414 } 1415 1416 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1417 if (!sp) 1418 goto done; 1419 1420 qla2x00_set_fcport_disc_state(fcport, DSC_GPDB); 1421 1422 fcport->flags |= FCF_ASYNC_SENT; 1423 sp->type = SRB_MB_IOCB; 1424 sp->name = "gpdb"; 1425 sp->gen1 = fcport->rscn_gen; 1426 sp->gen2 = fcport->login_gen; 1427 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 1428 qla24xx_async_gpdb_sp_done); 1429 1430 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1431 if (pd == NULL) { 1432 ql_log(ql_log_warn, vha, 0xd043, 1433 "Failed to allocate port database structure.\n"); 1434 goto done_free_sp; 1435 } 1436 1437 mb = sp->u.iocb_cmd.u.mbx.out_mb; 1438 mb[0] = MBC_GET_PORT_DATABASE; 1439 mb[1] = fcport->loop_id; 1440 mb[2] = MSW(pd_dma); 1441 mb[3] = LSW(pd_dma); 1442 mb[6] = MSW(MSD(pd_dma)); 1443 mb[7] = LSW(MSD(pd_dma)); 1444 mb[9] = vha->vp_idx; 1445 mb[10] = opt; 1446 1447 mbx = &sp->u.iocb_cmd; 1448 mbx->u.mbx.in = (void *)pd; 1449 mbx->u.mbx.in_dma = pd_dma; 1450 1451 ql_dbg(ql_dbg_disc, vha, 0x20dc, 1452 "Async-%s %8phC hndl %x opt %x\n", 1453 sp->name, fcport->port_name, sp->handle, opt); 1454 1455 rval = qla2x00_start_sp(sp); 1456 if (rval != QLA_SUCCESS) 1457 goto done_free_sp; 1458 return rval; 1459 1460 done_free_sp: 1461 if (pd) 1462 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1463 1464 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1465 fcport->flags &= ~FCF_ASYNC_SENT; 1466 done: 1467 fcport->flags &= ~FCF_ASYNC_ACTIVE; 1468 qla24xx_post_gpdb_work(vha, fcport, opt); 1469 return rval; 1470 } 1471 1472 static 1473 void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 1474 { 1475 unsigned long flags; 1476 1477 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1478 ea->fcport->login_gen++; 1479 ea->fcport->logout_on_delete = 1; 1480 1481 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) { 1482 vha->fcport_count++; 1483 ea->fcport->login_succ = 1; 1484 1485 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1486 qla24xx_sched_upd_fcport(ea->fcport); 1487 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1488 } else if (ea->fcport->login_succ) { 1489 /* 1490 * We have an existing session. A late RSCN delivery 1491 * must have triggered the session to be re-validate. 1492 * Session is still valid. 1493 */ 1494 ql_dbg(ql_dbg_disc, vha, 0x20d6, 1495 "%s %d %8phC session revalidate success\n", 1496 __func__, __LINE__, ea->fcport->port_name); 1497 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_COMPLETE); 1498 } 1499 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1500 } 1501 1502 static int qla_chk_secure_login(scsi_qla_host_t *vha, fc_port_t *fcport, 1503 struct port_database_24xx *pd) 1504 { 1505 int rc = 0; 1506 1507 if (pd->secure_login) { 1508 ql_dbg(ql_dbg_disc, vha, 0x104d, 1509 "Secure Login established on %8phC\n", 1510 fcport->port_name); 1511 fcport->flags |= FCF_FCSP_DEVICE; 1512 } else { 1513 ql_dbg(ql_dbg_disc, vha, 0x104d, 1514 "non-Secure Login %8phC", 1515 fcport->port_name); 1516 fcport->flags &= ~FCF_FCSP_DEVICE; 1517 } 1518 if (vha->hw->flags.edif_enabled) { 1519 if (fcport->flags & FCF_FCSP_DEVICE) { 1520 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_AUTH_PEND); 1521 /* Start edif prli timer & ring doorbell for app */ 1522 fcport->edif.rx_sa_set = 0; 1523 fcport->edif.tx_sa_set = 0; 1524 fcport->edif.rx_sa_pending = 0; 1525 fcport->edif.tx_sa_pending = 0; 1526 1527 qla2x00_post_aen_work(vha, FCH_EVT_PORT_ONLINE, 1528 fcport->d_id.b24); 1529 1530 if (DBELL_ACTIVE(vha)) { 1531 ql_dbg(ql_dbg_disc, vha, 0x20ef, 1532 "%s %d %8phC EDIF: post DB_AUTH: AUTH needed\n", 1533 __func__, __LINE__, fcport->port_name); 1534 fcport->edif.app_sess_online = 1; 1535 1536 qla_edb_eventcreate(vha, VND_CMD_AUTH_STATE_NEEDED, 1537 fcport->d_id.b24, 0, fcport); 1538 } 1539 1540 rc = 1; 1541 } else if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha)) { 1542 ql_dbg(ql_dbg_disc, vha, 0x2117, 1543 "%s %d %8phC post prli\n", 1544 __func__, __LINE__, fcport->port_name); 1545 qla24xx_post_prli_work(vha, fcport); 1546 rc = 1; 1547 } 1548 } 1549 return rc; 1550 } 1551 1552 static 1553 void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 1554 { 1555 fc_port_t *fcport = ea->fcport; 1556 struct port_database_24xx *pd; 1557 struct srb *sp = ea->sp; 1558 uint8_t ls; 1559 1560 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in; 1561 1562 fcport->flags &= ~FCF_ASYNC_SENT; 1563 1564 ql_dbg(ql_dbg_disc, vha, 0x20d2, 1565 "%s %8phC DS %d LS %x fc4_type %x rc %x\n", __func__, 1566 fcport->port_name, fcport->disc_state, pd->current_login_state, 1567 fcport->fc4_type, ea->rc); 1568 1569 if (fcport->disc_state == DSC_DELETE_PEND) { 1570 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC\n", 1571 __func__, __LINE__, fcport->port_name); 1572 return; 1573 } 1574 1575 if (NVME_TARGET(vha->hw, fcport)) 1576 ls = pd->current_login_state >> 4; 1577 else 1578 ls = pd->current_login_state & 0xf; 1579 1580 if (ea->sp->gen2 != fcport->login_gen) { 1581 /* target side must have changed it. */ 1582 1583 ql_dbg(ql_dbg_disc, vha, 0x20d3, 1584 "%s %8phC generation changed\n", 1585 __func__, fcport->port_name); 1586 return; 1587 } else if (ea->sp->gen1 != fcport->rscn_gen) { 1588 qla_rscn_replay(fcport); 1589 qlt_schedule_sess_for_deletion(fcport); 1590 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC, ls %x\n", 1591 __func__, __LINE__, fcport->port_name, ls); 1592 return; 1593 } 1594 1595 switch (ls) { 1596 case PDS_PRLI_COMPLETE: 1597 __qla24xx_parse_gpdb(vha, fcport, pd); 1598 break; 1599 case PDS_PLOGI_COMPLETE: 1600 if (qla_chk_secure_login(vha, fcport, pd)) { 1601 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC, ls %x\n", 1602 __func__, __LINE__, fcport->port_name, ls); 1603 return; 1604 } 1605 fallthrough; 1606 case PDS_PLOGI_PENDING: 1607 case PDS_PRLI_PENDING: 1608 case PDS_PRLI2_PENDING: 1609 /* Set discovery state back to GNL to Relogin attempt */ 1610 if (qla_dual_mode_enabled(vha) || 1611 qla_ini_mode_enabled(vha)) { 1612 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 1613 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1614 } 1615 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC, ls %x\n", 1616 __func__, __LINE__, fcport->port_name, ls); 1617 return; 1618 case PDS_LOGO_PENDING: 1619 case PDS_PORT_UNAVAILABLE: 1620 default: 1621 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n", 1622 __func__, __LINE__, fcport->port_name); 1623 qlt_schedule_sess_for_deletion(fcport); 1624 return; 1625 } 1626 __qla24xx_handle_gpdb_event(vha, ea); 1627 } /* gpdb event */ 1628 1629 static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport) 1630 { 1631 u8 login = 0; 1632 int rc; 1633 1634 ql_dbg(ql_dbg_disc, vha, 0x307b, 1635 "%s %8phC DS %d LS %d lid %d retries=%d\n", 1636 __func__, fcport->port_name, fcport->disc_state, 1637 fcport->fw_login_state, fcport->loop_id, fcport->login_retry); 1638 1639 if (qla_tgt_mode_enabled(vha)) 1640 return; 1641 1642 if (qla_dual_mode_enabled(vha)) { 1643 if (N2N_TOPO(vha->hw)) { 1644 u64 mywwn, wwn; 1645 1646 mywwn = wwn_to_u64(vha->port_name); 1647 wwn = wwn_to_u64(fcport->port_name); 1648 if (mywwn > wwn) 1649 login = 1; 1650 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP) 1651 && time_after_eq(jiffies, 1652 fcport->plogi_nack_done_deadline)) 1653 login = 1; 1654 } else { 1655 login = 1; 1656 } 1657 } else { 1658 /* initiator mode */ 1659 login = 1; 1660 } 1661 1662 if (login && fcport->login_retry) { 1663 fcport->login_retry--; 1664 if (fcport->loop_id == FC_NO_LOOP_ID) { 1665 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 1666 rc = qla2x00_find_new_loop_id(vha, fcport); 1667 if (rc) { 1668 ql_dbg(ql_dbg_disc, vha, 0x20e6, 1669 "%s %d %8phC post del sess - out of loopid\n", 1670 __func__, __LINE__, fcport->port_name); 1671 fcport->scan_state = 0; 1672 qlt_schedule_sess_for_deletion(fcport); 1673 return; 1674 } 1675 } 1676 ql_dbg(ql_dbg_disc, vha, 0x20bf, 1677 "%s %d %8phC post login\n", 1678 __func__, __LINE__, fcport->port_name); 1679 qla2x00_post_async_login_work(vha, fcport, NULL); 1680 } 1681 } 1682 1683 int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport) 1684 { 1685 u16 data[2]; 1686 u16 sec; 1687 1688 ql_dbg(ql_dbg_disc, vha, 0x20d8, 1689 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d fc4type %x\n", 1690 __func__, fcport->port_name, fcport->disc_state, 1691 fcport->fw_login_state, fcport->login_pause, fcport->flags, 1692 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen, 1693 fcport->login_gen, fcport->loop_id, fcport->scan_state, 1694 fcport->fc4_type); 1695 1696 if (fcport->scan_state != QLA_FCPORT_FOUND || 1697 fcport->disc_state == DSC_DELETE_PEND) 1698 return 0; 1699 1700 if ((fcport->loop_id != FC_NO_LOOP_ID) && 1701 qla_dual_mode_enabled(vha) && 1702 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 1703 (fcport->fw_login_state == DSC_LS_PRLI_PEND))) 1704 return 0; 1705 1706 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP && 1707 !N2N_TOPO(vha->hw)) { 1708 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) { 1709 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1710 return 0; 1711 } 1712 } 1713 1714 /* Target won't initiate port login if fabric is present */ 1715 if (vha->host->active_mode == MODE_TARGET && !N2N_TOPO(vha->hw)) 1716 return 0; 1717 1718 if (fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE)) { 1719 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1720 return 0; 1721 } 1722 1723 switch (fcport->disc_state) { 1724 case DSC_DELETED: 1725 switch (vha->hw->current_topology) { 1726 case ISP_CFG_N: 1727 if (fcport_is_smaller(fcport)) { 1728 /* this adapter is bigger */ 1729 if (fcport->login_retry) { 1730 if (fcport->loop_id == FC_NO_LOOP_ID) { 1731 qla2x00_find_new_loop_id(vha, 1732 fcport); 1733 fcport->fw_login_state = 1734 DSC_LS_PORT_UNAVAIL; 1735 } 1736 fcport->login_retry--; 1737 qla_post_els_plogi_work(vha, fcport); 1738 } else { 1739 ql_log(ql_log_info, vha, 0x705d, 1740 "Unable to reach remote port %8phC", 1741 fcport->port_name); 1742 } 1743 } else { 1744 qla24xx_post_gnl_work(vha, fcport); 1745 } 1746 break; 1747 default: 1748 if (fcport->loop_id == FC_NO_LOOP_ID) { 1749 ql_dbg(ql_dbg_disc, vha, 0x20bd, 1750 "%s %d %8phC post gnl\n", 1751 __func__, __LINE__, fcport->port_name); 1752 qla24xx_post_gnl_work(vha, fcport); 1753 } else { 1754 qla_chk_n2n_b4_login(vha, fcport); 1755 } 1756 break; 1757 } 1758 break; 1759 1760 case DSC_GNL: 1761 switch (vha->hw->current_topology) { 1762 case ISP_CFG_N: 1763 if ((fcport->current_login_state & 0xf) == 0x6) { 1764 ql_dbg(ql_dbg_disc, vha, 0x2118, 1765 "%s %d %8phC post GPDB work\n", 1766 __func__, __LINE__, fcport->port_name); 1767 fcport->chip_reset = 1768 vha->hw->base_qpair->chip_reset; 1769 qla24xx_post_gpdb_work(vha, fcport, 0); 1770 } else { 1771 ql_dbg(ql_dbg_disc, vha, 0x2118, 1772 "%s %d %8phC post %s PRLI\n", 1773 __func__, __LINE__, fcport->port_name, 1774 NVME_TARGET(vha->hw, fcport) ? "NVME" : 1775 "FC"); 1776 qla24xx_post_prli_work(vha, fcport); 1777 } 1778 break; 1779 default: 1780 if (fcport->login_pause) { 1781 ql_dbg(ql_dbg_disc, vha, 0x20d8, 1782 "%s %d %8phC exit\n", 1783 __func__, __LINE__, 1784 fcport->port_name); 1785 fcport->last_rscn_gen = fcport->rscn_gen; 1786 fcport->last_login_gen = fcport->login_gen; 1787 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1788 break; 1789 } 1790 qla_chk_n2n_b4_login(vha, fcport); 1791 break; 1792 } 1793 break; 1794 1795 case DSC_LOGIN_FAILED: 1796 if (N2N_TOPO(vha->hw)) 1797 qla_chk_n2n_b4_login(vha, fcport); 1798 else 1799 qlt_schedule_sess_for_deletion(fcport); 1800 break; 1801 1802 case DSC_LOGIN_COMPLETE: 1803 /* recheck login state */ 1804 data[0] = data[1] = 0; 1805 qla2x00_post_async_adisc_work(vha, fcport, data); 1806 break; 1807 1808 case DSC_LOGIN_PEND: 1809 if (vha->hw->flags.edif_enabled) 1810 break; 1811 1812 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) { 1813 ql_dbg(ql_dbg_disc, vha, 0x2118, 1814 "%s %d %8phC post %s PRLI\n", 1815 __func__, __LINE__, fcport->port_name, 1816 NVME_TARGET(vha->hw, fcport) ? "NVME" : "FC"); 1817 qla24xx_post_prli_work(vha, fcport); 1818 } 1819 break; 1820 1821 case DSC_UPD_FCPORT: 1822 sec = jiffies_to_msecs(jiffies - 1823 fcport->jiffies_at_registration)/1000; 1824 if (fcport->sec_since_registration < sec && sec && 1825 !(sec % 60)) { 1826 fcport->sec_since_registration = sec; 1827 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 1828 "%s %8phC - Slow Rport registration(%d Sec)\n", 1829 __func__, fcport->port_name, sec); 1830 } 1831 1832 if (fcport->next_disc_state != DSC_DELETE_PEND) 1833 fcport->next_disc_state = DSC_ADISC; 1834 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1835 break; 1836 1837 default: 1838 break; 1839 } 1840 1841 return 0; 1842 } 1843 1844 int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id, 1845 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type) 1846 { 1847 struct qla_work_evt *e; 1848 1849 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS); 1850 if (!e) 1851 return QLA_FUNCTION_FAILED; 1852 1853 e->u.new_sess.id = *id; 1854 e->u.new_sess.pla = pla; 1855 e->u.new_sess.fc4_type = fc4_type; 1856 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE); 1857 if (node_name) 1858 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE); 1859 1860 return qla2x00_post_work(vha, e); 1861 } 1862 1863 static void qla_rscn_gen_tick(scsi_qla_host_t *vha, u32 *ret_rscn_gen) 1864 { 1865 *ret_rscn_gen = atomic_inc_return(&vha->rscn_gen); 1866 /* memory barrier */ 1867 wmb(); 1868 } 1869 1870 void qla2x00_handle_rscn(scsi_qla_host_t *vha, struct event_arg *ea) 1871 { 1872 fc_port_t *fcport; 1873 unsigned long flags; 1874 u32 rscn_gen; 1875 1876 switch (ea->id.b.rsvd_1) { 1877 case RSCN_PORT_ADDR: 1878 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1); 1879 if (fcport) { 1880 if (vha->hw->flags.edif_enabled && DBELL_ACTIVE(vha)) { 1881 /* 1882 * On ipsec start by remote port, Target port 1883 * may use RSCN to trigger initiator to 1884 * relogin. If driver is already in the 1885 * process of a relogin, then ignore the RSCN 1886 * and allow the current relogin to continue. 1887 * This reduces thrashing of the connection. 1888 */ 1889 if (atomic_read(&fcport->state) == FCS_ONLINE) { 1890 /* 1891 * If state = online, then set scan_needed=1 to do relogin. 1892 * Otherwise we're already in the middle of a relogin 1893 */ 1894 fcport->scan_needed = 1; 1895 qla_rscn_gen_tick(vha, &fcport->rscn_gen); 1896 } 1897 } else { 1898 fcport->scan_needed = 1; 1899 qla_rscn_gen_tick(vha, &fcport->rscn_gen); 1900 } 1901 } 1902 break; 1903 case RSCN_AREA_ADDR: 1904 qla_rscn_gen_tick(vha, &rscn_gen); 1905 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1906 if (fcport->flags & FCF_FCP2_DEVICE && 1907 atomic_read(&fcport->state) == FCS_ONLINE) 1908 continue; 1909 1910 if ((ea->id.b24 & 0xffff00) == (fcport->d_id.b24 & 0xffff00)) { 1911 fcport->scan_needed = 1; 1912 fcport->rscn_gen = rscn_gen; 1913 } 1914 } 1915 break; 1916 case RSCN_DOM_ADDR: 1917 qla_rscn_gen_tick(vha, &rscn_gen); 1918 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1919 if (fcport->flags & FCF_FCP2_DEVICE && 1920 atomic_read(&fcport->state) == FCS_ONLINE) 1921 continue; 1922 1923 if ((ea->id.b24 & 0xff0000) == (fcport->d_id.b24 & 0xff0000)) { 1924 fcport->scan_needed = 1; 1925 fcport->rscn_gen = rscn_gen; 1926 } 1927 } 1928 break; 1929 case RSCN_FAB_ADDR: 1930 default: 1931 qla_rscn_gen_tick(vha, &rscn_gen); 1932 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1933 if (fcport->flags & FCF_FCP2_DEVICE && 1934 atomic_read(&fcport->state) == FCS_ONLINE) 1935 continue; 1936 1937 fcport->scan_needed = 1; 1938 fcport->rscn_gen = rscn_gen; 1939 } 1940 break; 1941 } 1942 1943 spin_lock_irqsave(&vha->work_lock, flags); 1944 if (vha->scan.scan_flags == 0) { 1945 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s: schedule\n", __func__); 1946 vha->scan.scan_flags |= SF_QUEUED; 1947 vha->scan.rscn_gen_start = atomic_read(&vha->rscn_gen); 1948 schedule_delayed_work(&vha->scan.scan_work, 5); 1949 } 1950 spin_unlock_irqrestore(&vha->work_lock, flags); 1951 } 1952 1953 void qla24xx_handle_relogin_event(scsi_qla_host_t *vha, 1954 struct event_arg *ea) 1955 { 1956 fc_port_t *fcport = ea->fcport; 1957 1958 if (test_bit(UNLOADING, &vha->dpc_flags)) 1959 return; 1960 1961 ql_dbg(ql_dbg_disc, vha, 0x2102, 1962 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n", 1963 __func__, fcport->port_name, fcport->disc_state, 1964 fcport->fw_login_state, fcport->login_pause, 1965 fcport->deleted, fcport->conflict, 1966 fcport->last_rscn_gen, fcport->rscn_gen, 1967 fcport->last_login_gen, fcport->login_gen, 1968 fcport->flags); 1969 1970 if (fcport->last_rscn_gen != fcport->rscn_gen) { 1971 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gnl\n", 1972 __func__, __LINE__, fcport->port_name); 1973 qla24xx_post_gnl_work(vha, fcport); 1974 return; 1975 } 1976 1977 qla24xx_fcport_handle_login(vha, fcport); 1978 } 1979 1980 void qla_handle_els_plogi_done(scsi_qla_host_t *vha, 1981 struct event_arg *ea) 1982 { 1983 if (N2N_TOPO(vha->hw) && fcport_is_smaller(ea->fcport) && 1984 vha->hw->flags.edif_enabled) { 1985 /* check to see if App support Secure */ 1986 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 1987 return; 1988 } 1989 1990 /* for pure Target Mode, PRLI will not be initiated */ 1991 if (vha->host->active_mode == MODE_TARGET) 1992 return; 1993 1994 ql_dbg(ql_dbg_disc, vha, 0x2118, 1995 "%s %d %8phC post PRLI\n", 1996 __func__, __LINE__, ea->fcport->port_name); 1997 qla24xx_post_prli_work(vha, ea->fcport); 1998 } 1999 2000 /* 2001 * RSCN(s) came in for this fcport, but the RSCN(s) was not able 2002 * to be consumed by the fcport 2003 */ 2004 void qla_rscn_replay(fc_port_t *fcport) 2005 { 2006 struct event_arg ea; 2007 2008 switch (fcport->disc_state) { 2009 case DSC_DELETE_PEND: 2010 return; 2011 default: 2012 break; 2013 } 2014 2015 if (fcport->scan_needed) { 2016 memset(&ea, 0, sizeof(ea)); 2017 ea.id = fcport->d_id; 2018 ea.id.b.rsvd_1 = RSCN_PORT_ADDR; 2019 qla2x00_handle_rscn(fcport->vha, &ea); 2020 } 2021 } 2022 2023 static void 2024 qla2x00_tmf_iocb_timeout(void *data) 2025 { 2026 srb_t *sp = data; 2027 struct srb_iocb *tmf = &sp->u.iocb_cmd; 2028 int rc, h; 2029 unsigned long flags; 2030 2031 if (sp->type == SRB_MARKER) 2032 rc = QLA_FUNCTION_FAILED; 2033 else 2034 rc = qla24xx_async_abort_cmd(sp, false); 2035 2036 if (rc) { 2037 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 2038 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; h++) { 2039 if (sp->qpair->req->outstanding_cmds[h] == sp) { 2040 sp->qpair->req->outstanding_cmds[h] = NULL; 2041 qla_put_fw_resources(sp->qpair, &sp->iores); 2042 break; 2043 } 2044 } 2045 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 2046 tmf->u.tmf.comp_status = cpu_to_le16(CS_TIMEOUT); 2047 tmf->u.tmf.data = QLA_FUNCTION_FAILED; 2048 complete(&tmf->u.tmf.comp); 2049 } 2050 } 2051 2052 static void qla_marker_sp_done(srb_t *sp, int res) 2053 { 2054 struct srb_iocb *tmf = &sp->u.iocb_cmd; 2055 2056 if (res != QLA_SUCCESS) 2057 ql_dbg(ql_dbg_taskm, sp->vha, 0x8004, 2058 "Async-marker fail hdl=%x portid=%06x ctrl=%x lun=%lld qp=%d.\n", 2059 sp->handle, sp->fcport->d_id.b24, sp->u.iocb_cmd.u.tmf.flags, 2060 sp->u.iocb_cmd.u.tmf.lun, sp->qpair->id); 2061 2062 sp->u.iocb_cmd.u.tmf.data = res; 2063 complete(&tmf->u.tmf.comp); 2064 } 2065 2066 #define START_SP_W_RETRIES(_sp, _rval, _chip_gen, _login_gen) \ 2067 {\ 2068 int cnt = 5; \ 2069 do { \ 2070 if (_chip_gen != sp->vha->hw->chip_reset || _login_gen != sp->fcport->login_gen) {\ 2071 _rval = -EINVAL; \ 2072 break; \ 2073 } \ 2074 _rval = qla2x00_start_sp(_sp); \ 2075 if (_rval == -EAGAIN) \ 2076 msleep(1); \ 2077 else \ 2078 break; \ 2079 cnt--; \ 2080 } while (cnt); \ 2081 } 2082 2083 /** 2084 * qla26xx_marker: send marker IOCB and wait for the completion of it. 2085 * @arg: pointer to argument list. 2086 * It is assume caller will provide an fcport pointer and modifier 2087 */ 2088 static int 2089 qla26xx_marker(struct tmf_arg *arg) 2090 { 2091 struct scsi_qla_host *vha = arg->vha; 2092 struct srb_iocb *tm_iocb; 2093 srb_t *sp; 2094 int rval = QLA_FUNCTION_FAILED; 2095 fc_port_t *fcport = arg->fcport; 2096 u32 chip_gen, login_gen; 2097 2098 if (TMF_NOT_READY(arg->fcport)) { 2099 ql_dbg(ql_dbg_taskm, vha, 0x8039, 2100 "FC port not ready for marker loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d.\n", 2101 fcport->loop_id, fcport->d_id.b24, 2102 arg->modifier, arg->lun, arg->qpair->id); 2103 return QLA_SUSPENDED; 2104 } 2105 2106 chip_gen = vha->hw->chip_reset; 2107 login_gen = fcport->login_gen; 2108 2109 /* ref: INIT */ 2110 sp = qla2xxx_get_qpair_sp(vha, arg->qpair, fcport, GFP_KERNEL); 2111 if (!sp) 2112 goto done; 2113 2114 sp->type = SRB_MARKER; 2115 sp->name = "marker"; 2116 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha), qla_marker_sp_done); 2117 sp->u.iocb_cmd.timeout = qla2x00_tmf_iocb_timeout; 2118 2119 tm_iocb = &sp->u.iocb_cmd; 2120 init_completion(&tm_iocb->u.tmf.comp); 2121 tm_iocb->u.tmf.modifier = arg->modifier; 2122 tm_iocb->u.tmf.lun = arg->lun; 2123 tm_iocb->u.tmf.loop_id = fcport->loop_id; 2124 tm_iocb->u.tmf.vp_index = vha->vp_idx; 2125 2126 START_SP_W_RETRIES(sp, rval, chip_gen, login_gen); 2127 2128 ql_dbg(ql_dbg_taskm, vha, 0x8006, 2129 "Async-marker hdl=%x loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d rval %d.\n", 2130 sp->handle, fcport->loop_id, fcport->d_id.b24, 2131 arg->modifier, arg->lun, sp->qpair->id, rval); 2132 2133 if (rval != QLA_SUCCESS) { 2134 ql_log(ql_log_warn, vha, 0x8031, 2135 "Marker IOCB send failure (%x).\n", rval); 2136 goto done_free_sp; 2137 } 2138 2139 wait_for_completion(&tm_iocb->u.tmf.comp); 2140 rval = tm_iocb->u.tmf.data; 2141 2142 if (rval != QLA_SUCCESS) { 2143 ql_log(ql_log_warn, vha, 0x8019, 2144 "Marker failed hdl=%x loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d rval %d.\n", 2145 sp->handle, fcport->loop_id, fcport->d_id.b24, 2146 arg->modifier, arg->lun, sp->qpair->id, rval); 2147 } 2148 2149 done_free_sp: 2150 /* ref: INIT */ 2151 kref_put(&sp->cmd_kref, qla2x00_sp_release); 2152 done: 2153 return rval; 2154 } 2155 2156 static void qla2x00_tmf_sp_done(srb_t *sp, int res) 2157 { 2158 struct srb_iocb *tmf = &sp->u.iocb_cmd; 2159 2160 if (res) 2161 tmf->u.tmf.data = res; 2162 complete(&tmf->u.tmf.comp); 2163 } 2164 2165 static int qla_tmf_wait(struct tmf_arg *arg) 2166 { 2167 /* there are only 2 types of error handling that reaches here, lun or target reset */ 2168 if (arg->flags & (TCF_LUN_RESET | TCF_ABORT_TASK_SET | TCF_CLEAR_TASK_SET)) 2169 return qla2x00_eh_wait_for_pending_commands(arg->vha, 2170 arg->fcport->d_id.b24, arg->lun, WAIT_LUN); 2171 else 2172 return qla2x00_eh_wait_for_pending_commands(arg->vha, 2173 arg->fcport->d_id.b24, arg->lun, WAIT_TARGET); 2174 } 2175 2176 static int 2177 __qla2x00_async_tm_cmd(struct tmf_arg *arg) 2178 { 2179 struct scsi_qla_host *vha = arg->vha; 2180 struct srb_iocb *tm_iocb; 2181 srb_t *sp; 2182 int rval = QLA_FUNCTION_FAILED; 2183 fc_port_t *fcport = arg->fcport; 2184 u32 chip_gen, login_gen; 2185 u64 jif; 2186 2187 if (TMF_NOT_READY(arg->fcport)) { 2188 ql_dbg(ql_dbg_taskm, vha, 0x8032, 2189 "FC port not ready for TM command loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d.\n", 2190 fcport->loop_id, fcport->d_id.b24, 2191 arg->modifier, arg->lun, arg->qpair->id); 2192 return QLA_SUSPENDED; 2193 } 2194 2195 chip_gen = vha->hw->chip_reset; 2196 login_gen = fcport->login_gen; 2197 2198 /* ref: INIT */ 2199 sp = qla2xxx_get_qpair_sp(vha, arg->qpair, fcport, GFP_KERNEL); 2200 if (!sp) 2201 goto done; 2202 2203 qla_vha_mark_busy(vha); 2204 sp->type = SRB_TM_CMD; 2205 sp->name = "tmf"; 2206 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha), 2207 qla2x00_tmf_sp_done); 2208 sp->u.iocb_cmd.timeout = qla2x00_tmf_iocb_timeout; 2209 2210 tm_iocb = &sp->u.iocb_cmd; 2211 init_completion(&tm_iocb->u.tmf.comp); 2212 tm_iocb->u.tmf.flags = arg->flags; 2213 tm_iocb->u.tmf.lun = arg->lun; 2214 2215 START_SP_W_RETRIES(sp, rval, chip_gen, login_gen); 2216 2217 ql_dbg(ql_dbg_taskm, vha, 0x802f, 2218 "Async-tmf hdl=%x loop-id=%x portid=%06x ctrl=%x lun=%lld qp=%d rval=%x.\n", 2219 sp->handle, fcport->loop_id, fcport->d_id.b24, 2220 arg->flags, arg->lun, sp->qpair->id, rval); 2221 2222 if (rval != QLA_SUCCESS) 2223 goto done_free_sp; 2224 wait_for_completion(&tm_iocb->u.tmf.comp); 2225 2226 rval = tm_iocb->u.tmf.data; 2227 2228 if (rval != QLA_SUCCESS) { 2229 ql_log(ql_log_warn, vha, 0x8030, 2230 "TM IOCB failed (%x).\n", rval); 2231 } 2232 2233 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) { 2234 jif = jiffies; 2235 if (qla_tmf_wait(arg)) { 2236 ql_log(ql_log_info, vha, 0x803e, 2237 "Waited %u ms Nexus=%ld:%06x:%llu.\n", 2238 jiffies_to_msecs(jiffies - jif), vha->host_no, 2239 fcport->d_id.b24, arg->lun); 2240 } 2241 2242 if (chip_gen == vha->hw->chip_reset && login_gen == fcport->login_gen) { 2243 rval = qla26xx_marker(arg); 2244 } else { 2245 ql_log(ql_log_info, vha, 0x803e, 2246 "Skip Marker due to disruption. Nexus=%ld:%06x:%llu.\n", 2247 vha->host_no, fcport->d_id.b24, arg->lun); 2248 rval = QLA_FUNCTION_FAILED; 2249 } 2250 } 2251 if (tm_iocb->u.tmf.data) 2252 rval = tm_iocb->u.tmf.data; 2253 2254 done_free_sp: 2255 /* ref: INIT */ 2256 kref_put(&sp->cmd_kref, qla2x00_sp_release); 2257 done: 2258 return rval; 2259 } 2260 2261 static void qla_put_tmf(struct tmf_arg *arg) 2262 { 2263 struct scsi_qla_host *vha = arg->vha; 2264 struct qla_hw_data *ha = vha->hw; 2265 unsigned long flags; 2266 2267 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 2268 ha->active_tmf--; 2269 list_del(&arg->tmf_elem); 2270 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 2271 } 2272 2273 static 2274 int qla_get_tmf(struct tmf_arg *arg) 2275 { 2276 struct scsi_qla_host *vha = arg->vha; 2277 struct qla_hw_data *ha = vha->hw; 2278 unsigned long flags; 2279 fc_port_t *fcport = arg->fcport; 2280 int rc = 0; 2281 struct tmf_arg *t; 2282 2283 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 2284 list_for_each_entry(t, &ha->tmf_active, tmf_elem) { 2285 if (t->fcport == arg->fcport && t->lun == arg->lun) { 2286 /* reject duplicate TMF */ 2287 ql_log(ql_log_warn, vha, 0x802c, 2288 "found duplicate TMF. Nexus=%ld:%06x:%llu.\n", 2289 vha->host_no, fcport->d_id.b24, arg->lun); 2290 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 2291 return -EINVAL; 2292 } 2293 } 2294 2295 list_add_tail(&arg->tmf_elem, &ha->tmf_pending); 2296 while (ha->active_tmf >= MAX_ACTIVE_TMF) { 2297 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 2298 2299 msleep(1); 2300 2301 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 2302 if (TMF_NOT_READY(fcport)) { 2303 ql_log(ql_log_warn, vha, 0x802c, 2304 "Unable to acquire TM resource due to disruption.\n"); 2305 rc = -EIO; 2306 break; 2307 } 2308 if (ha->active_tmf < MAX_ACTIVE_TMF && 2309 list_is_first(&arg->tmf_elem, &ha->tmf_pending)) 2310 break; 2311 } 2312 2313 list_del(&arg->tmf_elem); 2314 2315 if (!rc) { 2316 ha->active_tmf++; 2317 list_add_tail(&arg->tmf_elem, &ha->tmf_active); 2318 } 2319 2320 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 2321 2322 return rc; 2323 } 2324 2325 int 2326 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint64_t lun, 2327 uint32_t tag) 2328 { 2329 struct scsi_qla_host *vha = fcport->vha; 2330 struct tmf_arg a; 2331 int rval = QLA_SUCCESS; 2332 2333 if (TMF_NOT_READY(fcport)) 2334 return QLA_SUSPENDED; 2335 2336 a.vha = fcport->vha; 2337 a.fcport = fcport; 2338 a.lun = lun; 2339 a.flags = flags; 2340 INIT_LIST_HEAD(&a.tmf_elem); 2341 2342 if (flags & (TCF_LUN_RESET|TCF_ABORT_TASK_SET|TCF_CLEAR_TASK_SET|TCF_CLEAR_ACA)) { 2343 a.modifier = MK_SYNC_ID_LUN; 2344 } else { 2345 a.modifier = MK_SYNC_ID; 2346 } 2347 2348 if (qla_get_tmf(&a)) 2349 return QLA_FUNCTION_FAILED; 2350 2351 a.qpair = vha->hw->base_qpair; 2352 rval = __qla2x00_async_tm_cmd(&a); 2353 2354 qla_put_tmf(&a); 2355 return rval; 2356 } 2357 2358 int 2359 qla24xx_async_abort_command(srb_t *sp) 2360 { 2361 unsigned long flags = 0; 2362 2363 uint32_t handle; 2364 fc_port_t *fcport = sp->fcport; 2365 struct qla_qpair *qpair = sp->qpair; 2366 struct scsi_qla_host *vha = fcport->vha; 2367 struct req_que *req = qpair->req; 2368 2369 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 2370 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 2371 if (req->outstanding_cmds[handle] == sp) 2372 break; 2373 } 2374 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 2375 2376 if (handle == req->num_outstanding_cmds) { 2377 /* Command not found. */ 2378 return QLA_ERR_NOT_FOUND; 2379 } 2380 if (sp->type == SRB_FXIOCB_DCMD) 2381 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport, 2382 FXDISC_ABORT_IOCTL); 2383 2384 return qla24xx_async_abort_cmd(sp, true); 2385 } 2386 2387 static void 2388 qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 2389 { 2390 struct srb *sp; 2391 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 2392 ea->data[0]); 2393 2394 switch (ea->data[0]) { 2395 case MBS_COMMAND_COMPLETE: 2396 ql_dbg(ql_dbg_disc, vha, 0x2118, 2397 "%s %d %8phC post gpdb\n", 2398 __func__, __LINE__, ea->fcport->port_name); 2399 2400 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset; 2401 ea->fcport->logout_on_delete = 1; 2402 ea->fcport->nvme_prli_service_param = ea->iop[0]; 2403 if (ea->iop[0] & NVME_PRLI_SP_FIRST_BURST) 2404 ea->fcport->nvme_first_burst_size = 2405 (ea->iop[1] & 0xffff) * 512; 2406 else 2407 ea->fcport->nvme_first_burst_size = 0; 2408 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 2409 break; 2410 default: 2411 sp = ea->sp; 2412 ql_dbg(ql_dbg_disc, vha, 0x2118, 2413 "%s %d %8phC priority %s, fc4type %x prev try %s\n", 2414 __func__, __LINE__, ea->fcport->port_name, 2415 vha->hw->fc4_type_priority == FC4_PRIORITY_FCP ? 2416 "FCP" : "NVMe", ea->fcport->fc4_type, 2417 (sp->u.iocb_cmd.u.logio.flags & SRB_LOGIN_NVME_PRLI) ? 2418 "NVME" : "FCP"); 2419 2420 if (NVME_FCP_TARGET(ea->fcport)) { 2421 if (sp->u.iocb_cmd.u.logio.flags & SRB_LOGIN_NVME_PRLI) 2422 ea->fcport->do_prli_nvme = 0; 2423 else 2424 ea->fcport->do_prli_nvme = 1; 2425 } else { 2426 ea->fcport->do_prli_nvme = 0; 2427 } 2428 2429 if (N2N_TOPO(vha->hw)) { 2430 if (ea->fcport->n2n_link_reset_cnt == 2431 vha->hw->login_retry_count && 2432 ea->fcport->flags & FCF_FCSP_DEVICE) { 2433 /* remote authentication app just started */ 2434 ea->fcport->n2n_link_reset_cnt = 0; 2435 } 2436 2437 if (ea->fcport->n2n_link_reset_cnt < 2438 vha->hw->login_retry_count) { 2439 ea->fcport->n2n_link_reset_cnt++; 2440 vha->relogin_jif = jiffies + 2 * HZ; 2441 /* 2442 * PRLI failed. Reset link to kick start 2443 * state machine 2444 */ 2445 set_bit(N2N_LINK_RESET, &vha->dpc_flags); 2446 qla2xxx_wake_dpc(vha); 2447 } else { 2448 ql_log(ql_log_warn, vha, 0x2119, 2449 "%s %d %8phC Unable to reconnect\n", 2450 __func__, __LINE__, 2451 ea->fcport->port_name); 2452 } 2453 } else { 2454 /* 2455 * switch connect. login failed. Take connection down 2456 * and allow relogin to retrigger 2457 */ 2458 ea->fcport->flags &= ~FCF_ASYNC_SENT; 2459 ea->fcport->keep_nport_handle = 0; 2460 ea->fcport->logout_on_delete = 1; 2461 qlt_schedule_sess_for_deletion(ea->fcport); 2462 } 2463 break; 2464 } 2465 } 2466 2467 void 2468 qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 2469 { 2470 port_id_t cid; /* conflict Nport id */ 2471 u16 lid; 2472 struct fc_port *conflict_fcport; 2473 unsigned long flags; 2474 struct fc_port *fcport = ea->fcport; 2475 2476 ql_dbg(ql_dbg_disc, vha, 0xffff, 2477 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n", 2478 __func__, fcport->port_name, fcport->disc_state, 2479 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen, 2480 ea->sp->gen1, fcport->rscn_gen, 2481 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]); 2482 2483 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND) { 2484 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2485 "%s %d %8phC Remote is trying to login\n", 2486 __func__, __LINE__, fcport->port_name); 2487 /* 2488 * If we get here, there is port thats already logged in, 2489 * but it's state has not moved ahead. Recheck with FW on 2490 * what state it is in and proceed ahead 2491 */ 2492 if (!N2N_TOPO(vha->hw)) { 2493 fcport->fw_login_state = DSC_LS_PRLI_COMP; 2494 qla24xx_post_gpdb_work(vha, fcport, 0); 2495 } 2496 return; 2497 } 2498 2499 if (fcport->fw_login_state == DSC_LS_PRLI_PEND) { 2500 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2501 "%s %d %8phC Remote is trying to login\n", 2502 __func__, __LINE__, fcport->port_name); 2503 return; 2504 } 2505 2506 if ((fcport->disc_state == DSC_DELETE_PEND) || 2507 (fcport->disc_state == DSC_DELETED)) { 2508 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2509 return; 2510 } 2511 2512 if (ea->sp->gen2 != fcport->login_gen) { 2513 /* target side must have changed it. */ 2514 ql_dbg(ql_dbg_disc, vha, 0x20d3, 2515 "%s %8phC generation changed\n", 2516 __func__, fcport->port_name); 2517 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2518 return; 2519 } else if (ea->sp->gen1 != fcport->rscn_gen) { 2520 ql_dbg(ql_dbg_disc, vha, 0x20d3, 2521 "%s %8phC RSCN generation changed\n", 2522 __func__, fcport->port_name); 2523 qla_rscn_replay(fcport); 2524 qlt_schedule_sess_for_deletion(fcport); 2525 return; 2526 } 2527 2528 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 2529 ea->data[0]); 2530 2531 switch (ea->data[0]) { 2532 case MBS_COMMAND_COMPLETE: 2533 /* 2534 * Driver must validate login state - If PRLI not complete, 2535 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI 2536 * requests. 2537 */ 2538 if (vha->hw->flags.edif_enabled) { 2539 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 2540 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 2541 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset; 2542 ea->fcport->logout_on_delete = 1; 2543 ea->fcport->send_els_logo = 0; 2544 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP; 2545 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 2546 2547 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 2548 } else { 2549 if (NVME_TARGET(vha->hw, fcport)) { 2550 ql_dbg(ql_dbg_disc, vha, 0x2117, 2551 "%s %d %8phC post prli\n", 2552 __func__, __LINE__, fcport->port_name); 2553 qla24xx_post_prli_work(vha, fcport); 2554 } else { 2555 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2556 "%s %d %8phC LoopID 0x%x in use with %06x. post gpdb\n", 2557 __func__, __LINE__, fcport->port_name, 2558 fcport->loop_id, fcport->d_id.b24); 2559 2560 set_bit(fcport->loop_id, vha->hw->loop_id_map); 2561 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 2562 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 2563 fcport->logout_on_delete = 1; 2564 fcport->send_els_logo = 0; 2565 fcport->fw_login_state = DSC_LS_PRLI_COMP; 2566 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 2567 2568 qla24xx_post_gpdb_work(vha, fcport, 0); 2569 } 2570 } 2571 break; 2572 case MBS_COMMAND_ERROR: 2573 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n", 2574 __func__, __LINE__, ea->fcport->port_name, ea->data[1]); 2575 2576 qlt_schedule_sess_for_deletion(ea->fcport); 2577 break; 2578 case MBS_LOOP_ID_USED: 2579 /* data[1] = IO PARAM 1 = nport ID */ 2580 cid.b.domain = (ea->iop[1] >> 16) & 0xff; 2581 cid.b.area = (ea->iop[1] >> 8) & 0xff; 2582 cid.b.al_pa = ea->iop[1] & 0xff; 2583 cid.b.rsvd_1 = 0; 2584 2585 ql_dbg(ql_dbg_disc, vha, 0x20ec, 2586 "%s %d %8phC lid %#x in use with pid %06x post gnl\n", 2587 __func__, __LINE__, ea->fcport->port_name, 2588 ea->fcport->loop_id, cid.b24); 2589 2590 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 2591 ea->fcport->loop_id = FC_NO_LOOP_ID; 2592 qla24xx_post_gnl_work(vha, ea->fcport); 2593 break; 2594 case MBS_PORT_ID_USED: 2595 lid = ea->iop[1] & 0xffff; 2596 qlt_find_sess_invalidate_other(vha, 2597 wwn_to_u64(ea->fcport->port_name), 2598 ea->fcport->d_id, lid, &conflict_fcport); 2599 2600 if (conflict_fcport) { 2601 /* 2602 * Another fcport share the same loop_id/nport id. 2603 * Conflict fcport needs to finish cleanup before this 2604 * fcport can proceed to login. 2605 */ 2606 conflict_fcport->conflict = ea->fcport; 2607 ea->fcport->login_pause = 1; 2608 2609 ql_dbg(ql_dbg_disc, vha, 0x20ed, 2610 "%s %d %8phC NPortId %06x inuse with loopid 0x%x.\n", 2611 __func__, __LINE__, ea->fcport->port_name, 2612 ea->fcport->d_id.b24, lid); 2613 } else { 2614 ql_dbg(ql_dbg_disc, vha, 0x20ed, 2615 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n", 2616 __func__, __LINE__, ea->fcport->port_name, 2617 ea->fcport->d_id.b24, lid); 2618 2619 qla2x00_clear_loop_id(ea->fcport); 2620 set_bit(lid, vha->hw->loop_id_map); 2621 ea->fcport->loop_id = lid; 2622 ea->fcport->keep_nport_handle = 0; 2623 ea->fcport->logout_on_delete = 1; 2624 qlt_schedule_sess_for_deletion(ea->fcport); 2625 } 2626 break; 2627 } 2628 return; 2629 } 2630 2631 /****************************************************************************/ 2632 /* QLogic ISP2x00 Hardware Support Functions. */ 2633 /****************************************************************************/ 2634 2635 static int 2636 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) 2637 { 2638 int rval = QLA_SUCCESS; 2639 struct qla_hw_data *ha = vha->hw; 2640 uint32_t idc_major_ver, idc_minor_ver; 2641 uint16_t config[4]; 2642 2643 qla83xx_idc_lock(vha, 0); 2644 2645 /* SV: TODO: Assign initialization timeout from 2646 * flash-info / other param 2647 */ 2648 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; 2649 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; 2650 2651 /* Set our fcoe function presence */ 2652 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { 2653 ql_dbg(ql_dbg_p3p, vha, 0xb077, 2654 "Error while setting DRV-Presence.\n"); 2655 rval = QLA_FUNCTION_FAILED; 2656 goto exit; 2657 } 2658 2659 /* Decide the reset ownership */ 2660 qla83xx_reset_ownership(vha); 2661 2662 /* 2663 * On first protocol driver load: 2664 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery 2665 * register. 2666 * Others: Check compatibility with current IDC Major version. 2667 */ 2668 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); 2669 if (ha->flags.nic_core_reset_owner) { 2670 /* Set IDC Major version */ 2671 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; 2672 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); 2673 2674 /* Clearing IDC-Lock-Recovery register */ 2675 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); 2676 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { 2677 /* 2678 * Clear further IDC participation if we are not compatible with 2679 * the current IDC Major Version. 2680 */ 2681 ql_log(ql_log_warn, vha, 0xb07d, 2682 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", 2683 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); 2684 __qla83xx_clear_drv_presence(vha); 2685 rval = QLA_FUNCTION_FAILED; 2686 goto exit; 2687 } 2688 /* Each function sets its supported Minor version. */ 2689 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); 2690 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); 2691 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); 2692 2693 if (ha->flags.nic_core_reset_owner) { 2694 memset(config, 0, sizeof(config)); 2695 if (!qla81xx_get_port_config(vha, config)) 2696 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 2697 QLA8XXX_DEV_READY); 2698 } 2699 2700 rval = qla83xx_idc_state_handler(vha); 2701 2702 exit: 2703 qla83xx_idc_unlock(vha, 0); 2704 2705 return rval; 2706 } 2707 2708 void qla_enable_fce_trace(scsi_qla_host_t *vha) 2709 { 2710 int rval; 2711 struct qla_hw_data *ha = vha->hw; 2712 2713 if (ha->fce) { 2714 ha->flags.fce_enabled = 1; 2715 memset(ha->fce, 0, fce_calc_size(ha->fce_bufs)); 2716 rval = qla2x00_enable_fce_trace(vha, 2717 ha->fce_dma, ha->fce_bufs, ha->fce_mb, &ha->fce_bufs); 2718 2719 if (rval) { 2720 ql_log(ql_log_warn, vha, 0x8033, 2721 "Unable to reinitialize FCE (%d).\n", rval); 2722 ha->flags.fce_enabled = 0; 2723 } 2724 } 2725 } 2726 2727 static void qla_enable_eft_trace(scsi_qla_host_t *vha) 2728 { 2729 int rval; 2730 struct qla_hw_data *ha = vha->hw; 2731 2732 if (ha->eft) { 2733 memset(ha->eft, 0, EFT_SIZE); 2734 rval = qla2x00_enable_eft_trace(vha, ha->eft_dma, EFT_NUM_BUFFERS); 2735 2736 if (rval) { 2737 ql_log(ql_log_warn, vha, 0x8034, 2738 "Unable to reinitialize EFT (%d).\n", rval); 2739 } 2740 } 2741 } 2742 /* 2743 * qla2x00_initialize_adapter 2744 * Initialize board. 2745 * 2746 * Input: 2747 * ha = adapter block pointer. 2748 * 2749 * Returns: 2750 * 0 = success 2751 */ 2752 int 2753 qla2x00_initialize_adapter(scsi_qla_host_t *vha) 2754 { 2755 int rval; 2756 struct qla_hw_data *ha = vha->hw; 2757 struct req_que *req = ha->req_q_map[0]; 2758 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2759 2760 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats)); 2761 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat)); 2762 2763 /* Clear adapter flags. */ 2764 vha->flags.online = 0; 2765 ha->flags.chip_reset_done = 0; 2766 vha->flags.reset_active = 0; 2767 ha->flags.pci_channel_io_perm_failure = 0; 2768 ha->flags.eeh_busy = 0; 2769 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64(); 2770 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 2771 atomic_set(&vha->loop_state, LOOP_DOWN); 2772 vha->device_flags = DFLG_NO_CABLE; 2773 vha->dpc_flags = 0; 2774 vha->flags.management_server_logged_in = 0; 2775 vha->marker_needed = 0; 2776 ha->isp_abort_cnt = 0; 2777 ha->beacon_blink_led = 0; 2778 2779 set_bit(0, ha->req_qid_map); 2780 set_bit(0, ha->rsp_qid_map); 2781 2782 ql_dbg(ql_dbg_init, vha, 0x0040, 2783 "Configuring PCI space...\n"); 2784 rval = ha->isp_ops->pci_config(vha); 2785 if (rval) { 2786 ql_log(ql_log_warn, vha, 0x0044, 2787 "Unable to configure PCI space.\n"); 2788 return (rval); 2789 } 2790 2791 ha->isp_ops->reset_chip(vha); 2792 2793 /* Check for secure flash support */ 2794 if (IS_QLA28XX(ha) || IS_QLA29XX(ha)) { 2795 if (rd_reg_word(®->mailbox12) & BIT_0) 2796 ha->flags.secure_adapter = 1; 2797 ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n", 2798 (ha->flags.secure_adapter) ? "Yes" : "No"); 2799 } 2800 2801 2802 rval = qla2xxx_get_flash_info(vha); 2803 if (rval) { 2804 ql_log(ql_log_fatal, vha, 0x004f, 2805 "Unable to validate FLASH data.\n"); 2806 return rval; 2807 } 2808 2809 if (IS_QLA8044(ha)) { 2810 qla8044_read_reset_template(vha); 2811 2812 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0. 2813 * If DONRESET_BIT0 is set, drivers should not set dev_state 2814 * to NEED_RESET. But if NEED_RESET is set, drivers should 2815 * should honor the reset. */ 2816 if (ql2xdontresethba == 1) 2817 qla8044_set_idc_dontreset(vha); 2818 } 2819 2820 ha->isp_ops->get_flash_version(vha, req->ring); 2821 ql_dbg(ql_dbg_init, vha, 0x0061, 2822 "Configure NVRAM parameters...\n"); 2823 2824 /* Let priority default to FCP, can be overridden by nvram_config */ 2825 ha->fc4_type_priority = FC4_PRIORITY_FCP; 2826 2827 ha->isp_ops->nvram_config(vha); 2828 2829 if (ha->fc4_type_priority != FC4_PRIORITY_FCP && 2830 ha->fc4_type_priority != FC4_PRIORITY_NVME) 2831 ha->fc4_type_priority = FC4_PRIORITY_FCP; 2832 2833 ql_log(ql_log_info, vha, 0xffff, "FC4 priority set to %s\n", 2834 ha->fc4_type_priority == FC4_PRIORITY_FCP ? "FCP" : "NVMe"); 2835 2836 if (ha->flags.disable_serdes) { 2837 /* Mask HBA via NVRAM settings? */ 2838 ql_log(ql_log_info, vha, 0x0077, 2839 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name); 2840 return QLA_FUNCTION_FAILED; 2841 } 2842 2843 ql_dbg(ql_dbg_init, vha, 0x0078, 2844 "Verifying loaded RISC code...\n"); 2845 2846 /* If smartsan enabled then require fdmi and rdp enabled */ 2847 if (ql2xsmartsan) { 2848 ql2xfdmienable = 1; 2849 ql2xrdpenable = 1; 2850 } 2851 2852 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { 2853 rval = ha->isp_ops->chip_diag(vha); 2854 if (rval) 2855 return (rval); 2856 rval = qla2x00_setup_chip(vha); 2857 if (rval) 2858 return (rval); 2859 } 2860 2861 if (IS_QLA84XX(ha)) { 2862 ha->cs84xx = qla84xx_get_chip(vha); 2863 if (!ha->cs84xx) { 2864 ql_log(ql_log_warn, vha, 0x00d0, 2865 "Unable to configure ISP84XX.\n"); 2866 return QLA_FUNCTION_FAILED; 2867 } 2868 } 2869 2870 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha)) 2871 rval = qla2x00_init_rings(vha); 2872 2873 /* No point in continuing if firmware initialization failed. */ 2874 if (rval != QLA_SUCCESS) 2875 return rval; 2876 2877 ha->flags.chip_reset_done = 1; 2878 2879 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { 2880 /* Issue verify 84xx FW IOCB to complete 84xx initialization */ 2881 rval = qla84xx_init_chip(vha); 2882 if (rval != QLA_SUCCESS) { 2883 ql_log(ql_log_warn, vha, 0x00d4, 2884 "Unable to initialize ISP84XX.\n"); 2885 qla84xx_put_chip(vha); 2886 } 2887 } 2888 2889 /* Load the NIC Core f/w if we are the first protocol driver. */ 2890 if (IS_QLA8031(ha)) { 2891 rval = qla83xx_nic_core_fw_load(vha); 2892 if (rval) 2893 ql_log(ql_log_warn, vha, 0x0124, 2894 "Error in initializing NIC Core f/w.\n"); 2895 } 2896 2897 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) 2898 qla24xx_read_fcp_prio_cfg(vha); 2899 2900 if (IS_P3P_TYPE(ha)) 2901 qla82xx_set_driver_version(vha, QLA2XXX_VERSION); 2902 else 2903 qla25xx_set_driver_version(vha, QLA2XXX_VERSION); 2904 2905 return (rval); 2906 } 2907 2908 /** 2909 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. 2910 * @vha: HA context 2911 * 2912 * Returns 0 on success. 2913 */ 2914 int 2915 qla2100_pci_config(scsi_qla_host_t *vha) 2916 { 2917 uint16_t w; 2918 unsigned long flags; 2919 struct qla_hw_data *ha = vha->hw; 2920 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2921 2922 pci_set_master(ha->pdev); 2923 pci_try_set_mwi(ha->pdev); 2924 2925 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2926 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2927 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2928 2929 pci_disable_rom(ha->pdev); 2930 2931 /* Get PCI bus information. */ 2932 spin_lock_irqsave(&ha->hardware_lock, flags); 2933 ha->pci_attr = rd_reg_word(®->ctrl_status); 2934 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2935 2936 return QLA_SUCCESS; 2937 } 2938 2939 /** 2940 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. 2941 * @vha: HA context 2942 * 2943 * Returns 0 on success. 2944 */ 2945 int 2946 qla2300_pci_config(scsi_qla_host_t *vha) 2947 { 2948 uint16_t w; 2949 unsigned long flags = 0; 2950 uint32_t cnt; 2951 struct qla_hw_data *ha = vha->hw; 2952 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2953 2954 pci_set_master(ha->pdev); 2955 pci_try_set_mwi(ha->pdev); 2956 2957 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2958 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2959 2960 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2961 w &= ~PCI_COMMAND_INTX_DISABLE; 2962 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2963 2964 /* 2965 * If this is a 2300 card and not 2312, reset the 2966 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, 2967 * the 2310 also reports itself as a 2300 so we need to get the 2968 * fb revision level -- a 6 indicates it really is a 2300 and 2969 * not a 2310. 2970 */ 2971 if (IS_QLA2300(ha)) { 2972 spin_lock_irqsave(&ha->hardware_lock, flags); 2973 2974 /* Pause RISC. */ 2975 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2976 for (cnt = 0; cnt < 30000; cnt++) { 2977 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) 2978 break; 2979 2980 udelay(10); 2981 } 2982 2983 /* Select FPM registers. */ 2984 wrt_reg_word(®->ctrl_status, 0x20); 2985 rd_reg_word(®->ctrl_status); 2986 2987 /* Get the fb rev level */ 2988 ha->fb_rev = RD_FB_CMD_REG(ha, reg); 2989 2990 if (ha->fb_rev == FPM_2300) 2991 pci_clear_mwi(ha->pdev); 2992 2993 /* Deselect FPM registers. */ 2994 wrt_reg_word(®->ctrl_status, 0x0); 2995 rd_reg_word(®->ctrl_status); 2996 2997 /* Release RISC module. */ 2998 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2999 for (cnt = 0; cnt < 30000; cnt++) { 3000 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0) 3001 break; 3002 3003 udelay(10); 3004 } 3005 3006 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3007 } 3008 3009 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 3010 3011 pci_disable_rom(ha->pdev); 3012 3013 /* Get PCI bus information. */ 3014 spin_lock_irqsave(&ha->hardware_lock, flags); 3015 ha->pci_attr = rd_reg_word(®->ctrl_status); 3016 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3017 3018 return QLA_SUCCESS; 3019 } 3020 3021 /** 3022 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. 3023 * @vha: HA context 3024 * 3025 * Returns 0 on success. 3026 */ 3027 int 3028 qla24xx_pci_config(scsi_qla_host_t *vha) 3029 { 3030 uint16_t w; 3031 unsigned long flags = 0; 3032 struct qla_hw_data *ha = vha->hw; 3033 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 3034 3035 pci_set_master(ha->pdev); 3036 pci_try_set_mwi(ha->pdev); 3037 3038 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 3039 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 3040 w &= ~PCI_COMMAND_INTX_DISABLE; 3041 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 3042 3043 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 3044 3045 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 3046 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) 3047 pcix_set_mmrbc(ha->pdev, 2048); 3048 3049 /* PCIe -- adjust Maximum Read Request Size (2048). */ 3050 if (pci_is_pcie(ha->pdev)) 3051 pcie_set_readrq(ha->pdev, 4096); 3052 3053 pci_disable_rom(ha->pdev); 3054 3055 ha->chip_revision = ha->pdev->revision; 3056 3057 /* Get PCI bus information. */ 3058 spin_lock_irqsave(&ha->hardware_lock, flags); 3059 ha->pci_attr = rd_reg_dword(®->ctrl_status); 3060 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3061 3062 return QLA_SUCCESS; 3063 } 3064 3065 /** 3066 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. 3067 * @vha: HA context 3068 * 3069 * Returns 0 on success. 3070 */ 3071 int 3072 qla25xx_pci_config(scsi_qla_host_t *vha) 3073 { 3074 uint16_t w; 3075 struct qla_hw_data *ha = vha->hw; 3076 3077 pci_set_master(ha->pdev); 3078 pci_try_set_mwi(ha->pdev); 3079 3080 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 3081 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 3082 w &= ~PCI_COMMAND_INTX_DISABLE; 3083 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 3084 3085 /* PCIe -- adjust Maximum Read Request Size (2048). */ 3086 if (pci_is_pcie(ha->pdev)) 3087 pcie_set_readrq(ha->pdev, 4096); 3088 3089 pci_disable_rom(ha->pdev); 3090 3091 ha->chip_revision = ha->pdev->revision; 3092 3093 return QLA_SUCCESS; 3094 } 3095 3096 /** 3097 * qla2x00_isp_firmware() - Choose firmware image. 3098 * @vha: HA context 3099 * 3100 * Returns 0 on success. 3101 */ 3102 static int 3103 qla2x00_isp_firmware(scsi_qla_host_t *vha) 3104 { 3105 int rval; 3106 uint16_t loop_id, topo, sw_cap; 3107 uint8_t domain, area, al_pa; 3108 struct qla_hw_data *ha = vha->hw; 3109 3110 /* Assume loading risc code */ 3111 rval = QLA_FUNCTION_FAILED; 3112 3113 if (ha->flags.disable_risc_code_load) { 3114 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); 3115 3116 /* Verify checksum of loaded RISC code. */ 3117 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); 3118 if (rval == QLA_SUCCESS) { 3119 /* And, verify we are not in ROM code. */ 3120 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, 3121 &area, &domain, &topo, &sw_cap); 3122 } 3123 } 3124 3125 if (rval) 3126 ql_dbg(ql_dbg_init, vha, 0x007a, 3127 "**** Load RISC code ****.\n"); 3128 3129 return (rval); 3130 } 3131 3132 /** 3133 * qla2x00_reset_chip() - Reset ISP chip. 3134 * @vha: HA context 3135 * 3136 * Returns 0 on success. 3137 */ 3138 int 3139 qla2x00_reset_chip(scsi_qla_host_t *vha) 3140 { 3141 unsigned long flags = 0; 3142 struct qla_hw_data *ha = vha->hw; 3143 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3144 uint32_t cnt; 3145 uint16_t cmd; 3146 int rval = QLA_FUNCTION_FAILED; 3147 3148 if (unlikely(pci_channel_offline(ha->pdev))) 3149 return rval; 3150 3151 ha->isp_ops->disable_intrs(ha); 3152 3153 spin_lock_irqsave(&ha->hardware_lock, flags); 3154 3155 /* Turn off master enable */ 3156 cmd = 0; 3157 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); 3158 cmd &= ~PCI_COMMAND_MASTER; 3159 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 3160 3161 if (!IS_QLA2100(ha)) { 3162 /* Pause RISC. */ 3163 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 3164 if (IS_QLA2200(ha) || IS_QLA2300(ha)) { 3165 for (cnt = 0; cnt < 30000; cnt++) { 3166 if ((rd_reg_word(®->hccr) & 3167 HCCR_RISC_PAUSE) != 0) 3168 break; 3169 udelay(100); 3170 } 3171 } else { 3172 rd_reg_word(®->hccr); /* PCI Posting. */ 3173 udelay(10); 3174 } 3175 3176 /* Select FPM registers. */ 3177 wrt_reg_word(®->ctrl_status, 0x20); 3178 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 3179 3180 /* FPM Soft Reset. */ 3181 wrt_reg_word(®->fpm_diag_config, 0x100); 3182 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */ 3183 3184 /* Toggle Fpm Reset. */ 3185 if (!IS_QLA2200(ha)) { 3186 wrt_reg_word(®->fpm_diag_config, 0x0); 3187 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */ 3188 } 3189 3190 /* Select frame buffer registers. */ 3191 wrt_reg_word(®->ctrl_status, 0x10); 3192 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 3193 3194 /* Reset frame buffer FIFOs. */ 3195 if (IS_QLA2200(ha)) { 3196 WRT_FB_CMD_REG(ha, reg, 0xa000); 3197 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ 3198 } else { 3199 WRT_FB_CMD_REG(ha, reg, 0x00fc); 3200 3201 /* Read back fb_cmd until zero or 3 seconds max */ 3202 for (cnt = 0; cnt < 3000; cnt++) { 3203 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) 3204 break; 3205 udelay(100); 3206 } 3207 } 3208 3209 /* Select RISC module registers. */ 3210 wrt_reg_word(®->ctrl_status, 0); 3211 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 3212 3213 /* Reset RISC processor. */ 3214 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 3215 rd_reg_word(®->hccr); /* PCI Posting. */ 3216 3217 /* Release RISC processor. */ 3218 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 3219 rd_reg_word(®->hccr); /* PCI Posting. */ 3220 } 3221 3222 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT); 3223 wrt_reg_word(®->hccr, HCCR_CLR_HOST_INT); 3224 3225 /* Reset ISP chip. */ 3226 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 3227 3228 /* Wait for RISC to recover from reset. */ 3229 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 3230 /* 3231 * It is necessary to for a delay here since the card doesn't 3232 * respond to PCI reads during a reset. On some architectures 3233 * this will result in an MCA. 3234 */ 3235 udelay(20); 3236 for (cnt = 30000; cnt; cnt--) { 3237 if ((rd_reg_word(®->ctrl_status) & 3238 CSR_ISP_SOFT_RESET) == 0) 3239 break; 3240 udelay(100); 3241 } 3242 } else 3243 udelay(10); 3244 3245 /* Reset RISC processor. */ 3246 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 3247 3248 wrt_reg_word(®->semaphore, 0); 3249 3250 /* Release RISC processor. */ 3251 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 3252 rd_reg_word(®->hccr); /* PCI Posting. */ 3253 3254 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 3255 for (cnt = 0; cnt < 30000; cnt++) { 3256 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) 3257 break; 3258 3259 udelay(100); 3260 } 3261 } else 3262 udelay(100); 3263 3264 /* Turn on master enable */ 3265 cmd |= PCI_COMMAND_MASTER; 3266 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 3267 3268 /* Disable RISC pause on FPM parity error. */ 3269 if (!IS_QLA2100(ha)) { 3270 wrt_reg_word(®->hccr, HCCR_DISABLE_PARITY_PAUSE); 3271 rd_reg_word(®->hccr); /* PCI Posting. */ 3272 } 3273 3274 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3275 3276 return QLA_SUCCESS; 3277 } 3278 3279 /** 3280 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. 3281 * @vha: HA context 3282 * 3283 * Returns 0 on success. 3284 */ 3285 static int 3286 qla81xx_reset_mpi(scsi_qla_host_t *vha) 3287 { 3288 uint16_t mb[4] = {0x1010, 0, 1, 0}; 3289 3290 if (!IS_QLA81XX(vha->hw)) 3291 return QLA_SUCCESS; 3292 3293 return qla81xx_write_mpi_register(vha, mb); 3294 } 3295 3296 /* save MB regs at start of day for fw dump */ 3297 static void 3298 qla_save_mbregs(scsi_qla_host_t *vha) 3299 { 3300 struct qla_hw_data *ha = vha->hw; 3301 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 3302 __le16 __iomem *mbptr = ®->mailbox0; 3303 int i; 3304 u16 *mb = ha->mbregs; 3305 3306 if ((!IS_QLA27XX(ha) && !IS_QLA28XX(ha) && !IS_QLA29XX(ha)) || 3307 vha->flags.init_done) 3308 return; 3309 3310 for (i = 0; i < 32; i++) { 3311 mb[i] = rd_reg_word(mbptr); 3312 mbptr++; 3313 } 3314 3315 ql_log(ql_log_info, vha, 0x1015, 3316 "mb[0-7] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 3317 mb[0], mb[1], mb[2], mb[3], mb[4], mb[5], mb[6], mb[7]); 3318 ql_log(ql_log_info, vha, 0x1015, 3319 "mb[8-15] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 3320 mb[8], mb[9], mb[10], mb[11], mb[12], mb[13], mb[14], mb[15]); 3321 ql_log(ql_log_info, vha, 0x1015, 3322 "mb[16-23] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 3323 mb[16], mb[17], mb[18], mb[19], mb[20], mb[21], mb[22], mb[23]); 3324 ql_log(ql_log_info, vha, 0x1015, 3325 "mb[24-31] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 3326 mb[24], mb[25], mb[26], mb[27], mb[28], mb[29], mb[30], mb[31]); 3327 } 3328 3329 /** 3330 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. 3331 * @vha: HA context 3332 * 3333 * Returns 0 on success. 3334 */ 3335 static inline int 3336 qla24xx_reset_risc(scsi_qla_host_t *vha) 3337 { 3338 unsigned long flags = 0; 3339 struct qla_hw_data *ha = vha->hw; 3340 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 3341 uint32_t cnt; 3342 uint16_t wd; 3343 static int abts_cnt; /* ISP abort retry counts */ 3344 int rval = QLA_SUCCESS; 3345 3346 spin_lock_irqsave(&ha->hardware_lock, flags); 3347 3348 /* Reset RISC. */ 3349 wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 3350 for (cnt = 0; cnt < 30000; cnt++) { 3351 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 3352 break; 3353 3354 udelay(10); 3355 } 3356 3357 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)) 3358 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); 3359 3360 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e, 3361 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n", 3362 rd_reg_dword(®->hccr), 3363 rd_reg_dword(®->ctrl_status), 3364 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)); 3365 3366 wrt_reg_dword(®->ctrl_status, 3367 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 3368 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 3369 3370 udelay(100); 3371 3372 /* Wait for firmware to complete NVRAM accesses. */ 3373 rd_reg_word(®->mailbox0); 3374 for (cnt = 10000; rd_reg_word(®->mailbox0) != 0 && 3375 rval == QLA_SUCCESS; cnt--) { 3376 barrier(); 3377 if (cnt) 3378 udelay(5); 3379 else 3380 rval = QLA_FUNCTION_TIMEOUT; 3381 } 3382 3383 if (rval == QLA_SUCCESS) 3384 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags); 3385 3386 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f, 3387 "HCCR: 0x%x, MailBox0 Status 0x%x\n", 3388 rd_reg_dword(®->hccr), 3389 rd_reg_word(®->mailbox0)); 3390 3391 /* Wait for soft-reset to complete. */ 3392 rd_reg_dword(®->ctrl_status); 3393 for (cnt = 0; cnt < 60; cnt++) { 3394 barrier(); 3395 if ((rd_reg_dword(®->ctrl_status) & 3396 CSRX_ISP_SOFT_RESET) == 0) 3397 break; 3398 3399 udelay(5); 3400 } 3401 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) 3402 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags); 3403 3404 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d, 3405 "HCCR: 0x%x, Soft Reset status: 0x%x\n", 3406 rd_reg_dword(®->hccr), 3407 rd_reg_dword(®->ctrl_status)); 3408 3409 /* If required, do an MPI FW reset now */ 3410 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { 3411 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { 3412 if (++abts_cnt < 5) { 3413 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3414 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); 3415 } else { 3416 /* 3417 * We exhausted the ISP abort retries. We have to 3418 * set the board offline. 3419 */ 3420 abts_cnt = 0; 3421 vha->flags.online = 0; 3422 } 3423 } 3424 } 3425 3426 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 3427 rd_reg_dword(®->hccr); 3428 3429 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 3430 rd_reg_dword(®->hccr); 3431 3432 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET); 3433 mdelay(10); 3434 rd_reg_dword(®->hccr); 3435 3436 wd = rd_reg_word(®->mailbox0); 3437 for (cnt = 300; wd != 0 && rval == QLA_SUCCESS; cnt--) { 3438 barrier(); 3439 if (cnt) { 3440 mdelay(1); 3441 wd = rd_reg_word(®->mailbox0); 3442 } else { 3443 rval = QLA_FUNCTION_TIMEOUT; 3444 3445 ql_log(ql_log_warn, vha, 0x015e, 3446 "RISC reset timeout\n"); 3447 } 3448 } 3449 3450 if (rval == QLA_SUCCESS) 3451 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); 3452 3453 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e, 3454 "Host Risc 0x%x, mailbox0 0x%x\n", 3455 rd_reg_dword(®->hccr), 3456 rd_reg_word(®->mailbox0)); 3457 3458 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3459 3460 qla_save_mbregs(vha); 3461 3462 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f, 3463 "Driver in %s mode\n", 3464 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling"); 3465 3466 if (IS_NOPOLLING_TYPE(ha)) 3467 ha->isp_ops->enable_intrs(ha); 3468 3469 return rval; 3470 } 3471 3472 static void 3473 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) 3474 { 3475 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 3476 3477 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 3478 *data = rd_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET); 3479 } 3480 3481 static void 3482 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) 3483 { 3484 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 3485 3486 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 3487 wrt_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET, data); 3488 } 3489 3490 static void 3491 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) 3492 { 3493 uint32_t wd32 = 0; 3494 uint delta_msec = 100; 3495 uint elapsed_msec = 0; 3496 uint timeout_msec; 3497 ulong n; 3498 3499 if (vha->hw->pdev->subsystem_device != 0x0175 && 3500 vha->hw->pdev->subsystem_device != 0x0240) 3501 return; 3502 3503 wrt_reg_dword(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE); 3504 udelay(100); 3505 3506 attempt: 3507 timeout_msec = TIMEOUT_SEMAPHORE; 3508 n = timeout_msec / delta_msec; 3509 while (n--) { 3510 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); 3511 qla25xx_read_risc_sema_reg(vha, &wd32); 3512 if (wd32 & RISC_SEMAPHORE) 3513 break; 3514 msleep(delta_msec); 3515 elapsed_msec += delta_msec; 3516 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 3517 goto force; 3518 } 3519 3520 if (!(wd32 & RISC_SEMAPHORE)) 3521 goto force; 3522 3523 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 3524 goto acquired; 3525 3526 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); 3527 timeout_msec = TIMEOUT_SEMAPHORE_FORCE; 3528 n = timeout_msec / delta_msec; 3529 while (n--) { 3530 qla25xx_read_risc_sema_reg(vha, &wd32); 3531 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 3532 break; 3533 msleep(delta_msec); 3534 elapsed_msec += delta_msec; 3535 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 3536 goto force; 3537 } 3538 3539 if (wd32 & RISC_SEMAPHORE_FORCE) 3540 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); 3541 3542 goto attempt; 3543 3544 force: 3545 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); 3546 3547 acquired: 3548 return; 3549 } 3550 3551 /** 3552 * qla24xx_reset_chip() - Reset ISP24xx chip. 3553 * @vha: HA context 3554 * 3555 * Returns 0 on success. 3556 */ 3557 int 3558 qla24xx_reset_chip(scsi_qla_host_t *vha) 3559 { 3560 struct qla_hw_data *ha = vha->hw; 3561 int rval = QLA_FUNCTION_FAILED; 3562 3563 if (pci_channel_offline(ha->pdev) && 3564 ha->flags.pci_channel_io_perm_failure) { 3565 return rval; 3566 } 3567 3568 ha->isp_ops->disable_intrs(ha); 3569 3570 qla25xx_manipulate_risc_semaphore(vha); 3571 3572 /* Perform RISC reset. */ 3573 rval = qla24xx_reset_risc(vha); 3574 3575 return rval; 3576 } 3577 3578 /** 3579 * qla2x00_chip_diag() - Test chip for proper operation. 3580 * @vha: HA context 3581 * 3582 * Returns 0 on success. 3583 */ 3584 int 3585 qla2x00_chip_diag(scsi_qla_host_t *vha) 3586 { 3587 int rval; 3588 struct qla_hw_data *ha = vha->hw; 3589 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3590 unsigned long flags = 0; 3591 uint16_t data; 3592 uint32_t cnt; 3593 uint16_t mb[5]; 3594 struct req_que *req = ha->req_q_map[0]; 3595 3596 /* Assume a failed state */ 3597 rval = QLA_FUNCTION_FAILED; 3598 3599 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n", 3600 ®->flash_address); 3601 3602 spin_lock_irqsave(&ha->hardware_lock, flags); 3603 3604 /* Reset ISP chip. */ 3605 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 3606 3607 /* 3608 * We need to have a delay here since the card will not respond while 3609 * in reset causing an MCA on some architectures. 3610 */ 3611 udelay(20); 3612 data = qla2x00_debounce_register(®->ctrl_status); 3613 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { 3614 udelay(5); 3615 data = rd_reg_word(®->ctrl_status); 3616 barrier(); 3617 } 3618 3619 if (!cnt) 3620 goto chip_diag_failed; 3621 3622 ql_dbg(ql_dbg_init, vha, 0x007c, 3623 "Reset register cleared by chip reset.\n"); 3624 3625 /* Reset RISC processor. */ 3626 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 3627 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 3628 3629 /* Workaround for QLA2312 PCI parity error */ 3630 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 3631 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); 3632 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { 3633 udelay(5); 3634 data = RD_MAILBOX_REG(ha, reg, 0); 3635 barrier(); 3636 } 3637 } else 3638 udelay(10); 3639 3640 if (!cnt) 3641 goto chip_diag_failed; 3642 3643 /* Check product ID of chip */ 3644 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n"); 3645 3646 mb[1] = RD_MAILBOX_REG(ha, reg, 1); 3647 mb[2] = RD_MAILBOX_REG(ha, reg, 2); 3648 mb[3] = RD_MAILBOX_REG(ha, reg, 3); 3649 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); 3650 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || 3651 mb[3] != PROD_ID_3) { 3652 ql_log(ql_log_warn, vha, 0x0062, 3653 "Wrong product ID = 0x%x,0x%x,0x%x.\n", 3654 mb[1], mb[2], mb[3]); 3655 3656 goto chip_diag_failed; 3657 } 3658 ha->product_id[0] = mb[1]; 3659 ha->product_id[1] = mb[2]; 3660 ha->product_id[2] = mb[3]; 3661 ha->product_id[3] = mb[4]; 3662 3663 /* Adjust fw RISC transfer size */ 3664 if (req->length > 1024) 3665 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; 3666 else 3667 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 3668 req->length; 3669 3670 if (IS_QLA2200(ha) && 3671 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { 3672 /* Limit firmware transfer size with a 2200A */ 3673 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); 3674 3675 ha->device_type |= DT_ISP2200A; 3676 ha->fw_transfer_size = 128; 3677 } 3678 3679 /* Wrap Incoming Mailboxes Test. */ 3680 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3681 3682 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); 3683 rval = qla2x00_mbx_reg_test(vha); 3684 if (rval) 3685 ql_log(ql_log_warn, vha, 0x0080, 3686 "Failed mailbox send register test.\n"); 3687 else 3688 /* Flag a successful rval */ 3689 rval = QLA_SUCCESS; 3690 spin_lock_irqsave(&ha->hardware_lock, flags); 3691 3692 chip_diag_failed: 3693 if (rval) 3694 ql_log(ql_log_info, vha, 0x0081, 3695 "Chip diagnostics **** FAILED ****.\n"); 3696 3697 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3698 3699 return (rval); 3700 } 3701 3702 /** 3703 * qla24xx_chip_diag() - Test ISP24xx for proper operation. 3704 * @vha: HA context 3705 * 3706 * Returns 0 on success. 3707 */ 3708 int 3709 qla24xx_chip_diag(scsi_qla_host_t *vha) 3710 { 3711 int rval; 3712 struct qla_hw_data *ha = vha->hw; 3713 struct req_que *req = ha->req_q_map[0]; 3714 3715 if (IS_P3P_TYPE(ha)) 3716 return QLA_SUCCESS; 3717 3718 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; 3719 3720 rval = qla2x00_mbx_reg_test(vha); 3721 if (rval) { 3722 ql_log(ql_log_warn, vha, 0x0082, 3723 "Failed mailbox send register test.\n"); 3724 } else { 3725 /* Flag a successful rval */ 3726 rval = QLA_SUCCESS; 3727 } 3728 3729 return rval; 3730 } 3731 3732 int qla2x00_alloc_fce_trace(scsi_qla_host_t *vha) 3733 { 3734 dma_addr_t tc_dma; 3735 void *tc; 3736 struct qla_hw_data *ha = vha->hw; 3737 3738 if (!IS_FWI2_CAPABLE(ha)) 3739 return -EINVAL; 3740 3741 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 3742 !IS_QLA27XX(ha) && !IS_QLA28XX(ha) && !IS_QLA29XX(ha)) 3743 return -EINVAL; 3744 3745 if (ha->fce) { 3746 ql_dbg(ql_dbg_init, vha, 0x00bd, 3747 "%s: FCE Mem is already allocated.\n", 3748 __func__); 3749 return -EIO; 3750 } 3751 3752 /* Allocate memory for Fibre Channel Event Buffer. */ 3753 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, 3754 GFP_KERNEL); 3755 if (!tc) { 3756 ql_log(ql_log_warn, vha, 0x00be, 3757 "Unable to allocate (%d KB) for FCE.\n", 3758 FCE_SIZE / 1024); 3759 return -ENOMEM; 3760 } 3761 3762 ql_dbg(ql_dbg_init, vha, 0x00c0, 3763 "Allocated (%d KB) for FCE...\n", FCE_SIZE / 1024); 3764 3765 ha->fce_dma = tc_dma; 3766 ha->fce = tc; 3767 ha->fce_bufs = FCE_NUM_BUFFERS; 3768 return 0; 3769 } 3770 3771 void qla2x00_free_fce_trace(struct qla_hw_data *ha) 3772 { 3773 void *fce; 3774 dma_addr_t fce_dma; 3775 unsigned long flags; 3776 3777 /* 3778 * Unpublish ha->fce under hardware_lock so a firmware dump in 3779 * progress (which reads ha->fce under the same lock) cannot race 3780 * with the buffer being freed. 3781 */ 3782 spin_lock_irqsave(&ha->hardware_lock, flags); 3783 if (!ha->fce) { 3784 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3785 return; 3786 } 3787 fce = ha->fce; 3788 fce_dma = ha->fce_dma; 3789 ha->fce = NULL; 3790 ha->fce_dma = 0; 3791 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3792 3793 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, fce, fce_dma); 3794 } 3795 3796 static void 3797 qla2x00_alloc_eft_trace(scsi_qla_host_t *vha) 3798 { 3799 dma_addr_t tc_dma; 3800 void *tc; 3801 struct qla_hw_data *ha = vha->hw; 3802 3803 if (!IS_FWI2_CAPABLE(ha)) 3804 return; 3805 3806 if (ha->eft) { 3807 ql_dbg(ql_dbg_init, vha, 0x00bd, 3808 "%s: EFT Mem is already allocated.\n", 3809 __func__); 3810 return; 3811 } 3812 3813 /* Allocate memory for Extended Trace Buffer. */ 3814 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, 3815 GFP_KERNEL); 3816 if (!tc) { 3817 ql_log(ql_log_warn, vha, 0x00c1, 3818 "Unable to allocate (%d KB) for EFT.\n", 3819 EFT_SIZE / 1024); 3820 return; 3821 } 3822 3823 ql_dbg(ql_dbg_init, vha, 0x00c3, 3824 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); 3825 3826 ha->eft_dma = tc_dma; 3827 ha->eft = tc; 3828 } 3829 3830 void 3831 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) 3832 { 3833 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, 3834 eft_size, fce_size, mq_size; 3835 struct qla_hw_data *ha = vha->hw; 3836 struct req_que *req = ha->req_q_map[0]; 3837 struct rsp_que *rsp = ha->rsp_q_map[0]; 3838 struct qla2xxx_fw_dump *fw_dump, *prev_fw_dump; 3839 void *prev_mpi_fw_dump; 3840 size_t req_entry_size = qla_req_entry_size(ha); 3841 size_t rsp_entry_size = qla_rsp_entry_size(ha); 3842 3843 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; 3844 req_q_size = rsp_q_size = 0; 3845 3846 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3847 fixed_size = sizeof(struct qla2100_fw_dump); 3848 } else if (IS_QLA23XX(ha)) { 3849 fixed_size = offsetof(struct qla2300_fw_dump, data_ram); 3850 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 3851 sizeof(uint16_t); 3852 } else if (IS_FWI2_CAPABLE(ha)) { 3853 if (IS_QLA83XX(ha)) 3854 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); 3855 else if (IS_QLA81XX(ha)) 3856 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); 3857 else if (IS_QLA25XX(ha)) 3858 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); 3859 else 3860 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); 3861 3862 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 3863 sizeof(uint32_t); 3864 if (ha->mqenable) { 3865 if (!IS_QLA83XX(ha)) 3866 mq_size = sizeof(struct qla2xxx_mq_chain); 3867 /* 3868 * Allocate maximum buffer size for all queues - Q0. 3869 * Resizing must be done at end-of-dump processing. 3870 */ 3871 mq_size += (ha->max_req_queues - 1) * 3872 (req->length * req_entry_size); 3873 mq_size += (ha->max_rsp_queues - 1) * 3874 (rsp->length * rsp_entry_size); 3875 } 3876 if (ha->tgt.atio_ring) 3877 mq_size += ha->tgt.atio_q_length * sizeof(request_t); 3878 3879 if (ha->fce) { 3880 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; 3881 ha->flags.fce_dump_buf_alloced = 1; 3882 } 3883 qla2x00_alloc_eft_trace(vha); 3884 if (ha->eft) 3885 eft_size = EFT_SIZE; 3886 } 3887 3888 if (IS_QLA27XX(ha) || IS_QLA28XX(ha) || IS_QLA29XX(ha)) { 3889 struct fwdt *fwdt = ha->fwdt; 3890 uint j; 3891 3892 for (j = 0; j < 2; j++, fwdt++) { 3893 if (!fwdt->template) { 3894 ql_dbg(ql_dbg_init, vha, 0x00ba, 3895 "-> fwdt%u no template\n", j); 3896 continue; 3897 } 3898 ql_dbg(ql_dbg_init, vha, 0x00fa, 3899 "-> fwdt%u calculating fwdump size...\n", j); 3900 fwdt->dump_size = qla27xx_fwdt_calculate_dump_size( 3901 vha, fwdt->template); 3902 ql_dbg(ql_dbg_init, vha, 0x00fa, 3903 "-> fwdt%u calculated fwdump size = %#lx bytes\n", 3904 j, fwdt->dump_size); 3905 dump_size += fwdt->dump_size; 3906 } 3907 /* Add space for spare MPI fw dump. */ 3908 dump_size += ha->fwdt[1].dump_size; 3909 } else { 3910 req_q_size = req->length * req_entry_size; 3911 rsp_q_size = rsp->length * rsp_entry_size; 3912 dump_size = offsetof(struct qla2xxx_fw_dump, isp); 3913 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size 3914 + eft_size; 3915 ha->chain_offset = dump_size; 3916 dump_size += mq_size + fce_size; 3917 if (ha->exchoffld_buf) 3918 dump_size += sizeof(struct qla2xxx_offld_chain) + 3919 ha->exchoffld_size; 3920 if (ha->exlogin_buf) 3921 dump_size += sizeof(struct qla2xxx_offld_chain) + 3922 ha->exlogin_size; 3923 } 3924 3925 ql_dbg(ql_dbg_init, vha, 0x00c5, 3926 "%s dump_size %d fw_dump_len %d fw_dump_alloc_len %d\n", 3927 __func__, dump_size, ha->fw_dump_len, ha->fw_dump_alloc_len); 3928 3929 if (!ha->fw_dump_len || dump_size > ha->fw_dump_alloc_len) { 3930 fw_dump = vmalloc(dump_size); 3931 if (!fw_dump) { 3932 ql_log(ql_log_warn, vha, 0x00c4, 3933 "Unable to allocate (%d KB) for firmware dump.\n", 3934 dump_size / 1024); 3935 } else { 3936 mutex_lock(&ha->optrom_mutex); 3937 3938 if (ha->fw_dumped || ha->mpi_fw_dumped) { 3939 prev_fw_dump = ha->fw_dump; 3940 3941 if (ha->fw_dumped) 3942 memcpy(fw_dump, prev_fw_dump, 3943 ha->fw_dump_len); 3944 3945 if (IS_QLA27XX(ha) || IS_QLA28XX(ha) || 3946 IS_QLA29XX(ha)) { 3947 prev_mpi_fw_dump = ha->mpi_fw_dump; 3948 ha->mpi_fw_dump = (char *)fw_dump + 3949 ha->fwdt[0].dump_size; 3950 3951 if (ha->mpi_fw_dumped) 3952 memcpy(ha->mpi_fw_dump, 3953 prev_mpi_fw_dump, 3954 ha->mpi_fw_dump_len); 3955 } 3956 vfree(prev_fw_dump); 3957 ha->fw_dump = fw_dump; 3958 ha->fw_dump_alloc_len = dump_size; 3959 ql_dbg(ql_dbg_init, vha, 0x00c5, 3960 "Re-Allocated (%d KB) and save firmware dump.\n", 3961 dump_size / 1024); 3962 } else { 3963 vfree(ha->fw_dump); 3964 ha->fw_dump = fw_dump; 3965 3966 ha->fw_dump_len = ha->fw_dump_alloc_len = 3967 dump_size; 3968 ql_dbg(ql_dbg_init, vha, 0x00c5, 3969 "Allocated (%d KB) for firmware dump.\n", 3970 dump_size / 1024); 3971 3972 if (IS_QLA27XX(ha) || IS_QLA28XX(ha) || 3973 IS_QLA29XX(ha)) { 3974 ha->mpi_fw_dump = (char *)fw_dump + 3975 ha->fwdt[0].dump_size; 3976 mutex_unlock(&ha->optrom_mutex); 3977 return; 3978 } 3979 3980 ha->fw_dump->signature[0] = 'Q'; 3981 ha->fw_dump->signature[1] = 'L'; 3982 ha->fw_dump->signature[2] = 'G'; 3983 ha->fw_dump->signature[3] = 'C'; 3984 ha->fw_dump->version = htonl(1); 3985 3986 ha->fw_dump->fixed_size = htonl(fixed_size); 3987 ha->fw_dump->mem_size = htonl(mem_size); 3988 ha->fw_dump->req_q_size = htonl(req_q_size); 3989 ha->fw_dump->rsp_q_size = htonl(rsp_q_size); 3990 3991 ha->fw_dump->eft_size = htonl(eft_size); 3992 ha->fw_dump->eft_addr_l = 3993 htonl(LSD(ha->eft_dma)); 3994 ha->fw_dump->eft_addr_h = 3995 htonl(MSD(ha->eft_dma)); 3996 3997 ha->fw_dump->header_size = 3998 htonl(offsetof 3999 (struct qla2xxx_fw_dump, isp)); 4000 } 4001 mutex_unlock(&ha->optrom_mutex); 4002 } 4003 } 4004 } 4005 4006 static int 4007 qla81xx_mpi_sync(scsi_qla_host_t *vha) 4008 { 4009 #define MPS_MASK 0xe0 4010 int rval; 4011 uint16_t dc; 4012 uint32_t dw; 4013 4014 if (!IS_QLA81XX(vha->hw)) 4015 return QLA_SUCCESS; 4016 4017 rval = qla2x00_write_ram_word(vha, 0x7c00, 1); 4018 if (rval != QLA_SUCCESS) { 4019 ql_log(ql_log_warn, vha, 0x0105, 4020 "Unable to acquire semaphore.\n"); 4021 goto done; 4022 } 4023 4024 pci_read_config_word(vha->hw->pdev, 0x54, &dc); 4025 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); 4026 if (rval != QLA_SUCCESS) { 4027 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); 4028 goto done_release; 4029 } 4030 4031 dc &= MPS_MASK; 4032 if (dc == (dw & MPS_MASK)) 4033 goto done_release; 4034 4035 dw &= ~MPS_MASK; 4036 dw |= dc; 4037 rval = qla2x00_write_ram_word(vha, 0x7a15, dw); 4038 if (rval != QLA_SUCCESS) { 4039 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); 4040 } 4041 4042 done_release: 4043 rval = qla2x00_write_ram_word(vha, 0x7c00, 0); 4044 if (rval != QLA_SUCCESS) { 4045 ql_log(ql_log_warn, vha, 0x006d, 4046 "Unable to release semaphore.\n"); 4047 } 4048 4049 done: 4050 return rval; 4051 } 4052 4053 int 4054 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) 4055 { 4056 /* Don't try to reallocate the array */ 4057 if (req->outstanding_cmds) 4058 return QLA_SUCCESS; 4059 4060 if (!IS_FWI2_CAPABLE(ha)) 4061 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; 4062 else { 4063 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count) 4064 req->num_outstanding_cmds = ha->cur_fw_xcb_count; 4065 else 4066 req->num_outstanding_cmds = ha->cur_fw_iocb_count; 4067 } 4068 4069 req->outstanding_cmds = kzalloc_objs(srb_t *, req->num_outstanding_cmds); 4070 4071 if (!req->outstanding_cmds) { 4072 /* 4073 * Try to allocate a minimal size just so we can get through 4074 * initialization. 4075 */ 4076 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; 4077 req->outstanding_cmds = kzalloc_objs(srb_t *, 4078 req->num_outstanding_cmds); 4079 4080 if (!req->outstanding_cmds) { 4081 ql_log(ql_log_fatal, NULL, 0x0126, 4082 "Failed to allocate memory for " 4083 "outstanding_cmds for req_que %p.\n", req); 4084 req->num_outstanding_cmds = 0; 4085 return QLA_FUNCTION_FAILED; 4086 } 4087 } 4088 4089 return QLA_SUCCESS; 4090 } 4091 4092 #define PRINT_FIELD(_field, _flag, _str) { \ 4093 if (a0->_field & _flag) {\ 4094 if (p) {\ 4095 strcat(ptr, "|");\ 4096 ptr++;\ 4097 leftover--;\ 4098 } \ 4099 len = snprintf(ptr, leftover, "%s", _str); \ 4100 p = 1;\ 4101 leftover -= len;\ 4102 ptr += len; \ 4103 } \ 4104 } 4105 4106 static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha) 4107 { 4108 #define STR_LEN 64 4109 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data; 4110 u8 str[STR_LEN], *ptr, p; 4111 int leftover, len; 4112 4113 ql_dbg(ql_dbg_init, vha, 0x015a, 4114 "SFP: %.*s -> %.*s ->%s%s%s%s%s%s%s\n", 4115 (int)sizeof(a0->vendor_name), a0->vendor_name, 4116 (int)sizeof(a0->vendor_pn), a0->vendor_pn, 4117 a0->fc_sp_cc10 & FC_SP_2 ? a0->fiber_channel_speed2 & FC_SP_64 ? 4118 " 64G" : "" : "", 4119 a0->fc_sp_cc10 & FC_SP_32 ? " 32G" : "", 4120 a0->fc_sp_cc10 & FC_SP_16 ? " 16G" : "", 4121 a0->fc_sp_cc10 & FC_SP_8 ? " 8G" : "", 4122 a0->fc_sp_cc10 & FC_SP_4 ? " 4G" : "", 4123 a0->fc_sp_cc10 & FC_SP_2 ? " 2G" : "", 4124 a0->fc_sp_cc10 & FC_SP_1 ? " 1G" : ""); 4125 4126 if (!(ql2xextended_error_logging & ql_dbg_verbose)) 4127 return; 4128 4129 memset(str, 0, STR_LEN); 4130 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name); 4131 ql_dbg(ql_dbg_init, vha, 0x015a, 4132 "SFP MFG Name: %s\n", str); 4133 4134 memset(str, 0, STR_LEN); 4135 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn); 4136 ql_dbg(ql_dbg_init, vha, 0x015c, 4137 "SFP Part Name: %s\n", str); 4138 4139 /* media */ 4140 memset(str, 0, STR_LEN); 4141 ptr = str; 4142 leftover = STR_LEN; 4143 p = len = 0; 4144 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX"); 4145 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair"); 4146 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax"); 4147 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax"); 4148 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um"); 4149 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um"); 4150 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode"); 4151 ql_dbg(ql_dbg_init, vha, 0x0160, 4152 "SFP Media: %s\n", str); 4153 4154 /* link length */ 4155 memset(str, 0, STR_LEN); 4156 ptr = str; 4157 leftover = STR_LEN; 4158 p = len = 0; 4159 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long"); 4160 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short"); 4161 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate"); 4162 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long"); 4163 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium"); 4164 ql_dbg(ql_dbg_init, vha, 0x0196, 4165 "SFP Link Length: %s\n", str); 4166 4167 memset(str, 0, STR_LEN); 4168 ptr = str; 4169 leftover = STR_LEN; 4170 p = len = 0; 4171 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)"); 4172 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)"); 4173 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)"); 4174 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)"); 4175 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)"); 4176 ql_dbg(ql_dbg_init, vha, 0x016e, 4177 "SFP FC Link Tech: %s\n", str); 4178 4179 if (a0->length_km) 4180 ql_dbg(ql_dbg_init, vha, 0x016f, 4181 "SFP Distant: %d km\n", a0->length_km); 4182 if (a0->length_100m) 4183 ql_dbg(ql_dbg_init, vha, 0x0170, 4184 "SFP Distant: %d m\n", a0->length_100m*100); 4185 if (a0->length_50um_10m) 4186 ql_dbg(ql_dbg_init, vha, 0x0189, 4187 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10); 4188 if (a0->length_62um_10m) 4189 ql_dbg(ql_dbg_init, vha, 0x018a, 4190 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10); 4191 if (a0->length_om4_10m) 4192 ql_dbg(ql_dbg_init, vha, 0x0194, 4193 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10); 4194 if (a0->length_om3_10m) 4195 ql_dbg(ql_dbg_init, vha, 0x0195, 4196 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10); 4197 } 4198 4199 4200 /** 4201 * qla24xx_detect_sfp() 4202 * 4203 * @vha: adapter state pointer. 4204 * 4205 * @return 4206 * 0 -- Configure firmware to use short-range settings -- normal 4207 * buffer-to-buffer credits. 4208 * 4209 * 1 -- Configure firmware to use long-range settings -- extra 4210 * buffer-to-buffer credits should be allocated with 4211 * ha->lr_distance containing distance settings from NVRAM or SFP 4212 * (if supported). 4213 */ 4214 int 4215 qla24xx_detect_sfp(scsi_qla_host_t *vha) 4216 { 4217 int rc, used_nvram; 4218 struct sff_8247_a0 *a; 4219 struct qla_hw_data *ha = vha->hw; 4220 struct nvram_81xx *nv = ha->nvram; 4221 #define LR_DISTANCE_UNKNOWN 2 4222 static const char * const types[] = { "Short", "Long" }; 4223 static const char * const lengths[] = { "(10km)", "(5km)", "" }; 4224 u8 ll = 0; 4225 4226 /* Seed with NVRAM settings. */ 4227 used_nvram = 0; 4228 ha->flags.lr_detected = 0; 4229 if (IS_BPM_RANGE_CAPABLE(ha) && 4230 (le16_to_cpu(nv->enhanced_features) & NEF_LR_DIST_ENABLE)) { 4231 used_nvram = 1; 4232 ha->flags.lr_detected = 1; 4233 ha->lr_distance = 4234 (le16_to_cpu(nv->enhanced_features) >> LR_DIST_NV_POS) 4235 & LR_DIST_NV_MASK; 4236 } 4237 4238 if (!IS_BPM_ENABLED(vha)) 4239 goto out; 4240 /* Determine SR/LR capabilities of SFP/Transceiver. */ 4241 rc = qla2x00_read_sfp_dev(vha, NULL, 0); 4242 if (rc) 4243 goto out; 4244 4245 used_nvram = 0; 4246 a = (struct sff_8247_a0 *)vha->hw->sfp_data; 4247 qla2xxx_print_sfp_info(vha); 4248 4249 ha->flags.lr_detected = 0; 4250 ll = a->fc_ll_cc7; 4251 if (ll & FC_LL_VL || ll & FC_LL_L) { 4252 /* Long range, track length. */ 4253 ha->flags.lr_detected = 1; 4254 4255 if (a->length_km > 5 || a->length_100m > 50) 4256 ha->lr_distance = LR_DISTANCE_10K; 4257 else 4258 ha->lr_distance = LR_DISTANCE_5K; 4259 } 4260 4261 out: 4262 ql_dbg(ql_dbg_async, vha, 0x507b, 4263 "SFP detect: %s-Range SFP %s (nvr=%x ll=%x lr=%x lrd=%x).\n", 4264 types[ha->flags.lr_detected], 4265 ha->flags.lr_detected ? lengths[ha->lr_distance] : 4266 lengths[LR_DISTANCE_UNKNOWN], 4267 used_nvram, ll, ha->flags.lr_detected, ha->lr_distance); 4268 return ha->flags.lr_detected; 4269 } 4270 4271 static void __qla_adjust_iocb_limit(struct qla_qpair *qpair) 4272 { 4273 u8 num_qps; 4274 u16 limit; 4275 struct qla_hw_data *ha = qpair->vha->hw; 4276 4277 num_qps = ha->num_qpairs + 1; 4278 limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100; 4279 4280 qpair->fwres.iocbs_total = ha->orig_fw_iocb_count; 4281 qpair->fwres.iocbs_limit = limit; 4282 qpair->fwres.iocbs_qp_limit = limit / num_qps; 4283 4284 qpair->fwres.exch_total = ha->orig_fw_xcb_count; 4285 qpair->fwres.exch_limit = (ha->orig_fw_xcb_count * 4286 QLA_IOCB_PCT_LIMIT) / 100; 4287 } 4288 4289 void qla_init_iocb_limit(scsi_qla_host_t *vha) 4290 { 4291 u8 i; 4292 struct qla_hw_data *ha = vha->hw; 4293 4294 __qla_adjust_iocb_limit(ha->base_qpair); 4295 ha->base_qpair->fwres.iocbs_used = 0; 4296 ha->base_qpair->fwres.exch_used = 0; 4297 4298 for (i = 0; i < ha->max_qpairs; i++) { 4299 if (ha->queue_pair_map[i]) { 4300 __qla_adjust_iocb_limit(ha->queue_pair_map[i]); 4301 ha->queue_pair_map[i]->fwres.iocbs_used = 0; 4302 ha->queue_pair_map[i]->fwres.exch_used = 0; 4303 } 4304 } 4305 4306 ha->fwres.iocb_total = ha->orig_fw_iocb_count; 4307 ha->fwres.iocb_limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100; 4308 ha->fwres.exch_total = ha->orig_fw_xcb_count; 4309 ha->fwres.exch_limit = (ha->orig_fw_xcb_count * QLA_IOCB_PCT_LIMIT) / 100; 4310 4311 atomic_set(&ha->fwres.iocb_used, 0); 4312 atomic_set(&ha->fwres.exch_used, 0); 4313 } 4314 4315 void qla_adjust_iocb_limit(scsi_qla_host_t *vha) 4316 { 4317 u8 i; 4318 struct qla_hw_data *ha = vha->hw; 4319 4320 __qla_adjust_iocb_limit(ha->base_qpair); 4321 4322 for (i = 0; i < ha->max_qpairs; i++) { 4323 if (ha->queue_pair_map[i]) 4324 __qla_adjust_iocb_limit(ha->queue_pair_map[i]); 4325 } 4326 } 4327 4328 /** 4329 * qla2x00_setup_chip() - Load and start RISC firmware. 4330 * @vha: HA context 4331 * 4332 * Returns 0 on success. 4333 */ 4334 static int 4335 qla2x00_setup_chip(scsi_qla_host_t *vha) 4336 { 4337 int rval; 4338 uint32_t srisc_address = 0; 4339 struct qla_hw_data *ha = vha->hw; 4340 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4341 unsigned long flags; 4342 int done_once = 0; 4343 4344 if (IS_P3P_TYPE(ha)) { 4345 rval = ha->isp_ops->load_risc(vha, &srisc_address); 4346 if (rval == QLA_SUCCESS) { 4347 qla2x00_stop_firmware(vha); 4348 goto enable_82xx_npiv; 4349 } else 4350 goto failed; 4351 } 4352 4353 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 4354 /* Disable SRAM, Instruction RAM and GP RAM parity. */ 4355 spin_lock_irqsave(&ha->hardware_lock, flags); 4356 wrt_reg_word(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); 4357 rd_reg_word(®->hccr); 4358 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4359 } 4360 4361 qla81xx_mpi_sync(vha); 4362 4363 execute_fw_with_lr: 4364 /* Load firmware sequences */ 4365 rval = ha->isp_ops->load_risc(vha, &srisc_address); 4366 if (rval == QLA_SUCCESS) { 4367 ql_dbg(ql_dbg_init, vha, 0x00c9, 4368 "Verifying Checksum of loaded RISC code.\n"); 4369 4370 rval = qla2x00_verify_checksum(vha, srisc_address); 4371 if (rval == QLA_SUCCESS) { 4372 /* 4373 * Alloc a guestimate dump buffer to capture any failure 4374 * during early phase of driver load. 4375 */ 4376 if (ql2xallocfwdump && 4377 (IS_QLA27XX(ha) || IS_QLA28XX(ha) || 4378 IS_QLA29XX(ha)) && 4379 !vha->flags.init_done) 4380 qla2x00_alloc_fw_dump(vha); 4381 4382 /* Start firmware execution. */ 4383 ql_dbg(ql_dbg_init, vha, 0x00ca, 4384 "Starting firmware.\n"); 4385 4386 if (ql2xexlogins) 4387 ha->flags.exlogins_enabled = 1; 4388 4389 if (qla_is_exch_offld_enabled(vha)) 4390 ha->flags.exchoffld_enabled = 1; 4391 4392 rval = qla2x00_execute_fw(vha, srisc_address); 4393 /* Retrieve firmware information. */ 4394 if (rval == QLA_SUCCESS) { 4395 /* Enable BPM support? */ 4396 if (!done_once++ && qla24xx_detect_sfp(vha)) { 4397 ql_dbg(ql_dbg_init, vha, 0x00ca, 4398 "Re-starting firmware -- BPM.\n"); 4399 /* Best-effort - re-init. */ 4400 ha->isp_ops->reset_chip(vha); 4401 ha->isp_ops->chip_diag(vha); 4402 goto execute_fw_with_lr; 4403 } 4404 4405 if (IS_ZIO_THRESHOLD_CAPABLE(ha)) 4406 qla27xx_set_zio_threshold(vha, 4407 ha->last_zio_threshold); 4408 4409 rval = qla2x00_set_exlogins_buffer(vha); 4410 if (rval != QLA_SUCCESS) 4411 goto failed; 4412 4413 rval = qla2x00_set_exchoffld_buffer(vha); 4414 if (rval != QLA_SUCCESS) 4415 goto failed; 4416 4417 enable_82xx_npiv: 4418 if (IS_P3P_TYPE(ha)) 4419 qla82xx_check_md_needed(vha); 4420 else 4421 rval = qla2x00_get_fw_version(vha); 4422 if (rval != QLA_SUCCESS) 4423 goto failed; 4424 ha->flags.npiv_supported = 0; 4425 if (IS_QLA2XXX_MIDTYPE(ha) && 4426 (ha->fw_attributes & BIT_2)) { 4427 ha->flags.npiv_supported = 1; 4428 if ((!ha->max_npiv_vports) || 4429 ((ha->max_npiv_vports + 1) % 4430 MIN_MULTI_ID_FABRIC)) 4431 ha->max_npiv_vports = 4432 MIN_MULTI_ID_FABRIC - 1; 4433 4434 /* 4435 * The VP_CTRL IOCB selects target VPs 4436 * through the fixed vp_idx_map bitmap, 4437 * so a vp_index beyond it can be enabled 4438 * via VP_CONFIG but never disabled via 4439 * VP_CTRL, leaking the VP. Cap the count 4440 * to the bitmap capacity. 4441 */ 4442 if (ha->max_npiv_vports >= 4443 VP_CTRL_IDX_MAP_BITS) 4444 ha->max_npiv_vports = 4445 VP_CTRL_IDX_MAP_BITS - 1; 4446 } 4447 qlt_config_nvram_with_fw_version(vha); 4448 qla2x00_get_resource_cnts(vha); 4449 qla_init_iocb_limit(vha); 4450 4451 /* 4452 * Allocate the array of outstanding commands 4453 * now that we know the firmware resources. 4454 */ 4455 rval = qla2x00_alloc_outstanding_cmds(ha, 4456 vha->req); 4457 if (rval != QLA_SUCCESS) 4458 goto failed; 4459 4460 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha))) 4461 qla2x00_alloc_fw_dump(vha); 4462 4463 qla_enable_fce_trace(vha); 4464 qla_enable_eft_trace(vha); 4465 } else { 4466 goto failed; 4467 } 4468 } else { 4469 ql_log(ql_log_fatal, vha, 0x00cd, 4470 "ISP Firmware failed checksum.\n"); 4471 goto failed; 4472 } 4473 4474 /* Enable PUREX PASSTHRU */ 4475 if (ql2xrdpenable || ha->flags.scm_supported_f || 4476 ha->flags.edif_enabled) 4477 qla25xx_set_els_cmds_supported(vha); 4478 } else 4479 goto failed; 4480 4481 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 4482 /* Enable proper parity. */ 4483 spin_lock_irqsave(&ha->hardware_lock, flags); 4484 if (IS_QLA2300(ha)) 4485 /* SRAM parity */ 4486 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x1); 4487 else 4488 /* SRAM, Instruction RAM and GP RAM parity */ 4489 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x7); 4490 rd_reg_word(®->hccr); 4491 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4492 } 4493 4494 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4495 ha->flags.fac_supported = 1; 4496 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { 4497 uint32_t size; 4498 4499 rval = qla81xx_fac_get_sector_size(vha, &size); 4500 if (rval == QLA_SUCCESS) { 4501 ha->flags.fac_supported = 1; 4502 ha->fdt_block_size = size << 2; 4503 } else { 4504 ql_log(ql_log_warn, vha, 0x00ce, 4505 "Unsupported FAC firmware (%d.%02d.%02d).\n", 4506 ha->fw_major_version, ha->fw_minor_version, 4507 ha->fw_subminor_version); 4508 4509 if (IS_QLA83XX(ha)) { 4510 ha->flags.fac_supported = 0; 4511 rval = QLA_SUCCESS; 4512 } 4513 } 4514 } 4515 failed: 4516 if (rval) { 4517 ql_log(ql_log_fatal, vha, 0x00cf, 4518 "Setup chip ****FAILED****.\n"); 4519 } 4520 4521 return (rval); 4522 } 4523 4524 /** 4525 * qla2x00_init_response_q_entries() - Initializes response queue entries. 4526 * @rsp: response queue 4527 * 4528 * Beginning of request ring has initialization control block already built 4529 * by nvram config routine. 4530 * 4531 * Returns 0 on success. 4532 */ 4533 void 4534 qla2x00_init_response_q_entries(struct rsp_que *rsp) 4535 { 4536 uint16_t cnt; 4537 4538 rsp->ring_ptr = rsp->ring; 4539 rsp->ring_index = 0; 4540 rsp->status_srb = NULL; 4541 4542 if (rsp->hw && IS_QLA29XX(rsp->hw)) { 4543 /* 4544 * 29xx uses a 128-byte response-ring stride. The signature 4545 * field offset matches response_t, but the entry pitch is 4546 * sizeof(struct response_ext); walk via ring_ext_ptr / struct response_ext. 4547 */ 4548 struct response_ext *pkt; 4549 4550 rsp->ring_ext_ptr = rsp->ring_ext; 4551 pkt = rsp->ring_ext_ptr; 4552 for (cnt = 0; cnt < rsp->length; cnt++) { 4553 pkt->signature = RESPONSE_PROCESSED; 4554 pkt++; 4555 } 4556 } else { 4557 response_t *pkt; 4558 4559 pkt = rsp->ring_ptr; 4560 for (cnt = 0; cnt < rsp->length; cnt++) { 4561 pkt->signature = RESPONSE_PROCESSED; 4562 pkt++; 4563 } 4564 } 4565 } 4566 4567 /** 4568 * qla2x00_update_fw_options() - Read and process firmware options. 4569 * @vha: HA context 4570 * 4571 * Returns 0 on success. 4572 */ 4573 void 4574 qla2x00_update_fw_options(scsi_qla_host_t *vha) 4575 { 4576 uint16_t swing, emphasis, tx_sens, rx_sens; 4577 struct qla_hw_data *ha = vha->hw; 4578 4579 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 4580 qla2x00_get_fw_options(vha, ha->fw_options); 4581 4582 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 4583 return; 4584 4585 /* Serial Link options. */ 4586 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, 4587 "Serial link options.\n"); 4588 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, 4589 ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options)); 4590 4591 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 4592 if (ha->fw_seriallink_options[3] & BIT_2) { 4593 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; 4594 4595 /* 1G settings */ 4596 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); 4597 emphasis = (ha->fw_seriallink_options[2] & 4598 (BIT_4 | BIT_3)) >> 3; 4599 tx_sens = ha->fw_seriallink_options[0] & 4600 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4601 rx_sens = (ha->fw_seriallink_options[0] & 4602 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 4603 ha->fw_options[10] = (emphasis << 14) | (swing << 8); 4604 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 4605 if (rx_sens == 0x0) 4606 rx_sens = 0x3; 4607 ha->fw_options[10] |= (tx_sens << 4) | rx_sens; 4608 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 4609 ha->fw_options[10] |= BIT_5 | 4610 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 4611 (tx_sens & (BIT_1 | BIT_0)); 4612 4613 /* 2G settings */ 4614 swing = (ha->fw_seriallink_options[2] & 4615 (BIT_7 | BIT_6 | BIT_5)) >> 5; 4616 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); 4617 tx_sens = ha->fw_seriallink_options[1] & 4618 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4619 rx_sens = (ha->fw_seriallink_options[1] & 4620 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 4621 ha->fw_options[11] = (emphasis << 14) | (swing << 8); 4622 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 4623 if (rx_sens == 0x0) 4624 rx_sens = 0x3; 4625 ha->fw_options[11] |= (tx_sens << 4) | rx_sens; 4626 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 4627 ha->fw_options[11] |= BIT_5 | 4628 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 4629 (tx_sens & (BIT_1 | BIT_0)); 4630 } 4631 4632 /* FCP2 options. */ 4633 /* Return command IOCBs without waiting for an ABTS to complete. */ 4634 ha->fw_options[3] |= BIT_13; 4635 4636 /* LED scheme. */ 4637 if (ha->flags.enable_led_scheme) 4638 ha->fw_options[2] |= BIT_12; 4639 4640 /* Detect ISP6312. */ 4641 if (IS_QLA6312(ha)) 4642 ha->fw_options[2] |= BIT_13; 4643 4644 /* Set Retry FLOGI in case of P2P connection */ 4645 if (ha->operating_mode == P2P) { 4646 ha->fw_options[2] |= BIT_3; 4647 ql_dbg(ql_dbg_disc, vha, 0x2100, 4648 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 4649 __func__, ha->fw_options[2]); 4650 } 4651 4652 /* Update firmware options. */ 4653 qla2x00_set_fw_options(vha, ha->fw_options); 4654 } 4655 4656 void 4657 qla24xx_update_fw_options(scsi_qla_host_t *vha) 4658 { 4659 int rval; 4660 struct qla_hw_data *ha = vha->hw; 4661 4662 if (IS_P3P_TYPE(ha)) 4663 return; 4664 4665 /* Hold status IOCBs until ABTS response received. */ 4666 if (ql2xfwholdabts) 4667 ha->fw_options[3] |= BIT_12; 4668 4669 /* Set Retry FLOGI in case of P2P connection */ 4670 if (ha->operating_mode == P2P) { 4671 ha->fw_options[2] |= BIT_3; 4672 ql_dbg(ql_dbg_disc, vha, 0x2101, 4673 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 4674 __func__, ha->fw_options[2]); 4675 } 4676 4677 /* Move PUREX, ABTS RX & RIDA to ATIOQ */ 4678 if (ql2xmvasynctoatio && !ha->flags.edif_enabled && 4679 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) { 4680 if (qla_tgt_mode_enabled(vha) || 4681 qla_dual_mode_enabled(vha)) 4682 ha->fw_options[2] |= BIT_11; 4683 else 4684 ha->fw_options[2] &= ~BIT_11; 4685 } 4686 4687 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4688 IS_QLA28XX(ha)) { 4689 /* 4690 * Tell FW to track each exchange to prevent 4691 * driver from using stale exchange. 4692 */ 4693 if (qla_tgt_mode_enabled(vha) || 4694 qla_dual_mode_enabled(vha)) 4695 ha->fw_options[2] |= BIT_4; 4696 else 4697 ha->fw_options[2] &= ~(BIT_4); 4698 4699 /* Reserve 1/2 of emergency exchanges for ELS.*/ 4700 if (qla2xuseresexchforels) 4701 ha->fw_options[2] |= BIT_8; 4702 else 4703 ha->fw_options[2] &= ~BIT_8; 4704 4705 /* 4706 * N2N: set Secure=1 for PLOGI ACC and 4707 * fw shal not send PRLI after PLOGI Acc 4708 */ 4709 if (ha->flags.edif_enabled && 4710 DBELL_ACTIVE(vha)) { 4711 ha->fw_options[3] |= BIT_15; 4712 ha->flags.n2n_fw_acc_sec = 1; 4713 } else { 4714 ha->fw_options[3] &= ~BIT_15; 4715 ha->flags.n2n_fw_acc_sec = 0; 4716 } 4717 } 4718 4719 if (ql2xrdpenable || ha->flags.scm_supported_f || 4720 ha->flags.edif_enabled) 4721 ha->fw_options[1] |= ADD_FO1_ENABLE_PUREX_IOCB; 4722 4723 /* Enable Async 8130/8131 events -- transceiver insertion/removal */ 4724 if (IS_BPM_RANGE_CAPABLE(ha)) 4725 ha->fw_options[3] |= BIT_10; 4726 4727 ql_dbg(ql_dbg_init, vha, 0x00e8, 4728 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n", 4729 __func__, ha->fw_options[1], ha->fw_options[2], 4730 ha->fw_options[3], vha->host->active_mode); 4731 4732 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3]) 4733 qla2x00_set_fw_options(vha, ha->fw_options); 4734 4735 /* Update Serial Link options. */ 4736 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) 4737 return; 4738 4739 rval = qla2x00_set_serdes_params(vha, 4740 le16_to_cpu(ha->fw_seriallink_options24[1]), 4741 le16_to_cpu(ha->fw_seriallink_options24[2]), 4742 le16_to_cpu(ha->fw_seriallink_options24[3])); 4743 if (rval != QLA_SUCCESS) { 4744 ql_log(ql_log_warn, vha, 0x0104, 4745 "Unable to update Serial Link options (%x).\n", rval); 4746 } 4747 } 4748 4749 void 4750 qla2x00_config_rings(struct scsi_qla_host *vha) 4751 { 4752 struct qla_hw_data *ha = vha->hw; 4753 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4754 struct req_que *req = ha->req_q_map[0]; 4755 struct rsp_que *rsp = ha->rsp_q_map[0]; 4756 4757 /* Setup ring parameters in initialization control block. */ 4758 ha->init_cb->request_q_outpointer = cpu_to_le16(0); 4759 ha->init_cb->response_q_inpointer = cpu_to_le16(0); 4760 ha->init_cb->request_q_length = cpu_to_le16(req->length); 4761 ha->init_cb->response_q_length = cpu_to_le16(rsp->length); 4762 put_unaligned_le64(req->dma, &ha->init_cb->request_q_address); 4763 put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address); 4764 4765 wrt_reg_word(ISP_REQ_Q_IN(ha, reg), 0); 4766 wrt_reg_word(ISP_REQ_Q_OUT(ha, reg), 0); 4767 wrt_reg_word(ISP_RSP_Q_IN(ha, reg), 0); 4768 wrt_reg_word(ISP_RSP_Q_OUT(ha, reg), 0); 4769 rd_reg_word(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ 4770 } 4771 4772 void 4773 qla24xx_config_rings(struct scsi_qla_host *vha) 4774 { 4775 struct qla_hw_data *ha = vha->hw; 4776 device_reg_t *reg = ISP_QUE_REG(ha, 0); 4777 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; 4778 struct qla_msix_entry *msix; 4779 struct init_cb_24xx *icb; 4780 uint16_t rid = 0; 4781 struct req_que *req = ha->req_q_map[0]; 4782 struct rsp_que *rsp = ha->rsp_q_map[0]; 4783 4784 /* Setup ring parameters in initialization control block. */ 4785 icb = (struct init_cb_24xx *)ha->init_cb; 4786 icb->request_q_outpointer = cpu_to_le16(0); 4787 icb->response_q_inpointer = cpu_to_le16(0); 4788 icb->request_q_length = cpu_to_le16(req->length); 4789 icb->response_q_length = cpu_to_le16(rsp->length); 4790 put_unaligned_le64(req->dma, &icb->request_q_address); 4791 put_unaligned_le64(rsp->dma, &icb->response_q_address); 4792 4793 /* Setup ATIO queue dma pointers for target mode */ 4794 icb->atio_q_inpointer = cpu_to_le16(0); 4795 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); 4796 put_unaligned_le64(ha->tgt.atio_dma, &icb->atio_q_address); 4797 4798 if (IS_SHADOW_REG_CAPABLE(ha)) 4799 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29); 4800 4801 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4802 IS_QLA28XX(ha)) { 4803 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS); 4804 icb->rid = cpu_to_le16(rid); 4805 if (ha->flags.msix_enabled) { 4806 msix = &ha->msix_entries[1]; 4807 ql_dbg(ql_dbg_init, vha, 0x0019, 4808 "Registering vector 0x%x for base que.\n", 4809 msix->entry); 4810 icb->msix = cpu_to_le16(msix->entry); 4811 } 4812 /* Use alternate PCI bus number */ 4813 if (MSB(rid)) 4814 icb->firmware_options_2 |= cpu_to_le32(BIT_19); 4815 /* Use alternate PCI devfn */ 4816 if (LSB(rid)) 4817 icb->firmware_options_2 |= cpu_to_le32(BIT_18); 4818 4819 /* Use Disable MSIX Handshake mode for capable adapters */ 4820 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && 4821 (ha->flags.msix_enabled)) { 4822 icb->firmware_options_2 &= cpu_to_le32(~BIT_22); 4823 ha->flags.disable_msix_handshake = 1; 4824 ql_dbg(ql_dbg_init, vha, 0x00fe, 4825 "MSIX Handshake Disable Mode turned on.\n"); 4826 } else { 4827 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 4828 } 4829 icb->firmware_options_2 |= cpu_to_le32(BIT_23); 4830 4831 wrt_reg_dword(®->isp25mq.req_q_in, 0); 4832 wrt_reg_dword(®->isp25mq.req_q_out, 0); 4833 wrt_reg_dword(®->isp25mq.rsp_q_in, 0); 4834 wrt_reg_dword(®->isp25mq.rsp_q_out, 0); 4835 } else { 4836 wrt_reg_dword(®->isp24.req_q_in, 0); 4837 wrt_reg_dword(®->isp24.req_q_out, 0); 4838 wrt_reg_dword(®->isp24.rsp_q_in, 0); 4839 wrt_reg_dword(®->isp24.rsp_q_out, 0); 4840 } 4841 4842 qlt_24xx_config_rings(vha); 4843 4844 /* If the user has configured the speed, set it here */ 4845 if (ha->set_data_rate) { 4846 ql_dbg(ql_dbg_init, vha, 0x00fd, 4847 "Speed set by user : %s Gbps \n", 4848 qla2x00_get_link_speed_str(ha, ha->set_data_rate)); 4849 /* 4850 * The ICB data-rate field is 3 bits (bits 13-15); rates above 4851 * 64G do not fit and would overflow into bit 16 (75 ohm 4852 * termination select). Such rates are forced via MBC_DATA_RATE. 4853 */ 4854 if (ha->set_data_rate <= PORT_SPEED_64GB) 4855 icb->firmware_options_3 = 4856 cpu_to_le32(ha->set_data_rate << 13); 4857 } 4858 4859 /* PCI posting */ 4860 rd_reg_word(&ioreg->hccr); 4861 } 4862 4863 /** 4864 * qla2x00_init_rings() - Initializes firmware. 4865 * @vha: HA context 4866 * 4867 * Beginning of request ring has initialization control block already built 4868 * by nvram config routine. 4869 * 4870 * Returns 0 on success. 4871 */ 4872 int 4873 qla2x00_init_rings(scsi_qla_host_t *vha) 4874 { 4875 int rval; 4876 unsigned long flags = 0; 4877 int cnt, que; 4878 struct qla_hw_data *ha = vha->hw; 4879 struct req_que *req; 4880 struct rsp_que *rsp; 4881 struct mid_init_cb_24xx *mid_init_cb = 4882 (struct mid_init_cb_24xx *) ha->init_cb; 4883 4884 spin_lock_irqsave(&ha->hardware_lock, flags); 4885 4886 /* Clear outstanding commands array. */ 4887 for (que = 0; que < ha->max_req_queues; que++) { 4888 req = ha->req_q_map[que]; 4889 if (!req || !test_bit(que, ha->req_qid_map)) 4890 continue; 4891 if (IS_QLA29XX(ha)) 4892 req->out_ptr = 4893 (uint16_t *)(req->ring_ext + req->length); 4894 else 4895 req->out_ptr = 4896 (uint16_t *)(req->ring + req->length); 4897 *req->out_ptr = 0; 4898 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) 4899 req->outstanding_cmds[cnt] = NULL; 4900 4901 req->current_outstanding_cmd = 1; 4902 4903 /* Initialize firmware. */ 4904 req->ring_ptr = req->ring; 4905 req->ring_index = 0; 4906 req->cnt = req->length; 4907 if (IS_QLA29XX(ha)) 4908 req->ring_ext_ptr = req->ring_ext; 4909 } 4910 4911 for (que = 0; que < ha->max_rsp_queues; que++) { 4912 rsp = ha->rsp_q_map[que]; 4913 if (!rsp || !test_bit(que, ha->rsp_qid_map)) 4914 continue; 4915 if (IS_QLA29XX(ha)) 4916 rsp->in_ptr = 4917 (uint16_t *)(rsp->ring_ext + rsp->length); 4918 else 4919 rsp->in_ptr = (uint16_t *)(rsp->ring + rsp->length); 4920 *rsp->in_ptr = 0; 4921 /* Initialize response queue entries */ 4922 if (IS_QLAFX00(ha)) 4923 qlafx00_init_response_q_entries(rsp); 4924 else 4925 qla2x00_init_response_q_entries(rsp); 4926 } 4927 4928 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; 4929 ha->tgt.atio_ring_index = 0; 4930 /* Initialize ATIO queue entries */ 4931 qlt_init_atio_q_entries(vha); 4932 4933 ha->isp_ops->config_rings(vha); 4934 4935 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4936 4937 if (IS_QLAFX00(ha)) { 4938 rval = qlafx00_init_firmware(vha, ha->init_cb_size); 4939 goto next_check; 4940 } 4941 4942 /* Update any ISP specific firmware options before initialization. */ 4943 ha->isp_ops->update_fw_options(vha); 4944 4945 ql_dbg(ql_dbg_init, vha, 0x00d1, 4946 "Issue init firmware FW opt 1-3= %08x %08x %08x.\n", 4947 le32_to_cpu(mid_init_cb->init_cb.firmware_options_1), 4948 le32_to_cpu(mid_init_cb->init_cb.firmware_options_2), 4949 le32_to_cpu(mid_init_cb->init_cb.firmware_options_3)); 4950 4951 if (ha->flags.npiv_supported) { 4952 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) 4953 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; 4954 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); 4955 } 4956 4957 if (IS_FWI2_CAPABLE(ha)) { 4958 mid_init_cb->options = cpu_to_le16(BIT_1); 4959 mid_init_cb->init_cb.execution_throttle = 4960 cpu_to_le16(ha->cur_fw_xcb_count); 4961 ha->flags.dport_enabled = 4962 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) & 4963 BIT_7) != 0; 4964 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n", 4965 (ha->flags.dport_enabled) ? "enabled" : "disabled"); 4966 /* FA-WWPN Status */ 4967 ha->flags.fawwpn_enabled = 4968 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) & 4969 BIT_6) != 0; 4970 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n", 4971 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled"); 4972 /* Init_cb will be reused for other command(s). Save a backup copy of port_name */ 4973 memcpy(ha->port_name, ha->init_cb->port_name, WWN_SIZE); 4974 } 4975 4976 /* ELS pass through payload is limit by frame size. */ 4977 if (ha->flags.edif_enabled) 4978 mid_init_cb->init_cb.frame_payload_size = cpu_to_le16(ELS_MAX_PAYLOAD); 4979 4980 QLA_FW_STARTED(ha); 4981 rval = qla2x00_init_firmware(vha, ha->init_cb_size); 4982 next_check: 4983 if (rval) { 4984 QLA_FW_STOPPED(ha); 4985 ql_log(ql_log_fatal, vha, 0x00d2, 4986 "Init Firmware **** FAILED ****.\n"); 4987 } else { 4988 ql_dbg(ql_dbg_init, vha, 0x00d3, 4989 "Init Firmware -- success.\n"); 4990 vha->u_ql2xexchoffld = vha->u_ql2xiniexchg = 0; 4991 vha->hw->flags.t262_fail = 0; 4992 vha->hw->flags.t272_fail = 0; 4993 } 4994 4995 return (rval); 4996 } 4997 4998 /** 4999 * qla2x00_fw_ready() - Waits for firmware ready. 5000 * @vha: HA context 5001 * 5002 * Returns 0 on success. 5003 */ 5004 static int 5005 qla2x00_fw_ready(scsi_qla_host_t *vha) 5006 { 5007 int rval; 5008 unsigned long wtime, mtime, cs84xx_time; 5009 uint16_t min_wait; /* Minimum wait time if loop is down */ 5010 uint16_t wait_time; /* Wait time if loop is coming ready */ 5011 uint16_t state[16]; 5012 struct qla_hw_data *ha = vha->hw; 5013 5014 if (IS_QLAFX00(vha->hw)) 5015 return qlafx00_fw_ready(vha); 5016 5017 /* Time to wait for loop down */ 5018 if (IS_P3P_TYPE(ha)) 5019 min_wait = 30; 5020 else 5021 min_wait = 20; 5022 5023 /* 5024 * Firmware should take at most one RATOV to login, plus 5 seconds for 5025 * our own processing. 5026 */ 5027 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { 5028 wait_time = min_wait; 5029 } 5030 5031 /* Min wait time if loop down */ 5032 mtime = jiffies + (min_wait * HZ); 5033 5034 /* wait time before firmware ready */ 5035 wtime = jiffies + (wait_time * HZ); 5036 5037 /* Wait for ISP to finish LIP */ 5038 if (!vha->flags.init_done) 5039 ql_log(ql_log_info, vha, 0x801e, 5040 "Waiting for LIP to complete.\n"); 5041 5042 do { 5043 memset(state, -1, sizeof(state)); 5044 rval = qla2x00_get_firmware_state(vha, state); 5045 if (rval == QLA_SUCCESS) { 5046 if (state[0] < FSTATE_LOSS_OF_SYNC) { 5047 vha->device_flags &= ~DFLG_NO_CABLE; 5048 } 5049 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { 5050 ql_dbg(ql_dbg_taskm, vha, 0x801f, 5051 "fw_state=%x 84xx=%x.\n", state[0], 5052 state[2]); 5053 if ((state[2] & FSTATE_LOGGED_IN) && 5054 (state[2] & FSTATE_WAITING_FOR_VERIFY)) { 5055 ql_dbg(ql_dbg_taskm, vha, 0x8028, 5056 "Sending verify iocb.\n"); 5057 5058 cs84xx_time = jiffies; 5059 rval = qla84xx_init_chip(vha); 5060 if (rval != QLA_SUCCESS) { 5061 ql_log(ql_log_warn, 5062 vha, 0x8007, 5063 "Init chip failed.\n"); 5064 break; 5065 } 5066 5067 /* Add time taken to initialize. */ 5068 cs84xx_time = jiffies - cs84xx_time; 5069 wtime += cs84xx_time; 5070 mtime += cs84xx_time; 5071 ql_dbg(ql_dbg_taskm, vha, 0x8008, 5072 "Increasing wait time by %ld. " 5073 "New time %ld.\n", cs84xx_time, 5074 wtime); 5075 } 5076 } else if (state[0] == FSTATE_READY) { 5077 ql_dbg(ql_dbg_taskm, vha, 0x8037, 5078 "F/W Ready - OK.\n"); 5079 5080 qla2x00_get_retry_cnt(vha, &ha->retry_count, 5081 &ha->login_timeout, &ha->r_a_tov); 5082 5083 rval = QLA_SUCCESS; 5084 break; 5085 } 5086 5087 rval = QLA_FUNCTION_FAILED; 5088 5089 if (atomic_read(&vha->loop_down_timer) && 5090 state[0] != FSTATE_READY) { 5091 /* Loop down. Timeout on min_wait for states 5092 * other than Wait for Login. 5093 */ 5094 if (time_after_eq(jiffies, mtime)) { 5095 ql_log(ql_log_info, vha, 0x8038, 5096 "Cable is unplugged...\n"); 5097 5098 vha->device_flags |= DFLG_NO_CABLE; 5099 break; 5100 } 5101 } 5102 } else { 5103 /* Mailbox cmd failed. Timeout on min_wait. */ 5104 if (time_after_eq(jiffies, mtime) || 5105 ha->flags.isp82xx_fw_hung) 5106 break; 5107 } 5108 5109 if (time_after_eq(jiffies, wtime)) 5110 break; 5111 5112 /* Delay for a while */ 5113 msleep(500); 5114 } while (1); 5115 5116 ql_dbg(ql_dbg_taskm, vha, 0x803a, 5117 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0], 5118 state[1], state[2], state[3], state[4], state[5], jiffies); 5119 5120 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { 5121 ql_log(ql_log_warn, vha, 0x803b, 5122 "Firmware ready **** FAILED ****.\n"); 5123 } 5124 5125 return (rval); 5126 } 5127 5128 /* 5129 * qla2x00_configure_hba 5130 * Setup adapter context. 5131 * 5132 * Input: 5133 * ha = adapter state pointer. 5134 * 5135 * Returns: 5136 * 0 = success 5137 * 5138 * Context: 5139 * Kernel context. 5140 */ 5141 static int 5142 qla2x00_configure_hba(scsi_qla_host_t *vha) 5143 { 5144 int rval; 5145 uint16_t loop_id; 5146 uint16_t topo; 5147 uint16_t sw_cap; 5148 uint8_t al_pa; 5149 uint8_t area; 5150 uint8_t domain; 5151 char connect_type[22]; 5152 struct qla_hw_data *ha = vha->hw; 5153 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5154 port_id_t id; 5155 unsigned long flags; 5156 5157 /* Get host addresses. */ 5158 rval = qla2x00_get_adapter_id(vha, 5159 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); 5160 if (rval != QLA_SUCCESS) { 5161 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || 5162 IS_CNA_CAPABLE(ha) || 5163 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { 5164 ql_dbg(ql_dbg_disc, vha, 0x2008, 5165 "Loop is in a transition state.\n"); 5166 } else { 5167 ql_log(ql_log_warn, vha, 0x2009, 5168 "Unable to get host loop ID.\n"); 5169 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && 5170 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { 5171 ql_log(ql_log_warn, vha, 0x1151, 5172 "Doing link init.\n"); 5173 if (qla24xx_link_initialize(vha) == QLA_SUCCESS) 5174 return rval; 5175 } 5176 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 5177 } 5178 return (rval); 5179 } 5180 5181 if (topo == 4) { 5182 ql_log(ql_log_info, vha, 0x200a, 5183 "Cannot get topology - retrying.\n"); 5184 return (QLA_FUNCTION_FAILED); 5185 } 5186 5187 vha->loop_id = loop_id; 5188 5189 /* initialize */ 5190 ha->min_external_loopid = SNS_FIRST_LOOP_ID; 5191 ha->operating_mode = LOOP; 5192 5193 switch (topo) { 5194 case 0: 5195 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); 5196 ha->switch_cap = 0; 5197 ha->current_topology = ISP_CFG_NL; 5198 strcpy(connect_type, "(Loop)"); 5199 break; 5200 5201 case 1: 5202 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); 5203 ha->switch_cap = sw_cap; 5204 ha->current_topology = ISP_CFG_FL; 5205 strcpy(connect_type, "(FL_Port)"); 5206 break; 5207 5208 case 2: 5209 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); 5210 ha->switch_cap = 0; 5211 ha->operating_mode = P2P; 5212 ha->current_topology = ISP_CFG_N; 5213 strcpy(connect_type, "(N_Port-to-N_Port)"); 5214 break; 5215 5216 case 3: 5217 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); 5218 ha->switch_cap = sw_cap; 5219 ha->operating_mode = P2P; 5220 ha->current_topology = ISP_CFG_F; 5221 strcpy(connect_type, "(F_Port)"); 5222 break; 5223 5224 default: 5225 ql_dbg(ql_dbg_disc, vha, 0x200f, 5226 "HBA in unknown topology %x, using NL.\n", topo); 5227 ha->switch_cap = 0; 5228 ha->current_topology = ISP_CFG_NL; 5229 strcpy(connect_type, "(Loop)"); 5230 break; 5231 } 5232 5233 /* Save Host port and loop ID. */ 5234 /* byte order - Big Endian */ 5235 id.b.domain = domain; 5236 id.b.area = area; 5237 id.b.al_pa = al_pa; 5238 id.b.rsvd_1 = 0; 5239 spin_lock_irqsave(&ha->hardware_lock, flags); 5240 if (vha->hw->flags.edif_enabled) { 5241 if (topo != 2) 5242 qla_update_host_map(vha, id); 5243 } else if (!(topo == 2 && ha->flags.n2n_bigger)) 5244 qla_update_host_map(vha, id); 5245 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5246 5247 if (!vha->flags.init_done) 5248 ql_log(ql_log_info, vha, 0x2010, 5249 "Topology - %s, Host Loop address 0x%x.\n", 5250 connect_type, vha->loop_id); 5251 5252 return(rval); 5253 } 5254 5255 inline void 5256 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, 5257 const char *def) 5258 { 5259 char *st, *en; 5260 uint16_t index; 5261 uint64_t zero[2] = { 0 }; 5262 struct qla_hw_data *ha = vha->hw; 5263 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 5264 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); 5265 5266 if (len > sizeof(zero)) 5267 len = sizeof(zero); 5268 if (memcmp(model, &zero, len) != 0) { 5269 memcpy(ha->model_number, model, len); 5270 st = en = ha->model_number; 5271 en += len - 1; 5272 while (en > st) { 5273 if (*en != 0x20 && *en != 0x00) 5274 break; 5275 *en-- = '\0'; 5276 } 5277 5278 index = (ha->pdev->subsystem_device & 0xff); 5279 if (use_tbl && 5280 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 5281 index < QLA_MODEL_NAMES) 5282 strscpy(ha->model_desc, 5283 qla2x00_model_name[index * 2 + 1], 5284 sizeof(ha->model_desc)); 5285 } else { 5286 index = (ha->pdev->subsystem_device & 0xff); 5287 if (use_tbl && 5288 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 5289 index < QLA_MODEL_NAMES) { 5290 strscpy(ha->model_number, 5291 qla2x00_model_name[index * 2], 5292 sizeof(ha->model_number)); 5293 strscpy(ha->model_desc, 5294 qla2x00_model_name[index * 2 + 1], 5295 sizeof(ha->model_desc)); 5296 } else { 5297 strscpy(ha->model_number, def, 5298 sizeof(ha->model_number)); 5299 } 5300 } 5301 if (IS_FWI2_CAPABLE(ha)) 5302 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, 5303 sizeof(ha->model_desc)); 5304 } 5305 5306 /* On sparc systems, obtain port and node WWN from firmware 5307 * properties. 5308 */ 5309 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) 5310 { 5311 #ifdef CONFIG_SPARC 5312 struct qla_hw_data *ha = vha->hw; 5313 struct pci_dev *pdev = ha->pdev; 5314 struct device_node *dp = pci_device_to_OF_node(pdev); 5315 const u8 *val; 5316 int len; 5317 5318 val = of_get_property(dp, "port-wwn", &len); 5319 if (val && len >= WWN_SIZE) 5320 memcpy(nv->port_name, val, WWN_SIZE); 5321 5322 val = of_get_property(dp, "node-wwn", &len); 5323 if (val && len >= WWN_SIZE) 5324 memcpy(nv->node_name, val, WWN_SIZE); 5325 #endif 5326 } 5327 5328 /* 5329 * NVRAM configuration for ISP 2xxx 5330 * 5331 * Input: 5332 * ha = adapter block pointer. 5333 * 5334 * Output: 5335 * initialization control block in response_ring 5336 * host adapters parameters in host adapter block 5337 * 5338 * Returns: 5339 * 0 = success. 5340 */ 5341 int 5342 qla2x00_nvram_config(scsi_qla_host_t *vha) 5343 { 5344 int rval; 5345 uint8_t chksum = 0; 5346 uint16_t cnt; 5347 uint8_t *dptr1, *dptr2; 5348 struct qla_hw_data *ha = vha->hw; 5349 init_cb_t *icb = ha->init_cb; 5350 nvram_t *nv = ha->nvram; 5351 uint8_t *ptr = ha->nvram; 5352 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5353 5354 rval = QLA_SUCCESS; 5355 5356 /* Determine NVRAM starting address. */ 5357 ha->nvram_size = sizeof(*nv); 5358 ha->nvram_base = 0; 5359 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) 5360 if ((rd_reg_word(®->ctrl_status) >> 14) == 1) 5361 ha->nvram_base = 0x80; 5362 5363 /* Get NVRAM data and calculate checksum. */ 5364 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); 5365 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) 5366 chksum += *ptr++; 5367 5368 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, 5369 "Contents of NVRAM.\n"); 5370 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, 5371 nv, ha->nvram_size); 5372 5373 /* Bad NVRAM data, set defaults parameters. */ 5374 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 5375 nv->nvram_version < 1) { 5376 /* Reset NVRAM data. */ 5377 ql_log(ql_log_warn, vha, 0x0064, 5378 "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n", 5379 chksum, nv->id, nv->nvram_version); 5380 ql_log(ql_log_warn, vha, 0x0065, 5381 "Falling back to " 5382 "functioning (yet invalid -- WWPN) defaults.\n"); 5383 5384 /* 5385 * Set default initialization control block. 5386 */ 5387 memset(nv, 0, ha->nvram_size); 5388 nv->parameter_block_version = ICB_VERSION; 5389 5390 if (IS_QLA23XX(ha)) { 5391 nv->firmware_options[0] = BIT_2 | BIT_1; 5392 nv->firmware_options[1] = BIT_7 | BIT_5; 5393 nv->add_firmware_options[0] = BIT_5; 5394 nv->add_firmware_options[1] = BIT_5 | BIT_4; 5395 nv->frame_payload_size = cpu_to_le16(2048); 5396 nv->special_options[1] = BIT_7; 5397 } else if (IS_QLA2200(ha)) { 5398 nv->firmware_options[0] = BIT_2 | BIT_1; 5399 nv->firmware_options[1] = BIT_7 | BIT_5; 5400 nv->add_firmware_options[0] = BIT_5; 5401 nv->add_firmware_options[1] = BIT_5 | BIT_4; 5402 nv->frame_payload_size = cpu_to_le16(1024); 5403 } else if (IS_QLA2100(ha)) { 5404 nv->firmware_options[0] = BIT_3 | BIT_1; 5405 nv->firmware_options[1] = BIT_5; 5406 nv->frame_payload_size = cpu_to_le16(1024); 5407 } 5408 5409 nv->max_iocb_allocation = cpu_to_le16(256); 5410 nv->execution_throttle = cpu_to_le16(16); 5411 nv->retry_count = 8; 5412 nv->retry_delay = 1; 5413 5414 nv->port_name[0] = 33; 5415 nv->port_name[3] = 224; 5416 nv->port_name[4] = 139; 5417 5418 qla2xxx_nvram_wwn_from_ofw(vha, nv); 5419 5420 nv->login_timeout = 4; 5421 5422 /* 5423 * Set default host adapter parameters 5424 */ 5425 nv->host_p[1] = BIT_2; 5426 nv->reset_delay = 5; 5427 nv->port_down_retry_count = 8; 5428 nv->max_luns_per_target = cpu_to_le16(8); 5429 nv->link_down_timeout = 60; 5430 5431 rval = 1; 5432 } 5433 5434 /* Reset Initialization control block */ 5435 memset(icb, 0, ha->init_cb_size); 5436 5437 /* 5438 * Setup driver NVRAM options. 5439 */ 5440 nv->firmware_options[0] |= (BIT_6 | BIT_1); 5441 nv->firmware_options[0] &= ~(BIT_5 | BIT_4); 5442 nv->firmware_options[1] |= (BIT_5 | BIT_0); 5443 nv->firmware_options[1] &= ~BIT_4; 5444 5445 if (IS_QLA23XX(ha)) { 5446 nv->firmware_options[0] |= BIT_2; 5447 nv->firmware_options[0] &= ~BIT_3; 5448 nv->special_options[0] &= ~BIT_6; 5449 nv->add_firmware_options[1] |= BIT_5 | BIT_4; 5450 5451 if (IS_QLA2300(ha)) { 5452 if (ha->fb_rev == FPM_2310) { 5453 strcpy(ha->model_number, "QLA2310"); 5454 } else { 5455 strcpy(ha->model_number, "QLA2300"); 5456 } 5457 } else { 5458 qla2x00_set_model_info(vha, nv->model_number, 5459 sizeof(nv->model_number), "QLA23xx"); 5460 } 5461 } else if (IS_QLA2200(ha)) { 5462 nv->firmware_options[0] |= BIT_2; 5463 /* 5464 * 'Point-to-point preferred, else loop' is not a safe 5465 * connection mode setting. 5466 */ 5467 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == 5468 (BIT_5 | BIT_4)) { 5469 /* Force 'loop preferred, else point-to-point'. */ 5470 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); 5471 nv->add_firmware_options[0] |= BIT_5; 5472 } 5473 strcpy(ha->model_number, "QLA22xx"); 5474 } else /*if (IS_QLA2100(ha))*/ { 5475 strcpy(ha->model_number, "QLA2100"); 5476 } 5477 5478 /* 5479 * Copy over NVRAM RISC parameter block to initialization control block. 5480 */ 5481 dptr1 = (uint8_t *)icb; 5482 dptr2 = (uint8_t *)&nv->parameter_block_version; 5483 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; 5484 while (cnt--) 5485 *dptr1++ = *dptr2++; 5486 5487 /* Copy 2nd half. */ 5488 dptr1 = (uint8_t *)icb->add_firmware_options; 5489 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; 5490 while (cnt--) 5491 *dptr1++ = *dptr2++; 5492 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 5493 /* Use alternate WWN? */ 5494 if (nv->host_p[1] & BIT_7) { 5495 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 5496 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 5497 } 5498 5499 /* Prepare nodename */ 5500 if ((icb->firmware_options[1] & BIT_6) == 0) { 5501 /* 5502 * Firmware will apply the following mask if the nodename was 5503 * not provided. 5504 */ 5505 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 5506 icb->node_name[0] &= 0xF0; 5507 } 5508 5509 /* 5510 * Set host adapter parameters. 5511 */ 5512 5513 /* 5514 * BIT_7 in the host-parameters section allows for modification to 5515 * internal driver logging. 5516 */ 5517 if (nv->host_p[0] & BIT_7) 5518 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 5519 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); 5520 /* Always load RISC code on non ISP2[12]00 chips. */ 5521 if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 5522 ha->flags.disable_risc_code_load = 0; 5523 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); 5524 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); 5525 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); 5526 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; 5527 ha->flags.disable_serdes = 0; 5528 5529 ha->operating_mode = 5530 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; 5531 5532 memcpy(ha->fw_seriallink_options, nv->seriallink_options, 5533 sizeof(ha->fw_seriallink_options)); 5534 5535 /* save HBA serial number */ 5536 ha->serial0 = icb->port_name[5]; 5537 ha->serial1 = icb->port_name[6]; 5538 ha->serial2 = icb->port_name[7]; 5539 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 5540 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 5541 5542 icb->execution_throttle = cpu_to_le16(0xFFFF); 5543 5544 ha->retry_count = nv->retry_count; 5545 5546 /* Set minimum login_timeout to 4 seconds. */ 5547 if (nv->login_timeout != ql2xlogintimeout) 5548 nv->login_timeout = ql2xlogintimeout; 5549 if (nv->login_timeout < 4) 5550 nv->login_timeout = 4; 5551 ha->login_timeout = nv->login_timeout; 5552 5553 /* Set minimum RATOV to 100 tenths of a second. */ 5554 ha->r_a_tov = 100; 5555 5556 ha->loop_reset_delay = nv->reset_delay; 5557 5558 /* Link Down Timeout = 0: 5559 * 5560 * When Port Down timer expires we will start returning 5561 * I/O's to OS with "DID_NO_CONNECT". 5562 * 5563 * Link Down Timeout != 0: 5564 * 5565 * The driver waits for the link to come up after link down 5566 * before returning I/Os to OS with "DID_NO_CONNECT". 5567 */ 5568 if (nv->link_down_timeout == 0) { 5569 ha->loop_down_abort_time = 5570 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 5571 } else { 5572 ha->link_down_timeout = nv->link_down_timeout; 5573 ha->loop_down_abort_time = 5574 (LOOP_DOWN_TIME - ha->link_down_timeout); 5575 } 5576 5577 /* 5578 * Need enough time to try and get the port back. 5579 */ 5580 ha->port_down_retry_count = nv->port_down_retry_count; 5581 if (qlport_down_retry) 5582 ha->port_down_retry_count = qlport_down_retry; 5583 /* Set login_retry_count */ 5584 ha->login_retry_count = nv->retry_count; 5585 if (ha->port_down_retry_count == nv->port_down_retry_count && 5586 ha->port_down_retry_count > 3) 5587 ha->login_retry_count = ha->port_down_retry_count; 5588 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 5589 ha->login_retry_count = ha->port_down_retry_count; 5590 if (ql2xloginretrycount) 5591 ha->login_retry_count = ql2xloginretrycount; 5592 5593 icb->lun_enables = cpu_to_le16(0); 5594 icb->command_resource_count = 0; 5595 icb->immediate_notify_resource_count = 0; 5596 icb->timeout = cpu_to_le16(0); 5597 5598 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 5599 /* Enable RIO */ 5600 icb->firmware_options[0] &= ~BIT_3; 5601 icb->add_firmware_options[0] &= 5602 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 5603 icb->add_firmware_options[0] |= BIT_2; 5604 icb->response_accumulation_timer = 3; 5605 icb->interrupt_delay_timer = 5; 5606 5607 vha->flags.process_response_queue = 1; 5608 } else { 5609 /* Enable ZIO. */ 5610 if (!vha->flags.init_done) { 5611 ha->zio_mode = icb->add_firmware_options[0] & 5612 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 5613 ha->zio_timer = icb->interrupt_delay_timer ? 5614 icb->interrupt_delay_timer : 2; 5615 } 5616 icb->add_firmware_options[0] &= 5617 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 5618 vha->flags.process_response_queue = 0; 5619 if (ha->zio_mode != QLA_ZIO_DISABLED) { 5620 ha->zio_mode = QLA_ZIO_MODE_6; 5621 5622 ql_log(ql_log_info, vha, 0x0068, 5623 "ZIO mode %d enabled; timer delay (%d us).\n", 5624 ha->zio_mode, ha->zio_timer * 100); 5625 5626 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; 5627 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; 5628 vha->flags.process_response_queue = 1; 5629 } 5630 } 5631 5632 if (rval) { 5633 ql_log(ql_log_warn, vha, 0x0069, 5634 "NVRAM configuration failed.\n"); 5635 } 5636 return (rval); 5637 } 5638 5639 void qla2x00_set_fcport_state(fc_port_t *fcport, int state) 5640 { 5641 int old_state; 5642 5643 old_state = atomic_read(&fcport->state); 5644 atomic_set(&fcport->state, state); 5645 5646 /* Don't print state transitions during initial allocation of fcport */ 5647 if (old_state && old_state != state) { 5648 ql_dbg(ql_dbg_disc, fcport->vha, 0x207d, 5649 "FCPort %8phC state transitioned from %s to %s - portid=%02x%02x%02x.\n", 5650 fcport->port_name, port_state_str[old_state], 5651 port_state_str[state], fcport->d_id.b.domain, 5652 fcport->d_id.b.area, fcport->d_id.b.al_pa); 5653 } 5654 } 5655 5656 /** 5657 * qla2x00_alloc_fcport() - Allocate a generic fcport. 5658 * @vha: HA context 5659 * @flags: allocation flags 5660 * 5661 * Returns a pointer to the allocated fcport, or NULL, if none available. 5662 */ 5663 fc_port_t * 5664 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) 5665 { 5666 fc_port_t *fcport; 5667 5668 fcport = kzalloc_obj(fc_port_t, flags); 5669 if (!fcport) 5670 return NULL; 5671 5672 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev, 5673 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma, 5674 flags); 5675 if (!fcport->ct_desc.ct_sns) { 5676 ql_log(ql_log_warn, vha, 0xd049, 5677 "Failed to allocate ct_sns request.\n"); 5678 kfree(fcport); 5679 return NULL; 5680 } 5681 5682 /* Setup fcport template structure. */ 5683 fcport->vha = vha; 5684 fcport->port_type = FCT_UNKNOWN; 5685 fcport->loop_id = FC_NO_LOOP_ID; 5686 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); 5687 fcport->supported_classes = FC_COS_UNSPECIFIED; 5688 fcport->fp_speed = PORT_SPEED_UNKNOWN; 5689 5690 fcport->disc_state = DSC_DELETED; 5691 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 5692 fcport->deleted = QLA_SESS_DELETED; 5693 fcport->login_retry = vha->hw->login_retry_count; 5694 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5695 fcport->logout_on_delete = 1; 5696 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 5697 fcport->tgt_short_link_down_cnt = 0; 5698 fcport->dev_loss_tmo = 0; 5699 5700 if (!fcport->ct_desc.ct_sns) { 5701 ql_log(ql_log_warn, vha, 0xd049, 5702 "Failed to allocate ct_sns request.\n"); 5703 kfree(fcport); 5704 return NULL; 5705 } 5706 5707 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn); 5708 INIT_WORK(&fcport->free_work, qlt_free_session_done); 5709 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn); 5710 INIT_LIST_HEAD(&fcport->gnl_entry); 5711 INIT_LIST_HEAD(&fcport->list); 5712 INIT_LIST_HEAD(&fcport->unsol_ctx_head); 5713 spin_lock_init(&fcport->unsol_ctx_lock); 5714 5715 INIT_LIST_HEAD(&fcport->sess_cmd_list); 5716 spin_lock_init(&fcport->sess_cmd_lock); 5717 5718 spin_lock_init(&fcport->edif.sa_list_lock); 5719 INIT_LIST_HEAD(&fcport->edif.tx_sa_list); 5720 INIT_LIST_HEAD(&fcport->edif.rx_sa_list); 5721 5722 spin_lock_init(&fcport->edif.indx_list_lock); 5723 INIT_LIST_HEAD(&fcport->edif.edif_indx_list); 5724 5725 return fcport; 5726 } 5727 5728 void 5729 qla2x00_free_fcport(fc_port_t *fcport) 5730 { 5731 if (fcport->ct_desc.ct_sns) { 5732 dma_free_coherent(&fcport->vha->hw->pdev->dev, 5733 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns, 5734 fcport->ct_desc.ct_sns_dma); 5735 5736 fcport->ct_desc.ct_sns = NULL; 5737 } 5738 5739 qla_edif_flush_sa_ctl_lists(fcport); 5740 list_del(&fcport->list); 5741 qla2x00_clear_loop_id(fcport); 5742 5743 qla_edif_list_del(fcport); 5744 5745 kfree(fcport); 5746 } 5747 5748 static void qla_get_login_template(scsi_qla_host_t *vha) 5749 { 5750 struct qla_hw_data *ha = vha->hw; 5751 int rval; 5752 u32 *bp, sz; 5753 __be32 *q; 5754 5755 memset(ha->init_cb, 0, ha->init_cb_size); 5756 sz = min_t(int, sizeof(struct fc_els_flogi), ha->init_cb_size); 5757 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma, 5758 ha->init_cb, sz); 5759 if (rval != QLA_SUCCESS) { 5760 ql_dbg(ql_dbg_init, vha, 0x00d1, 5761 "PLOGI ELS param read fail.\n"); 5762 return; 5763 } 5764 q = (__be32 *)&ha->plogi_els_payld.fl_csp; 5765 5766 bp = (uint32_t *)ha->init_cb; 5767 cpu_to_be32_array(q, bp, sz / 4); 5768 ha->flags.plogi_template_valid = 1; 5769 } 5770 5771 /* 5772 * qla2x00_configure_loop 5773 * Updates Fibre Channel Device Database with what is actually on loop. 5774 * 5775 * Input: 5776 * ha = adapter block pointer. 5777 * 5778 * Returns: 5779 * 0 = success. 5780 * 1 = error. 5781 * 2 = database was full and device was not configured. 5782 */ 5783 static int 5784 qla2x00_configure_loop(scsi_qla_host_t *vha) 5785 { 5786 int rval; 5787 unsigned long flags, save_flags; 5788 struct qla_hw_data *ha = vha->hw; 5789 5790 rval = QLA_SUCCESS; 5791 5792 /* Get Initiator ID */ 5793 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { 5794 rval = qla2x00_configure_hba(vha); 5795 if (rval != QLA_SUCCESS) { 5796 ql_dbg(ql_dbg_disc, vha, 0x2013, 5797 "Unable to configure HBA.\n"); 5798 return (rval); 5799 } 5800 } 5801 5802 save_flags = flags = vha->dpc_flags; 5803 ql_dbg(ql_dbg_disc, vha, 0x2014, 5804 "Configure loop -- dpc flags = 0x%lx.\n", flags); 5805 5806 /* 5807 * If we have both an RSCN and PORT UPDATE pending then handle them 5808 * both at the same time. 5809 */ 5810 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5811 clear_bit(RSCN_UPDATE, &vha->dpc_flags); 5812 5813 qla2x00_get_data_rate(vha); 5814 qla_get_login_template(vha); 5815 5816 /* Determine what we need to do */ 5817 if ((ha->current_topology == ISP_CFG_FL || 5818 ha->current_topology == ISP_CFG_F) && 5819 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 5820 5821 set_bit(RSCN_UPDATE, &flags); 5822 clear_bit(LOCAL_LOOP_UPDATE, &flags); 5823 5824 } else if (ha->current_topology == ISP_CFG_NL || 5825 ha->current_topology == ISP_CFG_N) { 5826 clear_bit(RSCN_UPDATE, &flags); 5827 set_bit(LOCAL_LOOP_UPDATE, &flags); 5828 } else if (!vha->flags.online || 5829 (test_bit(ABORT_ISP_ACTIVE, &flags))) { 5830 set_bit(RSCN_UPDATE, &flags); 5831 set_bit(LOCAL_LOOP_UPDATE, &flags); 5832 } 5833 5834 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { 5835 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5836 ql_dbg(ql_dbg_disc, vha, 0x2015, 5837 "Loop resync needed, failing.\n"); 5838 rval = QLA_FUNCTION_FAILED; 5839 } else 5840 rval = qla2x00_configure_local_loop(vha); 5841 } 5842 5843 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { 5844 if (LOOP_TRANSITION(vha)) { 5845 ql_dbg(ql_dbg_disc, vha, 0x2099, 5846 "Needs RSCN update and loop transition.\n"); 5847 rval = QLA_FUNCTION_FAILED; 5848 } 5849 else 5850 rval = qla2x00_configure_fabric(vha); 5851 } 5852 5853 if (rval == QLA_SUCCESS) { 5854 if (atomic_read(&vha->loop_down_timer) || 5855 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5856 rval = QLA_FUNCTION_FAILED; 5857 } else { 5858 atomic_set(&vha->loop_state, LOOP_READY); 5859 ql_dbg(ql_dbg_disc, vha, 0x2069, 5860 "LOOP READY.\n"); 5861 ha->flags.fw_init_done = 1; 5862 5863 /* 5864 * use link up to wake up app to get ready for 5865 * authentication. 5866 */ 5867 if (ha->flags.edif_enabled && DBELL_INACTIVE(vha)) 5868 qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, 5869 ha->link_data_rate); 5870 5871 /* 5872 * Process any ATIO queue entries that came in 5873 * while we weren't online. 5874 */ 5875 if (qla_tgt_mode_enabled(vha) || 5876 qla_dual_mode_enabled(vha)) { 5877 spin_lock_irqsave(&ha->tgt.atio_lock, flags); 5878 qlt_24xx_process_atio_queue(vha, 0); 5879 spin_unlock_irqrestore(&ha->tgt.atio_lock, 5880 flags); 5881 } 5882 } 5883 } 5884 5885 if (rval) { 5886 ql_dbg(ql_dbg_disc, vha, 0x206a, 5887 "%s *** FAILED ***.\n", __func__); 5888 } else { 5889 ql_dbg(ql_dbg_disc, vha, 0x206b, 5890 "%s: exiting normally. local port wwpn %8phN id %06x)\n", 5891 __func__, vha->port_name, vha->d_id.b24); 5892 } 5893 5894 /* Restore state if a resync event occurred during processing */ 5895 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5896 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) 5897 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5898 if (test_bit(RSCN_UPDATE, &save_flags)) { 5899 set_bit(RSCN_UPDATE, &vha->dpc_flags); 5900 } 5901 } 5902 5903 return (rval); 5904 } 5905 5906 static int qla2x00_configure_n2n_loop(scsi_qla_host_t *vha) 5907 { 5908 unsigned long flags; 5909 fc_port_t *fcport; 5910 5911 ql_dbg(ql_dbg_disc, vha, 0x206a, "%s %d.\n", __func__, __LINE__); 5912 5913 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) 5914 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5915 5916 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5917 if (fcport->n2n_flag) { 5918 qla24xx_fcport_handle_login(vha, fcport); 5919 return QLA_SUCCESS; 5920 } 5921 } 5922 5923 spin_lock_irqsave(&vha->work_lock, flags); 5924 vha->scan.scan_retry++; 5925 spin_unlock_irqrestore(&vha->work_lock, flags); 5926 5927 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) { 5928 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5929 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5930 } 5931 return QLA_FUNCTION_FAILED; 5932 } 5933 5934 static void 5935 qla_reinitialize_link(scsi_qla_host_t *vha) 5936 { 5937 int rval; 5938 5939 atomic_set(&vha->loop_state, LOOP_DOWN); 5940 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 5941 rval = qla2x00_full_login_lip(vha); 5942 if (rval == QLA_SUCCESS) { 5943 ql_dbg(ql_dbg_disc, vha, 0xd050, "Link reinitialized\n"); 5944 } else { 5945 ql_dbg(ql_dbg_disc, vha, 0xd051, 5946 "Link reinitialization failed (%d)\n", rval); 5947 } 5948 } 5949 5950 /* 5951 * qla2x00_configure_local_loop 5952 * Updates Fibre Channel Device Database with local loop devices. 5953 * 5954 * Input: 5955 * ha = adapter block pointer. 5956 * 5957 * Returns: 5958 * 0 = success. 5959 */ 5960 static int 5961 qla2x00_configure_local_loop(scsi_qla_host_t *vha) 5962 { 5963 int rval, rval2; 5964 int found; 5965 fc_port_t *fcport, *new_fcport; 5966 uint16_t index; 5967 uint16_t entries; 5968 struct gid_list_info *gid; 5969 uint16_t loop_id; 5970 uint8_t domain, area, al_pa; 5971 struct qla_hw_data *ha = vha->hw; 5972 unsigned long flags; 5973 5974 /* Inititae N2N login. */ 5975 if (N2N_TOPO(ha)) 5976 return qla2x00_configure_n2n_loop(vha); 5977 5978 new_fcport = NULL; 5979 entries = MAX_FIBRE_DEVICES_LOOP; 5980 5981 /* Get list of logged in devices. */ 5982 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); 5983 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, 5984 &entries); 5985 if (rval != QLA_SUCCESS) 5986 goto err; 5987 5988 ql_dbg(ql_dbg_disc, vha, 0x2011, 5989 "Entries in ID list (%d).\n", entries); 5990 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, 5991 ha->gid_list, entries * sizeof(*ha->gid_list)); 5992 5993 if (entries == 0) { 5994 spin_lock_irqsave(&vha->work_lock, flags); 5995 vha->scan.scan_retry++; 5996 spin_unlock_irqrestore(&vha->work_lock, flags); 5997 5998 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) { 5999 u8 loop_map_entries = 0; 6000 int rc; 6001 6002 rc = qla2x00_get_fcal_position_map(vha, NULL, 6003 &loop_map_entries); 6004 if (rc == QLA_SUCCESS && loop_map_entries > 1) { 6005 /* 6006 * There are devices that are still not logged 6007 * in. Reinitialize to give them a chance. 6008 */ 6009 qla_reinitialize_link(vha); 6010 return QLA_FUNCTION_FAILED; 6011 } 6012 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 6013 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6014 } 6015 } else { 6016 vha->scan.scan_retry = 0; 6017 } 6018 6019 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6020 fcport->scan_state = QLA_FCPORT_SCAN; 6021 } 6022 6023 /* Allocate temporary fcport for any new fcports discovered. */ 6024 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 6025 if (new_fcport == NULL) { 6026 ql_log(ql_log_warn, vha, 0x2012, 6027 "Memory allocation failed for fcport.\n"); 6028 rval = QLA_MEMORY_ALLOC_FAILED; 6029 goto err; 6030 } 6031 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 6032 6033 /* Add devices to port list. */ 6034 gid = ha->gid_list; 6035 for (index = 0; index < entries; index++) { 6036 domain = gid->domain; 6037 area = gid->area; 6038 al_pa = gid->al_pa; 6039 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 6040 loop_id = gid->loop_id_2100; 6041 else 6042 loop_id = le16_to_cpu(gid->loop_id); 6043 gid = (void *)gid + ha->gid_list_info_size; 6044 6045 /* Bypass reserved domain fields. */ 6046 if ((domain & 0xf0) == 0xf0) 6047 continue; 6048 6049 /* Bypass if not same domain and area of adapter. */ 6050 if (area && domain && ((area != vha->d_id.b.area) || 6051 (domain != vha->d_id.b.domain)) && 6052 (ha->current_topology == ISP_CFG_NL)) 6053 continue; 6054 6055 6056 /* Bypass invalid local loop ID. */ 6057 if (loop_id > LAST_LOCAL_LOOP_ID) 6058 continue; 6059 6060 memset(new_fcport->port_name, 0, WWN_SIZE); 6061 6062 /* Fill in member data. */ 6063 new_fcport->d_id.b.domain = domain; 6064 new_fcport->d_id.b.area = area; 6065 new_fcport->d_id.b.al_pa = al_pa; 6066 new_fcport->loop_id = loop_id; 6067 new_fcport->scan_state = QLA_FCPORT_FOUND; 6068 6069 rval2 = qla2x00_get_port_database(vha, new_fcport, 0); 6070 if (rval2 != QLA_SUCCESS) { 6071 ql_dbg(ql_dbg_disc, vha, 0x2097, 6072 "Failed to retrieve fcport information " 6073 "-- get_port_database=%x, loop_id=0x%04x.\n", 6074 rval2, new_fcport->loop_id); 6075 /* Skip retry if N2N */ 6076 if (ha->current_topology != ISP_CFG_N) { 6077 ql_dbg(ql_dbg_disc, vha, 0x2105, 6078 "Scheduling resync.\n"); 6079 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6080 continue; 6081 } 6082 } 6083 6084 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 6085 /* Check for matching device in port list. */ 6086 found = 0; 6087 fcport = NULL; 6088 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6089 if (memcmp(new_fcport->port_name, fcport->port_name, 6090 WWN_SIZE)) 6091 continue; 6092 6093 fcport->flags &= ~FCF_FABRIC_DEVICE; 6094 fcport->loop_id = new_fcport->loop_id; 6095 fcport->port_type = new_fcport->port_type; 6096 fcport->d_id.b24 = new_fcport->d_id.b24; 6097 memcpy(fcport->node_name, new_fcport->node_name, 6098 WWN_SIZE); 6099 fcport->scan_state = QLA_FCPORT_FOUND; 6100 if (fcport->login_retry == 0) { 6101 fcport->login_retry = vha->hw->login_retry_count; 6102 ql_dbg(ql_dbg_disc, vha, 0x2135, 6103 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n", 6104 fcport->port_name, fcport->loop_id, 6105 fcport->login_retry); 6106 } 6107 found++; 6108 break; 6109 } 6110 6111 if (!found) { 6112 /* New device, add to fcports list. */ 6113 list_add_tail(&new_fcport->list, &vha->vp_fcports); 6114 6115 /* Allocate a new replacement fcport. */ 6116 fcport = new_fcport; 6117 6118 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6119 6120 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 6121 6122 if (new_fcport == NULL) { 6123 ql_log(ql_log_warn, vha, 0xd031, 6124 "Failed to allocate memory for fcport.\n"); 6125 rval = QLA_MEMORY_ALLOC_FAILED; 6126 goto err; 6127 } 6128 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 6129 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 6130 } 6131 6132 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6133 6134 /* Base iIDMA settings on HBA port speed. */ 6135 fcport->fp_speed = ha->link_data_rate; 6136 } 6137 6138 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6139 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6140 break; 6141 6142 if (fcport->scan_state == QLA_FCPORT_SCAN) { 6143 if ((qla_dual_mode_enabled(vha) || 6144 qla_ini_mode_enabled(vha)) && 6145 atomic_read(&fcport->state) == FCS_ONLINE) { 6146 qla2x00_mark_device_lost(vha, fcport, 6147 ql2xplogiabsentdevice); 6148 if (fcport->loop_id != FC_NO_LOOP_ID && 6149 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 6150 fcport->port_type != FCT_INITIATOR && 6151 fcport->port_type != FCT_BROADCAST) { 6152 ql_dbg(ql_dbg_disc, vha, 0x20f0, 6153 "%s %d %8phC post del sess\n", 6154 __func__, __LINE__, 6155 fcport->port_name); 6156 6157 qlt_schedule_sess_for_deletion(fcport); 6158 continue; 6159 } 6160 } 6161 } 6162 6163 if (fcport->scan_state == QLA_FCPORT_FOUND) 6164 qla24xx_fcport_handle_login(vha, fcport); 6165 } 6166 6167 qla2x00_free_fcport(new_fcport); 6168 6169 return rval; 6170 6171 err: 6172 ql_dbg(ql_dbg_disc, vha, 0x2098, 6173 "Configure local loop error exit: rval=%x.\n", rval); 6174 return rval; 6175 } 6176 6177 static void 6178 qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 6179 { 6180 int rval; 6181 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6182 struct qla_hw_data *ha = vha->hw; 6183 6184 if (!IS_IIDMA_CAPABLE(ha)) 6185 return; 6186 6187 if (atomic_read(&fcport->state) != FCS_ONLINE) 6188 return; 6189 6190 if (fcport->fp_speed == PORT_SPEED_UNKNOWN || 6191 fcport->fp_speed > ha->link_data_rate || 6192 !ha->flags.gpsc_supported) 6193 return; 6194 6195 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, 6196 mb); 6197 if (rval != QLA_SUCCESS) { 6198 ql_dbg(ql_dbg_disc, vha, 0x2004, 6199 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n", 6200 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]); 6201 } else { 6202 ql_dbg(ql_dbg_disc, vha, 0x2005, 6203 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n", 6204 qla2x00_get_link_speed_str(ha, fcport->fp_speed), 6205 fcport->fp_speed, fcport->port_name); 6206 } 6207 } 6208 6209 void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport) 6210 { 6211 qla2x00_iidma_fcport(vha, fcport); 6212 qla24xx_update_fcport_fcp_prio(vha, fcport); 6213 } 6214 6215 int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport) 6216 { 6217 struct qla_work_evt *e; 6218 6219 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA); 6220 if (!e) 6221 return QLA_FUNCTION_FAILED; 6222 6223 e->u.fcport.fcport = fcport; 6224 return qla2x00_post_work(vha, e); 6225 } 6226 6227 /* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/ 6228 static void 6229 qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) 6230 { 6231 struct fc_rport_identifiers rport_ids; 6232 struct fc_rport *rport; 6233 unsigned long flags; 6234 6235 if (atomic_read(&fcport->state) == FCS_ONLINE) 6236 return; 6237 6238 rport_ids.node_name = wwn_to_u64(fcport->node_name); 6239 rport_ids.port_name = wwn_to_u64(fcport->port_name); 6240 rport_ids.port_id = fcport->d_id.b.domain << 16 | 6241 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; 6242 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 6243 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); 6244 if (!rport) { 6245 ql_log(ql_log_warn, vha, 0x2006, 6246 "Unable to allocate fc remote port.\n"); 6247 return; 6248 } 6249 6250 spin_lock_irqsave(&fcport->vha->host->host_lock, flags); 6251 *((fc_port_t **)rport->dd_data) = fcport; 6252 spin_unlock_irqrestore(&fcport->vha->host->host_lock, flags); 6253 fcport->dev_loss_tmo = rport->dev_loss_tmo; 6254 6255 rport->supported_classes = fcport->supported_classes; 6256 6257 rport_ids.roles = FC_PORT_ROLE_UNKNOWN; 6258 if (fcport->port_type == FCT_INITIATOR) 6259 rport_ids.roles |= FC_PORT_ROLE_FCP_INITIATOR; 6260 if (fcport->port_type == FCT_TARGET) 6261 rport_ids.roles |= FC_PORT_ROLE_FCP_TARGET; 6262 if (fcport->port_type & FCT_NVME_INITIATOR) 6263 rport_ids.roles |= FC_PORT_ROLE_NVME_INITIATOR; 6264 if (fcport->port_type & FCT_NVME_TARGET) 6265 rport_ids.roles |= FC_PORT_ROLE_NVME_TARGET; 6266 if (fcport->port_type & FCT_NVME_DISCOVERY) 6267 rport_ids.roles |= FC_PORT_ROLE_NVME_DISCOVERY; 6268 6269 fc_remote_port_rolechg(rport, rport_ids.roles); 6270 6271 ql_dbg(ql_dbg_disc, vha, 0x20ee, 6272 "%s: %8phN. rport %ld:0:%d (%p) is %s mode\n", 6273 __func__, fcport->port_name, vha->host_no, 6274 rport->scsi_target_id, rport, 6275 (fcport->port_type == FCT_TARGET) ? "tgt" : 6276 ((fcport->port_type & FCT_NVME) ? "nvme" : "ini")); 6277 } 6278 6279 /* 6280 * qla2x00_update_fcport 6281 * Updates device on list. 6282 * 6283 * Input: 6284 * ha = adapter block pointer. 6285 * fcport = port structure pointer. 6286 * 6287 * Return: 6288 * 0 - Success 6289 * BIT_0 - error 6290 * 6291 * Context: 6292 * Kernel context. 6293 */ 6294 void 6295 qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 6296 { 6297 unsigned long flags; 6298 6299 if (IS_SW_RESV_ADDR(fcport->d_id)) 6300 return; 6301 6302 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n", 6303 __func__, fcport->port_name); 6304 6305 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 6306 fcport->login_retry = vha->hw->login_retry_count; 6307 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6308 6309 spin_lock_irqsave(&vha->work_lock, flags); 6310 fcport->deleted = 0; 6311 spin_unlock_irqrestore(&vha->work_lock, flags); 6312 6313 if (vha->hw->current_topology == ISP_CFG_NL) 6314 fcport->logout_on_delete = 0; 6315 else 6316 fcport->logout_on_delete = 1; 6317 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0; 6318 6319 if (fcport->tgt_link_down_time < fcport->dev_loss_tmo) { 6320 fcport->tgt_short_link_down_cnt++; 6321 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 6322 } 6323 6324 switch (vha->hw->current_topology) { 6325 case ISP_CFG_N: 6326 case ISP_CFG_NL: 6327 fcport->keep_nport_handle = 1; 6328 break; 6329 default: 6330 break; 6331 } 6332 6333 qla2x00_iidma_fcport(vha, fcport); 6334 6335 qla2x00_dfs_create_rport(vha, fcport); 6336 6337 qla24xx_update_fcport_fcp_prio(vha, fcport); 6338 6339 switch (vha->host->active_mode) { 6340 case MODE_INITIATOR: 6341 qla2x00_reg_remote_port(vha, fcport); 6342 break; 6343 case MODE_TARGET: 6344 if (!vha->vha_tgt.qla_tgt->tgt_stop && 6345 !vha->vha_tgt.qla_tgt->tgt_stopped) 6346 qlt_fc_port_added(vha, fcport); 6347 break; 6348 case MODE_DUAL: 6349 qla2x00_reg_remote_port(vha, fcport); 6350 if (!vha->vha_tgt.qla_tgt->tgt_stop && 6351 !vha->vha_tgt.qla_tgt->tgt_stopped) 6352 qlt_fc_port_added(vha, fcport); 6353 break; 6354 default: 6355 break; 6356 } 6357 6358 if (NVME_TARGET(vha->hw, fcport)) 6359 qla_nvme_register_remote(vha, fcport); 6360 6361 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 6362 6363 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) { 6364 if (fcport->id_changed) { 6365 fcport->id_changed = 0; 6366 ql_dbg(ql_dbg_disc, vha, 0x20d7, 6367 "%s %d %8phC post gfpnid fcp_cnt %d\n", 6368 __func__, __LINE__, fcport->port_name, 6369 vha->fcport_count); 6370 qla24xx_post_gfpnid_work(vha, fcport); 6371 } else { 6372 ql_dbg(ql_dbg_disc, vha, 0x20d7, 6373 "%s %d %8phC post gpsc fcp_cnt %d\n", 6374 __func__, __LINE__, fcport->port_name, 6375 vha->fcport_count); 6376 qla24xx_post_gpsc_work(vha, fcport); 6377 } 6378 } 6379 6380 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE); 6381 } 6382 6383 void qla_register_fcport_fn(struct work_struct *work) 6384 { 6385 fc_port_t *fcport = container_of(work, struct fc_port, reg_work); 6386 u32 rscn_gen = fcport->rscn_gen; 6387 u16 data[2]; 6388 6389 if (IS_SW_RESV_ADDR(fcport->d_id)) 6390 return; 6391 6392 qla2x00_update_fcport(fcport->vha, fcport); 6393 6394 ql_dbg(ql_dbg_disc, fcport->vha, 0x911e, 6395 "%s rscn gen %d/%d next DS %d\n", __func__, 6396 rscn_gen, fcport->rscn_gen, fcport->next_disc_state); 6397 6398 if (rscn_gen != fcport->rscn_gen) { 6399 /* RSCN(s) came in while registration */ 6400 switch (fcport->next_disc_state) { 6401 case DSC_DELETE_PEND: 6402 qlt_schedule_sess_for_deletion(fcport); 6403 break; 6404 case DSC_ADISC: 6405 data[0] = data[1] = 0; 6406 qla2x00_post_async_adisc_work(fcport->vha, fcport, 6407 data); 6408 break; 6409 default: 6410 break; 6411 } 6412 } 6413 } 6414 6415 /* 6416 * qla2x00_configure_fabric 6417 * Setup SNS devices with loop ID's. 6418 * 6419 * Input: 6420 * ha = adapter block pointer. 6421 * 6422 * Returns: 6423 * 0 = success. 6424 * BIT_0 = error 6425 */ 6426 static int 6427 qla2x00_configure_fabric(scsi_qla_host_t *vha) 6428 { 6429 int rval; 6430 fc_port_t *fcport; 6431 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6432 uint16_t loop_id; 6433 struct qla_hw_data *ha = vha->hw; 6434 int discovery_gen; 6435 6436 /* If FL port exists, then SNS is present */ 6437 if (IS_FWI2_CAPABLE(ha)) 6438 loop_id = NPH_F_PORT; 6439 else 6440 loop_id = SNS_FL_PORT; 6441 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); 6442 if (rval != QLA_SUCCESS) { 6443 ql_dbg(ql_dbg_disc, vha, 0x20a0, 6444 "MBX_GET_PORT_NAME failed, No FL Port.\n"); 6445 6446 vha->device_flags &= ~SWITCH_FOUND; 6447 return (QLA_SUCCESS); 6448 } 6449 vha->device_flags |= SWITCH_FOUND; 6450 6451 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_port_name, 0); 6452 if (rval != QLA_SUCCESS) 6453 ql_dbg(ql_dbg_disc, vha, 0x20ff, 6454 "Failed to get Fabric Port Name\n"); 6455 6456 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) { 6457 rval = qla2x00_send_change_request(vha, 0x3, 0); 6458 if (rval != QLA_SUCCESS) 6459 ql_log(ql_log_warn, vha, 0x121, 6460 "Failed to enable receiving of RSCN requests: 0x%x.\n", 6461 rval); 6462 } 6463 6464 do { 6465 qla2x00_mgmt_svr_login(vha); 6466 6467 /* Ensure we are logged into the SNS. */ 6468 loop_id = NPH_SNS_LID(ha); 6469 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, 6470 0xfc, mb, BIT_1|BIT_0); 6471 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 6472 ql_dbg(ql_dbg_disc, vha, 0x20a1, 6473 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n", 6474 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval); 6475 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6476 return rval; 6477 } 6478 6479 /* FDMI support. */ 6480 if (ql2xfdmienable && 6481 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) 6482 qla2x00_fdmi_register(vha); 6483 6484 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { 6485 if (qla2x00_rft_id(vha)) { 6486 /* EMPTY */ 6487 ql_dbg(ql_dbg_disc, vha, 0x20a2, 6488 "Register FC-4 TYPE failed.\n"); 6489 if (test_bit(LOOP_RESYNC_NEEDED, 6490 &vha->dpc_flags)) 6491 break; 6492 } 6493 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) { 6494 /* EMPTY */ 6495 ql_dbg(ql_dbg_disc, vha, 0x209a, 6496 "Register FC-4 Features failed.\n"); 6497 if (test_bit(LOOP_RESYNC_NEEDED, 6498 &vha->dpc_flags)) 6499 break; 6500 } 6501 if (vha->flags.nvme_enabled) { 6502 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) { 6503 ql_dbg(ql_dbg_disc, vha, 0x2049, 6504 "Register NVME FC Type Features failed.\n"); 6505 } 6506 } 6507 if (qla2x00_rnn_id(vha)) { 6508 /* EMPTY */ 6509 ql_dbg(ql_dbg_disc, vha, 0x2104, 6510 "Register Node Name failed.\n"); 6511 if (test_bit(LOOP_RESYNC_NEEDED, 6512 &vha->dpc_flags)) 6513 break; 6514 } else if (qla2x00_rsnn_nn(vha)) { 6515 /* EMPTY */ 6516 ql_dbg(ql_dbg_disc, vha, 0x209b, 6517 "Register Symbolic Node Name failed.\n"); 6518 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6519 break; 6520 } 6521 } 6522 6523 6524 /* Mark the time right before querying FW for connected ports. 6525 * This process is long, asynchronous and by the time it's done, 6526 * collected information might not be accurate anymore. E.g. 6527 * disconnected port might have re-connected and a brand new 6528 * session has been created. In this case session's generation 6529 * will be newer than discovery_gen. */ 6530 qlt_do_generation_tick(vha, &discovery_gen); 6531 6532 if (USE_ASYNC_SCAN(ha)) { 6533 /* start of scan begins here */ 6534 vha->scan.rscn_gen_end = atomic_read(&vha->rscn_gen); 6535 qla_fab_scan_start(vha); 6536 } else { 6537 list_for_each_entry(fcport, &vha->vp_fcports, list) 6538 fcport->scan_state = QLA_FCPORT_SCAN; 6539 6540 rval = qla2x00_find_all_fabric_devs(vha); 6541 } 6542 if (rval != QLA_SUCCESS) 6543 break; 6544 } while (0); 6545 6546 if (!vha->nvme_local_port && vha->flags.nvme_enabled) 6547 qla_nvme_register_hba(vha); 6548 6549 if (rval) 6550 ql_dbg(ql_dbg_disc, vha, 0x2068, 6551 "Configure fabric error exit rval=%d.\n", rval); 6552 6553 return (rval); 6554 } 6555 6556 /* 6557 * qla2x00_find_all_fabric_devs 6558 * 6559 * Input: 6560 * ha = adapter block pointer. 6561 * dev = database device entry pointer. 6562 * 6563 * Returns: 6564 * 0 = success. 6565 * 6566 * Context: 6567 * Kernel context. 6568 */ 6569 static int 6570 qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha) 6571 { 6572 int rval; 6573 uint16_t loop_id; 6574 fc_port_t *fcport, *new_fcport; 6575 int found; 6576 6577 sw_info_t *swl; 6578 int swl_idx; 6579 int first_dev, last_dev; 6580 port_id_t wrap = {}, nxt_d_id; 6581 struct qla_hw_data *ha = vha->hw; 6582 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 6583 unsigned long flags; 6584 6585 rval = QLA_SUCCESS; 6586 6587 /* Try GID_PT to get device list, else GAN. */ 6588 if (!ha->swl) 6589 ha->swl = kzalloc_objs(sw_info_t, ha->max_fibre_devices); 6590 swl = ha->swl; 6591 if (!swl) { 6592 /*EMPTY*/ 6593 ql_dbg(ql_dbg_disc, vha, 0x209c, 6594 "GID_PT allocations failed, fallback on GA_NXT.\n"); 6595 } else { 6596 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); 6597 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { 6598 swl = NULL; 6599 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6600 return rval; 6601 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { 6602 swl = NULL; 6603 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6604 return rval; 6605 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { 6606 swl = NULL; 6607 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6608 return rval; 6609 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) { 6610 swl = NULL; 6611 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6612 return rval; 6613 } 6614 6615 /* If other queries succeeded probe for FC-4 type */ 6616 if (swl) { 6617 qla2x00_gff_id(vha, swl); 6618 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6619 return rval; 6620 } 6621 } 6622 swl_idx = 0; 6623 6624 /* Allocate temporary fcport for any new fcports discovered. */ 6625 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 6626 if (new_fcport == NULL) { 6627 ql_log(ql_log_warn, vha, 0x209d, 6628 "Failed to allocate memory for fcport.\n"); 6629 return (QLA_MEMORY_ALLOC_FAILED); 6630 } 6631 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 6632 /* Set start port ID scan at adapter ID. */ 6633 first_dev = 1; 6634 last_dev = 0; 6635 6636 /* Starting free loop ID. */ 6637 loop_id = ha->min_external_loopid; 6638 for (; loop_id <= ha->max_loop_id; loop_id++) { 6639 if (qla2x00_is_reserved_id(vha, loop_id)) 6640 continue; 6641 6642 if (ha->current_topology == ISP_CFG_FL && 6643 (atomic_read(&vha->loop_down_timer) || 6644 LOOP_TRANSITION(vha))) { 6645 atomic_set(&vha->loop_down_timer, 0); 6646 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6647 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 6648 break; 6649 } 6650 6651 if (swl != NULL) { 6652 if (last_dev) { 6653 wrap.b24 = new_fcport->d_id.b24; 6654 } else { 6655 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; 6656 memcpy(new_fcport->node_name, 6657 swl[swl_idx].node_name, WWN_SIZE); 6658 memcpy(new_fcport->port_name, 6659 swl[swl_idx].port_name, WWN_SIZE); 6660 memcpy(new_fcport->fabric_port_name, 6661 swl[swl_idx].fabric_port_name, WWN_SIZE); 6662 new_fcport->fp_speed = swl[swl_idx].fp_speed; 6663 new_fcport->fc4_type = swl[swl_idx].fc4_type; 6664 6665 new_fcport->nvme_flag = 0; 6666 if (vha->flags.nvme_enabled && 6667 swl[swl_idx].fc4_type & FS_FC4TYPE_NVME) { 6668 ql_log(ql_log_info, vha, 0x2131, 6669 "FOUND: NVME port %8phC as FC Type 28h\n", 6670 new_fcport->port_name); 6671 } 6672 6673 if (swl[swl_idx].d_id.b.rsvd_1 != 0) { 6674 last_dev = 1; 6675 } 6676 swl_idx++; 6677 } 6678 } else { 6679 /* Send GA_NXT to the switch */ 6680 rval = qla2x00_ga_nxt(vha, new_fcport); 6681 if (rval != QLA_SUCCESS) { 6682 ql_log(ql_log_warn, vha, 0x209e, 6683 "SNS scan failed -- assuming " 6684 "zero-entry result.\n"); 6685 rval = QLA_SUCCESS; 6686 break; 6687 } 6688 } 6689 6690 /* If wrap on switch device list, exit. */ 6691 if (first_dev) { 6692 wrap.b24 = new_fcport->d_id.b24; 6693 first_dev = 0; 6694 } else if (new_fcport->d_id.b24 == wrap.b24) { 6695 ql_dbg(ql_dbg_disc, vha, 0x209f, 6696 "Device wrap (%02x%02x%02x).\n", 6697 new_fcport->d_id.b.domain, 6698 new_fcport->d_id.b.area, 6699 new_fcport->d_id.b.al_pa); 6700 break; 6701 } 6702 6703 /* Bypass if same physical adapter. */ 6704 if (new_fcport->d_id.b24 == base_vha->d_id.b24) 6705 continue; 6706 6707 /* Bypass virtual ports of the same host. */ 6708 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24)) 6709 continue; 6710 6711 /* Bypass if same domain and area of adapter. */ 6712 if (((new_fcport->d_id.b24 & 0xffff00) == 6713 (vha->d_id.b24 & 0xffff00)) && ha->current_topology == 6714 ISP_CFG_FL) 6715 continue; 6716 6717 /* Bypass reserved domain fields. */ 6718 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) 6719 continue; 6720 6721 /* Bypass ports whose FCP-4 type is not FCP_SCSI */ 6722 if (ql2xgffidenable && 6723 (!(new_fcport->fc4_type & FS_FC4TYPE_FCP) && 6724 new_fcport->fc4_type != 0)) 6725 continue; 6726 6727 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 6728 6729 /* Locate matching device in database. */ 6730 found = 0; 6731 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6732 if (memcmp(new_fcport->port_name, fcport->port_name, 6733 WWN_SIZE)) 6734 continue; 6735 6736 fcport->scan_state = QLA_FCPORT_FOUND; 6737 6738 found++; 6739 6740 /* Update port state. */ 6741 memcpy(fcport->fabric_port_name, 6742 new_fcport->fabric_port_name, WWN_SIZE); 6743 fcport->fp_speed = new_fcport->fp_speed; 6744 6745 /* 6746 * If address the same and state FCS_ONLINE 6747 * (or in target mode), nothing changed. 6748 */ 6749 if (fcport->d_id.b24 == new_fcport->d_id.b24 && 6750 (atomic_read(&fcport->state) == FCS_ONLINE || 6751 (vha->host->active_mode == MODE_TARGET))) { 6752 break; 6753 } 6754 6755 if (fcport->login_retry == 0) 6756 fcport->login_retry = 6757 vha->hw->login_retry_count; 6758 /* 6759 * If device was not a fabric device before. 6760 */ 6761 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { 6762 fcport->d_id.b24 = new_fcport->d_id.b24; 6763 qla2x00_clear_loop_id(fcport); 6764 fcport->flags |= (FCF_FABRIC_DEVICE | 6765 FCF_LOGIN_NEEDED); 6766 break; 6767 } 6768 6769 /* 6770 * Port ID changed or device was marked to be updated; 6771 * Log it out if still logged in and mark it for 6772 * relogin later. 6773 */ 6774 if (qla_tgt_mode_enabled(base_vha)) { 6775 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080, 6776 "port changed FC ID, %8phC" 6777 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n", 6778 fcport->port_name, 6779 fcport->d_id.b.domain, 6780 fcport->d_id.b.area, 6781 fcport->d_id.b.al_pa, 6782 fcport->loop_id, 6783 new_fcport->d_id.b.domain, 6784 new_fcport->d_id.b.area, 6785 new_fcport->d_id.b.al_pa); 6786 fcport->d_id.b24 = new_fcport->d_id.b24; 6787 break; 6788 } 6789 6790 fcport->d_id.b24 = new_fcport->d_id.b24; 6791 fcport->flags |= FCF_LOGIN_NEEDED; 6792 break; 6793 } 6794 6795 if (found && NVME_TARGET(vha->hw, fcport)) { 6796 if (fcport->disc_state == DSC_DELETE_PEND) { 6797 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 6798 vha->fcport_count--; 6799 fcport->login_succ = 0; 6800 } 6801 } 6802 6803 if (found) { 6804 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6805 continue; 6806 } 6807 /* If device was not in our fcports list, then add it. */ 6808 new_fcport->scan_state = QLA_FCPORT_FOUND; 6809 list_add_tail(&new_fcport->list, &vha->vp_fcports); 6810 6811 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6812 6813 6814 /* Allocate a new replacement fcport. */ 6815 nxt_d_id.b24 = new_fcport->d_id.b24; 6816 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 6817 if (new_fcport == NULL) { 6818 ql_log(ql_log_warn, vha, 0xd032, 6819 "Memory allocation failed for fcport.\n"); 6820 return (QLA_MEMORY_ALLOC_FAILED); 6821 } 6822 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 6823 new_fcport->d_id.b24 = nxt_d_id.b24; 6824 } 6825 6826 qla2x00_free_fcport(new_fcport); 6827 6828 /* 6829 * Logout all previous fabric dev marked lost, except FCP2 devices. 6830 */ 6831 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6832 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6833 break; 6834 6835 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) 6836 continue; 6837 6838 if (fcport->scan_state == QLA_FCPORT_SCAN) { 6839 if ((qla_dual_mode_enabled(vha) || 6840 qla_ini_mode_enabled(vha)) && 6841 atomic_read(&fcport->state) == FCS_ONLINE) { 6842 qla2x00_mark_device_lost(vha, fcport, 6843 ql2xplogiabsentdevice); 6844 if (fcport->loop_id != FC_NO_LOOP_ID && 6845 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 6846 fcport->port_type != FCT_INITIATOR && 6847 fcport->port_type != FCT_BROADCAST) { 6848 ql_dbg(ql_dbg_disc, vha, 0x20f0, 6849 "%s %d %8phC post del sess\n", 6850 __func__, __LINE__, 6851 fcport->port_name); 6852 qlt_schedule_sess_for_deletion(fcport); 6853 continue; 6854 } 6855 } 6856 } 6857 6858 if (fcport->scan_state == QLA_FCPORT_FOUND && 6859 (fcport->flags & FCF_LOGIN_NEEDED) != 0) 6860 qla24xx_fcport_handle_login(vha, fcport); 6861 } 6862 return (rval); 6863 } 6864 6865 /* FW does not set aside Loop id for MGMT Server/FFFFFAh */ 6866 int 6867 qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha) 6868 { 6869 int loop_id = FC_NO_LOOP_ID; 6870 int lid = NPH_MGMT_SERVER - vha->vp_idx; 6871 unsigned long flags; 6872 struct qla_hw_data *ha = vha->hw; 6873 6874 if (vha->vp_idx == 0) { 6875 set_bit(NPH_MGMT_SERVER, ha->loop_id_map); 6876 return NPH_MGMT_SERVER; 6877 } 6878 6879 /* pick id from high and work down to low */ 6880 spin_lock_irqsave(&ha->vport_slock, flags); 6881 for (; lid > 0; lid--) { 6882 if (!test_bit(lid, vha->hw->loop_id_map)) { 6883 set_bit(lid, vha->hw->loop_id_map); 6884 loop_id = lid; 6885 break; 6886 } 6887 } 6888 spin_unlock_irqrestore(&ha->vport_slock, flags); 6889 6890 return loop_id; 6891 } 6892 6893 /* 6894 * qla2x00_fabric_login 6895 * Issue fabric login command. 6896 * 6897 * Input: 6898 * ha = adapter block pointer. 6899 * device = pointer to FC device type structure. 6900 * 6901 * Returns: 6902 * 0 - Login successfully 6903 * 1 - Login failed 6904 * 2 - Initiator device 6905 * 3 - Fatal error 6906 */ 6907 int 6908 qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, 6909 uint16_t *next_loopid) 6910 { 6911 int rval; 6912 int retry; 6913 uint16_t tmp_loopid; 6914 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6915 struct qla_hw_data *ha = vha->hw; 6916 6917 retry = 0; 6918 tmp_loopid = 0; 6919 6920 for (;;) { 6921 ql_dbg(ql_dbg_disc, vha, 0x2000, 6922 "Trying Fabric Login w/loop id 0x%04x for port " 6923 "%02x%02x%02x.\n", 6924 fcport->loop_id, fcport->d_id.b.domain, 6925 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6926 6927 /* Login fcport on switch. */ 6928 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, 6929 fcport->d_id.b.domain, fcport->d_id.b.area, 6930 fcport->d_id.b.al_pa, mb, BIT_0); 6931 if (rval != QLA_SUCCESS) { 6932 return rval; 6933 } 6934 if (mb[0] == MBS_PORT_ID_USED) { 6935 /* 6936 * Device has another loop ID. The firmware team 6937 * recommends the driver perform an implicit login with 6938 * the specified ID again. The ID we just used is save 6939 * here so we return with an ID that can be tried by 6940 * the next login. 6941 */ 6942 retry++; 6943 tmp_loopid = fcport->loop_id; 6944 fcport->loop_id = mb[1]; 6945 6946 ql_dbg(ql_dbg_disc, vha, 0x2001, 6947 "Fabric Login: port in use - next loop " 6948 "id=0x%04x, port id= %02x%02x%02x.\n", 6949 fcport->loop_id, fcport->d_id.b.domain, 6950 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6951 6952 } else if (mb[0] == MBS_COMMAND_COMPLETE) { 6953 /* 6954 * Login succeeded. 6955 */ 6956 if (retry) { 6957 /* A retry occurred before. */ 6958 *next_loopid = tmp_loopid; 6959 } else { 6960 /* 6961 * No retry occurred before. Just increment the 6962 * ID value for next login. 6963 */ 6964 *next_loopid = (fcport->loop_id + 1); 6965 } 6966 6967 if (mb[1] & BIT_0) { 6968 fcport->port_type = FCT_INITIATOR; 6969 } else { 6970 fcport->port_type = FCT_TARGET; 6971 if (mb[1] & BIT_1) { 6972 fcport->flags |= FCF_FCP2_DEVICE; 6973 } 6974 } 6975 6976 if (mb[10] & BIT_0) 6977 fcport->supported_classes |= FC_COS_CLASS2; 6978 if (mb[10] & BIT_1) 6979 fcport->supported_classes |= FC_COS_CLASS3; 6980 6981 if (IS_FWI2_CAPABLE(ha)) { 6982 if (mb[10] & BIT_7) 6983 fcport->flags |= 6984 FCF_CONF_COMP_SUPPORTED; 6985 } 6986 6987 rval = QLA_SUCCESS; 6988 break; 6989 } else if (mb[0] == MBS_LOOP_ID_USED) { 6990 /* 6991 * Loop ID already used, try next loop ID. 6992 */ 6993 fcport->loop_id++; 6994 rval = qla2x00_find_new_loop_id(vha, fcport); 6995 if (rval != QLA_SUCCESS) { 6996 /* Ran out of loop IDs to use */ 6997 break; 6998 } 6999 } else if (mb[0] == MBS_COMMAND_ERROR) { 7000 /* 7001 * Firmware possibly timed out during login. If NO 7002 * retries are left to do then the device is declared 7003 * dead. 7004 */ 7005 *next_loopid = fcport->loop_id; 7006 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 7007 fcport->d_id.b.domain, fcport->d_id.b.area, 7008 fcport->d_id.b.al_pa); 7009 qla2x00_mark_device_lost(vha, fcport, 1); 7010 7011 rval = 1; 7012 break; 7013 } else { 7014 /* 7015 * unrecoverable / not handled error 7016 */ 7017 ql_dbg(ql_dbg_disc, vha, 0x2002, 7018 "Failed=%x port_id=%02x%02x%02x loop_id=%x " 7019 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, 7020 fcport->d_id.b.area, fcport->d_id.b.al_pa, 7021 fcport->loop_id, jiffies); 7022 7023 *next_loopid = fcport->loop_id; 7024 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 7025 fcport->d_id.b.domain, fcport->d_id.b.area, 7026 fcport->d_id.b.al_pa); 7027 qla2x00_clear_loop_id(fcport); 7028 fcport->login_retry = 0; 7029 7030 rval = 3; 7031 break; 7032 } 7033 } 7034 7035 return (rval); 7036 } 7037 7038 /* 7039 * qla2x00_local_device_login 7040 * Issue local device login command. 7041 * 7042 * Input: 7043 * ha = adapter block pointer. 7044 * loop_id = loop id of device to login to. 7045 * 7046 * Returns (Where's the #define!!!!): 7047 * 0 - Login successfully 7048 * 1 - Login failed 7049 * 3 - Fatal error 7050 */ 7051 int 7052 qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) 7053 { 7054 int rval; 7055 uint16_t mb[MAILBOX_REGISTER_COUNT]; 7056 7057 memset(mb, 0, sizeof(mb)); 7058 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); 7059 if (rval == QLA_SUCCESS) { 7060 /* Interrogate mailbox registers for any errors */ 7061 if (mb[0] == MBS_COMMAND_ERROR) 7062 rval = 1; 7063 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) 7064 /* device not in PCB table */ 7065 rval = 3; 7066 } 7067 7068 return (rval); 7069 } 7070 7071 /* 7072 * qla2x00_loop_resync 7073 * Resync with fibre channel devices. 7074 * 7075 * Input: 7076 * ha = adapter block pointer. 7077 * 7078 * Returns: 7079 * 0 = success 7080 */ 7081 int 7082 qla2x00_loop_resync(scsi_qla_host_t *vha) 7083 { 7084 int rval = QLA_SUCCESS; 7085 uint32_t wait_time; 7086 7087 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7088 if (vha->flags.online) { 7089 if (!(rval = qla2x00_fw_ready(vha))) { 7090 /* Wait at most MAX_TARGET RSCNs for a stable link. */ 7091 wait_time = 256; 7092 do { 7093 if (!IS_QLAFX00(vha->hw)) { 7094 /* 7095 * Issue a marker after FW becomes 7096 * ready. 7097 */ 7098 qla2x00_marker(vha, vha->hw->base_qpair, 7099 0, 0, MK_SYNC_ALL); 7100 vha->marker_needed = 0; 7101 } 7102 7103 /* Remap devices on Loop. */ 7104 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 7105 7106 if (IS_QLAFX00(vha->hw)) 7107 qlafx00_configure_devices(vha); 7108 else 7109 qla2x00_configure_loop(vha); 7110 7111 wait_time--; 7112 } while (!atomic_read(&vha->loop_down_timer) && 7113 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 7114 && wait_time && (test_bit(LOOP_RESYNC_NEEDED, 7115 &vha->dpc_flags))); 7116 } 7117 } 7118 7119 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 7120 return (QLA_FUNCTION_FAILED); 7121 7122 if (rval) 7123 ql_dbg(ql_dbg_disc, vha, 0x206c, 7124 "%s *** FAILED ***.\n", __func__); 7125 7126 return (rval); 7127 } 7128 7129 /* 7130 * qla2x00_perform_loop_resync 7131 * Description: This function will set the appropriate flags and call 7132 * qla2x00_loop_resync. If successful loop will be resynced 7133 * Arguments : scsi_qla_host_t pointer 7134 * returm : Success or Failure 7135 */ 7136 7137 int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) 7138 { 7139 int32_t rval = 0; 7140 7141 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { 7142 /*Configure the flags so that resync happens properly*/ 7143 atomic_set(&ha->loop_down_timer, 0); 7144 if (!(ha->device_flags & DFLG_NO_CABLE)) { 7145 atomic_set(&ha->loop_state, LOOP_UP); 7146 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); 7147 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 7148 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); 7149 7150 rval = qla2x00_loop_resync(ha); 7151 } else 7152 atomic_set(&ha->loop_state, LOOP_DEAD); 7153 7154 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); 7155 } 7156 7157 return rval; 7158 } 7159 7160 /* Assumes idc_lock always held on entry */ 7161 void 7162 qla83xx_reset_ownership(scsi_qla_host_t *vha) 7163 { 7164 struct qla_hw_data *ha = vha->hw; 7165 uint32_t drv_presence, drv_presence_mask; 7166 uint32_t dev_part_info1, dev_part_info2, class_type; 7167 uint32_t class_type_mask = 0x3; 7168 uint16_t fcoe_other_function = 0xffff, i; 7169 7170 if (IS_QLA8044(ha)) { 7171 drv_presence = qla8044_rd_direct(vha, 7172 QLA8044_CRB_DRV_ACTIVE_INDEX); 7173 dev_part_info1 = qla8044_rd_direct(vha, 7174 QLA8044_CRB_DEV_PART_INFO_INDEX); 7175 dev_part_info2 = qla8044_rd_direct(vha, 7176 QLA8044_CRB_DEV_PART_INFO2); 7177 } else { 7178 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 7179 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); 7180 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); 7181 } 7182 for (i = 0; i < 8; i++) { 7183 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); 7184 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 7185 (i != ha->portnum)) { 7186 fcoe_other_function = i; 7187 break; 7188 } 7189 } 7190 if (fcoe_other_function == 0xffff) { 7191 for (i = 0; i < 8; i++) { 7192 class_type = ((dev_part_info2 >> (i * 4)) & 7193 class_type_mask); 7194 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 7195 ((i + 8) != ha->portnum)) { 7196 fcoe_other_function = i + 8; 7197 break; 7198 } 7199 } 7200 } 7201 /* 7202 * Prepare drv-presence mask based on fcoe functions present. 7203 * However consider only valid physical fcoe function numbers (0-15). 7204 */ 7205 drv_presence_mask = ~((1 << (ha->portnum)) | 7206 ((fcoe_other_function == 0xffff) ? 7207 0 : (1 << (fcoe_other_function)))); 7208 7209 /* We are the reset owner iff: 7210 * - No other protocol drivers present. 7211 * - This is the lowest among fcoe functions. */ 7212 if (!(drv_presence & drv_presence_mask) && 7213 (ha->portnum < fcoe_other_function)) { 7214 ql_dbg(ql_dbg_p3p, vha, 0xb07f, 7215 "This host is Reset owner.\n"); 7216 ha->flags.nic_core_reset_owner = 1; 7217 } 7218 } 7219 7220 static int 7221 __qla83xx_set_drv_ack(scsi_qla_host_t *vha) 7222 { 7223 int rval = QLA_SUCCESS; 7224 struct qla_hw_data *ha = vha->hw; 7225 uint32_t drv_ack; 7226 7227 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 7228 if (rval == QLA_SUCCESS) { 7229 drv_ack |= (1 << ha->portnum); 7230 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 7231 } 7232 7233 return rval; 7234 } 7235 7236 static int 7237 __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) 7238 { 7239 int rval = QLA_SUCCESS; 7240 struct qla_hw_data *ha = vha->hw; 7241 uint32_t drv_ack; 7242 7243 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 7244 if (rval == QLA_SUCCESS) { 7245 drv_ack &= ~(1 << ha->portnum); 7246 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 7247 } 7248 7249 return rval; 7250 } 7251 7252 /* Assumes idc-lock always held on entry */ 7253 void 7254 qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) 7255 { 7256 struct qla_hw_data *ha = vha->hw; 7257 uint32_t idc_audit_reg = 0, duration_secs = 0; 7258 7259 switch (audit_type) { 7260 case IDC_AUDIT_TIMESTAMP: 7261 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); 7262 idc_audit_reg = (ha->portnum) | 7263 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); 7264 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 7265 break; 7266 7267 case IDC_AUDIT_COMPLETION: 7268 duration_secs = ((jiffies_to_msecs(jiffies) - 7269 jiffies_to_msecs(ha->idc_audit_ts)) / 1000); 7270 idc_audit_reg = (ha->portnum) | 7271 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); 7272 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 7273 break; 7274 7275 default: 7276 ql_log(ql_log_warn, vha, 0xb078, 7277 "Invalid audit type specified.\n"); 7278 break; 7279 } 7280 } 7281 7282 /* Assumes idc_lock always held on entry */ 7283 static int 7284 qla83xx_initiating_reset(scsi_qla_host_t *vha) 7285 { 7286 struct qla_hw_data *ha = vha->hw; 7287 uint32_t idc_control, dev_state; 7288 7289 __qla83xx_get_idc_control(vha, &idc_control); 7290 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { 7291 ql_log(ql_log_info, vha, 0xb080, 7292 "NIC Core reset has been disabled. idc-control=0x%x\n", 7293 idc_control); 7294 return QLA_FUNCTION_FAILED; 7295 } 7296 7297 /* Set NEED-RESET iff in READY state and we are the reset-owner */ 7298 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 7299 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { 7300 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 7301 QLA8XXX_DEV_NEED_RESET); 7302 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); 7303 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); 7304 } else { 7305 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", 7306 qdev_state(dev_state)); 7307 7308 /* SV: XXX: Is timeout required here? */ 7309 /* Wait for IDC state change READY -> NEED_RESET */ 7310 while (dev_state == QLA8XXX_DEV_READY) { 7311 qla83xx_idc_unlock(vha, 0); 7312 msleep(200); 7313 qla83xx_idc_lock(vha, 0); 7314 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 7315 } 7316 } 7317 7318 /* Send IDC ack by writing to drv-ack register */ 7319 __qla83xx_set_drv_ack(vha); 7320 7321 return QLA_SUCCESS; 7322 } 7323 7324 int 7325 __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) 7326 { 7327 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 7328 } 7329 7330 int 7331 __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) 7332 { 7333 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 7334 } 7335 7336 static int 7337 qla83xx_check_driver_presence(scsi_qla_host_t *vha) 7338 { 7339 uint32_t drv_presence = 0; 7340 struct qla_hw_data *ha = vha->hw; 7341 7342 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 7343 if (drv_presence & (1 << ha->portnum)) 7344 return QLA_SUCCESS; 7345 else 7346 return QLA_TEST_FAILED; 7347 } 7348 7349 int 7350 qla83xx_nic_core_reset(scsi_qla_host_t *vha) 7351 { 7352 int rval = QLA_SUCCESS; 7353 struct qla_hw_data *ha = vha->hw; 7354 7355 ql_dbg(ql_dbg_p3p, vha, 0xb058, 7356 "Entered %s().\n", __func__); 7357 7358 if (vha->device_flags & DFLG_DEV_FAILED) { 7359 ql_log(ql_log_warn, vha, 0xb059, 7360 "Device in unrecoverable FAILED state.\n"); 7361 return QLA_FUNCTION_FAILED; 7362 } 7363 7364 qla83xx_idc_lock(vha, 0); 7365 7366 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { 7367 ql_log(ql_log_warn, vha, 0xb05a, 7368 "Function=0x%x has been removed from IDC participation.\n", 7369 ha->portnum); 7370 rval = QLA_FUNCTION_FAILED; 7371 goto exit; 7372 } 7373 7374 qla83xx_reset_ownership(vha); 7375 7376 rval = qla83xx_initiating_reset(vha); 7377 7378 /* 7379 * Perform reset if we are the reset-owner, 7380 * else wait till IDC state changes to READY/FAILED. 7381 */ 7382 if (rval == QLA_SUCCESS) { 7383 rval = qla83xx_idc_state_handler(vha); 7384 7385 if (rval == QLA_SUCCESS) 7386 ha->flags.nic_core_hung = 0; 7387 __qla83xx_clear_drv_ack(vha); 7388 } 7389 7390 exit: 7391 qla83xx_idc_unlock(vha, 0); 7392 7393 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); 7394 7395 return rval; 7396 } 7397 7398 int 7399 qla2xxx_mctp_dump(scsi_qla_host_t *vha) 7400 { 7401 struct qla_hw_data *ha = vha->hw; 7402 int rval = QLA_FUNCTION_FAILED; 7403 7404 if (!IS_MCTP_CAPABLE(ha)) { 7405 /* This message can be removed from the final version */ 7406 ql_log(ql_log_info, vha, 0x506d, 7407 "This board is not MCTP capable\n"); 7408 return rval; 7409 } 7410 7411 if (!ha->mctp_dump) { 7412 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, 7413 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); 7414 7415 if (!ha->mctp_dump) { 7416 ql_log(ql_log_warn, vha, 0x506e, 7417 "Failed to allocate memory for mctp dump\n"); 7418 return rval; 7419 } 7420 } 7421 7422 #define MCTP_DUMP_STR_ADDR 0x00000000 7423 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, 7424 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); 7425 if (rval != QLA_SUCCESS) { 7426 ql_log(ql_log_warn, vha, 0x506f, 7427 "Failed to capture mctp dump\n"); 7428 } else { 7429 ql_log(ql_log_info, vha, 0x5070, 7430 "Mctp dump capture for host (%ld/%p).\n", 7431 vha->host_no, ha->mctp_dump); 7432 ha->mctp_dumped = 1; 7433 } 7434 7435 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { 7436 ha->flags.nic_core_reset_hdlr_active = 1; 7437 rval = qla83xx_restart_nic_firmware(vha); 7438 if (rval) 7439 /* NIC Core reset failed. */ 7440 ql_log(ql_log_warn, vha, 0x5071, 7441 "Failed to restart nic firmware\n"); 7442 else 7443 ql_dbg(ql_dbg_p3p, vha, 0xb084, 7444 "Restarted NIC firmware successfully.\n"); 7445 ha->flags.nic_core_reset_hdlr_active = 0; 7446 } 7447 7448 return rval; 7449 7450 } 7451 7452 /* 7453 * qla2x00_quiesce_io 7454 * Description: This function will block the new I/Os 7455 * Its not aborting any I/Os as context 7456 * is not destroyed during quiescence 7457 * Arguments: scsi_qla_host_t 7458 * return : void 7459 */ 7460 void 7461 qla2x00_quiesce_io(scsi_qla_host_t *vha) 7462 { 7463 struct qla_hw_data *ha = vha->hw; 7464 struct scsi_qla_host *vp, *tvp; 7465 unsigned long flags; 7466 7467 ql_dbg(ql_dbg_dpc, vha, 0x401d, 7468 "Quiescing I/O - ha=%p.\n", ha); 7469 7470 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); 7471 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 7472 atomic_set(&vha->loop_state, LOOP_DOWN); 7473 qla2x00_mark_all_devices_lost(vha); 7474 7475 spin_lock_irqsave(&ha->vport_slock, flags); 7476 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7477 atomic_inc(&vp->vref_count); 7478 spin_unlock_irqrestore(&ha->vport_slock, flags); 7479 7480 qla2x00_mark_all_devices_lost(vp); 7481 7482 spin_lock_irqsave(&ha->vport_slock, flags); 7483 atomic_dec(&vp->vref_count); 7484 } 7485 spin_unlock_irqrestore(&ha->vport_slock, flags); 7486 } else { 7487 if (!atomic_read(&vha->loop_down_timer)) 7488 atomic_set(&vha->loop_down_timer, 7489 LOOP_DOWN_TIME); 7490 } 7491 /* Wait for pending cmds to complete */ 7492 WARN_ON_ONCE(qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) 7493 != QLA_SUCCESS); 7494 } 7495 7496 void 7497 qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) 7498 { 7499 struct qla_hw_data *ha = vha->hw; 7500 struct scsi_qla_host *vp, *tvp; 7501 unsigned long flags; 7502 fc_port_t *fcport; 7503 u16 i; 7504 7505 /* For ISP82XX, driver waits for completion of the commands. 7506 * online flag should be set. 7507 */ 7508 if (!(IS_P3P_TYPE(ha))) 7509 vha->flags.online = 0; 7510 ha->flags.chip_reset_done = 0; 7511 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 7512 vha->qla_stats.total_isp_aborts++; 7513 7514 ql_log(ql_log_info, vha, 0x00af, 7515 "Performing ISP error recovery - ha=%p.\n", ha); 7516 7517 ha->flags.purge_mbox = 1; 7518 /* For ISP82XX, reset_chip is just disabling interrupts. 7519 * Driver waits for the completion of the commands. 7520 * the interrupts need to be enabled. 7521 */ 7522 if (!(IS_P3P_TYPE(ha))) 7523 ha->isp_ops->reset_chip(vha); 7524 7525 ha->link_data_rate = PORT_SPEED_UNKNOWN; 7526 SAVE_TOPO(ha); 7527 ha->flags.rida_fmt2 = 0; 7528 ha->flags.n2n_ae = 0; 7529 ha->flags.lip_ae = 0; 7530 ha->current_topology = 0; 7531 QLA_FW_STOPPED(ha); 7532 ha->flags.fw_init_done = 0; 7533 ha->chip_reset++; 7534 ha->base_qpair->chip_reset = ha->chip_reset; 7535 ha->base_qpair->cmd_cnt = ha->base_qpair->cmd_completion_cnt = 0; 7536 ha->base_qpair->prev_completion_cnt = 0; 7537 for (i = 0; i < ha->max_qpairs; i++) { 7538 if (ha->queue_pair_map[i]) { 7539 ha->queue_pair_map[i]->chip_reset = 7540 ha->base_qpair->chip_reset; 7541 ha->queue_pair_map[i]->cmd_cnt = 7542 ha->queue_pair_map[i]->cmd_completion_cnt = 0; 7543 ha->base_qpair->prev_completion_cnt = 0; 7544 } 7545 } 7546 7547 /* purge MBox commands */ 7548 spin_lock_irqsave(&ha->hardware_lock, flags); 7549 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) { 7550 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 7551 complete(&ha->mbx_intr_comp); 7552 } 7553 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7554 7555 i = 0; 7556 while (atomic_read(&ha->num_pend_mbx_stage2) || 7557 atomic_read(&ha->num_pend_mbx_stage1)) { 7558 msleep(20); 7559 i++; 7560 if (i > 50) 7561 break; 7562 } 7563 ha->flags.purge_mbox = 0; 7564 7565 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 7566 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 7567 atomic_set(&vha->loop_state, LOOP_DOWN); 7568 qla2x00_mark_all_devices_lost(vha); 7569 7570 spin_lock_irqsave(&ha->vport_slock, flags); 7571 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7572 atomic_inc(&vp->vref_count); 7573 spin_unlock_irqrestore(&ha->vport_slock, flags); 7574 7575 qla2x00_mark_all_devices_lost(vp); 7576 7577 spin_lock_irqsave(&ha->vport_slock, flags); 7578 atomic_dec(&vp->vref_count); 7579 } 7580 spin_unlock_irqrestore(&ha->vport_slock, flags); 7581 } else { 7582 if (!atomic_read(&vha->loop_down_timer)) 7583 atomic_set(&vha->loop_down_timer, 7584 LOOP_DOWN_TIME); 7585 } 7586 7587 /* Clear all async request states across all VPs. */ 7588 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7589 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7590 fcport->scan_state = 0; 7591 } 7592 spin_lock_irqsave(&ha->vport_slock, flags); 7593 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7594 atomic_inc(&vp->vref_count); 7595 spin_unlock_irqrestore(&ha->vport_slock, flags); 7596 7597 list_for_each_entry(fcport, &vp->vp_fcports, list) 7598 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7599 7600 spin_lock_irqsave(&ha->vport_slock, flags); 7601 atomic_dec(&vp->vref_count); 7602 } 7603 spin_unlock_irqrestore(&ha->vport_slock, flags); 7604 7605 /* Make sure for ISP 82XX IO DMA is complete */ 7606 if (IS_P3P_TYPE(ha)) { 7607 qla82xx_chip_reset_cleanup(vha); 7608 ql_log(ql_log_info, vha, 0x00b4, 7609 "Done chip reset cleanup.\n"); 7610 7611 /* Done waiting for pending commands. Reset online flag */ 7612 vha->flags.online = 0; 7613 } 7614 7615 /* Requeue all commands in outstanding command list. */ 7616 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 7617 /* memory barrier */ 7618 wmb(); 7619 } 7620 7621 /* 7622 * qla2x00_abort_isp 7623 * Resets ISP and aborts all outstanding commands. 7624 * 7625 * Input: 7626 * ha = adapter block pointer. 7627 * 7628 * Returns: 7629 * 0 = success 7630 */ 7631 int 7632 qla2x00_abort_isp(scsi_qla_host_t *vha) 7633 { 7634 uint8_t status = 0; 7635 struct qla_hw_data *ha = vha->hw; 7636 struct scsi_qla_host *vp, *tvp; 7637 struct req_que *req = ha->req_q_map[0]; 7638 unsigned long flags; 7639 fc_port_t *fcport; 7640 7641 if (vha->flags.online) { 7642 qla2x00_abort_isp_cleanup(vha); 7643 7644 vha->dport_status |= DPORT_DIAG_CHIP_RESET_IN_PROGRESS; 7645 vha->dport_status &= ~DPORT_DIAG_IN_PROGRESS; 7646 7647 if (vha->hw->flags.port_isolated) 7648 return status; 7649 7650 if (qla2x00_isp_reg_stat(ha)) { 7651 ql_log(ql_log_info, vha, 0x803f, 7652 "ISP Abort - ISP reg disconnect, exiting.\n"); 7653 return status; 7654 } 7655 7656 if (test_and_clear_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags)) { 7657 ha->flags.chip_reset_done = 1; 7658 vha->flags.online = 1; 7659 status = 0; 7660 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7661 return status; 7662 } 7663 7664 if (IS_QLA8031(ha)) { 7665 ql_dbg(ql_dbg_p3p, vha, 0xb05c, 7666 "Clearing fcoe driver presence.\n"); 7667 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) 7668 ql_dbg(ql_dbg_p3p, vha, 0xb073, 7669 "Error while clearing DRV-Presence.\n"); 7670 } 7671 7672 if (unlikely(pci_channel_offline(ha->pdev) && 7673 ha->flags.pci_channel_io_perm_failure)) { 7674 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7675 status = 0; 7676 return status; 7677 } 7678 7679 switch (vha->qlini_mode) { 7680 case QLA2XXX_INI_MODE_DISABLED: 7681 if (!qla_tgt_mode_enabled(vha)) 7682 return 0; 7683 break; 7684 case QLA2XXX_INI_MODE_DUAL: 7685 if (!qla_dual_mode_enabled(vha) && 7686 !qla_ini_mode_enabled(vha)) 7687 return 0; 7688 break; 7689 case QLA2XXX_INI_MODE_ENABLED: 7690 default: 7691 break; 7692 } 7693 7694 ha->isp_ops->get_flash_version(vha, req->ring); 7695 7696 if (qla2x00_isp_reg_stat(ha)) { 7697 ql_log(ql_log_info, vha, 0x803f, 7698 "ISP Abort - ISP reg disconnect pre nvram config, exiting.\n"); 7699 return status; 7700 } 7701 ha->isp_ops->nvram_config(vha); 7702 7703 if (qla2x00_isp_reg_stat(ha)) { 7704 ql_log(ql_log_info, vha, 0x803f, 7705 "ISP Abort - ISP reg disconnect post nvmram config, exiting.\n"); 7706 return status; 7707 } 7708 7709 /* User may have updated [fcp|nvme] prefer in flash */ 7710 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7711 if (NVME_PRIORITY(ha, fcport)) 7712 fcport->do_prli_nvme = 1; 7713 else 7714 fcport->do_prli_nvme = 0; 7715 } 7716 7717 if (!qla2x00_restart_isp(vha)) { 7718 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7719 7720 if (!atomic_read(&vha->loop_down_timer)) { 7721 /* 7722 * Issue marker command only when we are going 7723 * to start the I/O . 7724 */ 7725 vha->marker_needed = 1; 7726 } 7727 7728 vha->flags.online = 1; 7729 7730 ha->isp_ops->enable_intrs(ha); 7731 7732 ha->isp_abort_cnt = 0; 7733 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7734 7735 if (IS_QLA81XX(ha) || IS_QLA8031(ha)) 7736 qla2x00_get_fw_version(vha); 7737 7738 } else { /* failed the ISP abort */ 7739 vha->flags.online = 1; 7740 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 7741 if (ha->isp_abort_cnt == 0) { 7742 ql_log(ql_log_fatal, vha, 0x8035, 7743 "ISP error recover failed - " 7744 "board disabled.\n"); 7745 /* 7746 * The next call disables the board 7747 * completely. 7748 */ 7749 qla2x00_abort_isp_cleanup(vha); 7750 vha->flags.online = 0; 7751 clear_bit(ISP_ABORT_RETRY, 7752 &vha->dpc_flags); 7753 status = 0; 7754 } else { /* schedule another ISP abort */ 7755 ha->isp_abort_cnt--; 7756 ql_dbg(ql_dbg_taskm, vha, 0x8020, 7757 "ISP abort - retry remaining %d.\n", 7758 ha->isp_abort_cnt); 7759 status = 1; 7760 } 7761 } else { 7762 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 7763 ql_dbg(ql_dbg_taskm, vha, 0x8021, 7764 "ISP error recovery - retrying (%d) " 7765 "more times.\n", ha->isp_abort_cnt); 7766 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7767 status = 1; 7768 } 7769 } 7770 7771 } 7772 7773 if (vha->hw->flags.port_isolated) { 7774 qla2x00_abort_isp_cleanup(vha); 7775 return status; 7776 } 7777 7778 if (!status) { 7779 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); 7780 qla2x00_configure_hba(vha); 7781 spin_lock_irqsave(&ha->vport_slock, flags); 7782 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7783 if (vp->vp_idx) { 7784 atomic_inc(&vp->vref_count); 7785 spin_unlock_irqrestore(&ha->vport_slock, flags); 7786 7787 /* User may have updated [fcp|nvme] prefer in flash */ 7788 list_for_each_entry(fcport, &vp->vp_fcports, list) { 7789 if (NVME_PRIORITY(ha, fcport)) 7790 fcport->do_prli_nvme = 1; 7791 else 7792 fcport->do_prli_nvme = 0; 7793 } 7794 7795 qla2x00_vp_abort_isp(vp); 7796 7797 spin_lock_irqsave(&ha->vport_slock, flags); 7798 atomic_dec(&vp->vref_count); 7799 } 7800 } 7801 spin_unlock_irqrestore(&ha->vport_slock, flags); 7802 7803 if (IS_QLA8031(ha)) { 7804 ql_dbg(ql_dbg_p3p, vha, 0xb05d, 7805 "Setting back fcoe driver presence.\n"); 7806 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) 7807 ql_dbg(ql_dbg_p3p, vha, 0xb074, 7808 "Error while setting DRV-Presence.\n"); 7809 } 7810 } else { 7811 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", 7812 __func__); 7813 } 7814 7815 return(status); 7816 } 7817 7818 /* 7819 * qla2x00_restart_isp 7820 * restarts the ISP after a reset 7821 * 7822 * Input: 7823 * ha = adapter block pointer. 7824 * 7825 * Returns: 7826 * 0 = success 7827 */ 7828 static int 7829 qla2x00_restart_isp(scsi_qla_host_t *vha) 7830 { 7831 int status; 7832 struct qla_hw_data *ha = vha->hw; 7833 7834 /* If firmware needs to be loaded */ 7835 if (qla2x00_isp_firmware(vha)) { 7836 vha->flags.online = 0; 7837 status = ha->isp_ops->chip_diag(vha); 7838 if (status) 7839 return status; 7840 status = qla2x00_setup_chip(vha); 7841 if (status) 7842 return status; 7843 } 7844 7845 status = qla2x00_init_rings(vha); 7846 if (status) 7847 return status; 7848 7849 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7850 ha->flags.chip_reset_done = 1; 7851 7852 /* Initialize the queues in use */ 7853 qla25xx_init_queues(ha); 7854 7855 status = qla2x00_fw_ready(vha); 7856 if (status) { 7857 /* if no cable then assume it's good */ 7858 return vha->device_flags & DFLG_NO_CABLE ? 0 : status; 7859 } 7860 7861 /* Issue a marker after FW becomes ready. */ 7862 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 7863 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 7864 7865 return 0; 7866 } 7867 7868 static int 7869 qla25xx_init_queues(struct qla_hw_data *ha) 7870 { 7871 struct rsp_que *rsp = NULL; 7872 struct req_que *req = NULL; 7873 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7874 int ret = -1; 7875 int i; 7876 7877 for (i = 1; i < ha->max_rsp_queues; i++) { 7878 rsp = ha->rsp_q_map[i]; 7879 if (rsp && test_bit(i, ha->rsp_qid_map)) { 7880 rsp->options &= ~BIT_0; 7881 ret = qla25xx_init_rsp_que(base_vha, rsp); 7882 if (ret != QLA_SUCCESS) 7883 ql_dbg(ql_dbg_init, base_vha, 0x00ff, 7884 "%s Rsp que: %d init failed.\n", 7885 __func__, rsp->id); 7886 else 7887 ql_dbg(ql_dbg_init, base_vha, 0x0100, 7888 "%s Rsp que: %d inited.\n", 7889 __func__, rsp->id); 7890 } 7891 } 7892 for (i = 1; i < ha->max_req_queues; i++) { 7893 req = ha->req_q_map[i]; 7894 if (req && test_bit(i, ha->req_qid_map)) { 7895 /* Clear outstanding commands array. */ 7896 req->options &= ~BIT_0; 7897 ret = qla25xx_init_req_que(base_vha, req); 7898 if (ret != QLA_SUCCESS) 7899 ql_dbg(ql_dbg_init, base_vha, 0x0101, 7900 "%s Req que: %d init failed.\n", 7901 __func__, req->id); 7902 else 7903 ql_dbg(ql_dbg_init, base_vha, 0x0102, 7904 "%s Req que: %d inited.\n", 7905 __func__, req->id); 7906 } 7907 } 7908 return ret; 7909 } 7910 7911 /* 7912 * qla2x00_reset_adapter 7913 * Reset adapter. 7914 * 7915 * Input: 7916 * ha = adapter block pointer. 7917 */ 7918 int 7919 qla2x00_reset_adapter(scsi_qla_host_t *vha) 7920 { 7921 unsigned long flags = 0; 7922 struct qla_hw_data *ha = vha->hw; 7923 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7924 7925 vha->flags.online = 0; 7926 ha->isp_ops->disable_intrs(ha); 7927 7928 spin_lock_irqsave(&ha->hardware_lock, flags); 7929 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 7930 rd_reg_word(®->hccr); /* PCI Posting. */ 7931 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 7932 rd_reg_word(®->hccr); /* PCI Posting. */ 7933 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7934 7935 return QLA_SUCCESS; 7936 } 7937 7938 int 7939 qla24xx_reset_adapter(scsi_qla_host_t *vha) 7940 { 7941 unsigned long flags = 0; 7942 struct qla_hw_data *ha = vha->hw; 7943 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 7944 7945 if (IS_P3P_TYPE(ha)) 7946 return QLA_SUCCESS; 7947 7948 vha->flags.online = 0; 7949 ha->isp_ops->disable_intrs(ha); 7950 7951 spin_lock_irqsave(&ha->hardware_lock, flags); 7952 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 7953 rd_reg_dword(®->hccr); 7954 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 7955 rd_reg_dword(®->hccr); 7956 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7957 7958 if (IS_NOPOLLING_TYPE(ha)) 7959 ha->isp_ops->enable_intrs(ha); 7960 7961 return QLA_SUCCESS; 7962 } 7963 7964 /* On sparc systems, obtain port and node WWN from firmware 7965 * properties. 7966 */ 7967 static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, 7968 struct nvram_24xx *nv) 7969 { 7970 #ifdef CONFIG_SPARC 7971 struct qla_hw_data *ha = vha->hw; 7972 struct pci_dev *pdev = ha->pdev; 7973 struct device_node *dp = pci_device_to_OF_node(pdev); 7974 const u8 *val; 7975 int len; 7976 7977 val = of_get_property(dp, "port-wwn", &len); 7978 if (val && len >= WWN_SIZE) 7979 memcpy(nv->port_name, val, WWN_SIZE); 7980 7981 val = of_get_property(dp, "node-wwn", &len); 7982 if (val && len >= WWN_SIZE) 7983 memcpy(nv->node_name, val, WWN_SIZE); 7984 #endif 7985 } 7986 7987 int 7988 qla24xx_nvram_config(scsi_qla_host_t *vha) 7989 { 7990 int rval; 7991 struct init_cb_24xx *icb; 7992 struct nvram_24xx *nv; 7993 __le32 *dptr; 7994 uint8_t *dptr1, *dptr2; 7995 uint32_t chksum; 7996 uint16_t cnt; 7997 struct qla_hw_data *ha = vha->hw; 7998 7999 rval = QLA_SUCCESS; 8000 icb = (struct init_cb_24xx *)ha->init_cb; 8001 nv = ha->nvram; 8002 8003 /* Determine NVRAM starting address. */ 8004 if (ha->port_no == 0) { 8005 ha->nvram_base = FA_NVRAM_FUNC0_ADDR; 8006 ha->vpd_base = FA_NVRAM_VPD0_ADDR; 8007 } else { 8008 ha->nvram_base = FA_NVRAM_FUNC1_ADDR; 8009 ha->vpd_base = FA_NVRAM_VPD1_ADDR; 8010 } 8011 8012 ha->nvram_size = sizeof(*nv); 8013 ha->vpd_size = FA_NVRAM_VPD_SIZE; 8014 8015 /* Get VPD data into cache */ 8016 ha->vpd = ha->nvram + VPD_OFFSET; 8017 ha->isp_ops->read_nvram(vha, ha->vpd, 8018 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); 8019 8020 /* Get NVRAM data into cache and calculate checksum. */ 8021 dptr = (__force __le32 *)nv; 8022 ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size); 8023 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 8024 chksum += le32_to_cpu(*dptr); 8025 8026 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, 8027 "Contents of NVRAM\n"); 8028 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, 8029 nv, ha->nvram_size); 8030 8031 /* Bad NVRAM data, set defaults parameters. */ 8032 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 8033 le16_to_cpu(nv->nvram_version) < ICB_VERSION) { 8034 /* Reset NVRAM data. */ 8035 ql_log(ql_log_warn, vha, 0x006b, 8036 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n", 8037 chksum, nv->id, nv->nvram_version); 8038 ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv)); 8039 ql_log(ql_log_warn, vha, 0x006c, 8040 "Falling back to functioning (yet invalid -- WWPN) " 8041 "defaults.\n"); 8042 8043 /* 8044 * Set default initialization control block. 8045 */ 8046 memset(nv, 0, ha->nvram_size); 8047 nv->nvram_version = cpu_to_le16(ICB_VERSION); 8048 nv->version = cpu_to_le16(ICB_VERSION); 8049 nv->frame_payload_size = cpu_to_le16(2048); 8050 nv->execution_throttle = cpu_to_le16(0xFFFF); 8051 nv->exchange_count = cpu_to_le16(0); 8052 nv->hard_address = cpu_to_le16(124); 8053 nv->port_name[0] = 0x21; 8054 nv->port_name[1] = 0x00 + ha->port_no + 1; 8055 nv->port_name[2] = 0x00; 8056 nv->port_name[3] = 0xe0; 8057 nv->port_name[4] = 0x8b; 8058 nv->port_name[5] = 0x1c; 8059 nv->port_name[6] = 0x55; 8060 nv->port_name[7] = 0x86; 8061 nv->node_name[0] = 0x20; 8062 nv->node_name[1] = 0x00; 8063 nv->node_name[2] = 0x00; 8064 nv->node_name[3] = 0xe0; 8065 nv->node_name[4] = 0x8b; 8066 nv->node_name[5] = 0x1c; 8067 nv->node_name[6] = 0x55; 8068 nv->node_name[7] = 0x86; 8069 qla24xx_nvram_wwn_from_ofw(vha, nv); 8070 nv->login_retry_count = cpu_to_le16(8); 8071 nv->interrupt_delay_timer = cpu_to_le16(0); 8072 nv->login_timeout = cpu_to_le16(0); 8073 nv->firmware_options_1 = 8074 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 8075 nv->firmware_options_2 = cpu_to_le32(2 << 4); 8076 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 8077 nv->firmware_options_3 = cpu_to_le32(2 << 13); 8078 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 8079 nv->efi_parameters = cpu_to_le32(0); 8080 nv->reset_delay = 5; 8081 nv->max_luns_per_target = cpu_to_le16(128); 8082 nv->port_down_retry_count = cpu_to_le16(30); 8083 nv->link_down_timeout = cpu_to_le16(30); 8084 8085 rval = 1; 8086 } 8087 8088 if (qla_tgt_mode_enabled(vha)) { 8089 /* Don't enable full login after initial LIP */ 8090 nv->firmware_options_1 &= cpu_to_le32(~BIT_13); 8091 /* Don't enable LIP full login for initiator */ 8092 nv->host_p &= cpu_to_le32(~BIT_10); 8093 } 8094 8095 qlt_24xx_config_nvram_stage1(vha, nv); 8096 8097 /* Reset Initialization control block */ 8098 memset(icb, 0, ha->init_cb_size); 8099 8100 /* Copy 1st segment. */ 8101 dptr1 = (uint8_t *)icb; 8102 dptr2 = (uint8_t *)&nv->version; 8103 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 8104 while (cnt--) 8105 *dptr1++ = *dptr2++; 8106 8107 icb->login_retry_count = nv->login_retry_count; 8108 icb->link_down_on_nos = nv->link_down_on_nos; 8109 8110 /* Copy 2nd segment. */ 8111 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 8112 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 8113 cnt = (uint8_t *)&icb->reserved_3 - 8114 (uint8_t *)&icb->interrupt_delay_timer; 8115 while (cnt--) 8116 *dptr1++ = *dptr2++; 8117 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 8118 /* 8119 * Setup driver NVRAM options. 8120 */ 8121 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 8122 "QLA2462"); 8123 8124 qlt_24xx_config_nvram_stage2(vha, icb); 8125 8126 if (nv->host_p & cpu_to_le32(BIT_15)) { 8127 /* Use alternate WWN? */ 8128 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 8129 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 8130 } 8131 8132 /* Prepare nodename */ 8133 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 8134 /* 8135 * Firmware will apply the following mask if the nodename was 8136 * not provided. 8137 */ 8138 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 8139 icb->node_name[0] &= 0xF0; 8140 } 8141 8142 /* Set host adapter parameters. */ 8143 ha->flags.disable_risc_code_load = 0; 8144 ha->flags.enable_lip_reset = 0; 8145 ha->flags.enable_lip_full_login = 8146 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0; 8147 ha->flags.enable_target_reset = 8148 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0; 8149 ha->flags.enable_led_scheme = 0; 8150 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0; 8151 8152 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 8153 (BIT_6 | BIT_5 | BIT_4)) >> 4; 8154 8155 memcpy(ha->fw_seriallink_options24, nv->seriallink_options, 8156 sizeof(ha->fw_seriallink_options24)); 8157 8158 /* save HBA serial number */ 8159 ha->serial0 = icb->port_name[5]; 8160 ha->serial1 = icb->port_name[6]; 8161 ha->serial2 = icb->port_name[7]; 8162 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 8163 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 8164 8165 icb->execution_throttle = cpu_to_le16(0xFFFF); 8166 8167 ha->retry_count = le16_to_cpu(nv->login_retry_count); 8168 8169 /* Set minimum login_timeout to 4 seconds. */ 8170 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 8171 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 8172 if (le16_to_cpu(nv->login_timeout) < 4) 8173 nv->login_timeout = cpu_to_le16(4); 8174 ha->login_timeout = le16_to_cpu(nv->login_timeout); 8175 8176 /* Set minimum RATOV to 100 tenths of a second. */ 8177 ha->r_a_tov = 100; 8178 8179 ha->loop_reset_delay = nv->reset_delay; 8180 8181 /* Link Down Timeout = 0: 8182 * 8183 * When Port Down timer expires we will start returning 8184 * I/O's to OS with "DID_NO_CONNECT". 8185 * 8186 * Link Down Timeout != 0: 8187 * 8188 * The driver waits for the link to come up after link down 8189 * before returning I/Os to OS with "DID_NO_CONNECT". 8190 */ 8191 if (le16_to_cpu(nv->link_down_timeout) == 0) { 8192 ha->loop_down_abort_time = 8193 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 8194 } else { 8195 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 8196 ha->loop_down_abort_time = 8197 (LOOP_DOWN_TIME - ha->link_down_timeout); 8198 } 8199 8200 /* Need enough time to try and get the port back. */ 8201 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 8202 if (qlport_down_retry) 8203 ha->port_down_retry_count = qlport_down_retry; 8204 8205 /* Set login_retry_count */ 8206 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 8207 if (ha->port_down_retry_count == 8208 le16_to_cpu(nv->port_down_retry_count) && 8209 ha->port_down_retry_count > 3) 8210 ha->login_retry_count = ha->port_down_retry_count; 8211 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 8212 ha->login_retry_count = ha->port_down_retry_count; 8213 if (ql2xloginretrycount) 8214 ha->login_retry_count = ql2xloginretrycount; 8215 8216 /* N2N: driver will initiate Login instead of FW */ 8217 icb->firmware_options_3 |= cpu_to_le32(BIT_8); 8218 8219 /* Enable ZIO. */ 8220 if (!vha->flags.init_done) { 8221 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 8222 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 8223 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 8224 le16_to_cpu(icb->interrupt_delay_timer) : 2; 8225 } 8226 icb->firmware_options_2 &= cpu_to_le32( 8227 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 8228 if (ha->zio_mode != QLA_ZIO_DISABLED) { 8229 ha->zio_mode = QLA_ZIO_MODE_6; 8230 8231 ql_log(ql_log_info, vha, 0x006f, 8232 "ZIO mode %d enabled; timer delay (%d us).\n", 8233 ha->zio_mode, ha->zio_timer * 100); 8234 8235 icb->firmware_options_2 |= cpu_to_le32( 8236 (uint32_t)ha->zio_mode); 8237 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 8238 } 8239 8240 if (rval) { 8241 ql_log(ql_log_warn, vha, 0x0070, 8242 "NVRAM configuration failed.\n"); 8243 } 8244 return (rval); 8245 } 8246 8247 static void 8248 qla27xx_print_image(struct scsi_qla_host *vha, char *name, 8249 struct qla27xx_image_status *image_status) 8250 { 8251 ql_dbg(ql_dbg_init, vha, 0x018b, 8252 "%s %s: mask=%#02x gen=%#04x ver=%u.%u map=%#01x sum=%#08x sig=%#08x\n", 8253 name, "status", 8254 image_status->image_status_mask, 8255 le16_to_cpu(image_status->generation), 8256 image_status->ver_major, 8257 image_status->ver_minor, 8258 image_status->bitmap, 8259 le32_to_cpu(image_status->checksum), 8260 le32_to_cpu(image_status->signature)); 8261 } 8262 8263 static bool 8264 qla28xx_check_aux_image_status_signature( 8265 struct qla27xx_image_status *image_status) 8266 { 8267 ulong signature = le32_to_cpu(image_status->signature); 8268 8269 return signature != QLA28XX_AUX_IMG_STATUS_SIGN; 8270 } 8271 8272 static bool 8273 qla27xx_check_image_status_signature(struct qla27xx_image_status *image_status) 8274 { 8275 ulong signature = le32_to_cpu(image_status->signature); 8276 8277 return 8278 signature != QLA27XX_IMG_STATUS_SIGN && 8279 signature != QLA28XX_IMG_STATUS_SIGN; 8280 } 8281 8282 static ulong 8283 qla27xx_image_status_checksum(struct qla27xx_image_status *image_status) 8284 { 8285 __le32 *p = (__force __le32 *)image_status; 8286 uint n = sizeof(*image_status) / sizeof(*p); 8287 uint32_t sum = 0; 8288 8289 for ( ; n--; p++) 8290 sum += le32_to_cpup(p); 8291 8292 return sum; 8293 } 8294 8295 static inline uint 8296 qla28xx_component_bitmask(struct qla27xx_image_status *aux, uint bitmask) 8297 { 8298 return aux->bitmap & bitmask ? 8299 QLA27XX_SECONDARY_IMAGE : QLA27XX_PRIMARY_IMAGE; 8300 } 8301 8302 static void 8303 qla28xx_component_status( 8304 struct active_regions *active_regions, struct qla27xx_image_status *aux) 8305 { 8306 active_regions->aux.board_config = 8307 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_BOARD_CONFIG); 8308 8309 active_regions->aux.vpd_nvram = 8310 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_VPD_NVRAM); 8311 8312 active_regions->aux.npiv_config_0_1 = 8313 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_0_1); 8314 8315 active_regions->aux.npiv_config_2_3 = 8316 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3); 8317 8318 active_regions->aux.nvme_params = 8319 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NVME_PARAMS); 8320 } 8321 8322 static int 8323 qla27xx_compare_image_generation( 8324 struct qla27xx_image_status *pri_image_status, 8325 struct qla27xx_image_status *sec_image_status) 8326 { 8327 /* calculate generation delta as uint16 (this accounts for wrap) */ 8328 int16_t delta = 8329 le16_to_cpu(pri_image_status->generation) - 8330 le16_to_cpu(sec_image_status->generation); 8331 8332 ql_dbg(ql_dbg_init, NULL, 0x0180, "generation delta = %d\n", delta); 8333 8334 return delta; 8335 } 8336 8337 void 8338 qla28xx_get_aux_images( 8339 struct scsi_qla_host *vha, struct active_regions *active_regions) 8340 { 8341 struct qla_hw_data *ha = vha->hw; 8342 struct qla27xx_image_status pri_aux_image_status, sec_aux_image_status; 8343 bool valid_pri_image = false, valid_sec_image = false; 8344 bool active_pri_image = false, active_sec_image = false; 8345 int rc; 8346 8347 if (!ha->flt_region_aux_img_status_pri) { 8348 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary aux image not addressed\n"); 8349 goto check_sec_image; 8350 } 8351 8352 rc = qla24xx_read_flash_data(vha, (uint32_t *)&pri_aux_image_status, 8353 ha->flt_region_aux_img_status_pri, 8354 sizeof(pri_aux_image_status) >> 2); 8355 if (rc) { 8356 ql_log(ql_log_info, vha, 0x01a1, 8357 "Unable to read Primary aux image(%x).\n", rc); 8358 goto check_sec_image; 8359 } 8360 qla27xx_print_image(vha, "Primary aux image", &pri_aux_image_status); 8361 8362 if (qla28xx_check_aux_image_status_signature(&pri_aux_image_status)) { 8363 ql_dbg(ql_dbg_init, vha, 0x018b, 8364 "Primary aux image signature (%#x) not valid\n", 8365 le32_to_cpu(pri_aux_image_status.signature)); 8366 goto check_sec_image; 8367 } 8368 8369 if (qla27xx_image_status_checksum(&pri_aux_image_status)) { 8370 ql_dbg(ql_dbg_init, vha, 0x018c, 8371 "Primary aux image checksum failed\n"); 8372 goto check_sec_image; 8373 } 8374 8375 valid_pri_image = true; 8376 8377 if (pri_aux_image_status.image_status_mask & 1) { 8378 ql_dbg(ql_dbg_init, vha, 0x018d, 8379 "Primary aux image is active\n"); 8380 active_pri_image = true; 8381 } 8382 8383 check_sec_image: 8384 if (!ha->flt_region_aux_img_status_sec) { 8385 ql_dbg(ql_dbg_init, vha, 0x018a, 8386 "Secondary aux image not addressed\n"); 8387 goto check_valid_image; 8388 } 8389 8390 rc = qla24xx_read_flash_data(vha, (uint32_t *)&sec_aux_image_status, 8391 ha->flt_region_aux_img_status_sec, 8392 sizeof(sec_aux_image_status) >> 2); 8393 if (rc) { 8394 ql_log(ql_log_info, vha, 0x01a2, 8395 "Unable to read Secondary aux image(%x).\n", rc); 8396 goto check_valid_image; 8397 } 8398 8399 qla27xx_print_image(vha, "Secondary aux image", &sec_aux_image_status); 8400 8401 if (qla28xx_check_aux_image_status_signature(&sec_aux_image_status)) { 8402 ql_dbg(ql_dbg_init, vha, 0x018b, 8403 "Secondary aux image signature (%#x) not valid\n", 8404 le32_to_cpu(sec_aux_image_status.signature)); 8405 goto check_valid_image; 8406 } 8407 8408 if (qla27xx_image_status_checksum(&sec_aux_image_status)) { 8409 ql_dbg(ql_dbg_init, vha, 0x018c, 8410 "Secondary aux image checksum failed\n"); 8411 goto check_valid_image; 8412 } 8413 8414 valid_sec_image = true; 8415 8416 if (sec_aux_image_status.image_status_mask & 1) { 8417 ql_dbg(ql_dbg_init, vha, 0x018d, 8418 "Secondary aux image is active\n"); 8419 active_sec_image = true; 8420 } 8421 8422 check_valid_image: 8423 if (valid_pri_image && active_pri_image && 8424 valid_sec_image && active_sec_image) { 8425 if (qla27xx_compare_image_generation(&pri_aux_image_status, 8426 &sec_aux_image_status) >= 0) { 8427 qla28xx_component_status(active_regions, 8428 &pri_aux_image_status); 8429 } else { 8430 qla28xx_component_status(active_regions, 8431 &sec_aux_image_status); 8432 } 8433 } else if (valid_pri_image && active_pri_image) { 8434 qla28xx_component_status(active_regions, &pri_aux_image_status); 8435 } else if (valid_sec_image && active_sec_image) { 8436 qla28xx_component_status(active_regions, &sec_aux_image_status); 8437 } 8438 8439 ql_dbg(ql_dbg_init, vha, 0x018f, 8440 "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u, NVME=%u\n", 8441 active_regions->aux.board_config, 8442 active_regions->aux.vpd_nvram, 8443 active_regions->aux.npiv_config_0_1, 8444 active_regions->aux.npiv_config_2_3, 8445 active_regions->aux.nvme_params); 8446 } 8447 8448 void 8449 qla27xx_get_active_image(struct scsi_qla_host *vha, 8450 struct active_regions *active_regions) 8451 { 8452 struct qla_hw_data *ha = vha->hw; 8453 struct qla27xx_image_status pri_image_status, sec_image_status; 8454 bool valid_pri_image = false, valid_sec_image = false; 8455 bool active_pri_image = false, active_sec_image = false; 8456 int rc; 8457 8458 if (!ha->flt_region_img_status_pri) { 8459 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary image not addressed\n"); 8460 goto check_sec_image; 8461 } 8462 8463 if (qla24xx_read_flash_data(vha, (uint32_t *)&pri_image_status, 8464 ha->flt_region_img_status_pri, sizeof(pri_image_status) >> 2) != 8465 QLA_SUCCESS) { 8466 WARN_ON_ONCE(true); 8467 goto check_sec_image; 8468 } 8469 qla27xx_print_image(vha, "Primary image", &pri_image_status); 8470 8471 if (qla27xx_check_image_status_signature(&pri_image_status)) { 8472 ql_dbg(ql_dbg_init, vha, 0x018b, 8473 "Primary image signature (%#x) not valid\n", 8474 le32_to_cpu(pri_image_status.signature)); 8475 goto check_sec_image; 8476 } 8477 8478 if (qla27xx_image_status_checksum(&pri_image_status)) { 8479 ql_dbg(ql_dbg_init, vha, 0x018c, 8480 "Primary image checksum failed\n"); 8481 goto check_sec_image; 8482 } 8483 8484 valid_pri_image = true; 8485 8486 if (pri_image_status.image_status_mask & 1) { 8487 ql_dbg(ql_dbg_init, vha, 0x018d, 8488 "Primary image is active\n"); 8489 active_pri_image = true; 8490 } 8491 8492 check_sec_image: 8493 if (!ha->flt_region_img_status_sec) { 8494 ql_dbg(ql_dbg_init, vha, 0x018a, "Secondary image not addressed\n"); 8495 goto check_valid_image; 8496 } 8497 8498 rc = qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status), 8499 ha->flt_region_img_status_sec, sizeof(sec_image_status) >> 2); 8500 if (rc) { 8501 ql_log(ql_log_info, vha, 0x01a3, 8502 "Unable to read Secondary image status(%x).\n", rc); 8503 goto check_valid_image; 8504 } 8505 8506 qla27xx_print_image(vha, "Secondary image", &sec_image_status); 8507 8508 if (qla27xx_check_image_status_signature(&sec_image_status)) { 8509 ql_dbg(ql_dbg_init, vha, 0x018b, 8510 "Secondary image signature (%#x) not valid\n", 8511 le32_to_cpu(sec_image_status.signature)); 8512 goto check_valid_image; 8513 } 8514 8515 if (qla27xx_image_status_checksum(&sec_image_status)) { 8516 ql_dbg(ql_dbg_init, vha, 0x018c, 8517 "Secondary image checksum failed\n"); 8518 goto check_valid_image; 8519 } 8520 8521 valid_sec_image = true; 8522 8523 if (sec_image_status.image_status_mask & 1) { 8524 ql_dbg(ql_dbg_init, vha, 0x018d, 8525 "Secondary image is active\n"); 8526 active_sec_image = true; 8527 } 8528 8529 check_valid_image: 8530 if (valid_pri_image && active_pri_image) 8531 active_regions->global = QLA27XX_PRIMARY_IMAGE; 8532 8533 if (valid_sec_image && active_sec_image) { 8534 if (!active_regions->global || 8535 qla27xx_compare_image_generation( 8536 &pri_image_status, &sec_image_status) < 0) { 8537 active_regions->global = QLA27XX_SECONDARY_IMAGE; 8538 } 8539 } 8540 8541 ql_dbg(ql_dbg_init, vha, 0x018f, "active image %s (%u)\n", 8542 active_regions->global == QLA27XX_DEFAULT_IMAGE ? 8543 "default (boot/fw)" : 8544 active_regions->global == QLA27XX_PRIMARY_IMAGE ? 8545 "primary" : 8546 active_regions->global == QLA27XX_SECONDARY_IMAGE ? 8547 "secondary" : "invalid", 8548 active_regions->global); 8549 } 8550 8551 bool qla24xx_risc_firmware_invalid(uint32_t *dword) 8552 { 8553 return 8554 !(dword[4] | dword[5] | dword[6] | dword[7]) || 8555 !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]); 8556 } 8557 8558 static int 8559 qla28xx_get_srisc_addr(scsi_qla_host_t *vha, uint32_t *srisc_addr, 8560 uint32_t faddr) 8561 { 8562 struct qla_hw_data *ha = vha->hw; 8563 struct req_que *req = ha->req_q_map[0]; 8564 uint32_t *dcode; 8565 int rval; 8566 8567 *srisc_addr = 0; 8568 dcode = (uint32_t *)req->ring; 8569 8570 rval = qla24xx_read_flash_data(vha, dcode, faddr, 10); 8571 if (rval) { 8572 ql_log(ql_log_fatal, vha, 0x01aa, 8573 "-> Failed to read flash addr + size .\n"); 8574 return QLA_FUNCTION_FAILED; 8575 } 8576 8577 *srisc_addr = be32_to_cpu((__force __be32)dcode[2]); 8578 return QLA_SUCCESS; 8579 } 8580 8581 static int 8582 qla28xx_load_fw_template(scsi_qla_host_t *vha, uint32_t faddr) 8583 { 8584 struct qla_hw_data *ha = vha->hw; 8585 struct fwdt *fwdt = ha->fwdt; 8586 struct req_que *req = ha->req_q_map[0]; 8587 uint32_t risc_size, risc_attr = 0; 8588 uint templates, segments, fragment; 8589 uint32_t *dcode; 8590 ulong dlen; 8591 int rval; 8592 uint j; 8593 8594 dcode = (uint32_t *)req->ring; 8595 segments = FA_RISC_CODE_SEGMENTS; 8596 8597 for (j = 0; j < segments; j++) { 8598 rval = qla24xx_read_flash_data(vha, dcode, faddr, 10); 8599 if (rval) { 8600 ql_log(ql_log_fatal, vha, 0x01a1, 8601 "-> Failed to read flash addr + size .\n"); 8602 return QLA_FUNCTION_FAILED; 8603 } 8604 8605 risc_size = be32_to_cpu((__force __be32)dcode[3]); 8606 8607 if (risc_attr == 0) 8608 risc_attr = be32_to_cpu((__force __be32)dcode[9]); 8609 8610 dlen = ha->fw_transfer_size >> 2; 8611 for (fragment = 0; fragment < risc_size; fragment++) { 8612 if (dlen > risc_size) 8613 dlen = risc_size; 8614 8615 faddr += dlen; 8616 risc_size -= dlen; 8617 } 8618 } 8619 8620 templates = (risc_attr & BIT_9) ? 2 : 1; 8621 8622 ql_dbg(ql_dbg_init, vha, 0x01a1, "-> templates = %u\n", templates); 8623 8624 for (j = 0; j < templates; j++, fwdt++) { 8625 vfree(fwdt->template); 8626 fwdt->template = NULL; 8627 fwdt->length = 0; 8628 8629 dcode = (uint32_t *)req->ring; 8630 8631 rval = qla24xx_read_flash_data(vha, dcode, faddr, 7); 8632 if (rval) { 8633 ql_log(ql_log_fatal, vha, 0x01a2, 8634 "-> Unable to read template size.\n"); 8635 goto failed; 8636 } 8637 8638 risc_size = be32_to_cpu((__force __be32)dcode[2]); 8639 ql_dbg(ql_dbg_init, vha, 0x01a3, 8640 "-> fwdt%u template array at %#x (%#x dwords)\n", 8641 j, faddr, risc_size); 8642 if (!risc_size || !~risc_size) { 8643 ql_dbg(ql_dbg_init, vha, 0x01a4, 8644 "-> fwdt%u failed to read array\n", j); 8645 goto failed; 8646 } 8647 8648 /* skip header and ignore checksum */ 8649 faddr += 7; 8650 risc_size -= 8; 8651 8652 ql_dbg(ql_dbg_init, vha, 0x01a5, 8653 "-> fwdt%u template allocate template %#x words...\n", 8654 j, risc_size); 8655 fwdt->template = vmalloc(risc_size * sizeof(*dcode)); 8656 if (!fwdt->template) { 8657 ql_log(ql_log_warn, vha, 0x01a6, 8658 "-> fwdt%u failed allocate template.\n", j); 8659 goto failed; 8660 } 8661 8662 dcode = fwdt->template; 8663 rval = qla24xx_read_flash_data(vha, dcode, faddr, risc_size); 8664 8665 if (rval || !qla27xx_fwdt_template_valid(dcode)) { 8666 ql_log(ql_log_warn, vha, 0x01a7, 8667 "-> fwdt%u failed template validate (rval %x)\n", 8668 j, rval); 8669 goto failed; 8670 } 8671 8672 dlen = qla27xx_fwdt_template_size(dcode); 8673 ql_dbg(ql_dbg_init, vha, 0x01a7, 8674 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 8675 j, dlen, dlen / sizeof(*dcode)); 8676 if (dlen > risc_size * sizeof(*dcode)) { 8677 ql_log(ql_log_warn, vha, 0x01a8, 8678 "-> fwdt%u template exceeds array (%-lu bytes)\n", 8679 j, dlen - risc_size * sizeof(*dcode)); 8680 goto failed; 8681 } 8682 8683 fwdt->length = dlen; 8684 ql_dbg(ql_dbg_init, vha, 0x01a9, 8685 "-> fwdt%u loaded template ok\n", j); 8686 8687 faddr += risc_size + 1; 8688 } 8689 8690 return QLA_SUCCESS; 8691 8692 failed: 8693 vfree(fwdt->template); 8694 fwdt->template = NULL; 8695 fwdt->length = 0; 8696 8697 return QLA_SUCCESS; 8698 } 8699 8700 static int 8701 qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, 8702 uint32_t faddr) 8703 { 8704 int rval; 8705 uint templates, segments, fragment; 8706 ulong i; 8707 uint j; 8708 ulong dlen; 8709 uint32_t *dcode; 8710 uint32_t risc_addr, risc_size, risc_attr = 0; 8711 struct qla_hw_data *ha = vha->hw; 8712 struct req_que *req = ha->req_q_map[0]; 8713 struct fwdt *fwdt = ha->fwdt; 8714 8715 ql_dbg(ql_dbg_init, vha, 0x008b, 8716 "FW: Loading firmware from flash (%x).\n", faddr); 8717 8718 dcode = (uint32_t *)req->ring; 8719 rval = qla24xx_read_flash_data(vha, dcode, faddr, 8); 8720 if (rval || qla24xx_risc_firmware_invalid(dcode)) { 8721 ql_log(ql_log_fatal, vha, 0x008c, 8722 "Unable to verify the integrity of flash firmware image (rval %x).\n", rval); 8723 ql_log(ql_log_fatal, vha, 0x008d, 8724 "Firmware data: %08x %08x %08x %08x.\n", 8725 dcode[0], dcode[1], dcode[2], dcode[3]); 8726 8727 return QLA_FUNCTION_FAILED; 8728 } 8729 8730 dcode = (uint32_t *)req->ring; 8731 *srisc_addr = 0; 8732 segments = FA_RISC_CODE_SEGMENTS; 8733 for (j = 0; j < segments; j++) { 8734 ql_dbg(ql_dbg_init, vha, 0x008d, 8735 "-> Loading segment %u...\n", j); 8736 rval = qla24xx_read_flash_data(vha, dcode, faddr, 10); 8737 if (rval) { 8738 ql_log(ql_log_fatal, vha, 0x016a, 8739 "-> Unable to read segment addr + size .\n"); 8740 return QLA_FUNCTION_FAILED; 8741 } 8742 risc_addr = be32_to_cpu((__force __be32)dcode[2]); 8743 risc_size = be32_to_cpu((__force __be32)dcode[3]); 8744 if (!*srisc_addr) { 8745 *srisc_addr = risc_addr; 8746 risc_attr = be32_to_cpu((__force __be32)dcode[9]); 8747 } 8748 8749 dlen = ha->fw_transfer_size >> 2; 8750 for (fragment = 0; risc_size; fragment++) { 8751 if (dlen > risc_size) 8752 dlen = risc_size; 8753 8754 ql_dbg(ql_dbg_init, vha, 0x008e, 8755 "-> Loading fragment %u: %#x <- %#x (%#lx dwords)...\n", 8756 fragment, risc_addr, faddr, dlen); 8757 rval = qla24xx_read_flash_data(vha, dcode, faddr, dlen); 8758 if (rval) { 8759 ql_log(ql_log_fatal, vha, 0x016b, 8760 "-> Unable to read fragment(faddr %#x dlen %#lx).\n", 8761 faddr, dlen); 8762 return QLA_FUNCTION_FAILED; 8763 } 8764 for (i = 0; i < dlen; i++) 8765 dcode[i] = swab32(dcode[i]); 8766 8767 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 8768 dlen, 0); 8769 if (rval) { 8770 ql_log(ql_log_fatal, vha, 0x008f, 8771 "-> Failed load firmware fragment %u.\n", 8772 fragment); 8773 return QLA_FUNCTION_FAILED; 8774 } 8775 8776 faddr += dlen; 8777 risc_addr += dlen; 8778 risc_size -= dlen; 8779 } 8780 } 8781 8782 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 8783 return QLA_SUCCESS; 8784 8785 templates = (risc_attr & BIT_9) ? 2 : 1; 8786 ql_dbg(ql_dbg_init, vha, 0x0160, "-> templates = %u\n", templates); 8787 for (j = 0; j < templates; j++, fwdt++) { 8788 vfree(fwdt->template); 8789 fwdt->template = NULL; 8790 fwdt->length = 0; 8791 8792 dcode = (uint32_t *)req->ring; 8793 8794 rval = qla24xx_read_flash_data(vha, dcode, faddr, 7); 8795 if (rval) { 8796 ql_log(ql_log_fatal, vha, 0x016c, 8797 "-> Unable to read template size.\n"); 8798 goto failed; 8799 } 8800 8801 risc_size = be32_to_cpu((__force __be32)dcode[2]); 8802 ql_dbg(ql_dbg_init, vha, 0x0161, 8803 "-> fwdt%u template array at %#x (%#x dwords)\n", 8804 j, faddr, risc_size); 8805 if (!risc_size || !~risc_size) { 8806 ql_dbg(ql_dbg_init, vha, 0x0162, 8807 "-> fwdt%u failed to read array\n", j); 8808 goto failed; 8809 } 8810 8811 /* skip header and ignore checksum */ 8812 faddr += 7; 8813 risc_size -= 8; 8814 8815 ql_dbg(ql_dbg_init, vha, 0x0163, 8816 "-> fwdt%u template allocate template %#x words...\n", 8817 j, risc_size); 8818 fwdt->template = vmalloc_array(risc_size, sizeof(*dcode)); 8819 if (!fwdt->template) { 8820 ql_log(ql_log_warn, vha, 0x0164, 8821 "-> fwdt%u failed allocate template.\n", j); 8822 goto failed; 8823 } 8824 8825 dcode = fwdt->template; 8826 rval = qla24xx_read_flash_data(vha, dcode, faddr, risc_size); 8827 8828 if (rval || !qla27xx_fwdt_template_valid(dcode)) { 8829 ql_log(ql_log_warn, vha, 0x0165, 8830 "-> fwdt%u failed template validate (rval %x)\n", 8831 j, rval); 8832 goto failed; 8833 } 8834 8835 dlen = qla27xx_fwdt_template_size(dcode); 8836 ql_dbg(ql_dbg_init, vha, 0x0166, 8837 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 8838 j, dlen, dlen / sizeof(*dcode)); 8839 if (dlen > risc_size * sizeof(*dcode)) { 8840 ql_log(ql_log_warn, vha, 0x0167, 8841 "-> fwdt%u template exceeds array (%-lu bytes)\n", 8842 j, dlen - risc_size * sizeof(*dcode)); 8843 goto failed; 8844 } 8845 8846 fwdt->length = dlen; 8847 ql_dbg(ql_dbg_init, vha, 0x0168, 8848 "-> fwdt%u loaded template ok\n", j); 8849 8850 faddr += risc_size + 1; 8851 } 8852 8853 return QLA_SUCCESS; 8854 8855 failed: 8856 vfree(fwdt->template); 8857 fwdt->template = NULL; 8858 fwdt->length = 0; 8859 8860 return QLA_SUCCESS; 8861 } 8862 8863 int 8864 qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8865 { 8866 int rval; 8867 int i, fragment; 8868 uint16_t *wcode; 8869 __be16 *fwcode; 8870 uint32_t risc_addr, risc_size, fwclen, wlen, *seg; 8871 struct fw_blob *blob; 8872 struct qla_hw_data *ha = vha->hw; 8873 struct req_que *req = ha->req_q_map[0]; 8874 8875 /* Load firmware blob. */ 8876 blob = qla2x00_request_firmware(vha); 8877 if (!blob) { 8878 ql_log(ql_log_info, vha, 0x0083, 8879 "Firmware image unavailable.\n"); 8880 return QLA_FUNCTION_FAILED; 8881 } 8882 8883 rval = QLA_SUCCESS; 8884 8885 wcode = (uint16_t *)req->ring; 8886 *srisc_addr = 0; 8887 fwcode = (__force __be16 *)blob->fw->data; 8888 fwclen = 0; 8889 8890 /* Validate firmware image by checking version. */ 8891 if (blob->fw->size < 8 * sizeof(uint16_t)) { 8892 ql_log(ql_log_fatal, vha, 0x0085, 8893 "Unable to verify integrity of firmware image (%zd).\n", 8894 blob->fw->size); 8895 goto fail_fw_integrity; 8896 } 8897 for (i = 0; i < 4; i++) 8898 wcode[i] = be16_to_cpu(fwcode[i + 4]); 8899 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && 8900 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && 8901 wcode[2] == 0 && wcode[3] == 0)) { 8902 ql_log(ql_log_fatal, vha, 0x0086, 8903 "Unable to verify integrity of firmware image.\n"); 8904 ql_log(ql_log_fatal, vha, 0x0087, 8905 "Firmware data: %04x %04x %04x %04x.\n", 8906 wcode[0], wcode[1], wcode[2], wcode[3]); 8907 goto fail_fw_integrity; 8908 } 8909 8910 seg = blob->segs; 8911 while (*seg && rval == QLA_SUCCESS) { 8912 risc_addr = *seg; 8913 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; 8914 risc_size = be16_to_cpu(fwcode[3]); 8915 8916 /* Validate firmware image size. */ 8917 fwclen += risc_size * sizeof(uint16_t); 8918 if (blob->fw->size < fwclen) { 8919 ql_log(ql_log_fatal, vha, 0x0088, 8920 "Unable to verify integrity of firmware image " 8921 "(%zd).\n", blob->fw->size); 8922 goto fail_fw_integrity; 8923 } 8924 8925 fragment = 0; 8926 while (risc_size > 0 && rval == QLA_SUCCESS) { 8927 wlen = (uint16_t)(ha->fw_transfer_size >> 1); 8928 if (wlen > risc_size) 8929 wlen = risc_size; 8930 ql_dbg(ql_dbg_init, vha, 0x0089, 8931 "Loading risc segment@ risc addr %x number of " 8932 "words 0x%x.\n", risc_addr, wlen); 8933 8934 for (i = 0; i < wlen; i++) 8935 wcode[i] = swab16((__force u32)fwcode[i]); 8936 8937 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 8938 wlen, 0); 8939 if (rval) { 8940 ql_log(ql_log_fatal, vha, 0x008a, 8941 "Failed to load segment %d of firmware.\n", 8942 fragment); 8943 break; 8944 } 8945 8946 fwcode += wlen; 8947 risc_addr += wlen; 8948 risc_size -= wlen; 8949 fragment++; 8950 } 8951 8952 /* Next segment. */ 8953 seg++; 8954 } 8955 return rval; 8956 8957 fail_fw_integrity: 8958 return QLA_FUNCTION_FAILED; 8959 } 8960 8961 static int 8962 qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8963 { 8964 int rval; 8965 uint templates, segments, fragment; 8966 uint32_t *dcode; 8967 ulong dlen; 8968 uint32_t risc_addr, risc_size, risc_attr = 0; 8969 ulong i; 8970 uint j; 8971 struct fw_blob *blob; 8972 __be32 *fwcode; 8973 struct qla_hw_data *ha = vha->hw; 8974 struct req_que *req = ha->req_q_map[0]; 8975 struct fwdt *fwdt = ha->fwdt; 8976 8977 ql_dbg(ql_dbg_init, vha, 0x0090, 8978 "-> FW: Loading via request-firmware.\n"); 8979 8980 blob = qla2x00_request_firmware(vha); 8981 if (!blob) { 8982 ql_log(ql_log_warn, vha, 0x0092, 8983 "-> Firmware file not found.\n"); 8984 8985 return QLA_FUNCTION_FAILED; 8986 } 8987 8988 fwcode = (__force __be32 *)blob->fw->data; 8989 dcode = (__force uint32_t *)fwcode; 8990 if (qla24xx_risc_firmware_invalid(dcode)) { 8991 ql_log(ql_log_fatal, vha, 0x0093, 8992 "Unable to verify integrity of firmware image (%zd).\n", 8993 blob->fw->size); 8994 ql_log(ql_log_fatal, vha, 0x0095, 8995 "Firmware data: %08x %08x %08x %08x.\n", 8996 dcode[0], dcode[1], dcode[2], dcode[3]); 8997 return QLA_FUNCTION_FAILED; 8998 } 8999 9000 dcode = (uint32_t *)req->ring; 9001 *srisc_addr = 0; 9002 segments = FA_RISC_CODE_SEGMENTS; 9003 for (j = 0; j < segments; j++) { 9004 ql_dbg(ql_dbg_init, vha, 0x0096, 9005 "-> Loading segment %u...\n", j); 9006 risc_addr = be32_to_cpu(fwcode[2]); 9007 risc_size = be32_to_cpu(fwcode[3]); 9008 9009 if (!*srisc_addr) { 9010 *srisc_addr = risc_addr; 9011 risc_attr = be32_to_cpu(fwcode[9]); 9012 } 9013 9014 dlen = ha->fw_transfer_size >> 2; 9015 for (fragment = 0; risc_size; fragment++) { 9016 if (dlen > risc_size) 9017 dlen = risc_size; 9018 9019 ql_dbg(ql_dbg_init, vha, 0x0097, 9020 "-> Loading fragment %u: %#x <- %#x (%#lx words)...\n", 9021 fragment, risc_addr, 9022 (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data), 9023 dlen); 9024 9025 for (i = 0; i < dlen; i++) 9026 dcode[i] = swab32((__force u32)fwcode[i]); 9027 9028 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 9029 dlen, 0); 9030 if (rval) { 9031 ql_log(ql_log_fatal, vha, 0x0098, 9032 "-> Failed load firmware fragment %u.\n", 9033 fragment); 9034 return QLA_FUNCTION_FAILED; 9035 } 9036 9037 fwcode += dlen; 9038 risc_addr += dlen; 9039 risc_size -= dlen; 9040 } 9041 } 9042 9043 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 9044 return QLA_SUCCESS; 9045 9046 templates = (risc_attr & BIT_9) ? 2 : 1; 9047 ql_dbg(ql_dbg_init, vha, 0x0170, "-> templates = %u\n", templates); 9048 for (j = 0; j < templates; j++, fwdt++) { 9049 vfree(fwdt->template); 9050 fwdt->template = NULL; 9051 fwdt->length = 0; 9052 9053 risc_size = be32_to_cpu(fwcode[2]); 9054 ql_dbg(ql_dbg_init, vha, 0x0171, 9055 "-> fwdt%u template array at %#x (%#x dwords)\n", 9056 j, (uint32_t)((void *)fwcode - (void *)blob->fw->data), 9057 risc_size); 9058 if (!risc_size || !~risc_size) { 9059 ql_dbg(ql_dbg_init, vha, 0x0172, 9060 "-> fwdt%u failed to read array\n", j); 9061 goto failed; 9062 } 9063 9064 /* skip header and ignore checksum */ 9065 fwcode += 7; 9066 risc_size -= 8; 9067 9068 ql_dbg(ql_dbg_init, vha, 0x0173, 9069 "-> fwdt%u template allocate template %#x words...\n", 9070 j, risc_size); 9071 fwdt->template = vmalloc_array(risc_size, sizeof(*dcode)); 9072 if (!fwdt->template) { 9073 ql_log(ql_log_warn, vha, 0x0174, 9074 "-> fwdt%u failed allocate template.\n", j); 9075 goto failed; 9076 } 9077 9078 dcode = fwdt->template; 9079 for (i = 0; i < risc_size; i++) 9080 dcode[i] = (__force u32)fwcode[i]; 9081 9082 if (!qla27xx_fwdt_template_valid(dcode)) { 9083 ql_log(ql_log_warn, vha, 0x0175, 9084 "-> fwdt%u failed template validate\n", j); 9085 goto failed; 9086 } 9087 9088 dlen = qla27xx_fwdt_template_size(dcode); 9089 ql_dbg(ql_dbg_init, vha, 0x0176, 9090 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 9091 j, dlen, dlen / sizeof(*dcode)); 9092 if (dlen > risc_size * sizeof(*dcode)) { 9093 ql_log(ql_log_warn, vha, 0x0177, 9094 "-> fwdt%u template exceeds array (%-lu bytes)\n", 9095 j, dlen - risc_size * sizeof(*dcode)); 9096 goto failed; 9097 } 9098 9099 fwdt->length = dlen; 9100 ql_dbg(ql_dbg_init, vha, 0x0178, 9101 "-> fwdt%u loaded template ok\n", j); 9102 9103 fwcode += risc_size + 1; 9104 } 9105 9106 return QLA_SUCCESS; 9107 9108 failed: 9109 vfree(fwdt->template); 9110 fwdt->template = NULL; 9111 fwdt->length = 0; 9112 9113 return QLA_SUCCESS; 9114 } 9115 9116 int 9117 qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 9118 { 9119 int rval; 9120 9121 if (ql2xfwloadbin == 1) 9122 return qla81xx_load_risc(vha, srisc_addr); 9123 9124 /* 9125 * FW Load priority: 9126 * 1) Firmware via request-firmware interface (.bin file). 9127 * 2) Firmware residing in flash. 9128 */ 9129 rval = qla24xx_load_risc_blob(vha, srisc_addr); 9130 if (rval == QLA_SUCCESS) 9131 return rval; 9132 9133 return qla24xx_load_risc_flash(vha, srisc_addr, 9134 vha->hw->flt_region_fw); 9135 } 9136 9137 int 9138 qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 9139 { 9140 int rval; 9141 uint32_t f_region = 0; 9142 struct qla_hw_data *ha = vha->hw; 9143 struct active_regions active_regions = { }; 9144 9145 if (ql2xfwloadbin == 2 && !IS_QLA28XX(ha)) 9146 goto try_blob_fw; 9147 9148 /* FW Load priority: 9149 * 1) If 28xxx, ROM cmd to load flash firmware. 9150 * 2) Firmware residing in flash. 9151 * 3) Firmware via request-firmware interface (.bin file). 9152 * 4) Golden-Firmware residing in flash -- (limited operation). 9153 */ 9154 9155 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 9156 goto try_primary_fw; 9157 9158 qla27xx_get_active_image(vha, &active_regions); 9159 9160 /* For 28XXX, always load the flash firmware using rom mbx */ 9161 if (IS_QLA28XX_SECURED(ha)) { 9162 rval = qla28xx_load_flash_firmware(vha); 9163 if (rval != QLA_SUCCESS) { 9164 ql_log(ql_log_fatal, vha, 0x019e, 9165 "Failed to load flash firmware.\n"); 9166 goto exit_load_risc; 9167 } 9168 9169 f_region = 9170 (active_regions.global != QLA27XX_SECONDARY_IMAGE) ? 9171 ha->flt_region_fw : ha->flt_region_fw_sec; 9172 9173 ql_log(ql_log_info, vha, 0x019f, 9174 "Load flash firmware successful (%s).\n", 9175 ((active_regions.global != QLA27XX_SECONDARY_IMAGE) ? 9176 "Primary" : "Secondary")); 9177 9178 rval = qla28xx_get_srisc_addr(vha, srisc_addr, f_region); 9179 if (rval != QLA_SUCCESS) { 9180 ql_log(ql_log_warn, vha, 0x019f, 9181 "failed to read srisc address\n"); 9182 goto exit_load_risc; 9183 } 9184 9185 rval = qla28xx_load_fw_template(vha, f_region); 9186 if (rval != QLA_SUCCESS) { 9187 ql_log(ql_log_warn, vha, 0x01a0, 9188 "failed to read firmware template\n"); 9189 } 9190 9191 goto exit_load_risc; 9192 } 9193 9194 if (active_regions.global != QLA27XX_SECONDARY_IMAGE) 9195 goto try_primary_fw; 9196 9197 ql_dbg(ql_dbg_init, vha, 0x008b, 9198 "Loading secondary firmware image.\n"); 9199 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec); 9200 if (!rval) 9201 return rval; 9202 9203 try_primary_fw: 9204 ql_dbg(ql_dbg_init, vha, 0x008b, 9205 "Loading primary firmware image.\n"); 9206 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); 9207 if (!rval) 9208 return rval; 9209 9210 try_blob_fw: 9211 rval = qla24xx_load_risc_blob(vha, srisc_addr); 9212 if (!rval || !ha->flt_region_gold_fw) 9213 return rval; 9214 9215 ql_log(ql_log_info, vha, 0x0099, 9216 "Attempting to fallback to golden firmware.\n"); 9217 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); 9218 if (rval) 9219 return rval; 9220 9221 ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n"); 9222 ha->flags.running_gold_fw = 1; 9223 9224 exit_load_risc: 9225 return rval; 9226 } 9227 9228 static int qla29xx_validate_firmware_image(scsi_qla_host_t *vha, 9229 __be32 *dword) 9230 { 9231 if (be32_to_cpu(dword[0]) != LD_FL_HEADER_SIGNATURE) { 9232 ql_dbg(ql_dbg_init, vha, 0x0093, 9233 "Firmware image Signature does not match (0x%x).\n", 9234 be32_to_cpu(dword[0])); 9235 return QLA_FUNCTION_FAILED; 9236 } 9237 if (be32_to_cpu(dword[2]) != LD_FL_HEADER_VERSION) { 9238 ql_dbg(ql_dbg_init, vha, 0x0093, 9239 "Firmware image Version does not match (0x%x).\n", 9240 be32_to_cpu(dword[2])); 9241 return QLA_FUNCTION_FAILED; 9242 } 9243 return QLA_SUCCESS; 9244 } 9245 9246 static int qla29xx_process_rd_image(struct scsi_qla_host *vha, 9247 struct fcop_header *header, 9248 __be32 *fwcode, int section, 9249 uint32_t risc_addr, uint32_t section_size) 9250 { 9251 int rval = QLA_SUCCESS; 9252 uint32_t *dcode = NULL; 9253 struct qla_hw_data *ha = vha->hw; 9254 struct req_que *req = ha->req_q_map[0]; 9255 int num_segments = 0, segment = 0; 9256 int chunks_per_segment = 0, chunk = 0; 9257 int is_first_chunk = 0; 9258 int is_last_chunk = 0; 9259 int is_first_segment = 0; 9260 int is_last_segment = 0; 9261 int opt = 0; 9262 uint32_t size = 0; 9263 uint32_t size_remainder = 0; 9264 uint32_t seg_size_remainder = 0; 9265 int i = 0; 9266 9267 dcode = (uint32_t *)req->ring; 9268 9269 if (section == TIM) { 9270 if (section_size > req->length * qla_req_entry_size(ha)) { 9271 ql_log(ql_log_fatal, vha, 0x0098, 9272 "TIM section too large (0x%x bytes, ring 0x%zx bytes).\n", 9273 section_size, 9274 req->length * qla_req_entry_size(ha)); 9275 return QLA_FUNCTION_FAILED; 9276 } 9277 9278 opt = BIT_15 | BIT_2 | BIT_1 | BIT_0; 9279 for (i = 0; i < (section_size >> 2); i++) 9280 dcode[i] = swab32((__force u32)fwcode[i]); 9281 9282 ql_dbg(ql_dbg_init, vha, 0x0098, 9283 "TIM : process_rd_image [opt 0x%x]\n", opt); 9284 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 9285 section_size >> 2, opt); 9286 if (rval) { 9287 ql_log(ql_log_fatal, vha, 0x0098, 9288 "-> Failed load TIM\n"); 9289 return QLA_FUNCTION_FAILED; 9290 } 9291 } else { 9292 size_remainder = section_size; 9293 num_segments += (section_size % header->segment_size == 0) ? 9294 (section_size / header->segment_size) : 9295 (section_size / header->segment_size) + 1; 9296 chunks_per_segment = 9297 (header->segment_size % CHUNK_SIZE == 0) ? 9298 (header->segment_size / CHUNK_SIZE) : 9299 (header->segment_size / CHUNK_SIZE) + 1; 9300 9301 ql_dbg(ql_dbg_init, vha, 0x0098, 9302 "num seg 0x%x chunk per seg 0x%x\n", 9303 num_segments, chunks_per_segment); 9304 9305 for (segment = 0; segment < num_segments; segment++) { 9306 for (chunk = 0; chunk < chunks_per_segment; chunk++) { 9307 is_first_chunk = (chunk == 0); 9308 if (chunk == 0) { 9309 if (size_remainder >= 9310 header->segment_size) 9311 seg_size_remainder = 9312 header->segment_size; 9313 else 9314 seg_size_remainder = 9315 size_remainder; 9316 } 9317 9318 is_first_segment = 9319 (section == ARR1 && segment == 0); 9320 is_last_segment = 9321 (section == ARR2 && 9322 (segment == (num_segments - 1))); 9323 is_last_chunk = 9324 (chunk == (chunks_per_segment - 1) || 9325 size_remainder <= CHUNK_SIZE); 9326 9327 if (seg_size_remainder < CHUNK_SIZE) 9328 size = seg_size_remainder % CHUNK_SIZE; 9329 else 9330 size = CHUNK_SIZE; 9331 9332 ql_dbg(ql_dbg_init, vha, 0x0098, 9333 "[%d]chunk 0x%x segment 0x%x first_segment 0x%x first_chunk 0x%x last_segment 0x%x last_chunk 0x%x\n", 9334 __LINE__, chunk, segment, 9335 is_first_segment, is_first_chunk, 9336 is_last_segment, is_last_chunk); 9337 9338 opt = BIT_2; 9339 if (is_first_chunk) 9340 opt |= BIT_0; 9341 if (is_last_chunk) 9342 opt |= BIT_1; 9343 if (is_first_segment) 9344 opt |= BIT_3; 9345 if (is_last_segment) 9346 opt |= BIT_4; 9347 9348 for (i = 0; i < (size >> 2); i++) 9349 dcode[i] = 9350 swab32((__force u32)fwcode[i]); 9351 9352 ql_dbg(ql_dbg_init, vha, 0x0098, 9353 "ARR[0x%x] : opt 0x%x\n", size, opt); 9354 rval = qla2x00_load_ram(vha, req->dma, 9355 risc_addr, 9356 size >> 2, opt); 9357 if (rval) { 9358 ql_log(ql_log_fatal, vha, 0x0098, 9359 "-> Failed load ram\n"); 9360 return QLA_FUNCTION_FAILED; 9361 } 9362 9363 fwcode += size >> 2; 9364 size_remainder -= size; 9365 seg_size_remainder -= size; 9366 if (size_remainder == 0) 9367 break; 9368 } 9369 risc_addr += header->segment_size >> 2; 9370 } 9371 } 9372 return rval; 9373 } 9374 9375 static int 9376 qla29xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) 9377 { 9378 int rval; 9379 struct fcop_header *header; 9380 uint32_t *dcode = NULL; 9381 struct fw_blob *blob; 9382 __be32 *fwcode, *array1_addr, *array3_addr; 9383 uint templates; 9384 uint32_t array_size, risc_attr = 0; 9385 ulong i; 9386 uint j; 9387 ulong dlen, array3_offset; 9388 size_t max_dwords; 9389 struct qla_hw_data *ha = vha->hw; 9390 struct fwdt *fwdt = ha->fwdt; 9391 9392 header = vmalloc(sizeof(*header)); 9393 if (!header) 9394 return QLA_FUNCTION_FAILED; 9395 9396 ql_dbg(ql_dbg_init, vha, 0x0090, 9397 "-> FW: Loading via request-firmware.\n"); 9398 9399 blob = qla2x00_request_firmware(vha); 9400 if (!blob) { 9401 ql_log(ql_log_warn, vha, 0x0092, 9402 "-> Firmware file not found.\n"); 9403 vfree(header); 9404 return QLA_FUNCTION_FAILED; 9405 } 9406 9407 fwcode = (__force __be32 *)blob->fw->data; 9408 9409 if (blob->fw->size < sizeof(*header)) { 9410 ql_log(ql_log_fatal, vha, 0x0093, 9411 "Firmware image too small (%zu bytes, need %zu).\n", 9412 blob->fw->size, sizeof(*header)); 9413 vfree(header); 9414 return QLA_FUNCTION_FAILED; 9415 } 9416 9417 rval = qla29xx_validate_firmware_image(vha, fwcode); 9418 if (rval != QLA_SUCCESS) { 9419 ql_log(ql_log_fatal, vha, 0x0093, 9420 "Unable to verify integrity of firmware image\n"); 9421 vfree(header); 9422 return QLA_FUNCTION_FAILED; 9423 } 9424 9425 /* byte-swap big-endian firmware header to CPU endian */ 9426 for (i = 0; i < sizeof(*header) / sizeof(__be32); i++) 9427 ((uint32_t *)header)[i] = be32_to_cpu(fwcode[i]); 9428 9429 /* 9430 * Section lengths are dword counts from the firmware image. Reject 9431 * values that would overflow the u32 fields on conversion to bytes 9432 * (<< 2) or that exceed the image, before using them below. 9433 */ 9434 max_dwords = blob->fw->size >> 2; 9435 if (header->header_length > max_dwords || 9436 header->tim_length > max_dwords || 9437 header->array1_length > max_dwords || 9438 header->array2_length > max_dwords || 9439 header->array3_length > max_dwords || 9440 header->array4_length > max_dwords) { 9441 ql_log(ql_log_fatal, vha, 0x0098, 9442 "FW image has invalid section length.\n"); 9443 goto img_corrupt; 9444 } 9445 9446 header->header_length <<= 2; 9447 header->tim_length <<= 2; 9448 header->array1_length <<= 2; 9449 header->array2_length <<= 2; 9450 header->array3_length <<= 2; 9451 header->array4_length <<= 2; 9452 9453 if (!header->segment_size) { 9454 ql_log(ql_log_fatal, vha, 0x0098, 9455 "FW image has zero segment_size.\n"); 9456 goto img_corrupt; 9457 } 9458 9459 { 9460 size_t fw_size = blob->fw->size; 9461 size_t offset; 9462 9463 /* TIM */ 9464 offset = header->header_length; 9465 if (offset + header->tim_length > fw_size) { 9466 ql_log(ql_log_fatal, vha, 0x0098, 9467 "FW image too small for TIM (%#zx > %#zx).\n", 9468 offset + header->tim_length, fw_size); 9469 goto img_corrupt; 9470 } 9471 rval = qla29xx_process_rd_image(vha, header, 9472 (__be32 *)((char *)fwcode + offset), 9473 TIM, TIM_DEST_ADDR, header->tim_length); 9474 if (rval) { 9475 ql_log(ql_log_fatal, vha, 0x0098, 9476 "-> Failed load TIM\n"); 9477 goto img_corrupt; 9478 } 9479 9480 /* Array 1 */ 9481 offset += header->tim_length; 9482 if (offset + header->array1_length > fw_size) { 9483 ql_log(ql_log_fatal, vha, 0x0098, 9484 "FW image too small for Arr1 (%#zx > %#zx).\n", 9485 offset + header->array1_length, fw_size); 9486 goto img_corrupt; 9487 } 9488 rval = qla29xx_process_rd_image(vha, header, 9489 (__be32 *)((char *)fwcode + offset), 9490 ARR1, header->array1_destination_addr, 9491 header->array1_length); 9492 if (rval) { 9493 ql_log(ql_log_fatal, vha, 0x0098, 9494 "-> Failed load Arr1\n"); 9495 goto img_corrupt; 9496 } 9497 9498 /* Array 2 */ 9499 offset += header->array1_length; 9500 if (offset + header->array2_length > fw_size) { 9501 ql_log(ql_log_fatal, vha, 0x0098, 9502 "FW image too small for Arr2 (%#zx > %#zx).\n", 9503 offset + header->array2_length, fw_size); 9504 goto img_corrupt; 9505 } 9506 rval = qla29xx_process_rd_image(vha, header, 9507 (__be32 *)((char *)fwcode + offset), 9508 ARR2, header->array2_destination_addr, 9509 header->array2_length); 9510 if (rval) { 9511 ql_log(ql_log_fatal, vha, 0x0098, 9512 "-> Failed load Arr2\n"); 9513 goto img_corrupt; 9514 } 9515 9516 /* Array 3: FW_DUMP template */ 9517 if (offset + 10 * sizeof(__be32) > fw_size) { 9518 ql_log(ql_log_fatal, vha, 0x0098, 9519 "FW image too small for risc_attr.\n"); 9520 goto img_corrupt; 9521 } 9522 array1_addr = (__be32 *)((char *)fwcode + 9523 header->header_length + 9524 header->tim_length); 9525 risc_attr = be32_to_cpu(array1_addr[9]); 9526 } 9527 templates = (risc_attr & BIT_9) ? 2 : 1; 9528 ql_dbg(ql_dbg_init, vha, 0x0160, 9529 "-> templates = %u\n", templates); 9530 9531 array3_offset = header->header_length + header->tim_length + 9532 header->array1_length + header->array2_length; 9533 if (array3_offset > blob->fw->size) { 9534 ql_log(ql_log_fatal, vha, 0x0098, 9535 "FW image too small for Arr3 (%#lx > %#zx).\n", 9536 array3_offset, blob->fw->size); 9537 goto img_corrupt; 9538 } 9539 9540 array3_addr = (__be32 *)(((char *)fwcode) + array3_offset); 9541 for (j = 0; j < templates; j++, fwdt++) { 9542 vfree(fwdt->template); 9543 fwdt->template = NULL; 9544 fwdt->length = 0; 9545 9546 if ((char *)&array3_addr[7] > 9547 (char *)blob->fw->data + blob->fw->size) { 9548 ql_log(ql_log_warn, vha, 0x0169, 9549 "-> fwdt%u template header exceeds firmware blob.\n", 9550 j); 9551 goto failed; 9552 } 9553 9554 array_size = be32_to_cpu(array3_addr[2]); 9555 ql_dbg(ql_dbg_init, vha, 0x0161, 9556 "-> fwdt%u template array at %p (%#x dwords)\n", 9557 j, array3_addr, array_size); 9558 9559 if (!array_size || !~array_size || array_size <= 8) { 9560 ql_dbg(ql_dbg_init, vha, 0x0162, 9561 "-> fwdt%u failed to read array\n", j); 9562 goto failed; 9563 } 9564 9565 array3_addr += 7; 9566 array_size -= 8; 9567 9568 if ((char *)&array3_addr[array_size] > 9569 (char *)blob->fw->data + blob->fw->size) { 9570 ql_log(ql_log_warn, vha, 0x0163, 9571 "-> fwdt%u template array exceeds firmware blob.\n", 9572 j); 9573 goto failed; 9574 } 9575 9576 ql_dbg(ql_dbg_init, vha, 0x0163, 9577 "-> fwdt%u template allocate template %#x words...\n", 9578 j, array_size); 9579 fwdt->template = vmalloc_array(array_size, sizeof(*dcode)); 9580 if (!fwdt->template) { 9581 ql_log(ql_log_warn, vha, 0x0164, 9582 "-> fwdt%u failed allocate template.\n", j); 9583 goto failed; 9584 } 9585 9586 dcode = fwdt->template; 9587 for (i = 0; i < array_size; i++) 9588 dcode[i] = (__force u32)array3_addr[i]; 9589 9590 if (!qla27xx_fwdt_template_valid(dcode)) { 9591 ql_log(ql_log_warn, vha, 0x0165, 9592 "-> fwdt%u failed template validate\n", j); 9593 goto failed; 9594 } 9595 9596 dlen = qla27xx_fwdt_template_size(dcode); 9597 ql_dbg(ql_dbg_init, vha, 0x0166, 9598 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 9599 j, dlen, dlen / sizeof(*dcode)); 9600 if (dlen > array_size * sizeof(*dcode)) { 9601 ql_log(ql_log_warn, vha, 0x0167, 9602 "-> fwdt%u template exceeds array (%-lu bytes)\n", 9603 j, dlen - array_size * sizeof(*dcode)); 9604 goto failed; 9605 } 9606 9607 fwdt->length = dlen; 9608 ql_dbg(ql_dbg_init, vha, 0x0168, 9609 "-> fwdt%u loaded template ok\n", j); 9610 9611 array3_addr += array_size + 1; 9612 } 9613 vfree(header); 9614 return QLA_SUCCESS; 9615 9616 failed: 9617 vfree(fwdt->template); 9618 fwdt->template = NULL; 9619 fwdt->length = 0; 9620 img_corrupt: 9621 vfree(header); 9622 return QLA_FUNCTION_FAILED; 9623 } 9624 9625 static int 9626 qla29xx_load_fw_template(scsi_qla_host_t *vha) 9627 { 9628 struct qla_hw_data *ha = vha->hw; 9629 struct fwdt *fwdt = ha->fwdt; 9630 uint templates = 1; 9631 void *fw_dump_tmplt; 9632 uint32_t *dcode; 9633 void *buf = NULL; 9634 uint32_t len; 9635 uint32_t template_size; 9636 uint j = 0; 9637 int rval = 0; 9638 9639 ql_dbg(ql_dbg_init, vha, 0x01bf, 9640 "-> templates = %u fw_dump_tmplt_len = 0x%x\n", 9641 templates, ha->fw_dump_tmplt_len); 9642 9643 if (!ha->fw_dump_tmplt_len) { 9644 ql_dbg(ql_dbg_init, vha, 0x01bf, 9645 "no fw dump template available\n"); 9646 return QLA_SUCCESS; 9647 } 9648 9649 fw_dump_tmplt = kzalloc(ha->fw_dump_tmplt_len, GFP_KERNEL); 9650 if (!fw_dump_tmplt) { 9651 ql_log(ql_log_info, vha, 0x0013, 9652 "Unable to allocate memory\n"); 9653 return QLA_FUNCTION_FAILED; 9654 } 9655 9656 buf = qla29xx_read_optrom_data(vha, FLT_REG_FW_DUMP_TMPLT, 0, 9657 fw_dump_tmplt, 0, 9658 ha->fw_dump_tmplt_len); 9659 if (!buf) { 9660 ql_log(ql_log_info, vha, 0x0013, 9661 "Unable to read fw dump temp info.\n"); 9662 goto free_fw_dump; 9663 } 9664 9665 ql_dump_buffer(ql_dbg_init, vha, 0x006b, fw_dump_tmplt, 9666 min_t(uint32_t, ha->fw_dump_tmplt_len, 1024)); 9667 9668 for (j = 0; j < templates; j++, fwdt++) { 9669 vfree(fwdt->template); 9670 fwdt->template = NULL; 9671 fwdt->length = 0; 9672 9673 template_size = le32_to_cpu(((__le32 *)fw_dump_tmplt)[2]); 9674 9675 ql_dbg(ql_dbg_init, vha, 0x0161, 9676 "-> fwdt%u template array at %p (0x%x bytes)\n", 9677 j, fw_dump_tmplt, template_size); 9678 9679 if (!template_size || !~template_size || 9680 template_size > ha->fw_dump_tmplt_len) { 9681 ql_dbg(ql_dbg_init, vha, 0x0162, 9682 "-> fwdt%u failed to read array\n", j); 9683 goto failed; 9684 } 9685 9686 fwdt->template = vmalloc(template_size); 9687 if (!fwdt->template) { 9688 ql_log(ql_log_warn, vha, 0x0164, 9689 "-> fwdt%u failed allocate template.\n", j); 9690 goto failed; 9691 } 9692 9693 dcode = fwdt->template; 9694 memcpy((char *)dcode, (char *)fw_dump_tmplt, template_size); 9695 9696 if (!qla27xx_fwdt_template_valid(dcode)) { 9697 ql_log(ql_log_warn, vha, 0x0165, 9698 "-> fwdt%u failed template validate (rval %x)\n", 9699 j, rval); 9700 goto failed; 9701 } 9702 9703 len = qla27xx_fwdt_template_size(dcode); 9704 if (len > template_size) { 9705 ql_log(ql_log_warn, vha, 0x0167, 9706 "-> fwdt%u template exceeds array (%-u bytes)\n", 9707 j, len - template_size); 9708 goto failed; 9709 } 9710 9711 fwdt->length = len; 9712 } 9713 9714 kfree(fw_dump_tmplt); 9715 return QLA_SUCCESS; 9716 9717 failed: 9718 if (fwdt->template) { 9719 vfree(fwdt->template); 9720 fwdt->template = NULL; 9721 fwdt->length = 0; 9722 } 9723 free_fw_dump: 9724 kfree(fw_dump_tmplt); 9725 return QLA_FUNCTION_FAILED; 9726 } 9727 9728 int 9729 qla29xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 9730 { 9731 int rval; 9732 9733 *srisc_addr = 0x100000; 9734 9735 if (ql2xfwloadbin == 2) { 9736 rval = qla29xx_load_risc_blob(vha, srisc_addr); 9737 if (rval != QLA_SUCCESS) { 9738 ql_log(ql_log_fatal, vha, 0x019e, 9739 "Failed to load firmware from file.\n"); 9740 return QLA_FUNCTION_FAILED; 9741 } 9742 } else { 9743 rval = qla28xx_load_flash_firmware(vha); 9744 if (rval != QLA_SUCCESS) { 9745 ql_log(ql_log_fatal, vha, 0x019e, 9746 "Failed to load flash firmware.\n"); 9747 return QLA_FUNCTION_FAILED; 9748 } 9749 9750 rval = qla29xx_load_fw_template(vha); 9751 if (rval != QLA_SUCCESS) { 9752 ql_log(ql_log_warn, vha, 0x01bd, 9753 "failed to read firmware template\n"); 9754 return QLA_FUNCTION_FAILED; 9755 } 9756 } 9757 9758 return rval; 9759 } 9760 9761 void 9762 qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) 9763 { 9764 int ret, retries; 9765 struct qla_hw_data *ha = vha->hw; 9766 9767 if (ha->flags.pci_channel_io_perm_failure) 9768 return; 9769 if (!IS_FWI2_CAPABLE(ha)) 9770 return; 9771 if (!ha->fw_major_version) 9772 return; 9773 if (!ha->flags.fw_started) 9774 return; 9775 9776 ret = qla2x00_stop_firmware(vha); 9777 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && 9778 ret != QLA_INVALID_COMMAND && retries ; retries--) { 9779 ha->isp_ops->reset_chip(vha); 9780 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) 9781 continue; 9782 if (qla2x00_setup_chip(vha) != QLA_SUCCESS) 9783 continue; 9784 ql_log(ql_log_info, vha, 0x8015, 9785 "Attempting retry of stop-firmware command.\n"); 9786 ret = qla2x00_stop_firmware(vha); 9787 } 9788 9789 QLA_FW_STOPPED(ha); 9790 ha->flags.fw_init_done = 0; 9791 } 9792 9793 int 9794 qla24xx_configure_vhba(scsi_qla_host_t *vha) 9795 { 9796 int rval = QLA_SUCCESS; 9797 int rval2; 9798 uint16_t mb[MAILBOX_REGISTER_COUNT]; 9799 struct qla_hw_data *ha = vha->hw; 9800 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 9801 9802 if (!vha->vp_idx) 9803 return -EINVAL; 9804 9805 rval = qla2x00_fw_ready(base_vha); 9806 9807 if (rval == QLA_SUCCESS) { 9808 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 9809 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 9810 } 9811 9812 vha->flags.management_server_logged_in = 0; 9813 9814 /* Login to SNS first */ 9815 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, 9816 BIT_1); 9817 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 9818 if (rval2 == QLA_MEMORY_ALLOC_FAILED) 9819 ql_dbg(ql_dbg_init, vha, 0x0120, 9820 "Failed SNS login: loop_id=%x, rval2=%d\n", 9821 NPH_SNS, rval2); 9822 else 9823 ql_dbg(ql_dbg_init, vha, 0x0103, 9824 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " 9825 "mb[2]=%x mb[6]=%x mb[7]=%x.\n", 9826 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); 9827 return (QLA_FUNCTION_FAILED); 9828 } 9829 9830 atomic_set(&vha->loop_down_timer, 0); 9831 atomic_set(&vha->loop_state, LOOP_UP); 9832 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 9833 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 9834 rval = qla2x00_loop_resync(base_vha); 9835 9836 return rval; 9837 } 9838 9839 /* 84XX Support **************************************************************/ 9840 9841 static LIST_HEAD(qla_cs84xx_list); 9842 static DEFINE_MUTEX(qla_cs84xx_mutex); 9843 9844 static struct qla_chip_state_84xx * 9845 qla84xx_get_chip(struct scsi_qla_host *vha) 9846 { 9847 struct qla_chip_state_84xx *cs84xx; 9848 struct qla_hw_data *ha = vha->hw; 9849 9850 mutex_lock(&qla_cs84xx_mutex); 9851 9852 /* Find any shared 84xx chip. */ 9853 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { 9854 if (cs84xx->bus == ha->pdev->bus) { 9855 kref_get(&cs84xx->kref); 9856 goto done; 9857 } 9858 } 9859 9860 cs84xx = kzalloc_obj(*cs84xx); 9861 if (!cs84xx) 9862 goto done; 9863 9864 kref_init(&cs84xx->kref); 9865 spin_lock_init(&cs84xx->access_lock); 9866 mutex_init(&cs84xx->fw_update_mutex); 9867 cs84xx->bus = ha->pdev->bus; 9868 9869 list_add_tail(&cs84xx->list, &qla_cs84xx_list); 9870 done: 9871 mutex_unlock(&qla_cs84xx_mutex); 9872 return cs84xx; 9873 } 9874 9875 static void 9876 __qla84xx_chip_release(struct kref *kref) 9877 { 9878 struct qla_chip_state_84xx *cs84xx = 9879 container_of(kref, struct qla_chip_state_84xx, kref); 9880 9881 mutex_lock(&qla_cs84xx_mutex); 9882 list_del(&cs84xx->list); 9883 mutex_unlock(&qla_cs84xx_mutex); 9884 kfree(cs84xx); 9885 } 9886 9887 void 9888 qla84xx_put_chip(struct scsi_qla_host *vha) 9889 { 9890 struct qla_hw_data *ha = vha->hw; 9891 9892 if (ha->cs84xx) 9893 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); 9894 } 9895 9896 static int 9897 qla84xx_init_chip(scsi_qla_host_t *vha) 9898 { 9899 int rval; 9900 uint16_t status[2]; 9901 struct qla_hw_data *ha = vha->hw; 9902 9903 mutex_lock(&ha->cs84xx->fw_update_mutex); 9904 9905 rval = qla84xx_verify_chip(vha, status); 9906 9907 mutex_unlock(&ha->cs84xx->fw_update_mutex); 9908 9909 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED : 9910 QLA_SUCCESS; 9911 } 9912 9913 /* 81XX Support **************************************************************/ 9914 9915 int 9916 qla81xx_nvram_config(scsi_qla_host_t *vha) 9917 { 9918 int rval; 9919 struct init_cb_81xx *icb; 9920 struct nvram_81xx *nv; 9921 __le32 *dptr; 9922 uint8_t *dptr1, *dptr2; 9923 uint32_t chksum; 9924 uint16_t cnt; 9925 struct qla_hw_data *ha = vha->hw; 9926 uint32_t faddr; 9927 struct active_regions active_regions = { }; 9928 9929 rval = QLA_SUCCESS; 9930 icb = (struct init_cb_81xx *)ha->init_cb; 9931 nv = ha->nvram; 9932 9933 /* Determine NVRAM starting address. */ 9934 ha->nvram_size = sizeof(*nv); 9935 ha->vpd_size = FA_NVRAM_VPD_SIZE; 9936 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 9937 ha->vpd_size = FA_VPD_SIZE_82XX; 9938 9939 /* Get VPD data into cache */ 9940 ha->vpd = ha->nvram + VPD_OFFSET; 9941 9942 if (IS_QLA29XX(ha)) { 9943 uint16_t fw_options = 0, r_code; 9944 uint32_t vpd_r[] = {FLT_REG_VPD_0, FLT_REG_VPD_1, 9945 FLT_REG_VPD_2, FLT_REG_VPD_3}; 9946 uint32_t nvram_r[] = {FLT_REG_NVRAM_0, FLT_REG_NVRAM_1, 9947 FLT_REG_NVRAM_2, FLT_REG_NVRAM_3}; 9948 void *buf; 9949 9950 BUILD_BUG_ON((VPD_OFFSET + FA_NVRAM_VPD_SIZE + 9951 sizeof(struct qla_flash_memo_block)) > 9952 MAX_NVRAM_SIZE); 9953 9954 ha->fiv = (struct qla_flash_memo_block *) 9955 ((char *)ha->vpd + ha->vpd_size); 9956 9957 buf = qla29xx_read_optrom_data(vha, FLT_REG_FMB_PRI, 9958 fw_options, ha->fiv, 0, 9959 sizeof(struct qla_flash_memo_block)); 9960 if (!buf) { 9961 ql_log(ql_log_info, vha, 0x01be, 9962 "Unable to read Flash Image Version.\n"); 9963 } else if (ha->fiv->signature != QLFC_FMB_SIG) { 9964 ql_log(ql_log_warn, vha, 0x01bf, 9965 "Invalid FMB signature %#x, expected %#x.\n", 9966 le32_to_cpu(ha->fiv->signature), 9967 le32_to_cpu(QLFC_FMB_SIG)); 9968 ha->fiv = NULL; 9969 } else { 9970 ql_log(ql_log_info, vha, 0x0024, 9971 "Flash Image Version %u.%02u.%02u\n", 9972 ha->fiv->mbi_ver.major, 9973 ha->fiv->mbi_ver.minor, 9974 ha->fiv->mbi_ver.sub); 9975 } 9976 9977 if (ha->port_no >= ARRAY_SIZE(vpd_r)) { 9978 ql_log(ql_log_warn, vha, 0x002e, 9979 "Invalid port number %u, skipping VPD/NVRAM read.\n", 9980 ha->port_no); 9981 goto out_29xx; 9982 } 9983 9984 r_code = vpd_r[ha->port_no]; 9985 buf = qla29xx_read_optrom_data(vha, r_code, fw_options, 9986 ha->vpd, 0, ha->vpd_size); 9987 if (!buf) 9988 ql_log(ql_log_info, vha, 0x002d, 9989 "Unable to read VPD info.\n"); 9990 9991 r_code = nvram_r[ha->port_no]; 9992 buf = qla29xx_read_optrom_data(vha, r_code, fw_options, 9993 ha->nvram, 0, ha->nvram_size); 9994 if (!buf) 9995 ql_log(ql_log_info, vha, 0x0013, 9996 "Unable to read nvram config info.\n"); 9997 } else { 9998 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) 9999 qla28xx_get_aux_images(vha, &active_regions); 10000 10001 faddr = ha->flt_region_vpd; 10002 if (IS_QLA28XX(ha)) { 10003 if (active_regions.aux.vpd_nvram == 10004 QLA27XX_SECONDARY_IMAGE) 10005 faddr = ha->flt_region_vpd_sec; 10006 ql_dbg(ql_dbg_init, vha, 0x0110, 10007 "Loading %s nvram image.\n", 10008 active_regions.aux.vpd_nvram == 10009 QLA27XX_PRIMARY_IMAGE ? 10010 "primary" : "secondary"); 10011 } 10012 ha->isp_ops->read_optrom(vha, ha->vpd, faddr << 2, 10013 ha->vpd_size); 10014 10015 /* Get NVRAM data into cache and calculate checksum. */ 10016 faddr = ha->flt_region_nvram; 10017 if (IS_QLA28XX(ha)) { 10018 if (active_regions.aux.vpd_nvram == 10019 QLA27XX_SECONDARY_IMAGE) 10020 faddr = ha->flt_region_nvram_sec; 10021 } 10022 ql_dbg(ql_dbg_init, vha, 0x0110, 10023 "Loading %s nvram image.\n", 10024 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ? 10025 "primary" : "secondary"); 10026 ha->isp_ops->read_optrom(vha, ha->nvram, faddr << 2, 10027 ha->nvram_size); 10028 } 10029 10030 out_29xx: 10031 dptr = (__force __le32 *)nv; 10032 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 10033 chksum += le32_to_cpu(*dptr); 10034 10035 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, 10036 "Contents of NVRAM:\n"); 10037 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, 10038 nv, ha->nvram_size); 10039 10040 /* Bad NVRAM data, set defaults parameters. */ 10041 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 10042 le16_to_cpu(nv->nvram_version) < ICB_VERSION) { 10043 /* Reset NVRAM data. */ 10044 ql_log(ql_log_info, vha, 0x0073, 10045 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n", 10046 chksum, nv->id, le16_to_cpu(nv->nvram_version)); 10047 ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv)); 10048 ql_log(ql_log_info, vha, 0x0074, 10049 "Falling back to functioning (yet invalid -- WWPN) " 10050 "defaults.\n"); 10051 10052 /* 10053 * Set default initialization control block. 10054 */ 10055 memset(nv, 0, ha->nvram_size); 10056 nv->nvram_version = cpu_to_le16(ICB_VERSION); 10057 nv->version = cpu_to_le16(ICB_VERSION); 10058 nv->frame_payload_size = cpu_to_le16(2048); 10059 nv->execution_throttle = cpu_to_le16(0xFFFF); 10060 nv->exchange_count = cpu_to_le16(0); 10061 nv->port_name[0] = 0x21; 10062 nv->port_name[1] = 0x00 + ha->port_no + 1; 10063 nv->port_name[2] = 0x00; 10064 nv->port_name[3] = 0xe0; 10065 nv->port_name[4] = 0x8b; 10066 nv->port_name[5] = 0x1c; 10067 nv->port_name[6] = 0x55; 10068 nv->port_name[7] = 0x86; 10069 nv->node_name[0] = 0x20; 10070 nv->node_name[1] = 0x00; 10071 nv->node_name[2] = 0x00; 10072 nv->node_name[3] = 0xe0; 10073 nv->node_name[4] = 0x8b; 10074 nv->node_name[5] = 0x1c; 10075 nv->node_name[6] = 0x55; 10076 nv->node_name[7] = 0x86; 10077 nv->login_retry_count = cpu_to_le16(8); 10078 nv->interrupt_delay_timer = cpu_to_le16(0); 10079 nv->login_timeout = cpu_to_le16(0); 10080 nv->firmware_options_1 = 10081 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 10082 if (IS_QLA29XX(ha)) 10083 nv->firmware_options_2 = cpu_to_le32(BIT_4); 10084 else 10085 nv->firmware_options_2 = cpu_to_le32(BIT_5); 10086 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 10087 nv->firmware_options_3 = cpu_to_le32(2 << 13); 10088 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 10089 nv->efi_parameters = cpu_to_le32(0); 10090 nv->reset_delay = 5; 10091 nv->max_luns_per_target = cpu_to_le16(128); 10092 nv->port_down_retry_count = cpu_to_le16(30); 10093 nv->link_down_timeout = cpu_to_le16(180); 10094 nv->enode_mac[0] = 0x00; 10095 nv->enode_mac[1] = 0xC0; 10096 nv->enode_mac[2] = 0xDD; 10097 nv->enode_mac[3] = 0x04; 10098 nv->enode_mac[4] = 0x05; 10099 nv->enode_mac[5] = 0x06 + ha->port_no + 1; 10100 10101 rval = 1; 10102 } 10103 10104 if (IS_T10_PI_CAPABLE(ha)) 10105 nv->frame_payload_size &= cpu_to_le16(~7); 10106 10107 qlt_81xx_config_nvram_stage1(vha, nv); 10108 10109 /* Reset Initialization control block */ 10110 memset(icb, 0, ha->init_cb_size); 10111 10112 /* Copy 1st segment. */ 10113 dptr1 = (uint8_t *)icb; 10114 dptr2 = (uint8_t *)&nv->version; 10115 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 10116 while (cnt--) 10117 *dptr1++ = *dptr2++; 10118 10119 icb->login_retry_count = nv->login_retry_count; 10120 10121 /* Copy 2nd segment. */ 10122 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 10123 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 10124 cnt = (uint8_t *)&icb->reserved_5 - 10125 (uint8_t *)&icb->interrupt_delay_timer; 10126 while (cnt--) 10127 *dptr1++ = *dptr2++; 10128 10129 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); 10130 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ 10131 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { 10132 icb->enode_mac[0] = 0x00; 10133 icb->enode_mac[1] = 0xC0; 10134 icb->enode_mac[2] = 0xDD; 10135 icb->enode_mac[3] = 0x04; 10136 icb->enode_mac[4] = 0x05; 10137 icb->enode_mac[5] = 0x06 + ha->port_no + 1; 10138 } 10139 10140 /* Use extended-initialization control block. */ 10141 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); 10142 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 10143 /* 10144 * Setup driver NVRAM options. 10145 */ 10146 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 10147 "QLE8XXX"); 10148 10149 qlt_81xx_config_nvram_stage2(vha, icb); 10150 10151 /* Use alternate WWN? */ 10152 if (nv->host_p & cpu_to_le32(BIT_15)) { 10153 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 10154 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 10155 } 10156 10157 /* Prepare nodename */ 10158 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 10159 /* 10160 * Firmware will apply the following mask if the nodename was 10161 * not provided. 10162 */ 10163 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 10164 icb->node_name[0] &= 0xF0; 10165 } 10166 10167 /* SCM Enabled in NVRAM */ 10168 if (IS_QLA29XX(ha) || IS_QLA28XX(ha) || IS_QLA27XX(ha)) { 10169 if ((le16_to_cpu(nv->enhanced_features) & BIT_7) == 0) { 10170 ql_log(ql_log_info, vha, 0x0062, 10171 "USCM enabled in NVRAM\n"); 10172 ha->flags.scm_supported_a = 1; 10173 } 10174 } 10175 10176 /* Set host adapter parameters. */ 10177 ha->flags.disable_risc_code_load = 0; 10178 ha->flags.enable_lip_reset = 0; 10179 ha->flags.enable_lip_full_login = 10180 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0; 10181 ha->flags.enable_target_reset = 10182 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0; 10183 ha->flags.enable_led_scheme = 0; 10184 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0; 10185 10186 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 10187 (BIT_6 | BIT_5 | BIT_4)) >> 4; 10188 10189 /* save HBA serial number */ 10190 ha->serial0 = icb->port_name[5]; 10191 ha->serial1 = icb->port_name[6]; 10192 ha->serial2 = icb->port_name[7]; 10193 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 10194 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 10195 10196 icb->execution_throttle = cpu_to_le16(0xFFFF); 10197 10198 ha->retry_count = le16_to_cpu(nv->login_retry_count); 10199 10200 /* Set minimum login_timeout to 4 seconds. */ 10201 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 10202 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 10203 if (le16_to_cpu(nv->login_timeout) < 4) 10204 nv->login_timeout = cpu_to_le16(4); 10205 ha->login_timeout = le16_to_cpu(nv->login_timeout); 10206 10207 /* Set minimum RATOV to 100 tenths of a second. */ 10208 ha->r_a_tov = 100; 10209 10210 ha->loop_reset_delay = nv->reset_delay; 10211 10212 /* Link Down Timeout = 0: 10213 * 10214 * When Port Down timer expires we will start returning 10215 * I/O's to OS with "DID_NO_CONNECT". 10216 * 10217 * Link Down Timeout != 0: 10218 * 10219 * The driver waits for the link to come up after link down 10220 * before returning I/Os to OS with "DID_NO_CONNECT". 10221 */ 10222 if (le16_to_cpu(nv->link_down_timeout) == 0) { 10223 ha->loop_down_abort_time = 10224 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 10225 } else { 10226 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 10227 ha->loop_down_abort_time = 10228 (LOOP_DOWN_TIME - ha->link_down_timeout); 10229 } 10230 10231 /* Need enough time to try and get the port back. */ 10232 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 10233 if (qlport_down_retry) 10234 ha->port_down_retry_count = qlport_down_retry; 10235 10236 /* Set login_retry_count */ 10237 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 10238 if (ha->port_down_retry_count == 10239 le16_to_cpu(nv->port_down_retry_count) && 10240 ha->port_down_retry_count > 3) 10241 ha->login_retry_count = ha->port_down_retry_count; 10242 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 10243 ha->login_retry_count = ha->port_down_retry_count; 10244 if (ql2xloginretrycount) 10245 ha->login_retry_count = ql2xloginretrycount; 10246 10247 /* if not running MSI-X we need handshaking on interrupts */ 10248 if (!vha->hw->flags.msix_enabled && 10249 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha) || 10250 IS_QLA29XX(ha))) 10251 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 10252 10253 /* Enable ZIO. */ 10254 if (!vha->flags.init_done) { 10255 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 10256 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 10257 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 10258 le16_to_cpu(icb->interrupt_delay_timer) : 2; 10259 } 10260 icb->firmware_options_2 &= cpu_to_le32( 10261 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 10262 vha->flags.process_response_queue = 0; 10263 if (ha->zio_mode != QLA_ZIO_DISABLED) { 10264 ha->zio_mode = QLA_ZIO_MODE_6; 10265 10266 ql_log(ql_log_info, vha, 0x0075, 10267 "ZIO mode %d enabled; timer delay (%d us).\n", 10268 ha->zio_mode, 10269 ha->zio_timer * 100); 10270 10271 icb->firmware_options_2 |= cpu_to_le32( 10272 (uint32_t)ha->zio_mode); 10273 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 10274 vha->flags.process_response_queue = 1; 10275 } 10276 10277 /* enable RIDA Format2 */ 10278 icb->firmware_options_3 |= cpu_to_le32(BIT_0); 10279 10280 /* N2N: driver will initiate Login instead of FW */ 10281 icb->firmware_options_3 |= cpu_to_le32(BIT_8); 10282 10283 /* Determine NVMe/FCP priority for target ports */ 10284 ha->fc4_type_priority = qla2xxx_get_fc4_priority(vha); 10285 10286 if (rval) { 10287 ql_log(ql_log_warn, vha, 0x0076, 10288 "NVRAM configuration failed.\n"); 10289 } 10290 return (rval); 10291 } 10292 10293 int 10294 qla82xx_restart_isp(scsi_qla_host_t *vha) 10295 { 10296 int status, rval; 10297 struct qla_hw_data *ha = vha->hw; 10298 struct scsi_qla_host *vp, *tvp; 10299 unsigned long flags; 10300 10301 status = qla2x00_init_rings(vha); 10302 if (!status) { 10303 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 10304 ha->flags.chip_reset_done = 1; 10305 10306 status = qla2x00_fw_ready(vha); 10307 if (!status) { 10308 /* Issue a marker after FW becomes ready. */ 10309 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 10310 vha->flags.online = 1; 10311 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 10312 } 10313 10314 /* if no cable then assume it's good */ 10315 if ((vha->device_flags & DFLG_NO_CABLE)) 10316 status = 0; 10317 } 10318 10319 if (!status) { 10320 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 10321 10322 if (!atomic_read(&vha->loop_down_timer)) { 10323 /* 10324 * Issue marker command only when we are going 10325 * to start the I/O . 10326 */ 10327 vha->marker_needed = 1; 10328 } 10329 10330 ha->isp_ops->enable_intrs(ha); 10331 10332 ha->isp_abort_cnt = 0; 10333 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 10334 10335 /* Update the firmware version */ 10336 status = qla82xx_check_md_needed(vha); 10337 10338 if (ha->fce) { 10339 ha->flags.fce_enabled = 1; 10340 memset(ha->fce, 0, 10341 fce_calc_size(ha->fce_bufs)); 10342 rval = qla2x00_enable_fce_trace(vha, 10343 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 10344 &ha->fce_bufs); 10345 if (rval) { 10346 ql_log(ql_log_warn, vha, 0x8001, 10347 "Unable to reinitialize FCE (%d).\n", 10348 rval); 10349 ha->flags.fce_enabled = 0; 10350 } 10351 } 10352 10353 if (ha->eft) { 10354 memset(ha->eft, 0, EFT_SIZE); 10355 rval = qla2x00_enable_eft_trace(vha, 10356 ha->eft_dma, EFT_NUM_BUFFERS); 10357 if (rval) { 10358 ql_log(ql_log_warn, vha, 0x8010, 10359 "Unable to reinitialize EFT (%d).\n", 10360 rval); 10361 } 10362 } 10363 } 10364 10365 if (!status) { 10366 ql_dbg(ql_dbg_taskm, vha, 0x8011, 10367 "qla82xx_restart_isp succeeded.\n"); 10368 10369 spin_lock_irqsave(&ha->vport_slock, flags); 10370 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 10371 if (vp->vp_idx) { 10372 atomic_inc(&vp->vref_count); 10373 spin_unlock_irqrestore(&ha->vport_slock, flags); 10374 10375 qla2x00_vp_abort_isp(vp); 10376 10377 spin_lock_irqsave(&ha->vport_slock, flags); 10378 atomic_dec(&vp->vref_count); 10379 } 10380 } 10381 spin_unlock_irqrestore(&ha->vport_slock, flags); 10382 10383 } else { 10384 ql_log(ql_log_warn, vha, 0x8016, 10385 "qla82xx_restart_isp **** FAILED ****.\n"); 10386 } 10387 10388 return status; 10389 } 10390 10391 /* 10392 * qla24xx_get_fcp_prio 10393 * Gets the fcp cmd priority value for the logged in port. 10394 * Looks for a match of the port descriptors within 10395 * each of the fcp prio config entries. If a match is found, 10396 * the tag (priority) value is returned. 10397 * 10398 * Input: 10399 * vha = scsi host structure pointer. 10400 * fcport = port structure pointer. 10401 * 10402 * Return: 10403 * non-zero (if found) 10404 * -1 (if not found) 10405 * 10406 * Context: 10407 * Kernel context 10408 */ 10409 static int 10410 qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 10411 { 10412 int i, entries; 10413 uint8_t pid_match, wwn_match; 10414 int priority; 10415 uint32_t pid1, pid2; 10416 uint64_t wwn1, wwn2; 10417 struct qla_fcp_prio_entry *pri_entry; 10418 struct qla_hw_data *ha = vha->hw; 10419 10420 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) 10421 return -1; 10422 10423 priority = -1; 10424 entries = ha->fcp_prio_cfg->num_entries; 10425 pri_entry = &ha->fcp_prio_cfg->entry[0]; 10426 10427 for (i = 0; i < entries; i++) { 10428 pid_match = wwn_match = 0; 10429 10430 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { 10431 pri_entry++; 10432 continue; 10433 } 10434 10435 /* check source pid for a match */ 10436 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { 10437 pid1 = pri_entry->src_pid & INVALID_PORT_ID; 10438 pid2 = vha->d_id.b24 & INVALID_PORT_ID; 10439 if (pid1 == INVALID_PORT_ID) 10440 pid_match++; 10441 else if (pid1 == pid2) 10442 pid_match++; 10443 } 10444 10445 /* check destination pid for a match */ 10446 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { 10447 pid1 = pri_entry->dst_pid & INVALID_PORT_ID; 10448 pid2 = fcport->d_id.b24 & INVALID_PORT_ID; 10449 if (pid1 == INVALID_PORT_ID) 10450 pid_match++; 10451 else if (pid1 == pid2) 10452 pid_match++; 10453 } 10454 10455 /* check source WWN for a match */ 10456 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { 10457 wwn1 = wwn_to_u64(vha->port_name); 10458 wwn2 = wwn_to_u64(pri_entry->src_wwpn); 10459 if (wwn2 == (uint64_t)-1) 10460 wwn_match++; 10461 else if (wwn1 == wwn2) 10462 wwn_match++; 10463 } 10464 10465 /* check destination WWN for a match */ 10466 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { 10467 wwn1 = wwn_to_u64(fcport->port_name); 10468 wwn2 = wwn_to_u64(pri_entry->dst_wwpn); 10469 if (wwn2 == (uint64_t)-1) 10470 wwn_match++; 10471 else if (wwn1 == wwn2) 10472 wwn_match++; 10473 } 10474 10475 if (pid_match == 2 || wwn_match == 2) { 10476 /* Found a matching entry */ 10477 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) 10478 priority = pri_entry->tag; 10479 break; 10480 } 10481 10482 pri_entry++; 10483 } 10484 10485 return priority; 10486 } 10487 10488 /* 10489 * qla24xx_update_fcport_fcp_prio 10490 * Activates fcp priority for the logged in fc port 10491 * 10492 * Input: 10493 * vha = scsi host structure pointer. 10494 * fcp = port structure pointer. 10495 * 10496 * Return: 10497 * QLA_SUCCESS or QLA_FUNCTION_FAILED 10498 * 10499 * Context: 10500 * Kernel context. 10501 */ 10502 int 10503 qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 10504 { 10505 int ret; 10506 int priority; 10507 uint16_t mb[5]; 10508 10509 if (fcport->port_type != FCT_TARGET || 10510 fcport->loop_id == FC_NO_LOOP_ID) 10511 return QLA_FUNCTION_FAILED; 10512 10513 priority = qla24xx_get_fcp_prio(vha, fcport); 10514 if (priority < 0) 10515 return QLA_FUNCTION_FAILED; 10516 10517 if (IS_P3P_TYPE(vha->hw)) { 10518 fcport->fcp_prio = priority & 0xf; 10519 return QLA_SUCCESS; 10520 } 10521 10522 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); 10523 if (ret == QLA_SUCCESS) { 10524 if (fcport->fcp_prio != priority) 10525 ql_dbg(ql_dbg_user, vha, 0x709e, 10526 "Updated FCP_CMND priority - value=%d loop_id=%d " 10527 "port_id=%02x%02x%02x.\n", priority, 10528 fcport->loop_id, fcport->d_id.b.domain, 10529 fcport->d_id.b.area, fcport->d_id.b.al_pa); 10530 fcport->fcp_prio = priority & 0xf; 10531 } else 10532 ql_dbg(ql_dbg_user, vha, 0x704f, 10533 "Unable to update FCP_CMND priority - ret=0x%x for " 10534 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, 10535 fcport->d_id.b.domain, fcport->d_id.b.area, 10536 fcport->d_id.b.al_pa); 10537 return ret; 10538 } 10539 10540 /* 10541 * qla24xx_update_all_fcp_prio 10542 * Activates fcp priority for all the logged in ports 10543 * 10544 * Input: 10545 * ha = adapter block pointer. 10546 * 10547 * Return: 10548 * QLA_SUCCESS or QLA_FUNCTION_FAILED 10549 * 10550 * Context: 10551 * Kernel context. 10552 */ 10553 int 10554 qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) 10555 { 10556 int ret; 10557 fc_port_t *fcport; 10558 10559 ret = QLA_FUNCTION_FAILED; 10560 /* We need to set priority for all logged in ports */ 10561 list_for_each_entry(fcport, &vha->vp_fcports, list) 10562 ret = qla24xx_update_fcport_fcp_prio(vha, fcport); 10563 10564 return ret; 10565 } 10566 10567 struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, 10568 int vp_idx, bool startqp) 10569 { 10570 int rsp_id = 0; 10571 int req_id = 0; 10572 int i; 10573 struct qla_hw_data *ha = vha->hw; 10574 uint16_t qpair_id = 0; 10575 struct qla_qpair *qpair = NULL; 10576 struct qla_msix_entry *msix; 10577 10578 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) { 10579 ql_log(ql_log_warn, vha, 0x00181, 10580 "FW/Driver is not multi-queue capable.\n"); 10581 return NULL; 10582 } 10583 10584 if (ql2xmqsupport || ql2xnvmeenable) { 10585 qpair = kzalloc_obj(struct qla_qpair); 10586 if (qpair == NULL) { 10587 ql_log(ql_log_warn, vha, 0x0182, 10588 "Failed to allocate memory for queue pair.\n"); 10589 return NULL; 10590 } 10591 10592 qpair->hw = vha->hw; 10593 qpair->vha = vha; 10594 qpair->qp_lock_ptr = &qpair->qp_lock; 10595 spin_lock_init(&qpair->qp_lock); 10596 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 10597 10598 /* Assign available que pair id */ 10599 mutex_lock(&ha->mq_lock); 10600 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs); 10601 if (ha->num_qpairs >= ha->max_qpairs) { 10602 mutex_unlock(&ha->mq_lock); 10603 ql_log(ql_log_warn, vha, 0x0183, 10604 "No resources to create additional q pair.\n"); 10605 goto fail_qid_map; 10606 } 10607 ha->num_qpairs++; 10608 set_bit(qpair_id, ha->qpair_qid_map); 10609 ha->queue_pair_map[qpair_id] = qpair; 10610 qpair->id = qpair_id; 10611 qpair->vp_idx = vp_idx; 10612 qpair->fw_started = ha->flags.fw_started; 10613 INIT_LIST_HEAD(&qpair->hints_list); 10614 INIT_LIST_HEAD(&qpair->dsd_list); 10615 qpair->chip_reset = ha->base_qpair->chip_reset; 10616 qpair->enable_class_2 = ha->base_qpair->enable_class_2; 10617 qpair->enable_explicit_conf = 10618 ha->base_qpair->enable_explicit_conf; 10619 10620 for (i = 0; i < ha->msix_count; i++) { 10621 msix = &ha->msix_entries[i]; 10622 if (msix->in_use) 10623 continue; 10624 qpair->msix = msix; 10625 ql_dbg(ql_dbg_multiq, vha, 0xc00f, 10626 "Vector %x selected for qpair\n", msix->vector); 10627 break; 10628 } 10629 if (!qpair->msix) { 10630 ql_log(ql_log_warn, vha, 0x0184, 10631 "Out of MSI-X vectors!.\n"); 10632 goto fail_msix; 10633 } 10634 10635 qpair->msix->in_use = 1; 10636 list_add_tail(&qpair->qp_list_elem, &vha->qp_list); 10637 qpair->pdev = ha->pdev; 10638 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 10639 qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 10640 10641 mutex_unlock(&ha->mq_lock); 10642 10643 /* Create response queue first */ 10644 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp); 10645 if (!rsp_id) { 10646 ql_log(ql_log_warn, vha, 0x0185, 10647 "Failed to create response queue.\n"); 10648 goto fail_rsp; 10649 } 10650 10651 qpair->rsp = ha->rsp_q_map[rsp_id]; 10652 10653 /* Create request queue */ 10654 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos, 10655 startqp); 10656 if (!req_id) { 10657 ql_log(ql_log_warn, vha, 0x0186, 10658 "Failed to create request queue.\n"); 10659 goto fail_req; 10660 } 10661 10662 qpair->req = ha->req_q_map[req_id]; 10663 qpair->rsp->req = qpair->req; 10664 qpair->rsp->qpair = qpair; 10665 10666 if (!qpair->cpu_mapped) 10667 qla_cpu_update(qpair, raw_smp_processor_id()); 10668 10669 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 10670 if (ha->fw_attributes & BIT_4) 10671 qpair->difdix_supported = 1; 10672 } 10673 10674 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 10675 if (!qpair->srb_mempool) { 10676 ql_log(ql_log_warn, vha, 0xd036, 10677 "Failed to create srb mempool for qpair %d\n", 10678 qpair->id); 10679 goto fail_mempool; 10680 } 10681 10682 if (qla_create_buf_pool(vha, qpair)) { 10683 ql_log(ql_log_warn, vha, 0xd036, 10684 "Failed to initialize buf pool for qpair %d\n", 10685 qpair->id); 10686 goto fail_bufpool; 10687 } 10688 10689 /* Mark as online */ 10690 qpair->online = 1; 10691 10692 if (!vha->flags.qpairs_available) 10693 vha->flags.qpairs_available = 1; 10694 10695 ql_dbg(ql_dbg_multiq, vha, 0xc00d, 10696 "Request/Response queue pair created, id %d\n", 10697 qpair->id); 10698 ql_dbg(ql_dbg_init, vha, 0x0187, 10699 "Request/Response queue pair created, id %d\n", 10700 qpair->id); 10701 } 10702 return qpair; 10703 10704 fail_bufpool: 10705 mempool_destroy(qpair->srb_mempool); 10706 fail_mempool: 10707 qla25xx_delete_req_que(vha, qpair->req); 10708 fail_req: 10709 qla25xx_delete_rsp_que(vha, qpair->rsp); 10710 fail_rsp: 10711 mutex_lock(&ha->mq_lock); 10712 qpair->msix->in_use = 0; 10713 list_del(&qpair->qp_list_elem); 10714 if (list_empty(&vha->qp_list)) 10715 vha->flags.qpairs_available = 0; 10716 fail_msix: 10717 ha->queue_pair_map[qpair_id] = NULL; 10718 clear_bit(qpair_id, ha->qpair_qid_map); 10719 ha->num_qpairs--; 10720 mutex_unlock(&ha->mq_lock); 10721 fail_qid_map: 10722 kfree(qpair); 10723 return NULL; 10724 } 10725 10726 int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair) 10727 { 10728 int ret = QLA_FUNCTION_FAILED; 10729 struct qla_hw_data *ha = qpair->hw; 10730 struct rsp_que *rsp = qpair->rsp; 10731 10732 qpair->delete_in_progress = 1; 10733 10734 qla_free_buf_pool(qpair); 10735 10736 /* 10737 * The response-queue interrupt schedules qla_do_work(), which 10738 * dereferences qpair->rsp->req. Release the interrupt and flush 10739 * any pending work before the request queue is freed below so a 10740 * late completion cannot touch the freed request queue. The 10741 * firmware queue-delete order (request then response) is kept. 10742 */ 10743 if (rsp && rsp->msix && rsp->msix->have_irq) { 10744 free_irq(rsp->msix->vector, rsp->msix->handle); 10745 rsp->msix->have_irq = 0; 10746 rsp->msix->in_use = 0; 10747 rsp->msix->handle = NULL; 10748 } 10749 if (rsp && ha->wq) 10750 cancel_work_sync(&qpair->q_work); 10751 10752 ret = qla25xx_delete_req_que(vha, qpair->req); 10753 if (ret != QLA_SUCCESS) 10754 goto fail; 10755 10756 ret = qla25xx_delete_rsp_que(vha, qpair->rsp); 10757 if (ret != QLA_SUCCESS) 10758 goto fail; 10759 10760 if (!list_empty(&qpair->dsd_list)) { 10761 struct dsd_dma *dsd_ptr, *tdsd_ptr; 10762 10763 /* clean up allocated prev pool */ 10764 list_for_each_entry_safe(dsd_ptr, tdsd_ptr, 10765 &qpair->dsd_list, list) { 10766 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr, 10767 dsd_ptr->dsd_list_dma); 10768 list_del(&dsd_ptr->list); 10769 kfree(dsd_ptr); 10770 } 10771 } 10772 10773 mutex_lock(&ha->mq_lock); 10774 ha->queue_pair_map[qpair->id] = NULL; 10775 clear_bit(qpair->id, ha->qpair_qid_map); 10776 ha->num_qpairs--; 10777 list_del(&qpair->qp_list_elem); 10778 if (list_empty(&vha->qp_list)) { 10779 vha->flags.qpairs_available = 0; 10780 vha->flags.qpairs_req_created = 0; 10781 vha->flags.qpairs_rsp_created = 0; 10782 } 10783 mempool_destroy(qpair->srb_mempool); 10784 kfree(qpair); 10785 mutex_unlock(&ha->mq_lock); 10786 10787 return QLA_SUCCESS; 10788 fail: 10789 return ret; 10790 } 10791 10792 uint64_t 10793 qla2x00_count_set_bits(uint32_t num) 10794 { 10795 /* Brian Kernighan's Algorithm */ 10796 u64 count = 0; 10797 10798 while (num) { 10799 num &= (num - 1); 10800 count++; 10801 } 10802 return count; 10803 } 10804 10805 uint64_t 10806 qla2x00_get_num_tgts(scsi_qla_host_t *vha) 10807 { 10808 fc_port_t *f, *tf; 10809 u64 count = 0; 10810 10811 f = NULL; 10812 tf = NULL; 10813 10814 list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) { 10815 if (f->port_type != FCT_TARGET) 10816 continue; 10817 count++; 10818 } 10819 return count; 10820 } 10821 10822 int qla2xxx_reset_stats(struct Scsi_Host *host, u32 flags) 10823 { 10824 scsi_qla_host_t *vha = shost_priv(host); 10825 fc_port_t *fcport = NULL; 10826 unsigned long int_flags; 10827 10828 if (flags & QLA2XX_HW_ERROR) 10829 vha->hw_err_cnt = 0; 10830 if (flags & QLA2XX_SHT_LNK_DWN) 10831 vha->short_link_down_cnt = 0; 10832 if (flags & QLA2XX_INT_ERR) 10833 vha->interface_err_cnt = 0; 10834 if (flags & QLA2XX_CMD_TIMEOUT) 10835 vha->cmd_timeout_cnt = 0; 10836 if (flags & QLA2XX_RESET_CMD_ERR) 10837 vha->reset_cmd_err_cnt = 0; 10838 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) { 10839 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags); 10840 list_for_each_entry(fcport, &vha->vp_fcports, list) { 10841 fcport->tgt_short_link_down_cnt = 0; 10842 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 10843 } 10844 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags); 10845 } 10846 vha->link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 10847 return 0; 10848 } 10849 10850 int qla2xxx_start_stats(struct Scsi_Host *host, u32 flags) 10851 { 10852 return qla2xxx_reset_stats(host, flags); 10853 } 10854 10855 int qla2xxx_stop_stats(struct Scsi_Host *host, u32 flags) 10856 { 10857 return qla2xxx_reset_stats(host, flags); 10858 } 10859 10860 int qla2xxx_get_ini_stats(struct Scsi_Host *host, u32 flags, 10861 void *data, u64 size) 10862 { 10863 scsi_qla_host_t *vha = shost_priv(host); 10864 struct ql_vnd_host_stats_resp *resp = (struct ql_vnd_host_stats_resp *)data; 10865 struct ql_vnd_stats *rsp_data = &resp->stats; 10866 u64 ini_entry_count = 0; 10867 u64 i = 0; 10868 u64 entry_count = 0; 10869 u64 num_tgt = 0; 10870 u32 tmp_stat_type = 0; 10871 fc_port_t *fcport = NULL; 10872 unsigned long int_flags; 10873 10874 /* Copy stat type to work on it */ 10875 tmp_stat_type = flags; 10876 10877 if (tmp_stat_type & BIT_17) { 10878 num_tgt = qla2x00_get_num_tgts(vha); 10879 /* unset BIT_17 */ 10880 tmp_stat_type &= ~(1 << 17); 10881 } 10882 ini_entry_count = qla2x00_count_set_bits(tmp_stat_type); 10883 10884 entry_count = ini_entry_count + num_tgt; 10885 10886 rsp_data->entry_count = entry_count; 10887 10888 i = 0; 10889 if (flags & QLA2XX_HW_ERROR) { 10890 rsp_data->entry[i].stat_type = QLA2XX_HW_ERROR; 10891 rsp_data->entry[i].tgt_num = 0x0; 10892 rsp_data->entry[i].cnt = vha->hw_err_cnt; 10893 i++; 10894 } 10895 10896 if (flags & QLA2XX_SHT_LNK_DWN) { 10897 rsp_data->entry[i].stat_type = QLA2XX_SHT_LNK_DWN; 10898 rsp_data->entry[i].tgt_num = 0x0; 10899 rsp_data->entry[i].cnt = vha->short_link_down_cnt; 10900 i++; 10901 } 10902 10903 if (flags & QLA2XX_INT_ERR) { 10904 rsp_data->entry[i].stat_type = QLA2XX_INT_ERR; 10905 rsp_data->entry[i].tgt_num = 0x0; 10906 rsp_data->entry[i].cnt = vha->interface_err_cnt; 10907 i++; 10908 } 10909 10910 if (flags & QLA2XX_CMD_TIMEOUT) { 10911 rsp_data->entry[i].stat_type = QLA2XX_CMD_TIMEOUT; 10912 rsp_data->entry[i].tgt_num = 0x0; 10913 rsp_data->entry[i].cnt = vha->cmd_timeout_cnt; 10914 i++; 10915 } 10916 10917 if (flags & QLA2XX_RESET_CMD_ERR) { 10918 rsp_data->entry[i].stat_type = QLA2XX_RESET_CMD_ERR; 10919 rsp_data->entry[i].tgt_num = 0x0; 10920 rsp_data->entry[i].cnt = vha->reset_cmd_err_cnt; 10921 i++; 10922 } 10923 10924 /* i will continue from previous loop, as target 10925 * entries are after initiator 10926 */ 10927 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) { 10928 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags); 10929 list_for_each_entry(fcport, &vha->vp_fcports, list) { 10930 if (fcport->port_type != FCT_TARGET) 10931 continue; 10932 if (!fcport->rport) 10933 continue; 10934 rsp_data->entry[i].stat_type = QLA2XX_TGT_SHT_LNK_DOWN; 10935 rsp_data->entry[i].tgt_num = fcport->rport->number; 10936 rsp_data->entry[i].cnt = fcport->tgt_short_link_down_cnt; 10937 i++; 10938 } 10939 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags); 10940 } 10941 resp->status = EXT_STATUS_OK; 10942 10943 return 0; 10944 } 10945 10946 int qla2xxx_get_tgt_stats(struct Scsi_Host *host, u32 flags, 10947 struct fc_rport *rport, void *data, u64 size) 10948 { 10949 struct ql_vnd_tgt_stats_resp *tgt_data = data; 10950 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 10951 10952 tgt_data->status = 0; 10953 tgt_data->stats.entry_count = 1; 10954 tgt_data->stats.entry[0].stat_type = flags; 10955 tgt_data->stats.entry[0].tgt_num = rport->number; 10956 tgt_data->stats.entry[0].cnt = fcport->tgt_short_link_down_cnt; 10957 10958 return 0; 10959 } 10960 10961 int qla2xxx_disable_port(struct Scsi_Host *host) 10962 { 10963 scsi_qla_host_t *vha = shost_priv(host); 10964 10965 vha->hw->flags.port_isolated = 1; 10966 10967 if (qla2x00_isp_reg_stat(vha->hw)) { 10968 ql_log(ql_log_info, vha, 0x9006, 10969 "PCI/Register disconnect, exiting.\n"); 10970 qla_pci_set_eeh_busy(vha); 10971 return FAILED; 10972 } 10973 if (qla2x00_chip_is_down(vha)) 10974 return 0; 10975 10976 if (vha->flags.online) { 10977 qla2x00_abort_isp_cleanup(vha); 10978 qla2x00_wait_for_sess_deletion(vha); 10979 } 10980 10981 return 0; 10982 } 10983 10984 int qla2xxx_enable_port(struct Scsi_Host *host) 10985 { 10986 scsi_qla_host_t *vha = shost_priv(host); 10987 10988 if (qla2x00_isp_reg_stat(vha->hw)) { 10989 ql_log(ql_log_info, vha, 0x9001, 10990 "PCI/Register disconnect, exiting.\n"); 10991 qla_pci_set_eeh_busy(vha); 10992 return FAILED; 10993 } 10994 10995 vha->hw->flags.port_isolated = 0; 10996 /* Set the flag to 1, so that isp_abort can proceed */ 10997 vha->flags.online = 1; 10998 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 10999 qla2xxx_wake_dpc(vha); 11000 11001 return 0; 11002 } 11003