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Searched refs:pwm_parents (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/clk/spacemit/
H A Dccu-k3.c295 static const struct clk_parent_data pwm_parents[] = { variable
299 CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0);
300 CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0);
301 CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0);
302 CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0);
303 CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0);
304 CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0);
305 CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0);
306 CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0);
307 CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0);
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c85 static const char *const pwm_parents[] __initconst = { variable
185 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
H A Dclk-mt7981-topckgen.c139 static const char * const pwm_parents[] __initconst = { variable
302 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
H A Dclk-mt7988-topckgen.c78 static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4", variable
143 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
H A Dclk-mt6795-topckgen.c273 static const char * const pwm_parents[] = { variable
460 TOP_MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x50, 0, 2, 7, 0),
H A Dclk-mt8173-topckgen.c66 static const char * const pwm_parents[] = { variable
539 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
H A Dclk-mt2712.c153 static const char * const pwm_parents[] = { variable
649 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7),
743 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", pwm_parents, 0x560, 8, 2, 15),
H A Dclk-mt8186-topckgen.c243 static const char * const pwm_parents[] = { variable
581 pwm_parents, 0x00b0, 0x00b4, 0x00b8, 0, 2, 7, 0x0004, 28),
H A Dclk-mt7622.c66 static const char * const pwm_parents[] = { variable
395 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
H A Dclk-mt8167.c469 static const char * const pwm_parents[] = { variable
610 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
H A Dclk-mt8188-topckgen.c648 static const char * const pwm_parents[] = { variable
1086 pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21),
H A Dclk-mt8365.c277 static const char * const pwm_parents[] = { variable
489 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0,
H A Dclk-mt8192.c496 static const char * const pwm_parents[] = { variable
673 pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28),
H A Dclk-mt8195-topckgen.c562 static const char * const pwm_parents[] = { variable
1036 pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
H A Dclk-mt8196-topckgen.c506 static const char * const pwm_parents[] = { variable
834 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_PWM, "pwm", pwm_parents,
H A Dclk-mt2701.c174 static const char * const pwm_parents[] = { variable
495 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
H A Dclk-mt6765.c324 static const char * const pwm_parents[] = { variable
450 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6,
/linux/drivers/clk/sprd/
H A Dsc9860-clk.c563 static const char * const pwm_parents[] = { "ext-32k", "ext-26m", variable
566 static SPRD_MUX_CLK(pwm0_clk, "pwm0", pwm_parents, 0x248,
568 static SPRD_MUX_CLK(pwm1_clk, "pwm1", pwm_parents, 0x24c,
570 static SPRD_MUX_CLK(pwm2_clk, "pwm2", pwm_parents, 0x250,
572 static SPRD_MUX_CLK(pwm3_clk, "pwm3", pwm_parents, 0x254,
H A Dums512-clk.c764 static const struct clk_parent_data pwm_parents[] = { variable
771 static SPRD_MUX_CLK_DATA(pwm0_clk, "pwm0-clk", pwm_parents,
773 static SPRD_MUX_CLK_DATA(pwm1_clk, "pwm1-clk", pwm_parents,
775 static SPRD_MUX_CLK_DATA(pwm2_clk, "pwm2-clk", pwm_parents,
777 static SPRD_MUX_CLK_DATA(pwm3_clk, "pwm3-clk", pwm_parents,
H A Dsc9863a-clk.c365 static const struct clk_parent_data pwm_parents[] = { variable
371 static SPRD_MUX_CLK_DATA(pwm0_clk, "pwm0-clk", pwm_parents, 0x23c,
373 static SPRD_MUX_CLK_DATA(pwm1_clk, "pwm1-clk", pwm_parents, 0x240,
375 static SPRD_MUX_CLK_DATA(pwm2_clk, "pwm2-clk", pwm_parents, 0x244,