| /linux/drivers/clk/spacemit/ |
| H A D | ccu-k3.c | 287 static const struct clk_parent_data pwm_parents[] = { variable
291 CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0);
292 CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0);
293 CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0);
294 CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0);
295 CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0);
296 CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0);
297 CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0);
298 CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0);
299 CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RS
[all...] |
| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt7986-topckgen.c | 86 static const char *const pwm_parents[] __initconst = { variable
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
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| H A D | clk-mt7981-topckgen.c | 140 static const char * const pwm_parents[] __initconst = { variable
303 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| H A D | clk-mt7988-topckgen.c | 78 static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4", variable
143 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
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| H A D | clk-mt6795-topckgen.c | 273 static const char * const pwm_parents[] = { variable
460 TOP_MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x50, 0, 2, 7, 0),
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| H A D | clk-mt8173-topckgen.c | 66 static const char * const pwm_parents[] = { variable
539 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
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| H A D | clk-mt2712.c | 154 static const char * const pwm_parents[] = { variable
650 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7),
744 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", pwm_parents, 0x560, 8, 2, 15),
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| H A D | clk-mt8186-topckgen.c | 243 static const char * const pwm_parents[] = { variable
581 pwm_parents, 0x00b0, 0x00b4, 0x00b8, 0, 2, 7, 0x0004, 28),
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| H A D | clk-mt7622.c | 67 static const char * const pwm_parents[] = { variable
396 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| H A D | clk-mt8167.c | 469 static const char * const pwm_parents[] = { variable
610 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| H A D | clk-mt8365.c | 278 static const char * const pwm_parents[] = { variable
490 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0,
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| H A D | clk-mt8188-topckgen.c | 649 static const char * const pwm_parents[] = { variable
1087 pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21),
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| H A D | clk-mt8192.c | 497 static const char * const pwm_parents[] = { variable
674 pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28),
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| H A D | clk-mt8195-topckgen.c | 563 static const char * const pwm_parents[] = { variable
1037 pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
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| H A D | clk-mt8196-topckgen.c | 506 static const char * const pwm_parents[] = { variable
834 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_PWM, "pwm", pwm_parents,
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| /linux/drivers/clk/sprd/ |
| H A D | sc9860-clk.c | 563 static const char * const pwm_parents[] = { "ext-32k", "ext-26m", variable
566 static SPRD_MUX_CLK(pwm0_clk, "pwm0", pwm_parents, 0x248,
568 static SPRD_MUX_CLK(pwm1_clk, "pwm1", pwm_parents, 0x24c,
570 static SPRD_MUX_CLK(pwm2_clk, "pwm2", pwm_parents, 0x250,
572 static SPRD_MUX_CLK(pwm3_clk, "pwm3", pwm_parents, 0x254,
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| H A D | sc9863a-clk.c | 365 static const struct clk_parent_data pwm_parents[] = { variable
371 static SPRD_MUX_CLK_DATA(pwm0_clk, "pwm0-clk", pwm_parents, 0x23c,
373 static SPRD_MUX_CLK_DATA(pwm1_clk, "pwm1-clk", pwm_parents, 0x240,
375 static SPRD_MUX_CLK_DATA(pwm2_clk, "pwm2-clk", pwm_parents, 0x244,
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