1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/notifier.h>
49 #include <linux/refcount.h>
50 #include <linux/auxiliary_bus.h>
51 #include <linux/mutex.h>
52
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59
60 #define MLX5_ADEV_NAME "mlx5_core"
61
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63
64 enum {
65 MLX5_BOARD_ID_LEN = 64,
66 };
67
68 enum {
69 MLX5_CMD_WQ_MAX_NAME = 32,
70 };
71
72 enum {
73 CMD_OWNER_SW = 0x0,
74 CMD_OWNER_HW = 0x1,
75 CMD_STATUS_SUCCESS = 0,
76 };
77
78 enum mlx5_sqp_t {
79 MLX5_SQP_SMI = 0,
80 MLX5_SQP_GSI = 1,
81 MLX5_SQP_IEEE_1588 = 2,
82 MLX5_SQP_SNIFFER = 3,
83 MLX5_SQP_SYNC_UMR = 4,
84 };
85
86 enum {
87 MLX5_MAX_PORTS = 8,
88 };
89
90 enum {
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
100 };
101
102 enum {
103 MLX5_REG_SBPR = 0xb001,
104 MLX5_REG_SBCM = 0xb002,
105 MLX5_REG_QPTS = 0x4002,
106 MLX5_REG_QETCR = 0x4005,
107 MLX5_REG_QTCT = 0x400a,
108 MLX5_REG_QPDPM = 0x4013,
109 MLX5_REG_QCAM = 0x4019,
110 MLX5_REG_DCBX_PARAM = 0x4020,
111 MLX5_REG_DCBX_APP = 0x4021,
112 MLX5_REG_FPGA_CAP = 0x4022,
113 MLX5_REG_FPGA_CTRL = 0x4023,
114 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 MLX5_REG_CORE_DUMP = 0x402e,
116 MLX5_REG_PCAP = 0x5001,
117 MLX5_REG_PMTU = 0x5003,
118 MLX5_REG_PTYS = 0x5004,
119 MLX5_REG_PAOS = 0x5006,
120 MLX5_REG_PFCC = 0x5007,
121 MLX5_REG_PPCNT = 0x5008,
122 MLX5_REG_PPTB = 0x500b,
123 MLX5_REG_PBMC = 0x500c,
124 MLX5_REG_PMAOS = 0x5012,
125 MLX5_REG_PUDE = 0x5009,
126 MLX5_REG_PMPE = 0x5010,
127 MLX5_REG_PELC = 0x500e,
128 MLX5_REG_PVLC = 0x500f,
129 MLX5_REG_PCMR = 0x5041,
130 MLX5_REG_PDDR = 0x5031,
131 MLX5_REG_PMLP = 0x5002,
132 MLX5_REG_PPLM = 0x5023,
133 MLX5_REG_PCAM = 0x507f,
134 MLX5_REG_NODE_DESC = 0x6001,
135 MLX5_REG_HOST_ENDIANNESS = 0x7004,
136 MLX5_REG_MTCAP = 0x9009,
137 MLX5_REG_MTMP = 0x900A,
138 MLX5_REG_MCIA = 0x9014,
139 MLX5_REG_MFRL = 0x9028,
140 MLX5_REG_MLCR = 0x902b,
141 MLX5_REG_MRTC = 0x902d,
142 MLX5_REG_MTRC_CAP = 0x9040,
143 MLX5_REG_MTRC_CONF = 0x9041,
144 MLX5_REG_MTRC_STDB = 0x9042,
145 MLX5_REG_MTRC_CTRL = 0x9043,
146 MLX5_REG_MPEIN = 0x9050,
147 MLX5_REG_MPCNT = 0x9051,
148 MLX5_REG_MTPPS = 0x9053,
149 MLX5_REG_MTPPSE = 0x9054,
150 MLX5_REG_MTUTC = 0x9055,
151 MLX5_REG_MPEGC = 0x9056,
152 MLX5_REG_MPIR = 0x9059,
153 MLX5_REG_MCQS = 0x9060,
154 MLX5_REG_MCQI = 0x9061,
155 MLX5_REG_MCC = 0x9062,
156 MLX5_REG_MCDA = 0x9063,
157 MLX5_REG_MCAM = 0x907f,
158 MLX5_REG_MSECQ = 0x9155,
159 MLX5_REG_MSEES = 0x9156,
160 MLX5_REG_MIRC = 0x9162,
161 MLX5_REG_MTPTM = 0x9180,
162 MLX5_REG_MTCTR = 0x9181,
163 MLX5_REG_MRTCQ = 0x9182,
164 MLX5_REG_SBCAM = 0xB01F,
165 MLX5_REG_RESOURCE_DUMP = 0xC000,
166 MLX5_REG_NIC_CAP = 0xC00D,
167 MLX5_REG_DTOR = 0xC00E,
168 MLX5_REG_VHCA_ICM_CTRL = 0xC010,
169 };
170
171 enum mlx5_qpts_trust_state {
172 MLX5_QPTS_TRUST_PCP = 1,
173 MLX5_QPTS_TRUST_DSCP = 2,
174 };
175
176 enum mlx5_dcbx_oper_mode {
177 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
178 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
179 };
180
181 enum {
182 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
183 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
184 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
185 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
186 };
187
188 enum mlx5_page_fault_resume_flags {
189 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
190 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
191 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
192 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
193 };
194
195 enum dbg_rsc_type {
196 MLX5_DBG_RSC_QP,
197 MLX5_DBG_RSC_EQ,
198 MLX5_DBG_RSC_CQ,
199 };
200
201 enum port_state_policy {
202 MLX5_POLICY_DOWN = 0,
203 MLX5_POLICY_UP = 1,
204 MLX5_POLICY_FOLLOW = 2,
205 MLX5_POLICY_INVALID = 0xffffffff
206 };
207
208 enum mlx5_coredev_type {
209 MLX5_COREDEV_PF,
210 MLX5_COREDEV_VF,
211 MLX5_COREDEV_SF,
212 };
213
214 struct mlx5_field_desc {
215 int i;
216 };
217
218 struct mlx5_rsc_debug {
219 struct mlx5_core_dev *dev;
220 void *object;
221 enum dbg_rsc_type type;
222 struct dentry *root;
223 struct mlx5_field_desc fields[];
224 };
225
226 enum mlx5_dev_event {
227 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
228 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
229 MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
230 };
231
232 enum mlx5_port_status {
233 MLX5_PORT_UP = 1,
234 MLX5_PORT_DOWN = 2,
235 };
236
237 enum mlx5_cmdif_state {
238 MLX5_CMDIF_STATE_UNINITIALIZED,
239 MLX5_CMDIF_STATE_UP,
240 MLX5_CMDIF_STATE_DOWN,
241 };
242
243 struct mlx5_cmd_first {
244 __be32 data[4];
245 };
246
247 struct mlx5_cmd_msg {
248 struct list_head list;
249 struct cmd_msg_cache *parent;
250 u32 len;
251 struct mlx5_cmd_first first;
252 struct mlx5_cmd_mailbox *next;
253 };
254
255 struct mlx5_cmd_debug {
256 struct dentry *dbg_root;
257 void *in_msg;
258 void *out_msg;
259 u8 status;
260 u16 inlen;
261 u16 outlen;
262 };
263
264 struct cmd_msg_cache {
265 /* protect block chain allocations
266 */
267 spinlock_t lock;
268 struct list_head head;
269 unsigned int max_inbox_size;
270 unsigned int num_ent;
271 };
272
273 enum {
274 MLX5_NUM_COMMAND_CACHES = 5,
275 };
276
277 struct mlx5_cmd_stats {
278 u64 sum;
279 u64 n;
280 /* number of times command failed */
281 u64 failed;
282 /* number of times command failed on bad status returned by FW */
283 u64 failed_mbox_status;
284 /* last command failed returned errno */
285 u32 last_failed_errno;
286 /* last bad status returned by FW */
287 u8 last_failed_mbox_status;
288 /* last command failed syndrome returned by FW */
289 u32 last_failed_syndrome;
290 struct dentry *root;
291 /* protect command average calculations */
292 spinlock_t lock;
293 };
294
295 struct mlx5_cmd {
296 struct mlx5_nb nb;
297
298 /* members which needs to be queried or reinitialized each reload */
299 struct {
300 u16 cmdif_rev;
301 u8 log_sz;
302 u8 log_stride;
303 int max_reg_cmds;
304 unsigned long bitmask;
305 struct semaphore sem;
306 struct semaphore pages_sem;
307 struct semaphore throttle_sem;
308 } vars;
309 enum mlx5_cmdif_state state;
310 void *cmd_alloc_buf;
311 dma_addr_t alloc_dma;
312 int alloc_size;
313 void *cmd_buf;
314 dma_addr_t dma;
315
316 /* protect command queue allocations
317 */
318 spinlock_t alloc_lock;
319
320 /* protect token allocations
321 */
322 spinlock_t token_lock;
323 u8 token;
324 char wq_name[MLX5_CMD_WQ_MAX_NAME];
325 struct workqueue_struct *wq;
326 int mode;
327 u16 allowed_opcode;
328 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
329 struct dma_pool *pool;
330 struct mlx5_cmd_debug dbg;
331 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
332 int checksum_disabled;
333 struct xarray stats;
334 };
335
336 struct mlx5_cmd_mailbox {
337 void *buf;
338 dma_addr_t dma;
339 struct mlx5_cmd_mailbox *next;
340 };
341
342 struct mlx5_buf_list {
343 void *buf;
344 dma_addr_t map;
345 };
346
347 struct mlx5_frag_buf {
348 struct mlx5_buf_list *frags;
349 int npages;
350 int size;
351 u8 page_shift;
352 };
353
354 struct mlx5_frag_buf_ctrl {
355 struct mlx5_buf_list *frags;
356 u32 sz_m1;
357 u16 frag_sz_m1;
358 u16 strides_offset;
359 u8 log_sz;
360 u8 log_stride;
361 u8 log_frag_strides;
362 };
363
364 struct mlx5_core_psv {
365 u32 psv_idx;
366 struct psv_layout {
367 u32 pd;
368 u16 syndrome;
369 u16 reserved;
370 u16 bg;
371 u16 app_tag;
372 u32 ref_tag;
373 } psv;
374 };
375
376 struct mlx5_core_sig_ctx {
377 struct mlx5_core_psv psv_memory;
378 struct mlx5_core_psv psv_wire;
379 struct ib_sig_err err_item;
380 bool sig_status_checked;
381 bool sig_err_exists;
382 u32 sigerr_count;
383 };
384
385 #define MLX5_24BIT_MASK ((1 << 24) - 1)
386
387 enum mlx5_res_type {
388 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
389 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
390 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
391 MLX5_RES_SRQ = 3,
392 MLX5_RES_XSRQ = 4,
393 MLX5_RES_XRQ = 5,
394 };
395
396 struct mlx5_core_rsc_common {
397 enum mlx5_res_type res;
398 refcount_t refcount;
399 struct completion free;
400 };
401
402 struct mlx5_uars_page {
403 void __iomem *map;
404 bool wc;
405 u32 index;
406 struct list_head list;
407 unsigned int bfregs;
408 unsigned long *reg_bitmap; /* for non fast path bf regs */
409 unsigned long *fp_bitmap;
410 unsigned int reg_avail;
411 unsigned int fp_avail;
412 struct kref ref_count;
413 struct mlx5_core_dev *mdev;
414 };
415
416 struct mlx5_bfreg_head {
417 /* protect blue flame registers allocations */
418 struct mutex lock;
419 struct list_head list;
420 };
421
422 struct mlx5_bfreg_data {
423 struct mlx5_bfreg_head reg_head;
424 struct mlx5_bfreg_head wc_head;
425 };
426
427 struct mlx5_sq_bfreg {
428 void __iomem *map;
429 struct mlx5_uars_page *up;
430 bool wc;
431 u32 index;
432 unsigned int offset;
433 };
434
435 struct mlx5_core_health {
436 struct health_buffer __iomem *health;
437 __be32 __iomem *health_counter;
438 struct timer_list timer;
439 u32 prev;
440 int miss_counter;
441 u8 synd;
442 u32 fatal_error;
443 u32 crdump_size;
444 struct workqueue_struct *wq;
445 unsigned long flags;
446 struct work_struct fatal_report_work;
447 struct work_struct report_work;
448 struct devlink_health_reporter *fw_reporter;
449 struct devlink_health_reporter *fw_fatal_reporter;
450 struct devlink_health_reporter *vnic_reporter;
451 struct delayed_work update_fw_log_ts_work;
452 };
453
454 enum {
455 MLX5_PF_NOTIFY_DISABLE_VF,
456 MLX5_PF_NOTIFY_ENABLE_VF,
457 };
458
459 struct mlx5_vf_context {
460 int enabled;
461 u64 port_guid;
462 u64 node_guid;
463 /* Valid bits are used to validate administrative guid only.
464 * Enabled after ndo_set_vf_guid
465 */
466 u8 port_guid_valid:1;
467 u8 node_guid_valid:1;
468 enum port_state_policy policy;
469 struct blocking_notifier_head notifier;
470 };
471
472 struct mlx5_core_sriov {
473 struct mlx5_vf_context *vfs_ctx;
474 int num_vfs;
475 u16 max_vfs;
476 u16 max_ec_vfs;
477 };
478
479 struct mlx5_events;
480 struct mlx5_mpfs;
481 struct mlx5_eswitch;
482 struct mlx5_lag;
483 struct mlx5_devcom_dev;
484 struct mlx5_fw_reset;
485 struct mlx5_eq_table;
486 struct mlx5_irq_table;
487 struct mlx5_vhca_state_notifier;
488 struct mlx5_sf_dev_table;
489 struct mlx5_sf_hw_table;
490 struct mlx5_sf_table;
491 struct mlx5_crypto_dek_priv;
492
493 struct mlx5_rate_limit {
494 u32 rate;
495 u32 max_burst_sz;
496 u16 typical_pkt_sz;
497 };
498
499 struct mlx5_rl_entry {
500 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
501 u64 refcount;
502 u16 index;
503 u16 uid;
504 u8 dedicated : 1;
505 };
506
507 struct mlx5_rl_table {
508 /* protect rate limit table */
509 struct mutex rl_lock;
510 u16 max_size;
511 u32 max_rate;
512 u32 min_rate;
513 struct mlx5_rl_entry *rl_entry;
514 u64 refcount;
515 };
516
517 struct mlx5_core_roce {
518 struct mlx5_flow_table *ft;
519 struct mlx5_flow_group *fg;
520 struct mlx5_flow_handle *allow_rule;
521 };
522
523 enum {
524 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
525 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
526 /* Set during device detach to block any further devices
527 * creation/deletion on drivers rescan. Unset during device attach.
528 */
529 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
530 MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3,
531 };
532
533 struct mlx5_adev {
534 struct auxiliary_device adev;
535 struct mlx5_core_dev *mdev;
536 int idx;
537 };
538
539 struct mlx5_debugfs_entries {
540 struct dentry *dbg_root;
541 struct dentry *qp_debugfs;
542 struct dentry *eq_debugfs;
543 struct dentry *cq_debugfs;
544 struct dentry *cmdif_debugfs;
545 struct dentry *pages_debugfs;
546 struct dentry *lag_debugfs;
547 };
548
549 enum mlx5_func_type {
550 MLX5_PF,
551 MLX5_VF,
552 MLX5_SF,
553 MLX5_HOST_PF,
554 MLX5_EC_VF,
555 MLX5_FUNC_TYPE_NUM,
556 };
557
558 struct mlx5_ft_pool;
559 struct mlx5_priv {
560 /* IRQ table valid only for real pci devices PF or VF */
561 struct mlx5_irq_table *irq_table;
562 struct mlx5_eq_table *eq_table;
563
564 /* pages stuff */
565 struct mlx5_nb pg_nb;
566 struct workqueue_struct *pg_wq;
567 struct xarray page_root_xa;
568 atomic_t reg_pages;
569 struct list_head free_list;
570 u32 fw_pages;
571 u32 page_counters[MLX5_FUNC_TYPE_NUM];
572 u32 fw_pages_alloc_failed;
573 u32 give_pages_dropped;
574 u32 reclaim_pages_discard;
575
576 struct mlx5_core_health health;
577 struct list_head traps;
578
579 struct mlx5_debugfs_entries dbg;
580
581 /* start: alloc staff */
582 /* protect buffer allocation according to numa node */
583 struct mutex alloc_mutex;
584 int numa_node;
585
586 struct mutex pgdir_mutex;
587 struct list_head pgdir_list;
588 /* end: alloc staff */
589
590 struct mlx5_adev **adev;
591 int adev_idx;
592 int sw_vhca_id;
593 struct mlx5_events *events;
594 struct mlx5_vhca_events *vhca_events;
595
596 struct mlx5_flow_steering *steering;
597 struct mlx5_mpfs *mpfs;
598 struct mlx5_eswitch *eswitch;
599 struct mlx5_core_sriov sriov;
600 struct mlx5_lag *lag;
601 u32 flags;
602 struct mlx5_devcom_dev *devc;
603 struct mlx5_devcom_comp_dev *hca_devcom_comp;
604 struct mlx5_fw_reset *fw_reset;
605 struct mlx5_core_roce roce;
606 struct mlx5_fc_stats *fc_stats;
607 struct mlx5_rl_table rl_table;
608 struct mlx5_ft_pool *ft_pool;
609
610 struct mlx5_bfreg_data bfregs;
611 struct mlx5_uars_page *uar;
612 #ifdef CONFIG_MLX5_SF
613 struct mlx5_vhca_state_notifier *vhca_state_notifier;
614 struct mlx5_sf_dev_table *sf_dev_table;
615 struct mlx5_core_dev *parent_mdev;
616 #endif
617 #ifdef CONFIG_MLX5_SF_MANAGER
618 struct mlx5_sf_hw_table *sf_hw_table;
619 struct mlx5_sf_table *sf_table;
620 #endif
621 struct blocking_notifier_head lag_nh;
622 };
623
624 enum mlx5_device_state {
625 MLX5_DEVICE_STATE_UP = 1,
626 MLX5_DEVICE_STATE_INTERNAL_ERROR,
627 };
628
629 enum mlx5_interface_state {
630 MLX5_INTERFACE_STATE_UP = BIT(0),
631 MLX5_BREAK_FW_WAIT = BIT(1),
632 };
633
634 enum mlx5_pci_status {
635 MLX5_PCI_STATUS_DISABLED,
636 MLX5_PCI_STATUS_ENABLED,
637 };
638
639 enum mlx5_pagefault_type_flags {
640 MLX5_PFAULT_REQUESTOR = 1 << 0,
641 MLX5_PFAULT_WRITE = 1 << 1,
642 MLX5_PFAULT_RDMA = 1 << 2,
643 };
644
645 struct mlx5_td {
646 /* protects tirs list changes while tirs refresh */
647 struct mutex list_lock;
648 struct list_head tirs_list;
649 u32 tdn;
650 };
651
652 struct mlx5e_resources {
653 struct mlx5e_hw_objs {
654 u32 pdn;
655 struct mlx5_td td;
656 u32 mkey;
657 struct mlx5_sq_bfreg bfreg;
658 #define MLX5_MAX_NUM_TC 8
659 u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
660 bool tisn_valid;
661 } hw_objs;
662 struct net_device *uplink_netdev;
663 struct mutex uplink_netdev_lock;
664 struct mlx5_crypto_dek_priv *dek_priv;
665 };
666
667 enum mlx5_sw_icm_type {
668 MLX5_SW_ICM_TYPE_STEERING,
669 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
670 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
671 MLX5_SW_ICM_TYPE_SW_ENCAP,
672 };
673
674 #define MLX5_MAX_RESERVED_GIDS 8
675
676 struct mlx5_rsvd_gids {
677 unsigned int start;
678 unsigned int count;
679 struct ida ida;
680 };
681
682 #define MAX_PIN_NUM 8
683 struct mlx5_pps {
684 u8 pin_caps[MAX_PIN_NUM];
685 struct work_struct out_work;
686 u64 start[MAX_PIN_NUM];
687 u8 enabled;
688 u64 min_npps_period;
689 u64 min_out_pulse_duration_ns;
690 };
691
692 struct mlx5_timer {
693 struct cyclecounter cycles;
694 struct timecounter tc;
695 u32 nominal_c_mult;
696 unsigned long overflow_period;
697 };
698
699 struct mlx5_clock {
700 struct mlx5_nb pps_nb;
701 seqlock_t lock;
702 struct hwtstamp_config hwtstamp_config;
703 struct ptp_clock *ptp;
704 struct ptp_clock_info ptp_info;
705 struct mlx5_pps pps_info;
706 struct mlx5_timer timer;
707 };
708
709 struct mlx5_dm;
710 struct mlx5_fw_tracer;
711 struct mlx5_vxlan;
712 struct mlx5_geneve;
713 struct mlx5_hv_vhca;
714
715 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
716 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
717
718 enum {
719 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
720 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
721 };
722
723 enum {
724 MKEY_CACHE_LAST_STD_ENTRY = 20,
725 MLX5_IMR_KSM_CACHE_ENTRY,
726 MAX_MKEY_CACHE_ENTRIES
727 };
728
729 struct mlx5_profile {
730 u64 mask;
731 u8 log_max_qp;
732 u8 num_cmd_caches;
733 struct {
734 int size;
735 int limit;
736 } mr_cache[MAX_MKEY_CACHE_ENTRIES];
737 };
738
739 struct mlx5_hca_cap {
740 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
741 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
742 };
743
744 enum mlx5_wc_state {
745 MLX5_WC_STATE_UNINITIALIZED,
746 MLX5_WC_STATE_UNSUPPORTED,
747 MLX5_WC_STATE_SUPPORTED,
748 };
749
750 struct mlx5_core_dev {
751 struct device *device;
752 enum mlx5_coredev_type coredev_type;
753 struct pci_dev *pdev;
754 /* sync pci state */
755 struct mutex pci_status_mutex;
756 enum mlx5_pci_status pci_status;
757 u8 rev_id;
758 char board_id[MLX5_BOARD_ID_LEN];
759 struct mlx5_cmd cmd;
760 struct {
761 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
762 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
763 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
764 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
765 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
766 u8 embedded_cpu;
767 } caps;
768 struct mlx5_timeouts *timeouts;
769 u64 sys_image_guid;
770 phys_addr_t iseg_base;
771 struct mlx5_init_seg __iomem *iseg;
772 phys_addr_t bar_addr;
773 enum mlx5_device_state state;
774 /* sync interface state */
775 struct mutex intf_state_mutex;
776 struct lock_class_key lock_key;
777 unsigned long intf_state;
778 struct mlx5_priv priv;
779 struct mlx5_profile profile;
780 u32 issi;
781 struct mlx5e_resources mlx5e_res;
782 struct mlx5_dm *dm;
783 struct mlx5_vxlan *vxlan;
784 struct mlx5_geneve *geneve;
785 struct {
786 struct mlx5_rsvd_gids reserved_gids;
787 u32 roce_en;
788 } roce;
789 #ifdef CONFIG_MLX5_FPGA
790 struct mlx5_fpga_device *fpga;
791 #endif
792 struct mlx5_clock clock;
793 struct mlx5_ib_clock_info *clock_info;
794 struct mlx5_fw_tracer *tracer;
795 struct mlx5_rsc_dump *rsc_dump;
796 u32 vsc_addr;
797 struct mlx5_hv_vhca *hv_vhca;
798 struct mlx5_hwmon *hwmon;
799 u64 num_block_tc;
800 u64 num_block_ipsec;
801 #ifdef CONFIG_MLX5_MACSEC
802 struct mlx5_macsec_fs *macsec_fs;
803 /* MACsec notifier chain to sync MACsec core and IB database */
804 struct blocking_notifier_head macsec_nh;
805 #endif
806 u64 num_ipsec_offloads;
807 struct mlx5_sd *sd;
808 enum mlx5_wc_state wc_state;
809 /* sync write combining state */
810 struct mutex wc_state_lock;
811 };
812
813 struct mlx5_db {
814 __be32 *db;
815 union {
816 struct mlx5_db_pgdir *pgdir;
817 struct mlx5_ib_user_db_page *user_page;
818 } u;
819 dma_addr_t dma;
820 int index;
821 };
822
823 enum {
824 MLX5_COMP_EQ_SIZE = 1024,
825 };
826
827 enum {
828 MLX5_PTYS_IB = 1 << 0,
829 MLX5_PTYS_EN = 1 << 2,
830 };
831
832 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
833
834 enum {
835 MLX5_CMD_ENT_STATE_PENDING_COMP,
836 };
837
838 struct mlx5_cmd_work_ent {
839 unsigned long state;
840 struct mlx5_cmd_msg *in;
841 struct mlx5_cmd_msg *out;
842 void *uout;
843 int uout_size;
844 mlx5_cmd_cbk_t callback;
845 struct delayed_work cb_timeout_work;
846 void *context;
847 int idx;
848 struct completion handling;
849 struct completion slotted;
850 struct completion done;
851 struct mlx5_cmd *cmd;
852 struct work_struct work;
853 struct mlx5_cmd_layout *lay;
854 int ret;
855 int page_queue;
856 u8 status;
857 u8 token;
858 u64 ts1;
859 u64 ts2;
860 u16 op;
861 bool polling;
862 /* Track the max comp handlers */
863 refcount_t refcnt;
864 };
865
866 enum phy_port_state {
867 MLX5_AAA_111
868 };
869
870 struct mlx5_hca_vport_context {
871 u32 field_select;
872 bool sm_virt_aware;
873 bool has_smi;
874 bool has_raw;
875 enum port_state_policy policy;
876 enum phy_port_state phys_state;
877 enum ib_port_state vport_state;
878 u8 port_physical_state;
879 u64 sys_image_guid;
880 u64 port_guid;
881 u64 node_guid;
882 u32 cap_mask1;
883 u32 cap_mask1_perm;
884 u16 cap_mask2;
885 u16 cap_mask2_perm;
886 u16 lid;
887 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
888 u8 lmc;
889 u8 subnet_timeout;
890 u16 sm_lid;
891 u8 sm_sl;
892 u16 qkey_violation_counter;
893 u16 pkey_violation_counter;
894 bool grh_required;
895 u8 num_plane;
896 };
897
898 #define STRUCT_FIELD(header, field) \
899 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
900 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
901
902 extern struct dentry *mlx5_debugfs_root;
903
fw_rev_maj(struct mlx5_core_dev * dev)904 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
905 {
906 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
907 }
908
fw_rev_min(struct mlx5_core_dev * dev)909 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
910 {
911 return ioread32be(&dev->iseg->fw_rev) >> 16;
912 }
913
fw_rev_sub(struct mlx5_core_dev * dev)914 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
915 {
916 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
917 }
918
mlx5_base_mkey(const u32 key)919 static inline u32 mlx5_base_mkey(const u32 key)
920 {
921 return key & 0xffffff00u;
922 }
923
wq_get_byte_sz(u8 log_sz,u8 log_stride)924 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
925 {
926 return ((u32)1 << log_sz) << log_stride;
927 }
928
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)929 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
930 u8 log_stride, u8 log_sz,
931 u16 strides_offset,
932 struct mlx5_frag_buf_ctrl *fbc)
933 {
934 fbc->frags = frags;
935 fbc->log_stride = log_stride;
936 fbc->log_sz = log_sz;
937 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
938 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
939 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
940 fbc->strides_offset = strides_offset;
941 }
942
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)943 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
944 u8 log_stride, u8 log_sz,
945 struct mlx5_frag_buf_ctrl *fbc)
946 {
947 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
948 }
949
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)950 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
951 u32 ix)
952 {
953 unsigned int frag;
954
955 ix += fbc->strides_offset;
956 frag = ix >> fbc->log_frag_strides;
957
958 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
959 }
960
961 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)962 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
963 {
964 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
965
966 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
967 }
968
969 enum {
970 CMD_ALLOWED_OPCODE_ALL,
971 };
972
973 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
974 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
975 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
976
977 struct mlx5_async_ctx {
978 struct mlx5_core_dev *dev;
979 atomic_t num_inflight;
980 struct completion inflight_done;
981 };
982
983 struct mlx5_async_work;
984
985 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
986
987 struct mlx5_async_work {
988 struct mlx5_async_ctx *ctx;
989 mlx5_async_cbk_t user_callback;
990 u16 opcode; /* cmd opcode */
991 u16 op_mod; /* cmd op_mod */
992 void *out; /* pointer to the cmd output buffer */
993 };
994
995 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
996 struct mlx5_async_ctx *ctx);
997 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
998 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
999 void *out, int out_size, mlx5_async_cbk_t callback,
1000 struct mlx5_async_work *work);
1001 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
1002 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
1003 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
1004 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1005 int out_size);
1006
1007 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
1008 ({ \
1009 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
1010 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
1011 })
1012
1013 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
1014 ({ \
1015 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
1016 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
1017 })
1018
1019 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1020 void *out, int out_size);
1021 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1022
1023 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1024 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1025
1026 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1027
1028 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1029 int mlx5_health_init(struct mlx5_core_dev *dev);
1030 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1031 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1032 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1033 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1034 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1035 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1036 struct mlx5_frag_buf *buf, int node);
1037 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1038 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1039 int inlen);
1040 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1041 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1042 int outlen);
1043 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1044 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1045 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1046 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1047 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1048 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1049 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1050 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1051 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1052 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1053 void mlx5_register_debugfs(void);
1054 void mlx5_unregister_debugfs(void);
1055
1056 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1057 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1058 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1059 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1060 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1061
1062 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1063 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1064 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1065 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1066 void *data_out, int size_out, u16 reg_id, int arg,
1067 int write, bool verbose);
1068 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1069 int size_in, void *data_out, int size_out,
1070 u16 reg_num, int arg, int write);
1071
1072 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1073 int node);
1074
mlx5_db_alloc(struct mlx5_core_dev * dev,struct mlx5_db * db)1075 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1076 {
1077 return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1078 }
1079
1080 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1081
1082 const char *mlx5_command_str(int command);
1083 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1084 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1085 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1086 int npsvs, u32 *sig_index);
1087 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1088 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1089 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1090
1091 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1092 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1093 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1094 struct mlx5_rate_limit *rl);
1095 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1096 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1097 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1098 bool dedicated_entry, u16 *index);
1099 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1100 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1101 struct mlx5_rate_limit *rl_1);
1102 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1103 bool map_wc, bool fast_path);
1104 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1105
1106 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1107 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1108 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1109 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1110 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1111 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1112
mlx5_mkey_to_idx(u32 mkey)1113 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1114 {
1115 return mkey >> 8;
1116 }
1117
mlx5_idx_to_mkey(u32 mkey_idx)1118 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1119 {
1120 return mkey_idx << 8;
1121 }
1122
mlx5_mkey_variant(u32 mkey)1123 static inline u8 mlx5_mkey_variant(u32 mkey)
1124 {
1125 return mkey & 0xff;
1126 }
1127
1128 /* Async-atomic event notifier used by mlx5 core to forward FW
1129 * evetns received from event queue to mlx5 consumers.
1130 * Optimise event queue dipatching.
1131 */
1132 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1133 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1134
1135 /* Async-atomic event notifier used for forwarding
1136 * evetns from the event queue into the to mlx5 events dispatcher,
1137 * eswitch, clock and others.
1138 */
1139 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1140 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1141
1142 /* Blocking event notifier used to forward SW events, used for slow path */
1143 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1144 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1145 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1146 void *data);
1147
1148 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1149
1150 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1151 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1152 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1153 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1154 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1155 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1156 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1157 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1158 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1159 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1160 struct net_device *slave);
1161 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1162 u64 *values,
1163 int num_counters,
1164 size_t *offsets);
1165 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1166
1167 #define mlx5_lag_for_each_peer_mdev(dev, peer, i) \
1168 for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \
1169 peer; \
1170 peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1171
1172 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1173 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1174 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1175 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1176 u64 length, u32 log_alignment, u16 uid,
1177 phys_addr_t *addr, u32 *obj_id);
1178 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1179 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1180
1181 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1182 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1183
1184 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1185 int vf_id,
1186 struct notifier_block *nb);
1187 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1188 int vf_id,
1189 struct notifier_block *nb);
1190 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1191 struct ib_device *device,
1192 struct rdma_netdev_alloc_params *params);
1193
1194 enum {
1195 MLX5_PCI_DEV_IS_VF = 1 << 0,
1196 };
1197
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1198 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1199 {
1200 return dev->coredev_type == MLX5_COREDEV_PF;
1201 }
1202
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1203 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1204 {
1205 return dev->coredev_type == MLX5_COREDEV_VF;
1206 }
1207
mlx5_core_same_coredev_type(const struct mlx5_core_dev * dev1,const struct mlx5_core_dev * dev2)1208 static inline bool mlx5_core_same_coredev_type(const struct mlx5_core_dev *dev1,
1209 const struct mlx5_core_dev *dev2)
1210 {
1211 return dev1->coredev_type == dev2->coredev_type;
1212 }
1213
mlx5_core_is_ecpf(const struct mlx5_core_dev * dev)1214 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1215 {
1216 return dev->caps.embedded_cpu;
1217 }
1218
1219 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1220 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1221 {
1222 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1223 }
1224
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1225 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1226 {
1227 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1228 }
1229
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1230 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1231 {
1232 return dev->priv.sriov.max_vfs;
1233 }
1234
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)1235 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1236 {
1237 /* LACP owner conditions:
1238 * 1) Function is physical.
1239 * 2) LAG is supported by FW.
1240 * 3) LAG is managed by driver (currently the only option).
1241 */
1242 return MLX5_CAP_GEN(dev, vport_group_manager) &&
1243 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1244 MLX5_CAP_GEN(dev, lag_master);
1245 }
1246
mlx5_core_max_ec_vfs(const struct mlx5_core_dev * dev)1247 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1248 {
1249 return dev->priv.sriov.max_ec_vfs;
1250 }
1251
mlx5_get_gid_table_len(u16 param)1252 static inline int mlx5_get_gid_table_len(u16 param)
1253 {
1254 if (param > 4) {
1255 pr_warn("gid table length is zero\n");
1256 return 0;
1257 }
1258
1259 return 8 * (1 << param);
1260 }
1261
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1262 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1263 {
1264 return !!(dev->priv.rl_table.max_size);
1265 }
1266
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1267 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1268 {
1269 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1270 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1271 }
1272
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1273 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1274 {
1275 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1276 }
1277
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1278 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1279 {
1280 return mlx5_core_is_mp_slave(dev) ||
1281 mlx5_core_is_mp_master(dev);
1282 }
1283
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1284 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1285 {
1286 if (!mlx5_core_mp_enabled(dev))
1287 return 1;
1288
1289 return MLX5_CAP_GEN(dev, native_port_num);
1290 }
1291
mlx5_get_dev_index(struct mlx5_core_dev * dev)1292 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1293 {
1294 int idx = MLX5_CAP_GEN(dev, native_port_num);
1295
1296 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1297 return idx - 1;
1298 else
1299 return PCI_FUNC(dev->pdev->devfn);
1300 }
1301
1302 enum {
1303 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1304 };
1305
1306 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1307
mlx5_get_roce_state(struct mlx5_core_dev * dev)1308 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1309 {
1310 if (MLX5_CAP_GEN(dev, roce_rw_supported))
1311 return MLX5_CAP_GEN(dev, roce);
1312
1313 /* If RoCE cap is read-only in FW, get RoCE state from devlink
1314 * in order to support RoCE enable/disable feature
1315 */
1316 return mlx5_is_roce_on(dev);
1317 }
1318
1319 #ifdef CONFIG_MLX5_MACSEC
mlx5e_is_macsec_device(const struct mlx5_core_dev * mdev)1320 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1321 {
1322 if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1323 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1324 return false;
1325
1326 if (!MLX5_CAP_GEN(mdev, log_max_dek))
1327 return false;
1328
1329 if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1330 return false;
1331
1332 if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1333 !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1334 return false;
1335
1336 if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1337 !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1338 return false;
1339
1340 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1341 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1342 return false;
1343
1344 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1345 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1346 return false;
1347
1348 return true;
1349 }
1350
1351 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1352
mlx5_is_macsec_roce_supported(struct mlx5_core_dev * mdev)1353 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1354 {
1355 if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1356 NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1357 !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1358 !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1359 return false;
1360
1361 return true;
1362 }
1363 #endif
1364
1365 enum {
1366 MLX5_OCTWORD = 16,
1367 };
1368
1369 bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1370 #endif /* MLX5_DRIVER_H */
1371