Searched refs:post_divider (Results 1 – 13 of 13) sorted by relevance
50 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()65 post_divider = 1; in rv730_populate_sclk_value()67 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()90 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()129 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local140 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()143 post_divider = 1; in rv730_populate_mclk_value()165 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()152 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()154 step->vco_frequency = clock * step->post_divider; in rv6xx_convert_clock_to_stepping()173 if (step->post_divider == 1) in rv6xx_output_stepping()176 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()177 u32 hi_len = step->post_divider - 2 - lo_len; in rv6xx_output_stepping()199 next.post_divider = cur->post_divider; in rv6xx_next_vco_step()213 return (cur->post_divider > target->post_divider) && in rv6xx_can_step_post_div()214 ((cur->vco_frequency * target->post_divider) <= in rv6xx_can_step_post_div()215 (target->vco_frequency * (cur->post_divider - 1))); in rv6xx_can_step_post_div()[all …]
33 u32 post_divider; member
742 uint32_t post_divider = 0; in radeon_set_pll() local820 &reference_div, &post_divider); in radeon_set_pll()823 if (post_div->divider == post_divider) in radeon_set_pll()834 post_divider); in radeon_set_pll()
326 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()338 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()503 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local515 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()517 post_divider = 1; in rv770_populate_sclk_value()519 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()541 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
567 u32 post_divider; member
2927 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in radeon_atom_get_clock_dividers()2944 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in radeon_atom_get_clock_dividers()
346 u32 post_divider; in aty_var_to_pll_18818() local352 post_divider = 1; in aty_var_to_pll_18818()361 post_divider *= 2; in aty_var_to_pll_18818()372 switch (post_divider) { in aty_var_to_pll_18818()392 pll->ics2595.post_divider = post_divider; in aty_var_to_pll_18818()558 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703()676 pll->ics2595.post_divider = 0; in aty_var_to_pll_8398()794 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_408()
200 rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48); in radeon_get_panel_info_BIOS()207 pr_debug("post_divider = %x\n", rinfo->panel_info.post_divider); in radeon_get_panel_info_BIOS()669 rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7; in radeon_fixup_panel_info()675 (rinfo->panel_info.post_divider << 16), in radeon_fixup_panel_info()
81 u32 post_divider; member
265 int post_divider; member
1700 (rinfo->panel_info.post_divider << 16); in radeonfb_set_par()
363 u8 *post_divider) in anx7625_calculate_m_n() argument381 for (*post_divider = 1; in anx7625_calculate_m_n()382 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) in anx7625_calculate_m_n()383 *post_divider += 1; in anx7625_calculate_m_n()385 if (*post_divider > POST_DIVIDER_MAX) { in anx7625_calculate_m_n()386 for (*post_divider = 1; in anx7625_calculate_m_n()388 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) in anx7625_calculate_m_n()389 *post_divider += 1; in anx7625_calculate_m_n()391 if (*post_divider > POST_DIVIDER_MAX) { in anx7625_calculate_m_n()393 *post_divider); in anx7625_calculate_m_n()[all …]