1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver core for Samsung SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 */
8
9 /* Note on 2410 error handling
10 *
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
16 *
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
20 *
21 * BJD, 04-Nov-2004
22 */
23
24 #include <linux/console.h>
25 #include <linux/clk.h>
26 #include <linux/cpufreq.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmaengine.h>
30 #include <linux/init.h>
31 #include <linux/io.h>
32 #include <linux/ioport.h>
33 #include <linux/math.h>
34 #include <linux/module.h>
35 #include <linux/of.h>
36 #include <linux/platform_device.h>
37 #include <linux/serial.h>
38 #include <linux/serial_core.h>
39 #include <linux/serial_s3c.h>
40 #include <linux/slab.h>
41 #include <linux/sysrq.h>
42 #include <linux/tty.h>
43 #include <linux/tty_flip.h>
44 #include <linux/types.h>
45
46 #include <asm/irq.h>
47
48 /* UART name and device definitions */
49
50 #define S3C24XX_SERIAL_NAME "ttySAC"
51 #define S3C24XX_SERIAL_MAJOR 204
52 #define S3C24XX_SERIAL_MINOR 64
53
54 #ifdef CONFIG_ARM64
55 #define UART_NR 18
56 #else
57 #define UART_NR CONFIG_SERIAL_SAMSUNG_UARTS
58 #endif
59
60 #define S3C24XX_TX_PIO 1
61 #define S3C24XX_TX_DMA 2
62 #define S3C24XX_RX_PIO 1
63 #define S3C24XX_RX_DMA 2
64
65 /* flag to ignore all characters coming in */
66 #define RXSTAT_DUMMY_READ (0x10000000)
67
68 enum s3c24xx_port_type {
69 TYPE_S3C6400,
70 TYPE_APPLE_S5L,
71 };
72
73 struct s3c24xx_uart_info {
74 const char *name;
75 enum s3c24xx_port_type type;
76 unsigned int port_type;
77 unsigned int fifosize;
78 u32 rx_fifomask;
79 u32 rx_fifoshift;
80 u32 rx_fifofull;
81 u32 tx_fifomask;
82 u32 tx_fifoshift;
83 u32 tx_fifofull;
84 u32 clksel_mask;
85 u32 clksel_shift;
86 u32 ucon_mask;
87 u8 def_clk_sel;
88 u8 num_clks;
89 u8 iotype;
90
91 /* uart port features */
92 bool has_divslot;
93 };
94
95 struct s3c24xx_serial_drv_data {
96 const struct s3c24xx_uart_info info;
97 const struct s3c2410_uartcfg def_cfg;
98 const unsigned int fifosize[UART_NR];
99 };
100
101 struct s3c24xx_uart_dma {
102 unsigned int rx_chan_id;
103 unsigned int tx_chan_id;
104
105 struct dma_slave_config rx_conf;
106 struct dma_slave_config tx_conf;
107
108 struct dma_chan *rx_chan;
109 struct dma_chan *tx_chan;
110
111 dma_addr_t rx_addr;
112 dma_addr_t tx_addr;
113
114 dma_cookie_t rx_cookie;
115 dma_cookie_t tx_cookie;
116
117 char *rx_buf;
118
119 dma_addr_t tx_transfer_addr;
120
121 size_t rx_size;
122 size_t tx_size;
123
124 struct dma_async_tx_descriptor *tx_desc;
125 struct dma_async_tx_descriptor *rx_desc;
126
127 int tx_bytes_requested;
128 int rx_bytes_requested;
129 };
130
131 struct s3c24xx_uart_port {
132 unsigned char rx_enabled;
133 unsigned char tx_enabled;
134 unsigned int pm_level;
135 unsigned long baudclk_rate;
136 unsigned int min_dma_size;
137
138 unsigned int rx_irq;
139 unsigned int tx_irq;
140
141 unsigned int tx_in_progress;
142 unsigned int tx_mode;
143 unsigned int rx_mode;
144
145 const struct s3c24xx_uart_info *info;
146 struct clk *clk;
147 struct clk *baudclk;
148 struct uart_port port;
149 const struct s3c24xx_serial_drv_data *drv_data;
150
151 /* reference to platform data */
152 const struct s3c2410_uartcfg *cfg;
153
154 struct s3c24xx_uart_dma *dma;
155 };
156
157 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
158
159 /* conversion functions */
160
161 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
162
163 /* register access controls */
164
165 #define portaddr(port, reg) ((port)->membase + (reg))
166 #define portaddrl(port, reg) \
167 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
168
rd_reg(const struct uart_port * port,u32 reg)169 static u32 rd_reg(const struct uart_port *port, u32 reg)
170 {
171 switch (port->iotype) {
172 case UPIO_MEM:
173 return readb_relaxed(portaddr(port, reg));
174 case UPIO_MEM32:
175 return readl_relaxed(portaddr(port, reg));
176 default:
177 return 0;
178 }
179 return 0;
180 }
181
182 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
183
wr_reg(const struct uart_port * port,u32 reg,u32 val)184 static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
185 {
186 switch (port->iotype) {
187 case UPIO_MEM:
188 writeb_relaxed(val, portaddr(port, reg));
189 break;
190 case UPIO_MEM32:
191 writel_relaxed(val, portaddr(port, reg));
192 break;
193 default:
194 break;
195 }
196 }
197
198 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
199
200 /* Byte-order aware bit setting/clearing functions. */
201
s3c24xx_set_bit(const struct uart_port * port,int idx,u32 reg)202 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
203 u32 reg)
204 {
205 unsigned long flags;
206 u32 val;
207
208 local_irq_save(flags);
209 val = rd_regl(port, reg);
210 val |= (1 << idx);
211 wr_regl(port, reg, val);
212 local_irq_restore(flags);
213 }
214
s3c24xx_clear_bit(const struct uart_port * port,int idx,u32 reg)215 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
216 u32 reg)
217 {
218 unsigned long flags;
219 u32 val;
220
221 local_irq_save(flags);
222 val = rd_regl(port, reg);
223 val &= ~(1 << idx);
224 wr_regl(port, reg, val);
225 local_irq_restore(flags);
226 }
227
to_ourport(struct uart_port * port)228 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
229 {
230 return container_of(port, struct s3c24xx_uart_port, port);
231 }
232
233 /* translate a port to the device name */
234
s3c24xx_serial_portname(const struct uart_port * port)235 static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
236 {
237 return to_platform_device(port->dev)->name;
238 }
239
s3c24xx_serial_txempty_nofifo(const struct uart_port * port)240 static bool s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
241 {
242 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
243 }
244
s3c24xx_serial_rx_enable(struct uart_port * port)245 static void s3c24xx_serial_rx_enable(struct uart_port *port)
246 {
247 struct s3c24xx_uart_port *ourport = to_ourport(port);
248 int count = 10000;
249 u32 ucon, ufcon;
250
251 while (--count && !s3c24xx_serial_txempty_nofifo(port))
252 udelay(100);
253
254 ufcon = rd_regl(port, S3C2410_UFCON);
255 ufcon |= S3C2410_UFCON_RESETRX;
256 wr_regl(port, S3C2410_UFCON, ufcon);
257
258 ucon = rd_regl(port, S3C2410_UCON);
259 ucon |= S3C2410_UCON_RXIRQMODE;
260 wr_regl(port, S3C2410_UCON, ucon);
261
262 ourport->rx_enabled = 1;
263 }
264
s3c24xx_serial_rx_disable(struct uart_port * port)265 static void s3c24xx_serial_rx_disable(struct uart_port *port)
266 {
267 struct s3c24xx_uart_port *ourport = to_ourport(port);
268 u32 ucon;
269
270 ucon = rd_regl(port, S3C2410_UCON);
271 ucon &= ~S3C2410_UCON_RXIRQMODE;
272 wr_regl(port, S3C2410_UCON, ucon);
273
274 ourport->rx_enabled = 0;
275 }
276
s3c24xx_serial_stop_tx(struct uart_port * port)277 static void s3c24xx_serial_stop_tx(struct uart_port *port)
278 {
279 struct s3c24xx_uart_port *ourport = to_ourport(port);
280 struct s3c24xx_uart_dma *dma = ourport->dma;
281 struct dma_tx_state state;
282 int count;
283
284 if (!ourport->tx_enabled)
285 return;
286
287 switch (ourport->info->type) {
288 case TYPE_S3C6400:
289 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
290 break;
291 case TYPE_APPLE_S5L:
292 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
293 break;
294 default:
295 disable_irq_nosync(ourport->tx_irq);
296 break;
297 }
298
299 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
300 dmaengine_pause(dma->tx_chan);
301 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
302 dmaengine_terminate_all(dma->tx_chan);
303 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
304 dma->tx_transfer_addr, dma->tx_size,
305 DMA_TO_DEVICE);
306 async_tx_ack(dma->tx_desc);
307 count = dma->tx_bytes_requested - state.residue;
308 uart_xmit_advance(port, count);
309 }
310
311 ourport->tx_enabled = 0;
312 ourport->tx_in_progress = 0;
313
314 if (port->flags & UPF_CONS_FLOW)
315 s3c24xx_serial_rx_enable(port);
316
317 ourport->tx_mode = 0;
318 }
319
320 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
321
s3c24xx_serial_tx_dma_complete(void * args)322 static void s3c24xx_serial_tx_dma_complete(void *args)
323 {
324 struct s3c24xx_uart_port *ourport = args;
325 struct uart_port *port = &ourport->port;
326 struct tty_port *tport = &port->state->port;
327 struct s3c24xx_uart_dma *dma = ourport->dma;
328 struct dma_tx_state state;
329 unsigned long flags;
330 int count;
331
332 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
333 count = dma->tx_bytes_requested - state.residue;
334 async_tx_ack(dma->tx_desc);
335
336 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
337 dma->tx_transfer_addr, dma->tx_size,
338 DMA_TO_DEVICE);
339
340 uart_port_lock_irqsave(port, &flags);
341
342 uart_xmit_advance(port, count);
343 ourport->tx_in_progress = 0;
344
345 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
346 uart_write_wakeup(port);
347
348 s3c24xx_serial_start_next_tx(ourport);
349 uart_port_unlock_irqrestore(port, flags);
350 }
351
enable_tx_dma(struct s3c24xx_uart_port * ourport)352 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
353 {
354 const struct uart_port *port = &ourport->port;
355 u32 ucon;
356
357 /* Mask Tx interrupt */
358 switch (ourport->info->type) {
359 case TYPE_S3C6400:
360 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
361 break;
362 case TYPE_APPLE_S5L:
363 WARN_ON(1); // No DMA
364 break;
365 default:
366 disable_irq_nosync(ourport->tx_irq);
367 break;
368 }
369
370 /* Enable tx dma mode */
371 ucon = rd_regl(port, S3C2410_UCON);
372 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
373 ucon |= S3C64XX_UCON_TXBURST_1;
374 ucon |= S3C64XX_UCON_TXMODE_DMA;
375 wr_regl(port, S3C2410_UCON, ucon);
376
377 ourport->tx_mode = S3C24XX_TX_DMA;
378 }
379
enable_tx_pio(struct s3c24xx_uart_port * ourport)380 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
381 {
382 const struct uart_port *port = &ourport->port;
383 u32 ucon, ufcon;
384
385 /* Set ufcon txtrig */
386 ourport->tx_in_progress = S3C24XX_TX_PIO;
387 ufcon = rd_regl(port, S3C2410_UFCON);
388 wr_regl(port, S3C2410_UFCON, ufcon);
389
390 /* Enable tx pio mode */
391 ucon = rd_regl(port, S3C2410_UCON);
392 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
393 ucon |= S3C64XX_UCON_TXMODE_CPU;
394 wr_regl(port, S3C2410_UCON, ucon);
395
396 /* Unmask Tx interrupt */
397 switch (ourport->info->type) {
398 case TYPE_S3C6400:
399 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
400 S3C64XX_UINTM);
401 break;
402 case TYPE_APPLE_S5L:
403 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
404 wr_regl(port, S3C2410_UCON, ucon);
405 break;
406 default:
407 enable_irq(ourport->tx_irq);
408 break;
409 }
410
411 ourport->tx_mode = S3C24XX_TX_PIO;
412
413 /*
414 * The Apple version only has edge triggered TX IRQs, so we need
415 * to kick off the process by sending some characters here.
416 */
417 if (ourport->info->type == TYPE_APPLE_S5L)
418 s3c24xx_serial_tx_chars(ourport);
419 }
420
s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port * ourport)421 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
422 {
423 if (ourport->tx_mode != S3C24XX_TX_PIO)
424 enable_tx_pio(ourport);
425 }
426
s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port * ourport,unsigned int count,unsigned int tail)427 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
428 unsigned int count, unsigned int tail)
429 {
430 struct s3c24xx_uart_dma *dma = ourport->dma;
431
432 if (ourport->tx_mode != S3C24XX_TX_DMA)
433 enable_tx_dma(ourport);
434
435 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
436 dma->tx_transfer_addr = dma->tx_addr + tail;
437
438 dma_sync_single_for_device(dma->tx_chan->device->dev,
439 dma->tx_transfer_addr, dma->tx_size,
440 DMA_TO_DEVICE);
441
442 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
443 dma->tx_transfer_addr, dma->tx_size,
444 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
445 if (!dma->tx_desc) {
446 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
447 return -EIO;
448 }
449
450 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
451 dma->tx_desc->callback_param = ourport;
452 dma->tx_bytes_requested = dma->tx_size;
453
454 ourport->tx_in_progress = S3C24XX_TX_DMA;
455 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
456 dma_async_issue_pending(dma->tx_chan);
457 return 0;
458 }
459
s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port * ourport)460 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
461 {
462 struct uart_port *port = &ourport->port;
463 struct tty_port *tport = &port->state->port;
464 unsigned int count, tail;
465
466 /* Get data size up to the end of buffer */
467 count = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE);
468
469 if (!count) {
470 s3c24xx_serial_stop_tx(port);
471 return;
472 }
473
474 if (!ourport->dma || !ourport->dma->tx_chan ||
475 count < ourport->min_dma_size ||
476 tail & (dma_get_cache_alignment() - 1))
477 s3c24xx_serial_start_tx_pio(ourport);
478 else
479 s3c24xx_serial_start_tx_dma(ourport, count, tail);
480 }
481
s3c24xx_serial_start_tx(struct uart_port * port)482 static void s3c24xx_serial_start_tx(struct uart_port *port)
483 {
484 struct s3c24xx_uart_port *ourport = to_ourport(port);
485 struct tty_port *tport = &port->state->port;
486
487 if (!ourport->tx_enabled) {
488 if (port->flags & UPF_CONS_FLOW)
489 s3c24xx_serial_rx_disable(port);
490
491 ourport->tx_enabled = 1;
492 if (!ourport->dma || !ourport->dma->tx_chan)
493 s3c24xx_serial_start_tx_pio(ourport);
494 }
495
496 if (ourport->dma && ourport->dma->tx_chan) {
497 if (!kfifo_is_empty(&tport->xmit_fifo) &&
498 !ourport->tx_in_progress)
499 s3c24xx_serial_start_next_tx(ourport);
500 }
501 }
502
s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port * ourport,struct tty_port * tty,int count)503 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
504 struct tty_port *tty, int count)
505 {
506 struct s3c24xx_uart_dma *dma = ourport->dma;
507 int copied;
508
509 if (!count)
510 return;
511
512 dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
513 dma->rx_size, DMA_FROM_DEVICE);
514
515 ourport->port.icount.rx += count;
516 if (!tty) {
517 dev_err(ourport->port.dev, "No tty port\n");
518 return;
519 }
520 copied = tty_insert_flip_string(tty,
521 ((unsigned char *)(ourport->dma->rx_buf)), count);
522 if (copied != count) {
523 WARN_ON(1);
524 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
525 }
526 }
527
s3c24xx_serial_stop_rx(struct uart_port * port)528 static void s3c24xx_serial_stop_rx(struct uart_port *port)
529 {
530 struct s3c24xx_uart_port *ourport = to_ourport(port);
531 struct s3c24xx_uart_dma *dma = ourport->dma;
532 struct tty_port *t = &port->state->port;
533 struct dma_tx_state state;
534 enum dma_status dma_status;
535 unsigned int received;
536
537 if (ourport->rx_enabled) {
538 dev_dbg(port->dev, "stopping rx\n");
539 switch (ourport->info->type) {
540 case TYPE_S3C6400:
541 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
542 S3C64XX_UINTM);
543 break;
544 case TYPE_APPLE_S5L:
545 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
546 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
547 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON);
548 break;
549 default:
550 disable_irq_nosync(ourport->rx_irq);
551 break;
552 }
553 ourport->rx_enabled = 0;
554 }
555 if (dma && dma->rx_chan) {
556 dmaengine_pause(dma->tx_chan);
557 dma_status = dmaengine_tx_status(dma->rx_chan,
558 dma->rx_cookie, &state);
559 if (dma_status == DMA_IN_PROGRESS ||
560 dma_status == DMA_PAUSED) {
561 received = dma->rx_bytes_requested - state.residue;
562 dmaengine_terminate_all(dma->rx_chan);
563 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
564 }
565 }
566 }
567
568 static inline const struct s3c24xx_uart_info
s3c24xx_port_to_info(struct uart_port * port)569 *s3c24xx_port_to_info(struct uart_port *port)
570 {
571 return to_ourport(port)->info;
572 }
573
574 static inline const struct s3c2410_uartcfg
s3c24xx_port_to_cfg(const struct uart_port * port)575 *s3c24xx_port_to_cfg(const struct uart_port *port)
576 {
577 const struct s3c24xx_uart_port *ourport;
578
579 if (port->dev == NULL)
580 return NULL;
581
582 ourport = container_of(port, struct s3c24xx_uart_port, port);
583 return ourport->cfg;
584 }
585
586 static unsigned int
s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port * ourport,u32 ufstat)587 s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport, u32 ufstat)
588 {
589 const struct s3c24xx_uart_info *info = ourport->info;
590
591 if (ufstat & info->rx_fifofull)
592 return ourport->port.fifosize;
593
594 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
595 }
596
597 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
s3c24xx_serial_rx_dma_complete(void * args)598 static void s3c24xx_serial_rx_dma_complete(void *args)
599 {
600 struct s3c24xx_uart_port *ourport = args;
601 struct uart_port *port = &ourport->port;
602
603 struct s3c24xx_uart_dma *dma = ourport->dma;
604 struct tty_port *t = &port->state->port;
605 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
606
607 struct dma_tx_state state;
608 unsigned long flags;
609 int received;
610
611 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
612 received = dma->rx_bytes_requested - state.residue;
613 async_tx_ack(dma->rx_desc);
614
615 uart_port_lock_irqsave(port, &flags);
616
617 if (received)
618 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
619
620 if (tty) {
621 tty_flip_buffer_push(t);
622 tty_kref_put(tty);
623 }
624
625 s3c64xx_start_rx_dma(ourport);
626
627 uart_port_unlock_irqrestore(port, flags);
628 }
629
s3c64xx_start_rx_dma(struct s3c24xx_uart_port * ourport)630 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
631 {
632 struct s3c24xx_uart_dma *dma = ourport->dma;
633
634 dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
635 dma->rx_size, DMA_FROM_DEVICE);
636
637 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
638 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
639 DMA_PREP_INTERRUPT);
640 if (!dma->rx_desc) {
641 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
642 return;
643 }
644
645 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
646 dma->rx_desc->callback_param = ourport;
647 dma->rx_bytes_requested = dma->rx_size;
648
649 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
650 dma_async_issue_pending(dma->rx_chan);
651 }
652
653 /* ? - where has parity gone?? */
654 #define S3C2410_UERSTAT_PARITY (0x1000)
655
enable_rx_dma(struct s3c24xx_uart_port * ourport)656 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
657 {
658 struct uart_port *port = &ourport->port;
659 u32 ucon;
660
661 /* set Rx mode to DMA mode */
662 ucon = rd_regl(port, S3C2410_UCON);
663 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
664 S3C64XX_UCON_TIMEOUT_MASK |
665 S3C64XX_UCON_EMPTYINT_EN |
666 S3C64XX_UCON_DMASUS_EN |
667 S3C64XX_UCON_TIMEOUT_EN |
668 S3C64XX_UCON_RXMODE_MASK);
669 ucon |= S3C64XX_UCON_RXBURST_1 |
670 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
671 S3C64XX_UCON_EMPTYINT_EN |
672 S3C64XX_UCON_TIMEOUT_EN |
673 S3C64XX_UCON_RXMODE_DMA;
674 wr_regl(port, S3C2410_UCON, ucon);
675
676 ourport->rx_mode = S3C24XX_RX_DMA;
677 }
678
enable_rx_pio(struct s3c24xx_uart_port * ourport)679 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
680 {
681 struct uart_port *port = &ourport->port;
682 u32 ucon;
683
684 /* set Rx mode to DMA mode */
685 ucon = rd_regl(port, S3C2410_UCON);
686 ucon &= ~S3C64XX_UCON_RXMODE_MASK;
687 ucon |= S3C64XX_UCON_RXMODE_CPU;
688
689 /* Apple types use these bits for IRQ masks */
690 if (ourport->info->type != TYPE_APPLE_S5L) {
691 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
692 S3C64XX_UCON_EMPTYINT_EN |
693 S3C64XX_UCON_DMASUS_EN |
694 S3C64XX_UCON_TIMEOUT_EN);
695 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
696 S3C64XX_UCON_TIMEOUT_EN;
697 }
698 wr_regl(port, S3C2410_UCON, ucon);
699
700 ourport->rx_mode = S3C24XX_RX_PIO;
701 }
702
703 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
704
s3c24xx_serial_rx_chars_dma(struct s3c24xx_uart_port * ourport)705 static irqreturn_t s3c24xx_serial_rx_chars_dma(struct s3c24xx_uart_port *ourport)
706 {
707 struct uart_port *port = &ourport->port;
708 struct s3c24xx_uart_dma *dma = ourport->dma;
709 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
710 struct tty_port *t = &port->state->port;
711 struct dma_tx_state state;
712 unsigned int received;
713 u32 utrstat;
714
715 utrstat = rd_regl(port, S3C2410_UTRSTAT);
716 rd_regl(port, S3C2410_UFSTAT);
717
718 uart_port_lock(port);
719
720 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
721 s3c64xx_start_rx_dma(ourport);
722 if (ourport->rx_mode == S3C24XX_RX_PIO)
723 enable_rx_dma(ourport);
724 goto finish;
725 }
726
727 if (ourport->rx_mode == S3C24XX_RX_DMA) {
728 dmaengine_pause(dma->rx_chan);
729 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
730 dmaengine_terminate_all(dma->rx_chan);
731 received = dma->rx_bytes_requested - state.residue;
732 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
733
734 enable_rx_pio(ourport);
735 }
736
737 s3c24xx_serial_rx_drain_fifo(ourport);
738
739 if (tty) {
740 tty_flip_buffer_push(t);
741 tty_kref_put(tty);
742 }
743
744 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
745
746 finish:
747 uart_port_unlock(port);
748
749 return IRQ_HANDLED;
750 }
751
s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port * ourport)752 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
753 {
754 struct uart_port *port = &ourport->port;
755 unsigned int max_count = port->fifosize;
756 unsigned int fifocnt = 0;
757 u32 ufcon, ufstat, uerstat;
758 u8 ch, flag;
759
760 while (max_count-- > 0) {
761 /*
762 * Receive all characters known to be in FIFO
763 * before reading FIFO level again
764 */
765 if (fifocnt == 0) {
766 ufstat = rd_regl(port, S3C2410_UFSTAT);
767 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
768 if (fifocnt == 0)
769 break;
770 }
771 fifocnt--;
772
773 uerstat = rd_regl(port, S3C2410_UERSTAT);
774 ch = rd_reg(port, S3C2410_URXH);
775
776 if (port->flags & UPF_CONS_FLOW) {
777 bool txe = s3c24xx_serial_txempty_nofifo(port);
778
779 if (ourport->rx_enabled) {
780 if (!txe) {
781 ourport->rx_enabled = 0;
782 continue;
783 }
784 } else {
785 if (txe) {
786 ufcon = rd_regl(port, S3C2410_UFCON);
787 ufcon |= S3C2410_UFCON_RESETRX;
788 wr_regl(port, S3C2410_UFCON, ufcon);
789 ourport->rx_enabled = 1;
790 return;
791 }
792 continue;
793 }
794 }
795
796 /* insert the character into the buffer */
797
798 flag = TTY_NORMAL;
799 port->icount.rx++;
800
801 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
802 dev_dbg(port->dev,
803 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
804 ch, uerstat);
805
806 /* check for break */
807 if (uerstat & S3C2410_UERSTAT_BREAK) {
808 dev_dbg(port->dev, "break!\n");
809 port->icount.brk++;
810 if (uart_handle_break(port))
811 continue; /* Ignore character */
812 }
813
814 if (uerstat & S3C2410_UERSTAT_FRAME)
815 port->icount.frame++;
816 if (uerstat & S3C2410_UERSTAT_OVERRUN)
817 port->icount.overrun++;
818
819 uerstat &= port->read_status_mask;
820
821 if (uerstat & S3C2410_UERSTAT_BREAK)
822 flag = TTY_BREAK;
823 else if (uerstat & S3C2410_UERSTAT_PARITY)
824 flag = TTY_PARITY;
825 else if (uerstat & (S3C2410_UERSTAT_FRAME |
826 S3C2410_UERSTAT_OVERRUN))
827 flag = TTY_FRAME;
828 }
829
830 if (uart_handle_sysrq_char(port, ch))
831 continue; /* Ignore character */
832
833 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
834 ch, flag);
835 }
836
837 tty_flip_buffer_push(&port->state->port);
838 }
839
s3c24xx_serial_rx_chars_pio(struct s3c24xx_uart_port * ourport)840 static irqreturn_t s3c24xx_serial_rx_chars_pio(struct s3c24xx_uart_port *ourport)
841 {
842 struct uart_port *port = &ourport->port;
843
844 uart_port_lock(port);
845 s3c24xx_serial_rx_drain_fifo(ourport);
846 uart_port_unlock(port);
847
848 return IRQ_HANDLED;
849 }
850
s3c24xx_serial_rx_irq(struct s3c24xx_uart_port * ourport)851 static irqreturn_t s3c24xx_serial_rx_irq(struct s3c24xx_uart_port *ourport)
852 {
853 if (ourport->dma && ourport->dma->rx_chan)
854 return s3c24xx_serial_rx_chars_dma(ourport);
855 return s3c24xx_serial_rx_chars_pio(ourport);
856 }
857
s3c24xx_serial_tx_chars(struct s3c24xx_uart_port * ourport)858 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
859 {
860 struct uart_port *port = &ourport->port;
861 struct tty_port *tport = &port->state->port;
862 unsigned int count, dma_count = 0, tail;
863
864 count = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE);
865
866 if (ourport->dma && ourport->dma->tx_chan &&
867 count >= ourport->min_dma_size) {
868 int align = dma_get_cache_alignment() -
869 (tail & (dma_get_cache_alignment() - 1));
870 if (count - align >= ourport->min_dma_size) {
871 dma_count = count - align;
872 count = align;
873 tail += align;
874 }
875 }
876
877 if (port->x_char) {
878 wr_reg(port, S3C2410_UTXH, port->x_char);
879 port->icount.tx++;
880 port->x_char = 0;
881 return;
882 }
883
884 /* if there isn't anything more to transmit, or the uart is now
885 * stopped, disable the uart and exit
886 */
887
888 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
889 s3c24xx_serial_stop_tx(port);
890 return;
891 }
892
893 /* try and drain the buffer... */
894
895 if (count > port->fifosize) {
896 count = port->fifosize;
897 dma_count = 0;
898 }
899
900 while (!(rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)) {
901 unsigned char ch;
902
903 if (!uart_fifo_get(port, &ch))
904 break;
905
906 wr_reg(port, S3C2410_UTXH, ch);
907 count--;
908 }
909
910 if (!count && dma_count) {
911 s3c24xx_serial_start_tx_dma(ourport, dma_count, tail);
912 return;
913 }
914
915 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
916 uart_write_wakeup(port);
917
918 if (kfifo_is_empty(&tport->xmit_fifo))
919 s3c24xx_serial_stop_tx(port);
920 }
921
s3c24xx_serial_tx_irq(struct s3c24xx_uart_port * ourport)922 static irqreturn_t s3c24xx_serial_tx_irq(struct s3c24xx_uart_port *ourport)
923 {
924 struct uart_port *port = &ourport->port;
925
926 uart_port_lock(port);
927
928 s3c24xx_serial_tx_chars(ourport);
929
930 uart_port_unlock(port);
931 return IRQ_HANDLED;
932 }
933
934 /* interrupt handler for s3c64xx and later SoC's.*/
s3c64xx_serial_handle_irq(int irq,void * id)935 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
936 {
937 struct s3c24xx_uart_port *ourport = id;
938 const struct uart_port *port = &ourport->port;
939 u32 pend = rd_regl(port, S3C64XX_UINTP);
940 irqreturn_t ret = IRQ_HANDLED;
941
942 if (pend & S3C64XX_UINTM_RXD_MSK) {
943 ret = s3c24xx_serial_rx_irq(ourport);
944 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
945 }
946 if (pend & S3C64XX_UINTM_TXD_MSK) {
947 ret = s3c24xx_serial_tx_irq(ourport);
948 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
949 }
950 return ret;
951 }
952
953 /* interrupt handler for Apple SoC's.*/
apple_serial_handle_irq(int irq,void * id)954 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
955 {
956 struct s3c24xx_uart_port *ourport = id;
957 const struct uart_port *port = &ourport->port;
958 u32 pend = rd_regl(port, S3C2410_UTRSTAT);
959 irqreturn_t ret = IRQ_NONE;
960
961 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO |
962 APPLE_S5L_UTRSTAT_RXTO_LEGACY)) {
963 wr_regl(port, S3C2410_UTRSTAT,
964 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO |
965 APPLE_S5L_UTRSTAT_RXTO_LEGACY);
966 ret = s3c24xx_serial_rx_irq(ourport);
967 }
968 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
969 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
970 ret = s3c24xx_serial_tx_irq(ourport);
971 }
972
973 return ret;
974 }
975
s3c24xx_serial_tx_empty(struct uart_port * port)976 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
977 {
978 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
979 u32 ufstat = rd_regl(port, S3C2410_UFSTAT);
980 u32 ufcon = rd_regl(port, S3C2410_UFCON);
981
982 if (ufcon & S3C2410_UFCON_FIFOMODE) {
983 if ((ufstat & info->tx_fifomask) ||
984 (ufstat & info->tx_fifofull))
985 return 0;
986 return TIOCSER_TEMT;
987 }
988
989 return s3c24xx_serial_txempty_nofifo(port) ? TIOCSER_TEMT : 0;
990 }
991
992 /* no modem control lines */
s3c24xx_serial_get_mctrl(struct uart_port * port)993 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
994 {
995 u32 umstat = rd_reg(port, S3C2410_UMSTAT);
996
997 if (umstat & S3C2410_UMSTAT_CTS)
998 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
999 else
1000 return TIOCM_CAR | TIOCM_DSR;
1001 }
1002
s3c24xx_serial_set_mctrl(struct uart_port * port,unsigned int mctrl)1003 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1004 {
1005 u32 umcon = rd_regl(port, S3C2410_UMCON);
1006 u32 ucon = rd_regl(port, S3C2410_UCON);
1007
1008 if (mctrl & TIOCM_RTS)
1009 umcon |= S3C2410_UMCOM_RTS_LOW;
1010 else
1011 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1012
1013 wr_regl(port, S3C2410_UMCON, umcon);
1014
1015 if (mctrl & TIOCM_LOOP)
1016 ucon |= S3C2410_UCON_LOOPBACK;
1017 else
1018 ucon &= ~S3C2410_UCON_LOOPBACK;
1019
1020 wr_regl(port, S3C2410_UCON, ucon);
1021 }
1022
s3c24xx_serial_break_ctl(struct uart_port * port,int break_state)1023 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1024 {
1025 unsigned long flags;
1026 u32 ucon;
1027
1028 uart_port_lock_irqsave(port, &flags);
1029
1030 ucon = rd_regl(port, S3C2410_UCON);
1031
1032 if (break_state)
1033 ucon |= S3C2410_UCON_SBREAK;
1034 else
1035 ucon &= ~S3C2410_UCON_SBREAK;
1036
1037 wr_regl(port, S3C2410_UCON, ucon);
1038
1039 uart_port_unlock_irqrestore(port, flags);
1040 }
1041
s3c24xx_serial_request_dma(struct s3c24xx_uart_port * p)1042 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1043 {
1044 struct s3c24xx_uart_dma *dma = p->dma;
1045 struct dma_slave_caps dma_caps;
1046 const char *reason = NULL;
1047 int ret;
1048
1049 /* Default slave configuration parameters */
1050 dma->rx_conf.direction = DMA_DEV_TO_MEM;
1051 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1052 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
1053 dma->rx_conf.src_maxburst = 1;
1054
1055 dma->tx_conf.direction = DMA_MEM_TO_DEV;
1056 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1057 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
1058 dma->tx_conf.dst_maxburst = 1;
1059
1060 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1061
1062 if (IS_ERR(dma->rx_chan)) {
1063 reason = "DMA RX channel request failed";
1064 ret = PTR_ERR(dma->rx_chan);
1065 goto err_warn;
1066 }
1067
1068 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1069 if (ret < 0 ||
1070 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1071 reason = "insufficient DMA RX engine capabilities";
1072 ret = -EOPNOTSUPP;
1073 goto err_release_rx;
1074 }
1075
1076 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1077
1078 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1079 if (IS_ERR(dma->tx_chan)) {
1080 reason = "DMA TX channel request failed";
1081 ret = PTR_ERR(dma->tx_chan);
1082 goto err_release_rx;
1083 }
1084
1085 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1086 if (ret < 0 ||
1087 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1088 reason = "insufficient DMA TX engine capabilities";
1089 ret = -EOPNOTSUPP;
1090 goto err_release_tx;
1091 }
1092
1093 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1094
1095 /* RX buffer */
1096 dma->rx_size = PAGE_SIZE;
1097
1098 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1099 if (!dma->rx_buf) {
1100 ret = -ENOMEM;
1101 goto err_release_tx;
1102 }
1103
1104 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1105 dma->rx_size, DMA_FROM_DEVICE);
1106 if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1107 reason = "DMA mapping error for RX buffer";
1108 ret = -EIO;
1109 goto err_free_rx;
1110 }
1111
1112 /* TX buffer */
1113 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1114 p->port.state->port.xmit_buf,
1115 UART_XMIT_SIZE,
1116 DMA_TO_DEVICE);
1117 if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1118 reason = "DMA mapping error for TX buffer";
1119 ret = -EIO;
1120 goto err_unmap_rx;
1121 }
1122
1123 return 0;
1124
1125 err_unmap_rx:
1126 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1127 dma->rx_size, DMA_FROM_DEVICE);
1128 err_free_rx:
1129 kfree(dma->rx_buf);
1130 err_release_tx:
1131 dma_release_channel(dma->tx_chan);
1132 err_release_rx:
1133 dma_release_channel(dma->rx_chan);
1134 err_warn:
1135 if (reason)
1136 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1137 return ret;
1138 }
1139
s3c24xx_serial_release_dma(struct s3c24xx_uart_port * p)1140 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1141 {
1142 struct s3c24xx_uart_dma *dma = p->dma;
1143
1144 if (dma->rx_chan) {
1145 dmaengine_terminate_all(dma->rx_chan);
1146 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1147 dma->rx_size, DMA_FROM_DEVICE);
1148 kfree(dma->rx_buf);
1149 dma_release_channel(dma->rx_chan);
1150 dma->rx_chan = NULL;
1151 }
1152
1153 if (dma->tx_chan) {
1154 dmaengine_terminate_all(dma->tx_chan);
1155 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1156 UART_XMIT_SIZE, DMA_TO_DEVICE);
1157 dma_release_channel(dma->tx_chan);
1158 dma->tx_chan = NULL;
1159 }
1160 }
1161
s3c64xx_serial_shutdown(struct uart_port * port)1162 static void s3c64xx_serial_shutdown(struct uart_port *port)
1163 {
1164 struct s3c24xx_uart_port *ourport = to_ourport(port);
1165
1166 ourport->tx_enabled = 0;
1167 ourport->tx_mode = 0;
1168 ourport->rx_enabled = 0;
1169
1170 free_irq(port->irq, ourport);
1171
1172 wr_regl(port, S3C64XX_UINTP, 0xf);
1173 wr_regl(port, S3C64XX_UINTM, 0xf);
1174
1175 if (ourport->dma)
1176 s3c24xx_serial_release_dma(ourport);
1177
1178 ourport->tx_in_progress = 0;
1179 }
1180
apple_s5l_serial_shutdown(struct uart_port * port)1181 static void apple_s5l_serial_shutdown(struct uart_port *port)
1182 {
1183 struct s3c24xx_uart_port *ourport = to_ourport(port);
1184
1185 u32 ucon;
1186
1187 ucon = rd_regl(port, S3C2410_UCON);
1188 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1189 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1190 APPLE_S5L_UCON_RXTO_ENA_MSK |
1191 APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK);
1192 wr_regl(port, S3C2410_UCON, ucon);
1193
1194 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1195
1196 free_irq(port->irq, ourport);
1197
1198 ourport->tx_enabled = 0;
1199 ourport->tx_mode = 0;
1200 ourport->rx_enabled = 0;
1201
1202 if (ourport->dma)
1203 s3c24xx_serial_release_dma(ourport);
1204
1205 ourport->tx_in_progress = 0;
1206 }
1207
s3c64xx_serial_startup(struct uart_port * port)1208 static int s3c64xx_serial_startup(struct uart_port *port)
1209 {
1210 struct s3c24xx_uart_port *ourport = to_ourport(port);
1211 unsigned long flags;
1212 u32 ufcon;
1213 int ret;
1214
1215 wr_regl(port, S3C64XX_UINTM, 0xf);
1216 if (ourport->dma) {
1217 ret = s3c24xx_serial_request_dma(ourport);
1218 if (ret < 0) {
1219 devm_kfree(port->dev, ourport->dma);
1220 ourport->dma = NULL;
1221 }
1222 }
1223
1224 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1225 s3c24xx_serial_portname(port), ourport);
1226 if (ret) {
1227 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1228 return ret;
1229 }
1230
1231 /* For compatibility with s3c24xx Soc's */
1232 ourport->rx_enabled = 1;
1233 ourport->tx_enabled = 0;
1234
1235 uart_port_lock_irqsave(port, &flags);
1236
1237 ufcon = rd_regl(port, S3C2410_UFCON);
1238 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1239 if (!uart_console(port))
1240 ufcon |= S3C2410_UFCON_RESETTX;
1241 wr_regl(port, S3C2410_UFCON, ufcon);
1242
1243 enable_rx_pio(ourport);
1244
1245 uart_port_unlock_irqrestore(port, flags);
1246
1247 /* Enable Rx Interrupt */
1248 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1249
1250 return ret;
1251 }
1252
apple_s5l_serial_startup(struct uart_port * port)1253 static int apple_s5l_serial_startup(struct uart_port *port)
1254 {
1255 struct s3c24xx_uart_port *ourport = to_ourport(port);
1256 unsigned long flags;
1257 u32 ufcon;
1258 int ret;
1259
1260 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1261
1262 ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1263 s3c24xx_serial_portname(port), ourport);
1264 if (ret) {
1265 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1266 return ret;
1267 }
1268
1269 /* For compatibility with s3c24xx Soc's */
1270 ourport->rx_enabled = 1;
1271 ourport->tx_enabled = 0;
1272
1273 uart_port_lock_irqsave(port, &flags);
1274
1275 ufcon = rd_regl(port, S3C2410_UFCON);
1276 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1277 if (!uart_console(port))
1278 ufcon |= S3C2410_UFCON_RESETTX;
1279 wr_regl(port, S3C2410_UFCON, ufcon);
1280
1281 enable_rx_pio(ourport);
1282
1283 uart_port_unlock_irqrestore(port, flags);
1284
1285 /* Enable Rx Interrupt */
1286 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1287 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1288 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON);
1289
1290 return ret;
1291 }
1292
s3c24xx_serial_pm(struct uart_port * port,unsigned int level,unsigned int old)1293 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1294 unsigned int old)
1295 {
1296 struct s3c24xx_uart_port *ourport = to_ourport(port);
1297 int timeout = 10000;
1298
1299 ourport->pm_level = level;
1300
1301 switch (level) {
1302 case 3:
1303 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1304 udelay(100);
1305
1306 if (!IS_ERR(ourport->baudclk))
1307 clk_disable_unprepare(ourport->baudclk);
1308
1309 clk_disable_unprepare(ourport->clk);
1310 break;
1311
1312 case 0:
1313 clk_prepare_enable(ourport->clk);
1314
1315 if (!IS_ERR(ourport->baudclk))
1316 clk_prepare_enable(ourport->baudclk);
1317 break;
1318 default:
1319 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1320 }
1321 }
1322
1323 /* baud rate calculation
1324 *
1325 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1326 * of different sources, including the peripheral clock ("pclk") and an
1327 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1328 * with a programmable extra divisor.
1329 *
1330 * The following code goes through the clock sources, and calculates the
1331 * baud clocks (and the resultant actual baud rates) and then tries to
1332 * pick the closest one and select that.
1333 *
1334 */
1335
1336 #define MAX_CLK_NAME_LENGTH 15
1337
s3c24xx_serial_getsource(struct uart_port * port)1338 static inline u8 s3c24xx_serial_getsource(struct uart_port *port)
1339 {
1340 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1341 u32 ucon;
1342
1343 if (info->num_clks == 1)
1344 return 0;
1345
1346 ucon = rd_regl(port, S3C2410_UCON);
1347 ucon &= info->clksel_mask;
1348 return ucon >> info->clksel_shift;
1349 }
1350
s3c24xx_serial_setsource(struct uart_port * port,u8 clk_sel)1351 static void s3c24xx_serial_setsource(struct uart_port *port, u8 clk_sel)
1352 {
1353 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1354 u32 ucon;
1355
1356 if (info->num_clks == 1)
1357 return;
1358
1359 ucon = rd_regl(port, S3C2410_UCON);
1360 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1361 return;
1362
1363 ucon &= ~info->clksel_mask;
1364 ucon |= clk_sel << info->clksel_shift;
1365 wr_regl(port, S3C2410_UCON, ucon);
1366 }
1367
s3c24xx_serial_getclk(struct s3c24xx_uart_port * ourport,unsigned int req_baud,struct clk ** best_clk,u8 * clk_num)1368 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1369 unsigned int req_baud, struct clk **best_clk,
1370 u8 *clk_num)
1371 {
1372 const struct s3c24xx_uart_info *info = ourport->info;
1373 struct clk *clk;
1374 unsigned long rate;
1375 unsigned int baud, quot, best_quot = 0;
1376 char clkname[MAX_CLK_NAME_LENGTH];
1377 int calc_deviation, deviation = (1 << 30) - 1;
1378 u8 cnt;
1379
1380 for (cnt = 0; cnt < info->num_clks; cnt++) {
1381 /* Keep selected clock if provided */
1382 if (ourport->cfg->clk_sel &&
1383 !(ourport->cfg->clk_sel & (1 << cnt)))
1384 continue;
1385
1386 sprintf(clkname, "clk_uart_baud%d", cnt);
1387 clk = clk_get(ourport->port.dev, clkname);
1388 if (IS_ERR(clk))
1389 continue;
1390
1391 rate = clk_get_rate(clk);
1392 if (!rate) {
1393 dev_err(ourport->port.dev,
1394 "Failed to get clock rate for %s.\n", clkname);
1395 clk_put(clk);
1396 continue;
1397 }
1398
1399 if (ourport->info->has_divslot) {
1400 unsigned long div = rate / req_baud;
1401
1402 /* The UDIVSLOT register on the newer UARTs allows us to
1403 * get a divisor adjustment of 1/16th on the baud clock.
1404 *
1405 * We don't keep the UDIVSLOT value (the 16ths we
1406 * calculated by not multiplying the baud by 16) as it
1407 * is easy enough to recalculate.
1408 */
1409
1410 quot = div / 16;
1411 baud = rate / div;
1412 } else {
1413 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1414 baud = rate / (quot * 16);
1415 }
1416 quot--;
1417
1418 calc_deviation = abs(req_baud - baud);
1419
1420 if (calc_deviation < deviation) {
1421 /*
1422 * If we find a better clk, release the previous one, if
1423 * any.
1424 */
1425 if (!IS_ERR(*best_clk))
1426 clk_put(*best_clk);
1427 *best_clk = clk;
1428 best_quot = quot;
1429 *clk_num = cnt;
1430 deviation = calc_deviation;
1431 } else {
1432 clk_put(clk);
1433 }
1434 }
1435
1436 return best_quot;
1437 }
1438
1439 /* udivslot_table[]
1440 *
1441 * This table takes the fractional value of the baud divisor and gives
1442 * the recommended setting for the UDIVSLOT register.
1443 */
1444 static const u16 udivslot_table[16] = {
1445 [0] = 0x0000,
1446 [1] = 0x0080,
1447 [2] = 0x0808,
1448 [3] = 0x0888,
1449 [4] = 0x2222,
1450 [5] = 0x4924,
1451 [6] = 0x4A52,
1452 [7] = 0x54AA,
1453 [8] = 0x5555,
1454 [9] = 0xD555,
1455 [10] = 0xD5D5,
1456 [11] = 0xDDD5,
1457 [12] = 0xDDDD,
1458 [13] = 0xDFDD,
1459 [14] = 0xDFDF,
1460 [15] = 0xFFDF,
1461 };
1462
s3c24xx_serial_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1463 static void s3c24xx_serial_set_termios(struct uart_port *port,
1464 struct ktermios *termios,
1465 const struct ktermios *old)
1466 {
1467 const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1468 struct s3c24xx_uart_port *ourport = to_ourport(port);
1469 struct clk *clk = ERR_PTR(-EINVAL);
1470 unsigned long flags;
1471 unsigned int baud, quot;
1472 unsigned int udivslot = 0;
1473 u32 ulcon, umcon;
1474 u8 clk_sel = 0;
1475
1476 /*
1477 * We don't support modem control lines.
1478 */
1479 termios->c_cflag &= ~(HUPCL | CMSPAR);
1480 termios->c_cflag |= CLOCAL;
1481
1482 /*
1483 * Ask the core to calculate the divisor for us.
1484 */
1485
1486 baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1487 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1488 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1489 quot = port->custom_divisor;
1490 if (IS_ERR(clk))
1491 return;
1492
1493 /* check to see if we need to change clock source */
1494
1495 if (ourport->baudclk != clk) {
1496 clk_prepare_enable(clk);
1497
1498 s3c24xx_serial_setsource(port, clk_sel);
1499
1500 if (!IS_ERR(ourport->baudclk)) {
1501 clk_disable_unprepare(ourport->baudclk);
1502 ourport->baudclk = ERR_PTR(-EINVAL);
1503 }
1504
1505 ourport->baudclk = clk;
1506 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1507 }
1508
1509 if (ourport->info->has_divslot) {
1510 unsigned int div = ourport->baudclk_rate / baud;
1511
1512 if (cfg->has_fracval) {
1513 udivslot = (div & 15);
1514 dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1515 } else {
1516 udivslot = udivslot_table[div & 15];
1517 dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1518 udivslot, div & 15);
1519 }
1520 }
1521
1522 switch (termios->c_cflag & CSIZE) {
1523 case CS5:
1524 dev_dbg(port->dev, "config: 5bits/char\n");
1525 ulcon = S3C2410_LCON_CS5;
1526 break;
1527 case CS6:
1528 dev_dbg(port->dev, "config: 6bits/char\n");
1529 ulcon = S3C2410_LCON_CS6;
1530 break;
1531 case CS7:
1532 dev_dbg(port->dev, "config: 7bits/char\n");
1533 ulcon = S3C2410_LCON_CS7;
1534 break;
1535 case CS8:
1536 default:
1537 dev_dbg(port->dev, "config: 8bits/char\n");
1538 ulcon = S3C2410_LCON_CS8;
1539 break;
1540 }
1541
1542 /* preserve original lcon IR settings */
1543 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1544
1545 if (termios->c_cflag & CSTOPB)
1546 ulcon |= S3C2410_LCON_STOPB;
1547
1548 if (termios->c_cflag & PARENB) {
1549 if (termios->c_cflag & PARODD)
1550 ulcon |= S3C2410_LCON_PODD;
1551 else
1552 ulcon |= S3C2410_LCON_PEVEN;
1553 } else {
1554 ulcon |= S3C2410_LCON_PNONE;
1555 }
1556
1557 dev_dbg(port->dev,
1558 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1559 ulcon, quot, udivslot);
1560
1561 uart_port_lock_irqsave(port, &flags);
1562
1563 wr_regl(port, S3C2410_ULCON, ulcon);
1564 wr_regl(port, S3C2410_UBRDIV, quot);
1565
1566 port->status &= ~UPSTAT_AUTOCTS;
1567
1568 umcon = rd_regl(port, S3C2410_UMCON);
1569 if (termios->c_cflag & CRTSCTS) {
1570 umcon |= S3C2410_UMCOM_AFC;
1571 /* Disable RTS when RX FIFO contains 63 bytes */
1572 umcon &= ~S3C2412_UMCON_AFC_8;
1573 port->status = UPSTAT_AUTOCTS;
1574 } else {
1575 umcon &= ~S3C2410_UMCOM_AFC;
1576 }
1577 wr_regl(port, S3C2410_UMCON, umcon);
1578
1579 if (ourport->info->has_divslot)
1580 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1581
1582 /*
1583 * Update the per-port timeout.
1584 */
1585 uart_update_timeout(port, termios->c_cflag, baud);
1586
1587 /*
1588 * Which character status flags are we interested in?
1589 */
1590 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1591 if (termios->c_iflag & INPCK)
1592 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1593 S3C2410_UERSTAT_PARITY;
1594 /*
1595 * Which character status flags should we ignore?
1596 */
1597 port->ignore_status_mask = 0;
1598 if (termios->c_iflag & IGNPAR)
1599 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1600 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1601 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1602
1603 /*
1604 * Ignore all characters if CREAD is not set.
1605 */
1606 if ((termios->c_cflag & CREAD) == 0)
1607 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1608
1609 uart_port_unlock_irqrestore(port, flags);
1610 }
1611
s3c24xx_serial_type(struct uart_port * port)1612 static const char *s3c24xx_serial_type(struct uart_port *port)
1613 {
1614 const struct s3c24xx_uart_port *ourport = to_ourport(port);
1615
1616 switch (ourport->info->type) {
1617 case TYPE_S3C6400:
1618 return "S3C6400/10";
1619 case TYPE_APPLE_S5L:
1620 return "APPLE S5L";
1621 default:
1622 return NULL;
1623 }
1624 }
1625
s3c24xx_serial_config_port(struct uart_port * port,int flags)1626 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1627 {
1628 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1629
1630 if (flags & UART_CONFIG_TYPE)
1631 port->type = info->port_type;
1632 }
1633
1634 /*
1635 * verify the new serial_struct (for TIOCSSERIAL).
1636 */
1637 static int
s3c24xx_serial_verify_port(struct uart_port * port,struct serial_struct * ser)1638 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1639 {
1640 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1641
1642 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1643 return -EINVAL;
1644
1645 return 0;
1646 }
1647
1648 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1649
1650 static struct console s3c24xx_serial_console;
1651
s3c24xx_serial_register_console(void)1652 static void __init s3c24xx_serial_register_console(void)
1653 {
1654 register_console(&s3c24xx_serial_console);
1655 }
1656
s3c24xx_serial_unregister_console(void)1657 static void s3c24xx_serial_unregister_console(void)
1658 {
1659 if (console_is_registered(&s3c24xx_serial_console))
1660 unregister_console(&s3c24xx_serial_console);
1661 }
1662
1663 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1664 #else
s3c24xx_serial_register_console(void)1665 static inline void s3c24xx_serial_register_console(void) { }
s3c24xx_serial_unregister_console(void)1666 static inline void s3c24xx_serial_unregister_console(void) { }
1667 #define S3C24XX_SERIAL_CONSOLE NULL
1668 #endif
1669
1670 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1671 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1672 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1673 unsigned char c);
1674 #endif
1675
1676 static const struct uart_ops s3c64xx_serial_ops = {
1677 .pm = s3c24xx_serial_pm,
1678 .tx_empty = s3c24xx_serial_tx_empty,
1679 .get_mctrl = s3c24xx_serial_get_mctrl,
1680 .set_mctrl = s3c24xx_serial_set_mctrl,
1681 .stop_tx = s3c24xx_serial_stop_tx,
1682 .start_tx = s3c24xx_serial_start_tx,
1683 .stop_rx = s3c24xx_serial_stop_rx,
1684 .break_ctl = s3c24xx_serial_break_ctl,
1685 .startup = s3c64xx_serial_startup,
1686 .shutdown = s3c64xx_serial_shutdown,
1687 .set_termios = s3c24xx_serial_set_termios,
1688 .type = s3c24xx_serial_type,
1689 .config_port = s3c24xx_serial_config_port,
1690 .verify_port = s3c24xx_serial_verify_port,
1691 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1692 .poll_get_char = s3c24xx_serial_get_poll_char,
1693 .poll_put_char = s3c24xx_serial_put_poll_char,
1694 #endif
1695 };
1696
1697 static const struct uart_ops apple_s5l_serial_ops = {
1698 .pm = s3c24xx_serial_pm,
1699 .tx_empty = s3c24xx_serial_tx_empty,
1700 .get_mctrl = s3c24xx_serial_get_mctrl,
1701 .set_mctrl = s3c24xx_serial_set_mctrl,
1702 .stop_tx = s3c24xx_serial_stop_tx,
1703 .start_tx = s3c24xx_serial_start_tx,
1704 .stop_rx = s3c24xx_serial_stop_rx,
1705 .break_ctl = s3c24xx_serial_break_ctl,
1706 .startup = apple_s5l_serial_startup,
1707 .shutdown = apple_s5l_serial_shutdown,
1708 .set_termios = s3c24xx_serial_set_termios,
1709 .type = s3c24xx_serial_type,
1710 .config_port = s3c24xx_serial_config_port,
1711 .verify_port = s3c24xx_serial_verify_port,
1712 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1713 .poll_get_char = s3c24xx_serial_get_poll_char,
1714 .poll_put_char = s3c24xx_serial_put_poll_char,
1715 #endif
1716 };
1717
1718 static struct uart_driver s3c24xx_uart_drv = {
1719 .owner = THIS_MODULE,
1720 .driver_name = "s3c2410_serial",
1721 .nr = UART_NR,
1722 .cons = S3C24XX_SERIAL_CONSOLE,
1723 .dev_name = S3C24XX_SERIAL_NAME,
1724 .major = S3C24XX_SERIAL_MAJOR,
1725 .minor = S3C24XX_SERIAL_MINOR,
1726 };
1727
1728 static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR];
1729
s3c24xx_serial_init_port_default(int index)1730 static void s3c24xx_serial_init_port_default(int index)
1731 {
1732 struct uart_port *port = &s3c24xx_serial_ports[index].port;
1733
1734 spin_lock_init(&port->lock);
1735
1736 port->uartclk = 0;
1737 port->fifosize = 16;
1738 port->flags = UPF_BOOT_AUTOCONF;
1739 port->line = index;
1740 }
1741
1742 /* s3c24xx_serial_resetport
1743 *
1744 * reset the fifos and other the settings.
1745 */
1746
s3c24xx_serial_resetport(struct uart_port * port,const struct s3c2410_uartcfg * cfg)1747 static void s3c24xx_serial_resetport(struct uart_port *port,
1748 const struct s3c2410_uartcfg *cfg)
1749 {
1750 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1751 u32 ucon = rd_regl(port, S3C2410_UCON);
1752
1753 ucon &= (info->clksel_mask | info->ucon_mask);
1754 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1755
1756 /* reset both fifos */
1757 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1758 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1759
1760 /* some delay is required after fifo reset */
1761 udelay(1);
1762 }
1763
s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port * ourport)1764 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1765 {
1766 struct device *dev = ourport->port.dev;
1767 const struct s3c24xx_uart_info *info = ourport->info;
1768 char clk_name[MAX_CLK_NAME_LENGTH];
1769 struct clk *clk;
1770 int ret;
1771 u8 clk_sel, clk_num;
1772
1773 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1774 for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1775 if (!(clk_sel & (1 << clk_num)))
1776 continue;
1777
1778 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1779 clk = clk_get(dev, clk_name);
1780 if (IS_ERR(clk))
1781 continue;
1782
1783 ret = clk_prepare_enable(clk);
1784 if (ret) {
1785 clk_put(clk);
1786 continue;
1787 }
1788
1789 ourport->baudclk = clk;
1790 ourport->baudclk_rate = clk_get_rate(clk);
1791 s3c24xx_serial_setsource(&ourport->port, clk_num);
1792
1793 return 0;
1794 }
1795
1796 return -EINVAL;
1797 }
1798
1799 /* s3c24xx_serial_init_port
1800 *
1801 * initialise a single serial port from the platform device given
1802 */
1803
s3c24xx_serial_init_port(struct s3c24xx_uart_port * ourport,struct platform_device * platdev)1804 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1805 struct platform_device *platdev)
1806 {
1807 struct uart_port *port = &ourport->port;
1808 const struct s3c2410_uartcfg *cfg = ourport->cfg;
1809 struct resource *res;
1810 int ret;
1811
1812 if (platdev == NULL)
1813 return -ENODEV;
1814
1815 if (port->mapbase != 0)
1816 return -EINVAL;
1817
1818 /* setup info for port */
1819 port->dev = &platdev->dev;
1820
1821 port->uartclk = 1;
1822
1823 if (cfg->uart_flags & UPF_CONS_FLOW) {
1824 dev_dbg(port->dev, "enabling flow control\n");
1825 port->flags |= UPF_CONS_FLOW;
1826 }
1827
1828 /* sort our the physical and virtual addresses for each UART */
1829
1830 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1831 if (res == NULL) {
1832 dev_err(port->dev, "failed to find memory resource for uart\n");
1833 return -EINVAL;
1834 }
1835
1836 dev_dbg(port->dev, "resource %pR)\n", res);
1837
1838 port->membase = devm_ioremap_resource(port->dev, res);
1839 if (IS_ERR(port->membase)) {
1840 dev_err(port->dev, "failed to remap controller address\n");
1841 return -EBUSY;
1842 }
1843
1844 port->mapbase = res->start;
1845 ret = platform_get_irq(platdev, 0);
1846 if (ret < 0) {
1847 port->irq = 0;
1848 } else {
1849 port->irq = ret;
1850 ourport->rx_irq = ret;
1851 ourport->tx_irq = ret + 1;
1852 }
1853
1854 /*
1855 * DMA is currently supported only on DT platforms, if DMA properties
1856 * are specified.
1857 */
1858 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1859 "dmas", NULL)) {
1860 ourport->dma = devm_kzalloc(port->dev,
1861 sizeof(*ourport->dma),
1862 GFP_KERNEL);
1863 if (!ourport->dma) {
1864 ret = -ENOMEM;
1865 goto err;
1866 }
1867 }
1868
1869 ourport->clk = clk_get(&platdev->dev, "uart");
1870 if (IS_ERR(ourport->clk)) {
1871 pr_err("%s: Controller clock not found\n",
1872 dev_name(&platdev->dev));
1873 ret = PTR_ERR(ourport->clk);
1874 goto err;
1875 }
1876
1877 ret = clk_prepare_enable(ourport->clk);
1878 if (ret) {
1879 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1880 clk_put(ourport->clk);
1881 goto err;
1882 }
1883
1884 ret = s3c24xx_serial_enable_baudclk(ourport);
1885 if (ret)
1886 pr_warn("uart: failed to enable baudclk\n");
1887
1888 /* Keep all interrupts masked and cleared */
1889 switch (ourport->info->type) {
1890 case TYPE_S3C6400:
1891 wr_regl(port, S3C64XX_UINTM, 0xf);
1892 wr_regl(port, S3C64XX_UINTP, 0xf);
1893 wr_regl(port, S3C64XX_UINTSP, 0xf);
1894 break;
1895 case TYPE_APPLE_S5L: {
1896 u32 ucon;
1897
1898 ucon = rd_regl(port, S3C2410_UCON);
1899 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1900 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1901 APPLE_S5L_UCON_RXTO_ENA_MSK);
1902 wr_regl(port, S3C2410_UCON, ucon);
1903
1904 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1905 break;
1906 }
1907 default:
1908 break;
1909 }
1910
1911 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1912 &port->mapbase, port->membase, port->irq,
1913 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1914
1915 /* reset the fifos (and setup the uart) */
1916 s3c24xx_serial_resetport(port, cfg);
1917
1918 return 0;
1919
1920 err:
1921 port->mapbase = 0;
1922 return ret;
1923 }
1924
1925 /* Device driver serial port probe */
1926
1927 static int probe_index;
1928
1929 static inline const struct s3c24xx_serial_drv_data *
s3c24xx_get_driver_data(struct platform_device * pdev)1930 s3c24xx_get_driver_data(struct platform_device *pdev)
1931 {
1932 if (dev_of_node(&pdev->dev))
1933 return of_device_get_match_data(&pdev->dev);
1934
1935 return (struct s3c24xx_serial_drv_data *)
1936 platform_get_device_id(pdev)->driver_data;
1937 }
1938
s3c24xx_serial_probe(struct platform_device * pdev)1939 static int s3c24xx_serial_probe(struct platform_device *pdev)
1940 {
1941 struct device_node *np = pdev->dev.of_node;
1942 struct s3c24xx_uart_port *ourport;
1943 int index = probe_index;
1944 int ret, prop = 0, fifosize_prop = 1;
1945
1946 if (np) {
1947 ret = of_alias_get_id(np, "serial");
1948 if (ret >= 0)
1949 index = ret;
1950 }
1951
1952 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1953 dev_err(&pdev->dev, "serial%d out of range\n", index);
1954 return -EINVAL;
1955 }
1956 ourport = &s3c24xx_serial_ports[index];
1957
1958 s3c24xx_serial_init_port_default(index);
1959
1960 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1961 if (!ourport->drv_data) {
1962 dev_err(&pdev->dev, "could not find driver data\n");
1963 return -ENODEV;
1964 }
1965
1966 ourport->baudclk = ERR_PTR(-EINVAL);
1967 ourport->info = &ourport->drv_data->info;
1968 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1969 dev_get_platdata(&pdev->dev) :
1970 &ourport->drv_data->def_cfg;
1971
1972 switch (ourport->info->type) {
1973 case TYPE_S3C6400:
1974 ourport->port.ops = &s3c64xx_serial_ops;
1975 break;
1976 case TYPE_APPLE_S5L:
1977 ourport->port.ops = &apple_s5l_serial_ops;
1978 break;
1979 }
1980
1981 ourport->port.iotype = ourport->info->iotype;
1982
1983 if (np) {
1984 fifosize_prop = of_property_read_u32(np, "samsung,uart-fifosize",
1985 &ourport->port.fifosize);
1986
1987 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
1988 switch (prop) {
1989 case 1:
1990 ourport->port.iotype = UPIO_MEM;
1991 break;
1992 case 4:
1993 ourport->port.iotype = UPIO_MEM32;
1994 break;
1995 default:
1996 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
1997 prop);
1998 return -EINVAL;
1999 }
2000 }
2001 }
2002
2003 if (fifosize_prop) {
2004 if (ourport->drv_data->fifosize[index])
2005 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2006 else if (ourport->info->fifosize)
2007 ourport->port.fifosize = ourport->info->fifosize;
2008 }
2009
2010 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2011
2012 /*
2013 * DMA transfers must be aligned at least to cache line size,
2014 * so find minimal transfer size suitable for DMA mode
2015 */
2016 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2017 dma_get_cache_alignment());
2018
2019 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2020
2021 ret = s3c24xx_serial_init_port(ourport, pdev);
2022 if (ret < 0)
2023 return ret;
2024
2025 if (!s3c24xx_uart_drv.state) {
2026 ret = uart_register_driver(&s3c24xx_uart_drv);
2027 if (ret < 0) {
2028 pr_err("Failed to register Samsung UART driver\n");
2029 return ret;
2030 }
2031 }
2032
2033 dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2034 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2035 platform_set_drvdata(pdev, &ourport->port);
2036
2037 /*
2038 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2039 * so that a potential re-enablement through the pm-callback overlaps
2040 * and keeps the clock enabled in this case.
2041 */
2042 clk_disable_unprepare(ourport->clk);
2043 if (!IS_ERR(ourport->baudclk))
2044 clk_disable_unprepare(ourport->baudclk);
2045
2046 probe_index++;
2047
2048 return 0;
2049 }
2050
s3c24xx_serial_remove(struct platform_device * dev)2051 static void s3c24xx_serial_remove(struct platform_device *dev)
2052 {
2053 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2054
2055 if (port)
2056 uart_remove_one_port(&s3c24xx_uart_drv, port);
2057
2058 uart_unregister_driver(&s3c24xx_uart_drv);
2059 }
2060
2061 /* UART power management code */
2062 #ifdef CONFIG_PM_SLEEP
s3c24xx_serial_suspend(struct device * dev)2063 static int s3c24xx_serial_suspend(struct device *dev)
2064 {
2065 struct uart_port *port = s3c24xx_dev_to_port(dev);
2066
2067 if (port)
2068 uart_suspend_port(&s3c24xx_uart_drv, port);
2069
2070 return 0;
2071 }
2072
s3c24xx_serial_resume(struct device * dev)2073 static int s3c24xx_serial_resume(struct device *dev)
2074 {
2075 struct uart_port *port = s3c24xx_dev_to_port(dev);
2076 struct s3c24xx_uart_port *ourport = to_ourport(port);
2077
2078 if (port) {
2079 clk_prepare_enable(ourport->clk);
2080 if (!IS_ERR(ourport->baudclk))
2081 clk_prepare_enable(ourport->baudclk);
2082 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2083 if (!IS_ERR(ourport->baudclk))
2084 clk_disable_unprepare(ourport->baudclk);
2085 clk_disable_unprepare(ourport->clk);
2086
2087 uart_resume_port(&s3c24xx_uart_drv, port);
2088 }
2089
2090 return 0;
2091 }
2092
s3c24xx_serial_resume_noirq(struct device * dev)2093 static int s3c24xx_serial_resume_noirq(struct device *dev)
2094 {
2095 struct uart_port *port = s3c24xx_dev_to_port(dev);
2096 struct s3c24xx_uart_port *ourport = to_ourport(port);
2097
2098 if (port) {
2099 /* restore IRQ mask */
2100 switch (ourport->info->type) {
2101 case TYPE_S3C6400: {
2102 u32 uintm = 0xf;
2103
2104 if (ourport->tx_enabled)
2105 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2106 if (ourport->rx_enabled)
2107 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2108 clk_prepare_enable(ourport->clk);
2109 if (!IS_ERR(ourport->baudclk))
2110 clk_prepare_enable(ourport->baudclk);
2111 wr_regl(port, S3C64XX_UINTM, uintm);
2112 if (!IS_ERR(ourport->baudclk))
2113 clk_disable_unprepare(ourport->baudclk);
2114 clk_disable_unprepare(ourport->clk);
2115 break;
2116 }
2117 case TYPE_APPLE_S5L: {
2118 u32 ucon;
2119 int ret;
2120
2121 ret = clk_prepare_enable(ourport->clk);
2122 if (ret) {
2123 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2124 return ret;
2125 }
2126 if (!IS_ERR(ourport->baudclk)) {
2127 ret = clk_prepare_enable(ourport->baudclk);
2128 if (ret) {
2129 dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2130 clk_disable_unprepare(ourport->clk);
2131 return ret;
2132 }
2133 }
2134
2135 ucon = rd_regl(port, S3C2410_UCON);
2136
2137 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2138 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2139 APPLE_S5L_UCON_RXTO_ENA_MSK |
2140 APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK);
2141
2142 if (ourport->tx_enabled)
2143 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2144 if (ourport->rx_enabled)
2145 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2146 APPLE_S5L_UCON_RXTO_ENA_MSK |
2147 APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK;
2148
2149 wr_regl(port, S3C2410_UCON, ucon);
2150
2151 if (!IS_ERR(ourport->baudclk))
2152 clk_disable_unprepare(ourport->baudclk);
2153 clk_disable_unprepare(ourport->clk);
2154 break;
2155 }
2156 default:
2157 break;
2158 }
2159 }
2160
2161 return 0;
2162 }
2163
2164 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2165 SET_SYSTEM_SLEEP_PM_OPS(s3c24xx_serial_suspend, s3c24xx_serial_resume)
2166 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, s3c24xx_serial_resume_noirq)
2167 };
2168 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
2169
2170 #else /* !CONFIG_PM_SLEEP */
2171
2172 #define SERIAL_SAMSUNG_PM_OPS NULL
2173 #endif /* CONFIG_PM_SLEEP */
2174
2175 /* Console code */
2176
2177 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2178
2179 static struct uart_port *cons_uart;
2180
2181 static bool
s3c24xx_serial_console_txrdy(struct uart_port * port,u32 ufcon)2182 s3c24xx_serial_console_txrdy(struct uart_port *port, u32 ufcon)
2183 {
2184 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2185 u32 ufstat, utrstat;
2186
2187 if (ufcon & S3C2410_UFCON_FIFOMODE) {
2188 /* fifo mode - check amount of data in fifo registers... */
2189
2190 ufstat = rd_regl(port, S3C2410_UFSTAT);
2191 return !(ufstat & info->tx_fifofull);
2192 }
2193
2194 /* in non-fifo mode, we go and use the tx buffer empty */
2195
2196 utrstat = rd_regl(port, S3C2410_UTRSTAT);
2197 return utrstat & S3C2410_UTRSTAT_TXE;
2198 }
2199
2200 static bool
s3c24xx_port_configured(u32 ucon)2201 s3c24xx_port_configured(u32 ucon)
2202 {
2203 /* consider the serial port configured if the tx/rx mode set */
2204 return (ucon & 0xf) != 0;
2205 }
2206
2207 #ifdef CONFIG_CONSOLE_POLL
2208 /*
2209 * Console polling routines for writing and reading from the uart while
2210 * in an interrupt or debug context.
2211 */
2212
s3c24xx_serial_get_poll_char(struct uart_port * port)2213 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2214 {
2215 const struct s3c24xx_uart_port *ourport = to_ourport(port);
2216 u32 ufstat;
2217
2218 ufstat = rd_regl(port, S3C2410_UFSTAT);
2219 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2220 return NO_POLL_CHAR;
2221
2222 return rd_reg(port, S3C2410_URXH);
2223 }
2224
s3c24xx_serial_put_poll_char(struct uart_port * port,unsigned char c)2225 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2226 unsigned char c)
2227 {
2228 u32 ufcon = rd_regl(port, S3C2410_UFCON);
2229 u32 ucon = rd_regl(port, S3C2410_UCON);
2230
2231 /* not possible to xmit on unconfigured port */
2232 if (!s3c24xx_port_configured(ucon))
2233 return;
2234
2235 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2236 cpu_relax();
2237 wr_reg(port, S3C2410_UTXH, c);
2238 }
2239
2240 #endif /* CONFIG_CONSOLE_POLL */
2241
2242 static void
s3c24xx_serial_console_putchar(struct uart_port * port,unsigned char ch)2243 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2244 {
2245 u32 ufcon = rd_regl(port, S3C2410_UFCON);
2246
2247 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2248 cpu_relax();
2249 wr_reg(port, S3C2410_UTXH, ch);
2250 }
2251
2252 static void
s3c24xx_serial_console_write(struct console * co,const char * s,unsigned int count)2253 s3c24xx_serial_console_write(struct console *co, const char *s,
2254 unsigned int count)
2255 {
2256 u32 ucon = rd_regl(cons_uart, S3C2410_UCON);
2257 unsigned long flags;
2258 bool locked = true;
2259
2260 /* not possible to xmit on unconfigured port */
2261 if (!s3c24xx_port_configured(ucon))
2262 return;
2263
2264 if (cons_uart->sysrq)
2265 locked = false;
2266 else if (oops_in_progress)
2267 locked = uart_port_trylock_irqsave(cons_uart, &flags);
2268 else
2269 uart_port_lock_irqsave(cons_uart, &flags);
2270
2271 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2272
2273 if (locked)
2274 uart_port_unlock_irqrestore(cons_uart, flags);
2275 }
2276
2277 /* Shouldn't be __init, as it can be instantiated from other module */
2278 static void
s3c24xx_serial_get_options(struct uart_port * port,int * baud,int * parity,int * bits)2279 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2280 int *parity, int *bits)
2281 {
2282 struct clk *clk;
2283 unsigned long rate;
2284 u32 ulcon, ucon, ubrdiv;
2285 char clk_name[MAX_CLK_NAME_LENGTH];
2286 u8 clk_sel;
2287
2288 ulcon = rd_regl(port, S3C2410_ULCON);
2289 ucon = rd_regl(port, S3C2410_UCON);
2290 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2291
2292 if (s3c24xx_port_configured(ucon)) {
2293 switch (ulcon & S3C2410_LCON_CSMASK) {
2294 case S3C2410_LCON_CS5:
2295 *bits = 5;
2296 break;
2297 case S3C2410_LCON_CS6:
2298 *bits = 6;
2299 break;
2300 case S3C2410_LCON_CS7:
2301 *bits = 7;
2302 break;
2303 case S3C2410_LCON_CS8:
2304 default:
2305 *bits = 8;
2306 break;
2307 }
2308
2309 switch (ulcon & S3C2410_LCON_PMASK) {
2310 case S3C2410_LCON_PEVEN:
2311 *parity = 'e';
2312 break;
2313
2314 case S3C2410_LCON_PODD:
2315 *parity = 'o';
2316 break;
2317
2318 case S3C2410_LCON_PNONE:
2319 default:
2320 *parity = 'n';
2321 }
2322
2323 /* now calculate the baud rate */
2324
2325 clk_sel = s3c24xx_serial_getsource(port);
2326 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2327
2328 clk = clk_get(port->dev, clk_name);
2329 if (!IS_ERR(clk))
2330 rate = clk_get_rate(clk);
2331 else
2332 rate = 1;
2333
2334 *baud = rate / (16 * (ubrdiv + 1));
2335 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2336 }
2337 }
2338
2339 /* Shouldn't be __init, as it can be instantiated from other module */
2340 static int
s3c24xx_serial_console_setup(struct console * co,char * options)2341 s3c24xx_serial_console_setup(struct console *co, char *options)
2342 {
2343 struct uart_port *port;
2344 int baud = 9600;
2345 int bits = 8;
2346 int parity = 'n';
2347 int flow = 'n';
2348
2349 /* is this a valid port */
2350
2351 if (co->index == -1 || co->index >= UART_NR)
2352 co->index = 0;
2353
2354 port = &s3c24xx_serial_ports[co->index].port;
2355
2356 /* is the port configured? */
2357
2358 if (port->mapbase == 0x0)
2359 return -ENODEV;
2360
2361 cons_uart = port;
2362
2363 /*
2364 * Check whether an invalid uart number has been specified, and
2365 * if so, search for the first available port that does have
2366 * console support.
2367 */
2368 if (options)
2369 uart_parse_options(options, &baud, &parity, &bits, &flow);
2370 else
2371 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2372
2373 dev_dbg(port->dev, "baud %d\n", baud);
2374
2375 return uart_set_options(port, co, baud, parity, bits, flow);
2376 }
2377
2378 static struct console s3c24xx_serial_console = {
2379 .name = S3C24XX_SERIAL_NAME,
2380 .device = uart_console_device,
2381 .flags = CON_PRINTBUFFER,
2382 .index = -1,
2383 .write = s3c24xx_serial_console_write,
2384 .setup = s3c24xx_serial_console_setup,
2385 .data = &s3c24xx_uart_drv,
2386 };
2387 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2388
2389 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2390 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2391 .info = {
2392 .name = "Samsung S3C6400 UART",
2393 .type = TYPE_S3C6400,
2394 .port_type = PORT_S3C6400,
2395 .iotype = UPIO_MEM,
2396 .fifosize = 64,
2397 .has_divslot = true,
2398 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2399 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2400 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2401 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2402 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2403 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2404 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2405 .num_clks = 4,
2406 .clksel_mask = S3C6400_UCON_CLKMASK,
2407 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2408 },
2409 .def_cfg = {
2410 .ucon = S3C2410_UCON_DEFAULT,
2411 .ufcon = S3C2410_UFCON_DEFAULT,
2412 },
2413 };
2414 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2415 #else
2416 #define S3C6400_SERIAL_DRV_DATA NULL
2417 #endif
2418
2419 #ifdef CONFIG_CPU_S5PV210
2420 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2421 .info = {
2422 .name = "Samsung S5PV210 UART",
2423 .type = TYPE_S3C6400,
2424 .port_type = PORT_S3C6400,
2425 .iotype = UPIO_MEM,
2426 .has_divslot = true,
2427 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2428 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2429 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2430 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2431 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2432 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2433 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2434 .num_clks = 2,
2435 .clksel_mask = S5PV210_UCON_CLKMASK,
2436 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2437 },
2438 .def_cfg = {
2439 .ucon = S5PV210_UCON_DEFAULT,
2440 .ufcon = S5PV210_UFCON_DEFAULT,
2441 },
2442 .fifosize = { 256, 64, 16, 16 },
2443 };
2444 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2445 #else
2446 #define S5PV210_SERIAL_DRV_DATA NULL
2447 #endif
2448
2449 #if defined(CONFIG_ARCH_EXYNOS)
2450 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2451 .info = { \
2452 .name = "Samsung Exynos UART", \
2453 .type = TYPE_S3C6400, \
2454 .port_type = PORT_S3C6400, \
2455 .iotype = UPIO_MEM, \
2456 .has_divslot = true, \
2457 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2458 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2459 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2460 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2461 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2462 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2463 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2464 .num_clks = 1, \
2465 .clksel_mask = 0, \
2466 .clksel_shift = 0, \
2467 }, \
2468 .def_cfg = { \
2469 .ucon = S5PV210_UCON_DEFAULT, \
2470 .ufcon = S5PV210_UFCON_DEFAULT, \
2471 .has_fracval = 1, \
2472 } \
2473
2474 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2475 EXYNOS_COMMON_SERIAL_DRV_DATA,
2476 .fifosize = { 256, 64, 16, 16 },
2477 };
2478
2479 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2480 EXYNOS_COMMON_SERIAL_DRV_DATA,
2481 .fifosize = { 64, 256, 16, 256 },
2482 };
2483
2484 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2485 EXYNOS_COMMON_SERIAL_DRV_DATA,
2486 .fifosize = { 256, 64, 64, 64 },
2487 };
2488
2489 static const struct s3c24xx_serial_drv_data exynos8895_serial_drv_data = {
2490 EXYNOS_COMMON_SERIAL_DRV_DATA,
2491 /* samsung,uart-fifosize must be specified in the device tree. */
2492 .fifosize = { 0 },
2493 };
2494
2495 static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
2496 .info = {
2497 .name = "Google GS101 UART",
2498 .type = TYPE_S3C6400,
2499 .port_type = PORT_S3C6400,
2500 .iotype = UPIO_MEM32,
2501 .has_divslot = true,
2502 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2503 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2504 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2505 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2506 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2507 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2508 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2509 .num_clks = 1,
2510 .clksel_mask = 0,
2511 .clksel_shift = 0,
2512 },
2513 .def_cfg = {
2514 .ucon = S5PV210_UCON_DEFAULT,
2515 .ufcon = S5PV210_UFCON_DEFAULT,
2516 .has_fracval = 1,
2517 },
2518 /* samsung,uart-fifosize must be specified in the device tree. */
2519 .fifosize = { 0 },
2520 };
2521
2522 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2523 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2524 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2525 #define EXYNOS8895_SERIAL_DRV_DATA (&exynos8895_serial_drv_data)
2526 #define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)
2527
2528 #else
2529 #define EXYNOS4210_SERIAL_DRV_DATA NULL
2530 #define EXYNOS5433_SERIAL_DRV_DATA NULL
2531 #define EXYNOS850_SERIAL_DRV_DATA NULL
2532 #define EXYNOS8895_SERIAL_DRV_DATA NULL
2533 #define GS101_SERIAL_DRV_DATA NULL
2534 #endif
2535
2536 #ifdef CONFIG_ARCH_APPLE
2537 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2538 .info = {
2539 .name = "Apple S5L UART",
2540 .type = TYPE_APPLE_S5L,
2541 .port_type = PORT_8250,
2542 .iotype = UPIO_MEM32,
2543 .fifosize = 16,
2544 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2545 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2546 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2547 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2548 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2549 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2550 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2551 .num_clks = 1,
2552 .clksel_mask = 0,
2553 .clksel_shift = 0,
2554 .ucon_mask = APPLE_S5L_UCON_MASK,
2555 },
2556 .def_cfg = {
2557 .ucon = APPLE_S5L_UCON_DEFAULT,
2558 .ufcon = S3C2410_UFCON_DEFAULT,
2559 },
2560 };
2561 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2562 #else
2563 #define S5L_SERIAL_DRV_DATA NULL
2564 #endif
2565
2566 #if defined(CONFIG_ARCH_ARTPEC)
2567 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2568 .info = {
2569 .name = "Axis ARTPEC-8 UART",
2570 .type = TYPE_S3C6400,
2571 .port_type = PORT_S3C6400,
2572 .iotype = UPIO_MEM,
2573 .fifosize = 64,
2574 .has_divslot = true,
2575 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2576 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2577 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2578 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2579 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2580 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2581 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2582 .num_clks = 1,
2583 .clksel_mask = 0,
2584 .clksel_shift = 0,
2585 },
2586 .def_cfg = {
2587 .ucon = S5PV210_UCON_DEFAULT,
2588 .ufcon = S5PV210_UFCON_DEFAULT,
2589 .has_fracval = 1,
2590 }
2591 };
2592 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2593 #else
2594 #define ARTPEC8_SERIAL_DRV_DATA (NULL)
2595 #endif
2596
2597 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2598 {
2599 .name = "s3c6400-uart",
2600 .driver_data = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2601 }, {
2602 .name = "s5pv210-uart",
2603 .driver_data = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2604 }, {
2605 .name = "exynos4210-uart",
2606 .driver_data = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2607 }, {
2608 .name = "exynos5433-uart",
2609 .driver_data = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2610 }, {
2611 .name = "s5l-uart",
2612 .driver_data = (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2613 }, {
2614 .name = "exynos850-uart",
2615 .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2616 }, {
2617 .name = "artpec8-uart",
2618 .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2619 }, {
2620 .name = "gs101-uart",
2621 .driver_data = (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
2622 }, {
2623 .name = "exynos8895-uart",
2624 .driver_data = (kernel_ulong_t)EXYNOS8895_SERIAL_DRV_DATA,
2625 },
2626 { },
2627 };
2628 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2629
2630 #ifdef CONFIG_OF
2631 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2632 { .compatible = "samsung,s3c6400-uart",
2633 .data = S3C6400_SERIAL_DRV_DATA },
2634 { .compatible = "samsung,s5pv210-uart",
2635 .data = S5PV210_SERIAL_DRV_DATA },
2636 { .compatible = "samsung,exynos4210-uart",
2637 .data = EXYNOS4210_SERIAL_DRV_DATA },
2638 { .compatible = "samsung,exynos5433-uart",
2639 .data = EXYNOS5433_SERIAL_DRV_DATA },
2640 { .compatible = "apple,s5l-uart",
2641 .data = S5L_SERIAL_DRV_DATA },
2642 { .compatible = "samsung,exynos850-uart",
2643 .data = EXYNOS850_SERIAL_DRV_DATA },
2644 { .compatible = "axis,artpec8-uart",
2645 .data = ARTPEC8_SERIAL_DRV_DATA },
2646 { .compatible = "google,gs101-uart",
2647 .data = GS101_SERIAL_DRV_DATA },
2648 { .compatible = "samsung,exynos8895-uart",
2649 .data = EXYNOS8895_SERIAL_DRV_DATA },
2650 {},
2651 };
2652 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2653 #endif
2654
2655 static struct platform_driver samsung_serial_driver = {
2656 .probe = s3c24xx_serial_probe,
2657 .remove = s3c24xx_serial_remove,
2658 .id_table = s3c24xx_serial_driver_ids,
2659 .driver = {
2660 .name = "samsung-uart",
2661 .pm = SERIAL_SAMSUNG_PM_OPS,
2662 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2663 },
2664 };
2665
samsung_serial_init(void)2666 static int __init samsung_serial_init(void)
2667 {
2668 int ret;
2669
2670 s3c24xx_serial_register_console();
2671
2672 ret = platform_driver_register(&samsung_serial_driver);
2673 if (ret) {
2674 s3c24xx_serial_unregister_console();
2675 return ret;
2676 }
2677
2678 return 0;
2679 }
2680
samsung_serial_exit(void)2681 static void __exit samsung_serial_exit(void)
2682 {
2683 platform_driver_unregister(&samsung_serial_driver);
2684 s3c24xx_serial_unregister_console();
2685 }
2686
2687 module_init(samsung_serial_init);
2688 module_exit(samsung_serial_exit);
2689
2690 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2691 /*
2692 * Early console.
2693 */
2694
wr_reg_barrier(const struct uart_port * port,u32 reg,u32 val)2695 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2696 {
2697 switch (port->iotype) {
2698 case UPIO_MEM:
2699 writeb(val, portaddr(port, reg));
2700 break;
2701 case UPIO_MEM32:
2702 writel(val, portaddr(port, reg));
2703 break;
2704 default:
2705 break;
2706 }
2707 }
2708
2709 struct samsung_early_console_data {
2710 u32 txfull_mask;
2711 u32 rxfifo_mask;
2712 };
2713
samsung_early_busyuart(const struct uart_port * port)2714 static void samsung_early_busyuart(const struct uart_port *port)
2715 {
2716 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2717 ;
2718 }
2719
samsung_early_busyuart_fifo(const struct uart_port * port)2720 static void samsung_early_busyuart_fifo(const struct uart_port *port)
2721 {
2722 const struct samsung_early_console_data *data = port->private_data;
2723
2724 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2725 ;
2726 }
2727
samsung_early_putc(struct uart_port * port,unsigned char c)2728 static void samsung_early_putc(struct uart_port *port, unsigned char c)
2729 {
2730 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2731 samsung_early_busyuart_fifo(port);
2732 else
2733 samsung_early_busyuart(port);
2734
2735 wr_reg_barrier(port, S3C2410_UTXH, c);
2736 }
2737
samsung_early_write(struct console * con,const char * s,unsigned int n)2738 static void samsung_early_write(struct console *con, const char *s,
2739 unsigned int n)
2740 {
2741 struct earlycon_device *dev = con->data;
2742
2743 uart_console_write(&dev->port, s, n, samsung_early_putc);
2744 }
2745
samsung_early_read(struct console * con,char * s,unsigned int n)2746 static int samsung_early_read(struct console *con, char *s, unsigned int n)
2747 {
2748 struct earlycon_device *dev = con->data;
2749 const struct samsung_early_console_data *data = dev->port.private_data;
2750 int num_read = 0;
2751 u32 ch, ufstat;
2752
2753 while (num_read < n) {
2754 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
2755 if (!(ufstat & data->rxfifo_mask))
2756 break;
2757 ch = rd_reg(&dev->port, S3C2410_URXH);
2758 if (ch == NO_POLL_CHAR)
2759 break;
2760
2761 s[num_read++] = ch;
2762 }
2763
2764 return num_read;
2765 }
2766
samsung_early_console_setup(struct earlycon_device * device,const char * opt)2767 static int __init samsung_early_console_setup(struct earlycon_device *device,
2768 const char *opt)
2769 {
2770 if (!device->port.membase)
2771 return -ENODEV;
2772
2773 device->con->write = samsung_early_write;
2774 device->con->read = samsung_early_read;
2775 return 0;
2776 }
2777
2778 /* S3C2410 */
2779 static struct samsung_early_console_data s3c2410_early_console_data = {
2780 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2781 .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
2782 };
2783
2784 /* S3C64xx */
2785 static struct samsung_early_console_data s3c2440_early_console_data = {
2786 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2787 .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
2788 };
2789
s3c2440_early_console_setup(struct earlycon_device * device,const char * opt)2790 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2791 const char *opt)
2792 {
2793 device->port.private_data = &s3c2440_early_console_data;
2794 return samsung_early_console_setup(device, opt);
2795 }
2796
2797 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2798 s3c2440_early_console_setup);
2799
2800 /* S5PV210, Exynos */
2801 static struct samsung_early_console_data s5pv210_early_console_data = {
2802 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2803 .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
2804 };
2805
s5pv210_early_console_setup(struct earlycon_device * device,const char * opt)2806 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2807 const char *opt)
2808 {
2809 device->port.private_data = &s5pv210_early_console_data;
2810 return samsung_early_console_setup(device, opt);
2811 }
2812
2813 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2814 s5pv210_early_console_setup);
2815 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2816 s5pv210_early_console_setup);
2817 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
2818 s5pv210_early_console_setup);
2819 OF_EARLYCON_DECLARE(exynos850, "samsung,exynos850-uart",
2820 s5pv210_early_console_setup);
2821
gs101_early_console_setup(struct earlycon_device * device,const char * opt)2822 static int __init gs101_early_console_setup(struct earlycon_device *device,
2823 const char *opt)
2824 {
2825 /* gs101 always expects MMIO32 register accesses. */
2826 device->port.iotype = UPIO_MEM32;
2827
2828 return s5pv210_early_console_setup(device, opt);
2829 }
2830
2831 OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup);
2832
2833 /* Apple S5L */
apple_s5l_early_console_setup(struct earlycon_device * device,const char * opt)2834 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
2835 const char *opt)
2836 {
2837 /* Apple A7-A11 requires MMIO32 register accesses. */
2838 device->port.iotype = UPIO_MEM32;
2839
2840 /* Close enough to S3C2410 for earlycon... */
2841 device->port.private_data = &s3c2410_early_console_data;
2842
2843 #ifdef CONFIG_ARM64
2844 /* ... but we need to override the existing fixmap entry as nGnRnE */
2845 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
2846 __pgprot(PROT_DEVICE_nGnRnE));
2847 #endif
2848 return samsung_early_console_setup(device, opt);
2849 }
2850
2851 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
2852 #endif
2853
2854 MODULE_ALIAS("platform:samsung-uart");
2855 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2856 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2857 MODULE_LICENSE("GPL v2");
2858