Searched refs:port_clock (Results 1 – 4 of 4) sorted by relevance
28 enum pipe pipe, int port_clock);
271 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()306 static u32 ddi_buf_phy_link_rate(int port_clock) in ddi_buf_phy_link_rate() argument308 switch (port_clock) { in ddi_buf_phy_link_rate()326 MISSING_CASE(port_clock); in ddi_buf_phy_link_rate()331 static int dp_phy_lane_stagger_delay(int port_clock) in dp_phy_lane_stagger_delay() argument350 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); in dp_phy_lane_stagger_delay()377 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()383 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()1162 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()1359 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); in icl_mg_phy_set_signal_levels()[all …]
174 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72, in intel_dp_mst_max_dpt_bpp()189 return intel_dp_link_bw_overhead(crtc_state->port_clock, in intel_dp_mst_bw_overhead()208 crtc_state->port_clock, in intel_dp_mst_compute_m_n()282 mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, in intel_dp_mtp_tu_compute_config()460 crtc_state->port_clock = max_link_config.rate; in mst_stream_compute_link_config()497 crtc_state->port_clock = max_link_config.rate; in mst_stream_dsc_compute_link_config()1237 crtc_state->port_clock, crtc_state->lane_count)) in intel_mst_reprobe_topology()1243 crtc_state->port_clock, crtc_state->lane_count); in intel_mst_reprobe_topology()
3281 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()