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Searched refs:port_clock (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_pmdemand.c173 enum pipe pipe, int port_clock) in intel_pmdemand_update_port_clock() argument
178 pmdemand_state->ddi_clocks[pipe] = port_clock; in intel_pmdemand_update_port_clock()
194 new_crtc_state->port_clock); in intel_pmdemand_update_max_ddiclk()
313 if (new_crtc_state->port_clock != old_crtc_state->port_clock) in intel_pmdemand_needs_update()
H A Dintel_alpm.c51 return SILENCE_PERIOD_TIME * intel_dp_link_symbol_clock(crtc_state->port_clock) / in get_silence_period_symbols()
58 if (crtc_state->port_clock < 540000) { in get_lfps_cycle_min_max_time()
79 return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 / in get_lfps_half_cycle_clocks()
108 int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock; in _lnl_compute_aux_less_wake_time()
H A Dintel_pmdemand.h28 enum pipe pipe, int port_clock);
H A Dintel_dp_mst.c172 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72, in intel_dp_mst_max_dpt_bpp()
187 return intel_dp_link_bw_overhead(crtc_state->port_clock, in intel_dp_mst_bw_overhead()
206 crtc_state->port_clock, in intel_dp_mst_compute_m_n()
280 mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, in intel_dp_mtp_tu_compute_config()
447 crtc_state->port_clock = limits->max_rate; in mst_stream_compute_link_config()
474 crtc_state->port_clock = limits->max_rate; in mst_stream_dsc_compute_link_config()
1145 crtc_state->port_clock, crtc_state->lane_count)) in intel_mst_reprobe_topology()
1151 crtc_state->port_clock, crtc_state->lane_count); in intel_mst_reprobe_topology()
H A Dintel_dp.c145 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr()
1594 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, in intel_dp_compute_rate() argument
1600 if (display->platform.g4x && port_clock == 268800) in intel_dp_compute_rate()
1601 port_clock = 270000; in intel_dp_compute_rate()
1607 intel_dp_rate_select(intel_dp, port_clock); in intel_dp_compute_rate()
1609 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
1795 pipe_config->port_clock = link_rate; in intel_dp_compute_link_config_wide()
2019 pipe_config->port_clock = link_rate; in dsc_compute_link_config()
2231 pipe_config->port_clock = limits->max_rate; in dsc_compute_compressed_bpp()
2748 return intel_dp_link_required(crtc_state->port_clock, crtc_state->lane_count, in intel_dp_config_required_rate()
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H A Dintel_tv.c1126 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1153 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); in intel_tv_get_config()
1219 pipe_config->port_clock = tv_mode->clock; in intel_tv_compute_config()
1227 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock); in intel_tv_compute_config()
H A Dintel_crt.c155 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_crt_get_config()
468 crtc_state->port_clock = 135000 * 2; in hsw_crt_compute_config()
H A Dintel_dvo.c182 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
H A Dintel_display.c3142 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
4091 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in intel_crtc_dotclock()
4094 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, in intel_crtc_dotclock()
4097 dotclock = pipe_config->port_clock; in intel_crtc_dotclock()
4733 crtc_state->port_clock = 0; in intel_modeset_pipe_config()
4764 if (!crtc_state->port_clock) in intel_modeset_pipe_config()
4765 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
5410 PIPE_CONF_CHECK_I(port_clock); in intel_pipe_config_compare()
H A Dintel_lvds.c154 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_lvds_get_config()
H A Dintel_display_types.h1197 int port_clock; member
H A Dvlv_dsi.c1193 pipe_config->port_clock = pclk; in intel_dsi_get_config()
H A Dicl_dsi.c1700 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; in gen11_dsi_compute_config()
H A Dintel_sdvo.c1751 dotclock = pipe_config->port_clock; in intel_sdvo_get_config()
H A Dintel_cdclk.c3191 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
H A Dintel_psr.c1364 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()