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Searched refs:port_clock (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c430 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_vboost_lvl()
431 crtc_state->port_clock == 810000)) in intel_c10_get_tx_vboost_lvl()
444 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_term_ctl()
445 crtc_state->port_clock == 810000)) in intel_c10_get_tx_term_ctl()
2061 bool is_dp, int port_clock, in intel_c10pll_calc_state_from_table() argument
2067 if (port_clock == tables[i]->clock) { in intel_c10pll_calc_state_from_table()
2092 crtc_state->port_clock, in intel_c10pll_calc_state()
2100 crtc_state->port_clock); in intel_c10pll_calc_state()
2253 if (crtc_state->port_clock < 25175 || crtc_state->port_clock > 600000) in intel_c20_compute_hdmi_tmds_pll()
2256 datarate = ((u64)crtc_state->port_clock * 1000) * 10; in intel_c20_compute_hdmi_tmds_pll()
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H A Dintel_ddi.c267 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
302 static u32 ddi_buf_phy_link_rate(int port_clock) in ddi_buf_phy_link_rate() argument
304 switch (port_clock) { in ddi_buf_phy_link_rate()
322 MISSING_CASE(port_clock); in ddi_buf_phy_link_rate()
327 static int dp_phy_lane_stagger_delay(int port_clock) in dp_phy_lane_stagger_delay() argument
346 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); in dp_phy_lane_stagger_delay()
373 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
379 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
1155 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
1352 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); in icl_mg_phy_set_signal_levels()
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H A Dintel_pmdemand.h28 enum pipe pipe, int port_clock);
H A Dintel_audio.c248 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
469 link_clk = crtc_state->port_clock; in calc_hblank_early_prog()
507 link_clk = crtc_state->port_clock; in calc_samples_room()
784 crtc_state->port_clock, in intel_audio_codec_enable()
1010 crtc_state->port_clock >= 540000 && in intel_audio_min_cdclk()
1037 min_cdclk = max(min_cdclk, crtc_state->port_clock); in intel_audio_min_cdclk()
H A Dintel_dp_mst.c172 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72, in intel_dp_mst_max_dpt_bpp()
216 crtc_state->port_clock, in intel_dp_mst_compute_m_n()
290 mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, in intel_dp_mtp_tu_compute_config()
447 crtc_state->port_clock = limits->max_rate; in mst_stream_compute_link_config()
511 crtc_state->port_clock = limits->max_rate; in mst_stream_dsc_compute_link_config()
1178 crtc_state->port_clock, crtc_state->lane_count)) in intel_mst_reprobe_topology()
1184 crtc_state->port_clock, crtc_state->lane_count); in intel_mst_reprobe_topology()
H A Dvlv_dsi.c1193 pipe_config->port_clock = pclk; in intel_dsi_get_config()
H A Dintel_psr.c1325 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()