1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* Copyright (C) 2025-2026 MediaTek Inc. */ 3 4 #ifndef __MT7925_NAN_H 5 #define __MT7925_NAN_H 6 7 #include <linux/if_ether.h> 8 #include <linux/types.h> 9 10 #include "../mt76_connac_mcu.h" 11 12 #define NAN_MAX_SOCIAL_CHANNELS 3 13 #define NAN_ANCHOR_MASTER_RANK_NUM 8 14 #define NAN_5G_LOW_DISC_CHANNEL 44 15 #define NAN_5G_HIGH_DISC_CHANNEL 149 16 #define NAN_MAX_MASTER_PREFERENCE 255 17 #define NAN_DEFAULT_DW_INTERVAL 1 18 #define NAN_DEFAULT_DISC_BCN_INTERVAL 100 19 #define NAN_TOTAL_DW 16 20 #define NAN_SUPPORTED_2G_FAW_CH_NUM 4 21 #define NAN_SUPPORTED_5G_FAW_CH_NUM 4 22 #define NAN_TIMELINE_MGMT_SIZE 2 23 #define NAN_TIMELINE_MGMT_CHNL_LIST_NUM \ 24 ((NAN_SUPPORTED_2G_FAW_CH_NUM + \ 25 NAN_SUPPORTED_5G_FAW_CH_NUM) / NAN_TIMELINE_MGMT_SIZE) 26 #define NAN_NUM_AVAIL_DB 2 27 #define NAN_NDC_ATTRIBUTE_ID_LENGTH 6 28 #define NAN_MAX_CONN_CFG 8 29 #define NAN_MAX_NDP_CXT 4 30 31 #define MT7925_NAN_CONF_MAX_SIZE \ 32 (sizeof(struct mt7925_nan_common_hdr) + \ 33 sizeof(struct mt7925_nan_master_preference_tlv) + \ 34 sizeof(struct mt7925_nan_dw_interval_tlv) + \ 35 sizeof(struct mt7925_nan_cluster_id_tlv) + \ 36 sizeof(struct mt7925_nan_sync_rssi_tlv)) 37 38 #define MT7925_NAN_AVAIL_MAX_SIZE \ 39 (sizeof(struct mt7925_nan_common_hdr) + \ 40 sizeof(struct mt7925_nan_avail_ctrl_tlv) + \ 41 sizeof(struct mt7925_nan_avail_entry_tlv)) 42 43 #define MT7925_NAN_PEER_MAX_SIZE \ 44 (sizeof(struct mt7925_nan_common_hdr) + \ 45 sizeof(struct mt7925_nan_sched_manage_peer_rec_tlv) + \ 46 sizeof(struct mt7925_nan_sched_update_peer_cap_tlv) + \ 47 sizeof(struct mt7925_nan_sched_update_crb_tlv)) 48 49 /* NAN Availability Attribute */ 50 #define NAN_AVAIL_ATTR_ID_OFFSET 0 51 #define NAN_AVAIL_ATTR_LEN_OFFSET 1 52 #define NAN_AVAIL_SEQ_ID_OFFSET 3 53 #define NAN_AVAIL_ATTR_CTRL_OFFSET 4 54 55 /* NAN Availability Attribute - Attribute Control Field */ 56 #define NAN_AVAIL_CTRL_MAPID GENMASK(3, 0) 57 #define NAN_AVAIL_CTRL_COMMIT_CHANGED BIT(4) 58 #define NAN_AVAIL_CTRL_POTN_CHANGED BIT(5) 59 #define NAN_AVAIL_CTRL_PUBLIC_AVAIL_CHANGED BIT(6) 60 #define NAN_AVAIL_CTRL_NDC_CHANGED BIT(7) 61 #define NAN_AVAIL_CTRL_CHECK_FOR_CHANGED GENMASK(7, 4) 62 63 #define UNII1_LOWER_BOUND 36 64 #define UNII1_UPPER_BOUND 50 65 #define UNII3_LOWER_BOUND 149 66 #define UNII3_UPPER_BOUND 165 67 68 enum nan_uni_cmd_tag { 69 NAN_UNI_CMD_SET_MASTER_PREFERENCE = 0, 70 NAN_UNI_CMD_ENABLE_REQUEST = 7, 71 NAN_UNI_CMD_DISABLE_REQUEST = 8, 72 NAN_UNI_CMD_UPDATE_AVAILABILITY = 9, 73 NAN_UNI_CMD_UPDATE_CRB = 10, 74 NAN_UNI_CMD_MANAGE_PEER_SCH_RECORD = 12, 75 NAN_UNI_CMD_MAP_STA_RECORD = 13, 76 NAN_UNI_CMD_UPDATE_AVAILABILITY_CTRL = 20, 77 NAN_UNI_CMD_UPDATE_PEER_CAPABILITY = 21, 78 NAN_UNI_CMD_CHANGE_NMI_ADDRESS = 24, 79 NAN_UNI_CMD_SET_DW_INTERVAL = 26, 80 NAN_UNI_CMD_SET_SYNC_RSSI = 39, 81 NAN_UNI_CMD_SET_CLUSTER_ID = 40, 82 NAN_UNI_CMD_KEY_MANAGEMENT = 53, 83 }; 84 85 enum nan_uni_event_tag { 86 NAN_UNI_EVENT_ID_DE_EVENT_IND = 19, 87 NAN_UNI_EVENT_REPORT_DW_END = 60, 88 }; 89 90 enum nan_disc_event_type { 91 NAN_EVENT_ID_DISC_MAC_ADDR = 0, 92 NAN_EVENT_ID_JOINED_CLUSTER = 2, 93 }; 94 95 /* NAN 4.0 Table 79. Device Capability attribute format, Supported Bands */ 96 enum nan_supported_bands { 97 NAN_SUPPORTED_BAND_ID_2P4G = 2, 98 NAN_SUPPORTED_BAND_ID_5G = 4, 99 NAN_PROPRIETARY_BAND_ID_6G = 6, 100 NAN_SUPPORTED_BAND_ID_6G = 7, 101 }; 102 103 enum nan_peer_supported_bands { 104 NAN_SUPPORTED_BN_2G = 0, 105 NAN_SUPPORTED_BN_5G_LOW, 106 NAN_SUPPORTED_BN_5G_HIGH, 107 NAN_SUPPORTED_BN_6G, 108 NAN_SUPPORTED_BN_NUM 109 }; 110 111 #define NAN_CH_CTRL_OP_CLASS GENMASK(15, 8) 112 #define NAN_CH_CTRL_PRIMARY_CH GENMASK(23, 16) 113 114 #define NAN_CRB_USE_DATA_PATH BIT(0) 115 #define NAN_CRB_AVAIL_6G_FORMAT GENMASK(2, 1) 116 117 struct mt7925_nan_social_ch_scan_params { 118 u8 dwell_time[NAN_MAX_SOCIAL_CHANNELS]; 119 __le16 scan_period[NAN_MAX_SOCIAL_CHANNELS]; 120 } __packed; 121 122 /* Firmware-reported NAN device information */ 123 struct nan_dev_info_evt { 124 u8 is_enabled; 125 u8 my_addr[ETH_ALEN]; 126 u8 en_fw_election; 127 __le32 nan_dev_role; 128 __le32 nan_dev_state; 129 u8 mst_preference; 130 u8 random_factor; 131 u8 cnt_hop; 132 u8 cluster_id[ETH_ALEN]; 133 u8 anchor_mst_addr[ETH_ALEN]; 134 u8 am_preference; 135 u8 am_random_factor; 136 u8 parent_mac[ETH_ALEN]; 137 u8 parent_am_preference; 138 u8 parent_am_factor; 139 __le32 ambtt; 140 __le32 tsf[2]; 141 u8 pn_igtk[6]; 142 u8 pn_bigtk[6]; 143 }; 144 145 /* Firmware NAN discovery window event */ 146 struct nan_rpt_dw_evt { 147 struct nan_dev_info_evt device_info; 148 __le32 expected_tsf_h; 149 __le32 expected_tsf_l; 150 __le32 actual_tsf_h; 151 __le32 actual_tsf_l; 152 __le16 channel; 153 __le16 dw_num; 154 }; 155 156 struct mt7925_nan_conf_dw { 157 u8 config_2dot4g_dw_band; 158 __le32 dw_2dot4g_interval_val; 159 160 u8 config_5g_dw_band; 161 __le32 dw_5g_interval_val; 162 } __packed; 163 164 struct mt7925_nan_enable_req_tlv { 165 __le16 tag; 166 __le16 len; 167 168 u8 master_pref; 169 __le16 cluster_low; 170 __le16 cluster_high; 171 172 u8 config_support_5g; 173 u8 support_5g_val; 174 175 u8 config_sid_beacon; 176 u8 sid_beacon_val; 177 178 u8 config_2dot4g_rssi_close; 179 u8 rssi_close_2dot4g_val; 180 u8 config_2dot4g_rssi_middle; 181 u8 rssi_middle_2dot4g_val; 182 183 u8 config_2dot4g_rssi_proximity; 184 u8 rssi_proximity_2dot4g_val; 185 u8 config_hop_count_limit; 186 u8 hop_count_limit_val; 187 188 u8 config_2dot4g_support; 189 u8 support_2dot4g_val; 190 191 u8 config_2dot4g_beacons; 192 u8 beacon_2dot4g_val; 193 194 u8 config_2dot4g_sdf; 195 u8 sdf_2dot4g_val; 196 197 u8 config_5g_beacons; 198 u8 beacon_5g_val; 199 200 u8 config_5g_sdf; 201 u8 sdf_5g_val; 202 203 u8 config_5g_rssi_close; 204 u8 rssi_close_5g_val; 205 206 u8 config_5g_rssi_middle; 207 u8 rssi_middle_5g_val; 208 209 u8 config_5g_rssi_close_proximity; 210 u8 rssi_close_proximity_5g_val; 211 212 u8 config_rssi_window_size; 213 u8 rssi_window_size_val; 214 215 u8 config_oui; 216 __le32 oui_val; 217 218 u8 config_intf_addr; 219 u8 intf_addr_val[ETH_ALEN]; 220 221 u8 config_cluster_attribute_val; 222 223 u8 config_scan_params; 224 struct mt7925_nan_social_ch_scan_params scan_params_val; 225 226 u8 config_random_factor_force; 227 u8 random_factor_force_val; 228 229 u8 config_hop_count_force; 230 u8 hop_count_force_val; 231 232 u8 config_24g_channel; 233 __le32 channel_24g_val; 234 235 u8 config_5g_channel; 236 __le32 channel_5g_val; 237 238 struct mt7925_nan_conf_dw config_dw; 239 240 u8 config_disc_mac_addr_randomization; 241 __le32 disc_mac_addr_rand_interval_sec; 242 243 u8 discovery_indication_cfg; 244 245 u8 config_subscribe_sid_beacon; 246 __le32 subscribe_sid_beacon_val; 247 248 u8 enable_log_slot_statistics; 249 } __packed __aligned(4); 250 251 struct mt7925_nan_common_hdr { 252 u8 reserved[4]; 253 }; 254 255 struct mt7925_nan_master_preference_tlv { 256 __le16 tag; 257 __le16 len; 258 u8 master_preference; 259 u8 reserved[3]; 260 } __packed __aligned(4); 261 262 struct mt7925_nan_dw_interval_tlv { 263 __le16 tag; 264 __le16 len; 265 u8 dw_interval; 266 u8 vendor_ioctl; 267 __le16 disc_bcn_interval; 268 } __packed __aligned(4); 269 270 struct mt7925_nan_cluster_id_tlv { 271 __le16 tag; 272 __le16 len; 273 u8 cluster_id[ETH_ALEN]; 274 u8 reserved[2]; 275 } __packed __aligned(4); 276 277 struct mt7925_nan_sync_rssi_tlv { 278 __le16 tag; 279 __le16 len; 280 s8 rssi_close_2g; 281 s8 rssi_middle_2g; 282 s8 rssi_close_5g; 283 s8 rssi_middle_5g; 284 } __packed __aligned(4); 285 286 struct mt7925_nan_de_event { 287 u8 event_type; 288 u8 cluster_id[ETH_ALEN]; 289 u8 anchor_master_rank[NAN_ANCHOR_MASTER_RANK_NUM]; 290 u8 own_nmi[ETH_ALEN]; 291 u8 master_nmi[ETH_ALEN]; 292 }; 293 294 struct mt7925_nan_nmi_addr_tlv { 295 __le16 tag; 296 __le16 len; 297 u8 nmi_addr[ETH_ALEN]; 298 } __packed __aligned(4); 299 300 struct mt7925_nan_avail_ctrl_tlv { 301 __le16 tag; 302 __le16 len; 303 __le16 avail_ctrl; 304 u8 seq_id; 305 u8 reserved[1]; 306 } __packed __aligned(4); 307 308 struct mt7925_nan_ch_timeline { 309 u8 is_valid; 310 u8 reserved[3]; 311 312 __le32 ch_info; 313 314 __le32 num; 315 __le32 avail_map[NAN_TOTAL_DW]; 316 }; 317 318 struct mt7925_nan_avail_entry_tlv { 319 __le16 tag; 320 __le16 len; 321 u8 map_id; 322 u8 is_cond_avail; 323 u8 timeline_idx; 324 u8 is_multi_map; 325 326 struct mt7925_nan_ch_timeline ch_list[NAN_TIMELINE_MGMT_CHNL_LIST_NUM]; 327 } __packed __aligned(4); 328 329 struct mt7925_nan_sched_manage_peer_rec_tlv { 330 __le16 tag; 331 __le16 len; 332 __le32 sch_idx; 333 u8 is_activate; 334 u8 nmi_addr[ETH_ALEN]; 335 u8 reserved[1]; 336 } __packed __aligned(4); 337 338 struct mt7925_nan_sched_update_peer_cap_tlv { 339 __le16 tag; 340 __le16 len; 341 __le32 sch_idx; 342 u8 supported_bands; 343 __le16 max_chnl_switch_time; 344 u8 peer_supported_bands; 345 } __packed __aligned(4); 346 347 struct mt7925_nan_sched_timeline { 348 u8 map_id; 349 u8 local_map_id; 350 u8 reserved[2]; 351 union { 352 __le32 avail_map[NAN_TOTAL_DW]; 353 u8 avail_block[NAN_TOTAL_DW * 4]; 354 }; 355 }; 356 357 struct mt7925_nan_sched_faw_ndc_timeline { 358 __le32 avail_map[NAN_TOTAL_DW]; 359 }; 360 361 struct mt7925_nan_sched_ndc_ctrl { 362 u8 is_valid; 363 u8 ndc_id[NAN_NDC_ATTRIBUTE_ID_LENGTH]; 364 u8 ndc_idx; 365 struct mt7925_nan_sched_timeline timeline[NAN_NUM_AVAIL_DB]; 366 }; 367 368 struct mt7925_nan_sched_update_crb_tlv { 369 __le16 tag; 370 __le16 len; 371 __le32 sch_idx; 372 u8 flags; 373 u8 is_use_ranging; 374 u8 reserved[2]; 375 struct mt7925_nan_sched_timeline comm_ranging_timeline[NAN_TIMELINE_MGMT_SIZE]; 376 struct mt7925_nan_sched_timeline comm_faw_timeline[NAN_TIMELINE_MGMT_SIZE]; 377 struct mt7925_nan_sched_ndc_ctrl comm_ndc_ctrl; 378 struct mt7925_nan_sched_faw_ndc_timeline faw_ndc_timeline[NAN_TIMELINE_MGMT_SIZE]; 379 } __packed __aligned(4); 380 381 struct mt7925_nan_sched_map_sta_rec_tlv { 382 __le16 tag; 383 __le16 len; 384 u8 nmi_addr[ETH_ALEN]; 385 u8 sta_rec_idx; 386 u8 ndp_ctx_id; 387 388 __le32 role_idx; 389 u8 ndi_addr[ETH_ALEN]; 390 u8 reserved[2]; 391 } __packed __aligned(4); 392 393 int mt7925_nan_enable(struct ieee80211_vif *vif, 394 struct mt792x_dev *dev, 395 struct cfg80211_nan_conf *conf); 396 397 int mt7925_nan_disable(struct ieee80211_vif *vif, 398 struct mt792x_dev *dev); 399 400 int mt7925_nan_change_configure(struct ieee80211_vif *vif, 401 struct mt792x_dev *dev, 402 struct cfg80211_nan_conf *conf); 403 404 void mt7925_nan_mcu_event(struct mt792x_dev *dev, struct sk_buff *skb); 405 406 int mt7925_nan_set_nmi_addr(struct mt792x_dev *dev, const u8 *addr); 407 408 void mt7925_nan_local_sched_changed(struct mt792x_dev *dev, 409 struct ieee80211_vif *vif); 410 411 int mt792x_nan_set_peer_schedule(struct mt792x_dev *dev, 412 struct ieee80211_sta *sta); 413 414 int mt792x_nan_set_peer_rec(struct mt76_dev *mdev, 415 struct ieee80211_sta *sta); 416 417 int mt792x_nan_map_sta_rec(struct mt76_dev *mdev, 418 struct ieee80211_vif *vif, 419 struct ieee80211_sta *sta); 420 421 #endif 422