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Searched refs:pll_enable (Results 1 – 8 of 8) sorted by relevance

/linux/arch/arm/mach-tegra/
H A Dsleep-tegra20.S67 .macro pll_enable, rd, r_car_base, pll_base, test_mask macro
205 pll_enable r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
206 pll_enable r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
207 pll_enable r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
H A Dsleep-tegra30.S132 .macro pll_enable, rd, r_car_base, pll_base, pll_misc, test_mask macro
396 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0, PLLM_STORE_MASK
397 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK
398 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK
407 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC, PLLM_STORE_MASK
408 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK
411 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC, PLLP_STORE_MASK
412 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC, PLLA_STORE_MASK
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-pll.c157 static int pll_enable(struct clk_hw *hw) in pll_enable() function
180 .enable = pll_enable,
410 .enable = pll_enable,
/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-core.c369 if (priv->pll_enable) { in mcp251xfd_chip_sleep()
480 if (priv->pll_enable) { in mcp251xfd_chip_clock_init()
1858 priv->pll_enable ? '+' : '-', in mcp251xfd_register_done()
2012 bool pll_enable = false; in mcp251xfd_probe() local
2064 pll_enable = true; in mcp251xfd_probe()
2080 if (pll_enable) in mcp251xfd_probe()
2095 priv->pll_enable = pll_enable; in mcp251xfd_probe()
2130 if (priv->pll_enable) in mcp251xfd_probe()
H A Dmcp251xfd.h667 bool pll_enable; member
/linux/sound/soc/codecs/
H A Dtas2552.c164 u8 pll_enable; in tas2552_setup_pll() local
174 pll_enable = snd_soc_component_read(component, TAS2552_CFG_2) & TAS2552_PLL_ENABLE; in tas2552_setup_pll()
232 pll_enable); in tas2552_setup_pll()
/linux/drivers/clk/
H A Dclk-stm32h7.c705 static int pll_enable(struct clk_hw *hw) in pll_enable() function
775 .enable = pll_enable,
870 pll_enable(hwp); in odf_divider_set_rate()
900 pll_enable(hwp); in odf_gate_enable()
923 pll_enable(hwp); in odf_gate_disable()
/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c778 static int pll_enable(struct clk_hw *hw) in pll_enable() function
890 .enable = pll_enable,