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Searched refs:pll_clks (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/clk/mmp/
H A Dclk-of-mmp2.c105 static struct mmp_param_pll_clk pll_clks[] = { variable
192 mmp_register_pll_clks(unit, pll_clks, in mmp2_main_clk_init()
194 ARRAY_SIZE(pll_clks)); in mmp2_main_clk_init()
/linux/drivers/clk/samsung/
H A Dclk.c337 if (cmu->pll_clks) in samsung_cmu_register_clocks()
338 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks); in samsung_cmu_register_clocks()
H A Dclk-exynos5260.c401 .pll_clks = egl_pll_clks,
653 .pll_clks = g3d_pll_clks,
971 .pll_clks = kfc_pll_clks,
1174 .pll_clks = mif_pll_clks,
1834 .pll_clks = top_pll_clks,
H A Dclk-exynos850.c564 .pll_clks = top_pll_clks,
985 .pll_clks = aud_pll_clks,
1290 .pll_clks = cpucl0_pll_clks,
1445 .pll_clks = cpucl1_pll_clks,
1553 .pll_clks = g3d_pll_clks,
H A Dclk-exynos7885.c344 .pll_clks = top_pll_clks,
799 .pll_clks = fsys_pll_clks,
H A Dclk-exynos5410.c258 .pll_clks = exynos5410_plls,
H A Dclk-fsd.c295 .pll_clks = cmu_pll_clks,
1533 .pll_clks = mfc_pll_clks,
1737 .pll_clks = cam_csi_pll_clks,
H A Dclk.h343 const struct samsung_pll_clock *pll_clks; member
H A Dclk-exynos3250.c803 .pll_clks = exynos3250_plls,
925 .pll_clks = exynos3250_dmc_plls,
H A Dclk-exynos5433.c812 .pll_clks = top_pll_clks,
895 .pll_clks = cpif_pll_clks,
1547 .pll_clks = mif_pll_clks,
2901 .pll_clks = disp_pll_clks,
3358 .pll_clks = g3d_pll_clks,
3708 .pll_clks = apollo_pll_clks,
3952 .pll_clks = atlas_pll_clks,
H A Dclk-exynosautov9.c946 .pll_clks = top_pll_clks,
1512 .pll_clks = fsys1_pll_clks,
H A Dclk-exynosautov920.c980 .pll_clks = top_pll_clks,
H A Dclk-exynos7.c187 .pll_clks = topc_pll_clks,
H A Dclk-gs101.c1431 .pll_clks = cmu_top_pll_clks,
2373 .pll_clks = cmu_hsi0_pll_clks,
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-pll.c474 struct sg2042_pll_clock pll_clks[], in sg2042_clk_register_plls() argument
482 pll = &pll_clks[i]; in sg2042_clk_register_plls()
/linux/drivers/phy/cadence/
H A Dphy-cadence-sierra.c407 struct clk *pll_clks[SIERRA_NUM_CMN_PLLC]; member
787 sp->pll_clks[clk_index] = devm_clk_hw_get_clk(dev, &mux->hw, in cdns_sierra_pll_mux_register()
1200 ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); in cdns_sierra_phy_enable_clocks()
1204 ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]); in cdns_sierra_phy_enable_clocks()
1211 clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); in cdns_sierra_phy_enable_clocks()
1218 clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]); in cdns_sierra_phy_disable_clocks()
1219 clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); in cdns_sierra_phy_disable_clocks()