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Searched refs:pll1 (Results 1 – 21 of 21) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,clkgen-pll.txt15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
/linux/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
292 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
299 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
315 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
/linux/drivers/clk/spacemit/
H A Dccu-k1.c57 CCU_PLL_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK,
64 CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1);
65 CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1);
66 CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1);
67 CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1);
68 CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1);
69 CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1);
70 CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1,
72 CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1);
73 CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1);
[all …]
/linux/drivers/clk/
H A Dclk-ep93xx.c599 struct clk_hw *hw, *pll1; in ep93xx_plls_init() local
610 pll1 = devm_clk_hw_register_fixed_rate_parent_data(dev, "pll1", &xtali, in ep93xx_plls_init()
612 if (IS_ERR(pll1)) in ep93xx_plls_init()
613 return PTR_ERR(pll1); in ep93xx_plls_init()
615 priv->fixed[EP93XX_CLK_PLL1] = pll1; in ep93xx_plls_init()
622 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "fclk", pll1, 0, 1, clk_f_div); in ep93xx_plls_init()
628 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "hclk", pll1, 0, 1, clk_h_div); in ep93xx_plls_init()
H A Dclk-k210.c1002 struct k210_pll pll1; in k210_clk_early_init() local
1008 k210_init_pll(regs, K210_PLL1, &pll1); in k210_clk_early_init()
1009 k210_pll_enable_hw(regs, &pll1); in k210_clk_early_init()
/linux/arch/arm/boot/dts/st/
H A Dstih410-clock.dtsi101 clk_s_c0_pll1: clk-s-c0-pll1 {
103 compatible = "st,clkgen-pll1-c0";
H A Dstih418-clock.dtsi101 clk_s_c0_pll1: clk-s-c0-pll1 {
103 compatible = "st,clkgen-pll1-c0";
H A Dste-nomadik-stn8815.dtsi219 pll1: pll1@0 { label
230 clocks = <&pll1>;
/linux/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra72x.dtsi72 reg-names = "dss", "pll1_clkctrl", "pll1";
H A Ddra74x.dtsi138 reg-names = "dss", "pll1_clkctrl", "pll1",
/linux/arch/arm/boot/dts/marvell/
H A Ddove-cubox.dts101 /* connect xtal input as source of pll0 and pll1 */
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,dra7-dss.txt24 'pll1', 'pll2_clkctrl', 'pll2'
/linux/arch/arm64/boot/dts/sprd/
H A Dums512.dtsi280 pll1: clock-controller@0 { label
856 assigned-clock-parents = <&pll1 CLK_RPLL>;
868 assigned-clock-parents = <&pll1 CLK_RPLL>;
/linux/drivers/phy/ti/
H A DKconfig49 three clock selects (pll0, pll1, dig) and resets for each of the
/linux/Documentation/translations/zh_CN/core-api/
H A Dprintk-formats.rst525 %pC pll1
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi696 pll1: clock-controller@21a000 { label
697 compatible = "ti,da850-pll1";
/linux/Documentation/core-api/
H A Dprintk-formats.rst580 %pC pll1