| /linux/drivers/clk/mediatek/ |
| H A D | clk-pll.c | 36 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
38 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; in mtk_pll_is_prepared()
43 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_fenc_is_prepared() local
45 return !!(readl(pll->fenc_addr) & BIT(pll->data->fenc_sta_bit)); in mtk_pll_fenc_is_prepared()
48 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
51 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
58 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; in __mtk_pll_recalc_rate()
75 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) in __mtk_pll_tuner_enable() argument
79 if (pll->tuner_en_addr) { in __mtk_pll_tuner_enable()
80 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); in __mtk_pll_tuner_enable()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-pll.c | 276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) in clk_pll_enable_lock() argument
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
286 val = pll_readl_misc(pll); in clk_pll_enable_lock()
287 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
288 pll_writel_misc(val, pll); in clk_pll_enable_lock()
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) in clk_pll_wait_for_lock() argument
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
298 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
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| /linux/drivers/video/fbdev/aty/ |
| H A D | mach64_ct.c | 18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
118 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) in aty_dsp_gt() argument
125 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; in aty_dsp_gt()
126 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
128 ras_multiplier = pll->xclkmaxrasdelay; in aty_dsp_gt()
134 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ in aty_dsp_gt()
140 if (pll->xres != 0) { in aty_dsp_gt()
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| /linux/drivers/clk/sprd/ |
| H A D | pll.c | 18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
28 ((pwidth(pll, member)) ? \
29 GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \
30 pshift(pll, member)) : 0)
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| /linux/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 61 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
63 u32 val = readl_relaxed(pll->base) & pll->power_bit; in clk_pllv3_wait_lock()
66 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) in clk_pllv3_wait_lock()
69 return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, in clk_pllv3_wait_lock()
75 struct clk_pllv3 *pll = to_clk_pllv3(hw); in clk_pllv3_prepare() local
78 val = readl_relaxed(pll->base); in clk_pllv3_prepare()
79 if (pll->powerup_set) in clk_pllv3_prepare()
80 val |= pll->power_bit; in clk_pllv3_prepare()
82 val &= ~pll->power_bit; in clk_pllv3_prepare()
83 writel_relaxed(val, pll->base); in clk_pllv3_prepare()
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| H A D | clk-pllv4.c | 60 static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll) in clk_pllv4_wait_lock() argument
64 return readl_poll_timeout(pll->base + PLL_CSR_OFFSET, in clk_pllv4_wait_lock()
70 struct clk_pllv4 *pll = to_clk_pllv4(hw); in clk_pllv4_is_prepared() local
72 if (readl_relaxed(pll->base) & PLL_EN) in clk_pllv4_is_prepared()
81 struct clk_pllv4 *pll = to_clk_pllv4(hw); in clk_pllv4_recalc_rate() local
85 mult = readl_relaxed(pll->base + pll->cfg_offset); in clk_pllv4_recalc_rate()
89 mfn = readl_relaxed(pll->base + pll->num_offset); in clk_pllv4_recalc_rate()
90 mfd = readl_relaxed(pll->base + pll->denom_offset); in clk_pllv4_recalc_rate()
101 struct clk_pllv4 *pll = to_clk_pllv4(hw); in clk_pllv4_determine_rate() local
109 if (pll->use_mult_range) { in clk_pllv4_determine_rate()
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| H A D | clk-fracn-gppll.c | 127 imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate) in imx_get_pll_settings() argument
129 const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; in imx_get_pll_settings()
132 for (i = 0; i < pll->rate_count; i++) in imx_get_pll_settings()
142 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); in clk_fracn_gppll_determine_rate() local
143 const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; in clk_fracn_gppll_determine_rate()
147 for (i = 0; i < pll->rate_count; i++) in clk_fracn_gppll_determine_rate()
155 req->rate = rate_table[pll->rate_count - 1].rate; in clk_fracn_gppll_determine_rate()
162 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); in clk_fracn_gppll_recalc_rate() local
163 const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; in clk_fracn_gppll_recalc_rate()
170 pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR); in clk_fracn_gppll_recalc_rate()
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| H A D | clk-pll14xx.c | 94 struct clk_pll14xx *pll, unsigned long rate) in imx_get_pll_settings() argument
96 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; in imx_get_pll_settings()
99 for (i = 0; i < pll->rate_count; i++) in imx_get_pll_settings()
106 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, in pll14xx_calc_rate() argument
131 static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate, in imx_pll14xx_calc_settings() argument
152 tt = imx_get_pll_settings(pll, rate); in imx_pll14xx_calc_settings()
155 clk_hw_get_name(&pll->hw), prate, rate); in imx_pll14xx_calc_settings()
164 pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); in imx_pll14xx_calc_settings()
168 pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); in imx_pll14xx_calc_settings()
171 rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); in imx_pll14xx_calc_settings()
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| /linux/drivers/clk/bcm/ |
| H A D | clk-iproc-pll.c | 75 struct iproc_pll *pll; member
118 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) in pll_get_rate_index() argument
122 for (i = 0; i < pll->num_vco_entries; i++) in pll_get_rate_index()
123 if (target_rate == pll->vco_param[i].rate) in pll_get_rate_index()
126 if (i >= pll->num_vco_entries) in pll_get_rate_index()
147 static int pll_wait_for_lock(struct iproc_pll *pll) in pll_wait_for_lock() argument
150 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_wait_for_lock()
153 u32 val = readl(pll->status_base + ctrl->status.offset); in pll_wait_for_lock()
163 static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, in iproc_pll_write() argument
166 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_write()
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| H A D | clk-iproc-armpll.c | 66 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
106 static int __get_mdiv(struct iproc_arm_pll *pll) in __get_mdiv() argument
112 fid = __get_fid(pll); in __get_mdiv()
121 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); in __get_mdiv()
128 val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET); in __get_mdiv()
141 static unsigned int __get_ndiv(struct iproc_arm_pll *pll) in __get_ndiv() argument
146 val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET); in __get_ndiv()
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| /linux/drivers/clk/qcom/ |
| H A D | clk-pll.c | 26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
67 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
71 regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_disable()
76 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); in clk_pll_disable()
82 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
87 regmap_read(pll->clkr.regmap, pll->l_reg, &l); in clk_pll_recalc_rate()
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| /linux/drivers/clk/visconti/ |
| H A D | pll.c | 56 static void visconti_pll_get_params(struct visconti_pll *pll, in visconti_pll_get_params() argument
61 val = readl(pll->pll_base + PLL_FRACMODE_REG); in visconti_pll_get_params()
66 rate_table->fracin = readl(pll->pll_base + PLL_FRACIN_REG) & PLL_FRACIN_MASK; in visconti_pll_get_params()
67 rate_table->intin = readl(pll->pll_base + PLL_INTIN_REG) & PLL_INTIN_MASK; in visconti_pll_get_params()
68 rate_table->refdiv = readl(pll->pll_base + PLL_REFDIV_REG) & PLL_REFDIV_MASK; in visconti_pll_get_params()
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG); in visconti_pll_get_params()
75 static const struct visconti_pll_rate_table *visconti_get_pll_settings(struct visconti_pll *pll, in visconti_get_pll_settings() argument
78 const struct visconti_pll_rate_table *rate_table = pll->rate_table; in visconti_get_pll_settings()
81 for (i = 0; i < pll->rate_count; i++) in visconti_get_pll_settings()
88 static unsigned long visconti_get_pll_rate_from_data(struct visconti_pll *pll, in visconti_get_pll_rate_from_data() argument
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| /linux/drivers/clk/at91/ |
| H A D | clk-pll.c | 57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
58 struct regmap *regmap = pll->regmap; in clk_pll_prepare()
59 const struct clk_pll_layout *layout = pll->layout; in clk_pll_prepare()
61 pll->characteristics; in clk_pll_prepare()
62 u8 id = pll->id; in clk_pll_prepare()
77 (div == pll->div && mul == pll->mul)) in clk_pll_prepare()
81 out = characteristics->out[pll->range]; in clk_pll_prepare()
85 characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id)); in clk_pll_prepare()
88 pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) | in clk_pll_prepare()
90 ((pll->mul & layout->mul_mask) << layout->mul_shift)); in clk_pll_prepare()
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_determine_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_determine_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_determine_rate()
91 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_pll_wait_lock() argument
93 struct regmap *grf = pll->ctx->grf; in rockchip_pll_wait_lock()
97 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, in rockchip_pll_wait_lock()
98 val & BIT(pll->lock_shift), 0, 1000); in rockchip_pll_wait_lock()
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-cv18xx-pll.c | 36 struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); in ipll_recalc_rate() local
39 value = readl(pll->common.base + pll->pll_reg); in ipll_recalc_rate()
91 struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); in ipll_determine_rate() local
93 return ipll_find_rate(pll->pll_limit, req->best_parent_rate, in ipll_determine_rate()
135 struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); in ipll_set_rate() local
137 ipll_find_rate(pll->pll_limit, parent_rate, &rate, &detected); in ipll_set_rate()
140 pll->pll_limit, &detected); in ipll_set_rate()
142 spin_lock_irqsave(pll->common.lock, flags); in ipll_set_rate()
144 regval = readl(pll->common.base + pll->pll_reg); in ipll_set_rate()
147 writel(regval, pll->common.base + pll->pll_reg); in ipll_set_rate()
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| /linux/drivers/clk/samsung/ |
| H A D | clk-pll.c | 37 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
39 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
42 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
53 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_determine_rate() local
54 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_determine_rate()
58 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_determine_rate()
73 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, in samsung_pll_lock_wait() argument
91 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, in samsung_pll_lock_wait()
95 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); in samsung_pll_lock_wait()
102 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable() local
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| /linux/drivers/clk/pistachio/ |
| H A D | clk-pll.c | 78 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) in pll_readl() argument
80 return readl(pll->base + reg); in pll_readl()
83 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) in pll_writel() argument
85 writel(val, pll->base + reg); in pll_writel()
88 static inline void pll_lock(struct pistachio_clk_pll *pll) in pll_lock() argument
90 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) in pll_lock()
107 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_get_mode() local
110 val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD; in pll_frac_get_mode()
116 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_set_mode() local
119 val = pll_readl(pll, PLL_CTRL3); in pll_frac_set_mode()
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| /linux/drivers/clk/baikal-t1/ |
| H A D | ccu-pll.c | 88 static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk, in ccu_pll_reset() argument
97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
100 return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val, in ccu_pll_reset()
107 struct ccu_pll *pll = to_ccu_pll(hw); in ccu_pll_enable() local
117 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_enable()
121 spin_lock_irqsave(&pll->lock, flags); in ccu_pll_enable()
122 regmap_write(pll->sys_regs, pll->reg_ctl, val | CCU_PLL_CTL_EN); in ccu_pll_enable()
123 ret = ccu_pll_reset(pll, clk_hw_get_rate(parent_hw), in ccu_pll_enable()
125 spin_unlock_irqrestore(&pll->lock, flags); in ccu_pll_enable()
134 struct ccu_pll *pll = to_ccu_pll(hw); in ccu_pll_disable() local
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| /linux/drivers/gpu/drm/sprd/ |
| H A D | megacores_pll.c | 30 static int dphy_calc_pll_param(struct dphy_pll *pll) in dphy_calc_pll_param() argument
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
42 if (pll->potential_fvco >= VCO_BAND_LOW && in dphy_calc_pll_param()
43 pll->potential_fvco <= VCO_BAND_HIGH) { in dphy_calc_pll_param()
44 pll->fvco = pll->potential_fvco; in dphy_calc_pll_param()
45 pll->out_sel = BIT(i); in dphy_calc_pll_param()
48 pll->potential_fvco <<= 1; in dphy_calc_pll_param()
50 if (pll->fvco == 0) in dphy_calc_pll_param()
53 if (pll->fvco >= VCO_BAND_LOW && pll->fvco <= VCO_BAND_MID) { in dphy_calc_pll_param()
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| /linux/drivers/clk/mmp/ |
| H A D | clk-pll.c | 31 struct mmp_clk_pll *pll = to_clk_mmp_pll(hw); in mmp_clk_pll_is_enabled() local
34 val = readl_relaxed(pll->enable_reg); in mmp_clk_pll_is_enabled()
35 if ((val & pll->enable) == pll->enable) in mmp_clk_pll_is_enabled()
39 if (pll->default_rate > 0) in mmp_clk_pll_is_enabled()
48 struct mmp_clk_pll *pll = to_clk_mmp_pll(hw); in mmp_clk_pll_recalc_rate() local
53 val = readl_relaxed(pll->enable_reg); in mmp_clk_pll_recalc_rate()
54 if ((val & pll->enable) != pll->enable) in mmp_clk_pll_recalc_rate()
55 return pll->default_rate; in mmp_clk_pll_recalc_rate()
57 if (pll->reg) { in mmp_clk_pll_recalc_rate()
58 val = readl_relaxed(pll->reg); in mmp_clk_pll_recalc_rate()
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| /linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | hdmi_pll.c | 23 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) in hdmi_pll_dump() argument
26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
41 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_enable() local
42 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable()
45 r = pm_runtime_get_sync(&pll->pdev->dev); in hdmi_pll_enable()
59 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_disable() local
60 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable()
67 r = pm_runtime_put_sync(&pll->pdev->dev); in hdmi_pll_disable()
132 struct dss_pll *pll = &hpll->pll; in hdmi_init_pll_data() local
142 pll->name = "hdmi"; in hdmi_init_pll_data()
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| H A D | video-pll.c | 18 struct dss_pll pll; member
54 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
56 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable()
59 r = dss_runtime_get(pll->dss); in dss_video_pll_enable()
63 dss_ctrl_pll_enable(pll, true); in dss_video_pll_enable()
67 r = dss_pll_wait_reset_done(pll); in dss_video_pll_enable()
77 dss_ctrl_pll_enable(pll, false); in dss_video_pll_enable()
78 dss_runtime_put(pll->dss); in dss_video_pll_enable()
83 static void dss_video_pll_disable(struct dss_pll *pll) in dss_video_pll_disable() argument
85 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_disable()
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| /linux/drivers/clk/st/ |
| H A D | clkgen-pll.c | 230 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_locked() local
231 u32 locked = CLKGEN_READ(pll, locked_status); in clkgen_pll_is_locked()
238 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_enabled() local
239 u32 poweroff = CLKGEN_READ(pll, pdn_status); in clkgen_pll_is_enabled()
245 struct clkgen_pll *pll = to_clkgen_pll(hw); in __clkgen_pll_enable() local
246 void __iomem *base = pll->regs_base; in __clkgen_pll_enable()
247 struct clkgen_field *field = &pll->data->locked_status; in __clkgen_pll_enable()
254 CLKGEN_WRITE(pll, pdn_ctrl, 0); in __clkgen_pll_enable()
260 if (pll->data->switch2pll_en) in __clkgen_pll_enable()
261 CLKGEN_WRITE(pll, switch2pll, 0); in __clkgen_pll_enable()
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| /linux/drivers/clk/x86/ |
| H A D | clk-cgu-pll.c | 42 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_recalc_rate() local
45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
46 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
47 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
49 if (pll->type == TYPE_LJPLL) in lgm_pll_recalc_rate()
57 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_is_enabled() local
60 ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1); in lgm_pll_is_enabled()
67 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_enable() local
71 lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1); in lgm_pll_enable()
72 ret = regmap_read_poll_timeout_atomic(pll->membase, pll->reg, in lgm_pll_enable()
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| /linux/arch/mips/ath79/ |
| H A D | clock.c | 99 u32 pll; in ar71xx_clocks_init() local
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
107 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
110 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
113 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_clocks_init()
116 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_clocks_init()
127 u32 pll; in ar724x_clocks_init() local
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
133 mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); in ar724x_clocks_init()
134 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; in ar724x_clocks_init()
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