Home
last modified time | relevance | path

Searched refs:pixelclock (Results 1 – 25 of 63) sorted by relevance

123

/linux/drivers/gpu/drm/panel/
H A Dpanel-simple.c826 .pixelclock = { 29930000, 33260000, 36590000 },
867 .pixelclock = { 34500000, 39600000, 50400000 },
897 .pixelclock = { 26400000, 33300000, 46800000 },
1003 .pixelclock = { 33300000, 34209000, 45000000 },
1103 .pixelclock = { 60000000, 74400000, 90000000 },
1127 .pixelclock = { 134000000, 141200000, 149000000 },
1157 .pixelclock = { 137000000, 141000000, 146000000 },
1212 .pixelclock = { 120000000, 144000000, 175000000 },
1242 .pixelclock = { 90000000, 108000000, 135000000 },
1272 .pixelclock = { 106000000, 148500000, 164000000 },
[all …]
H A Dpanel-olimex-lcd-olinuxino.c28 u32 pixelclock; member
124 mode->clock = lcd_mode->pixelclock; in lcd_olinuxino_get_modes()
/linux/drivers/media/i2c/
H A Dths7303.c145 state->bt.pixelclock = 0; in ths7303_s_std_output()
170 if (state->bt.pixelclock > 120000000) in ths7303_config()
172 else if (state->bt.pixelclock > 70000000) in ths7303_config()
174 else if (state->bt.pixelclock > 20000000) in ths7303_config()
286 if (state->bt.pixelclock) { in ths7303_log_status()
296 (int)bt->pixelclock / in ths7303_log_status()
299 (int)bt->pixelclock, bt->polarities); in ths7303_log_status()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddpi.c335 r = dpi_set_dsi_clk(dpi, mgr->id, t->pixelclock, &fck, in dpi_set_mode()
338 r = dpi_set_dispc_clk(dpi, t->pixelclock, &fck, in dpi_set_mode()
345 if (pck != t->pixelclock) { in dpi_set_mode()
347 t->pixelclock, pck); in dpi_set_mode()
349 t->pixelclock = pck; in dpi_set_mode()
509 if (timings->pixelclock == 0) in dpi_check_timings()
513 ok = dpi_dsi_clk_calc(dpi, timings->pixelclock, &ctx); in dpi_check_timings()
519 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx); in dpi_check_timings()
531 timings->pixelclock = pck; in dpi_check_timings()
H A Dsdi.c146 r = sdi_calc_clock_div(t->pixelclock, &fck, &dispc_cinfo); in sdi_display_enable()
154 if (pck != t->pixelclock) { in sdi_display_enable()
156 t->pixelclock, pck); in sdi_display_enable()
158 t->pixelclock = pck; in sdi_display_enable()
240 if (timings->pixelclock == 0) in sdi_check_timings()
H A Ddisplay.c264 ovt->pixelclock = vm->pixelclock; in videomode_to_omap_video_timings()
296 vm->pixelclock = ovt->pixelclock; in omap_video_timings_to_videomode()
H A Dhdmi4.c163 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
257 dispc_set_tv_pclk(timings->pixelclock); in hdmi_display_set_timing()
339 hdmi.cfg.timings.pixelclock); in hdmi_display_enable()
631 hd->cfg.timings.pixelclock); in hdmi_audio_config()
H A Dhdmi5.c175 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
278 dispc_set_tv_pclk(timings->pixelclock); in hdmi_display_set_timing()
369 hdmi.cfg.timings.pixelclock); in hdmi_display_enable()
663 hd->cfg.timings.pixelclock); in hdmi_audio_config()
H A Ddisplay-sysfs.c98 t.pixelclock, in display_timings_show()
123 &t.pixelclock, in display_timings_store()
/linux/drivers/gpu/ipu-v3/
H A Dipu-di.c424 clk_set_rate(clk, sig->mode.pixelclock); in ipu_di_config_clock()
427 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); in ipu_di_config_clock()
444 div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); in ipu_di_config_clock()
448 error = rate / (sig->mode.pixelclock / 1000); in ipu_di_config_clock()
465 clk_set_rate(clk, sig->mode.pixelclock); in ipu_di_config_clock()
468 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); in ipu_di_config_clock()
495 sig->mode.pixelclock, in ipu_di_config_clock()
573 sig->mode.pixelclock); in ipu_di_init_sync_panel()
/linux/drivers/video/
H A Dvideomode.c16 vm->pixelclock = dt->pixelclock.typ; in videomode_from_timing()
H A Dof_display_timing.c73 ret |= parse_timing_property(np, "clock-frequency", &dt->pixelclock); in of_parse_display_timing()
/linux/drivers/media/i2c/adv748x/
H A Dadv748x-hdmi.c278 int pixelclock; in adv748x_hdmi_query_dv_timings() local
299 pixelclock = adv748x_hdmi_read_pixelclock(state); in adv748x_hdmi_query_dv_timings()
300 if (pixelclock < 0) in adv748x_hdmi_query_dv_timings()
305 bt->pixelclock = pixelclock; in adv748x_hdmi_query_dv_timings()
415 return adv748x_csi2_set_pixelrate(tx, timings.bt.pixelclock); in adv748x_hdmi_propagate_pixelrate()
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dpi.c521 pll_rate = vm.pixelclock * factor; in mtk_dpi_set_display_mode()
524 pll_rate, vm.pixelclock); in mtk_dpi_set_display_mode()
534 vm.pixelclock = pll_rate / factor; in mtk_dpi_set_display_mode()
535 vm.pixelclock /= dpi->conf->pixels_per_iter; in mtk_dpi_set_display_mode()
539 clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); in mtk_dpi_set_display_mode()
541 clk_set_rate(dpi->pixel_clk, vm.pixelclock); in mtk_dpi_set_display_mode()
544 vm.pixelclock = clk_get_rate(dpi->pixel_clk); in mtk_dpi_set_display_mode()
547 pll_rate, vm.pixelclock); in mtk_dpi_set_display_mode()
/linux/include/video/
H A Dvideomode.h19 unsigned long pixelclock; /* pixelclock in Hz */ member
H A Ddisplay_timing.h64 struct timing_entry pixelclock; member
/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c360 static int anx7625_calculate_m_n(u32 pixelclock, in anx7625_calculate_m_n() argument
365 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { in anx7625_calculate_m_n()
368 pixelclock, in anx7625_calculate_m_n()
373 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { in anx7625_calculate_m_n()
376 pixelclock, in anx7625_calculate_m_n()
382 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) in anx7625_calculate_m_n()
387 (pixelclock < in anx7625_calculate_m_n()
410 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { in anx7625_calculate_m_n()
412 pixelclock * (*post_divider), in anx7625_calculate_m_n()
417 *m = pixelclock; in anx7625_calculate_m_n()
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-dv-timings-cap.rst81 - Minimum pixelclock frequency in Hz.
84 - Maximum pixelclock frequency in Hz.
/linux/drivers/gpu/drm/xen/
H A Dxen_drm_front_conn.c81 videomode.pixelclock = width * height * XEN_DRM_CRTC_VREFRESH_HZ; in connector_get_modes()
/linux/Documentation/fb/
H A Dmodedb.rst102 pixelclock, the horizontal sync frequency, or the vertical refresh rate.
105 It artificially increases the pixelclock because of its high blanking
107 data rate which requires that it conserves the pixelclock as much as possible.
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4.c167 pc = vm->pixelclock; in hdmi_power_on_full()
394 hdmi->cfg.vm.pixelclock); in hdmi4_bridge_enable()
599 hd->cfg.vm.pixelclock); in hdmi_audio_config()
H A Dhdmi5.c161 pc = vm->pixelclock; in hdmi_power_on_full()
392 hdmi->cfg.vm.pixelclock); in hdmi5_bridge_enable()
575 hd->cfg.vm.pixelclock); in hdmi_audio_config()
/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c587 static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock, in tc_pxl_pll_calc() argument
614 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, in tc_pxl_pll_calc()
616 best_delta = pixelclock; in tc_pxl_pll_calc()
635 tmp = pixelclock * ext_div[i_pre] * in tc_pxl_pll_calc()
649 delta = clk - pixelclock; in tc_pxl_pll_calc()
664 pixelclock); in tc_pxl_pll_calc()
697 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) in tc_pxl_pll_en() argument
702 ret = tc_pxl_pll_calc(tc, refclk, pixelclock, NULL, &pxl_pllparam); in tc_pxl_pll_en()
/linux/drivers/media/pci/mgb4/
H A Dmgb4_vout.c82 timings->bt.pixelclock = voutdev->freq * 1000; in get_timings()
411 ival->stepwise.min.denominator = timings.bt.pixelclock; in vidioc_enum_frameintervals()
435 tpf->denominator = timings.bt.pixelclock; in vidioc_g_parm()
462 timings.bt.pixelclock); in vidioc_s_parm()
H A Dmgb4_vin.c163 timings->bt.pixelclock = pclk * 1000; in get_timings()
393 ival->stepwise.min.denominator = vindev->timings.bt.pixelclock; in vidioc_enum_frameintervals()
567 tpf->denominator = vindev->timings.bt.pixelclock; in vidioc_g_parm()
592 vindev->timings.bt.pixelclock); in vidioc_s_parm()

123