Home
last modified time | relevance | path

Searched refs:pix_clk (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/sti/
H A Dsti_crtc.c54 struct clk *compo_clk, *pix_clk; in sti_crtc_mode_set() local
64 pix_clk = compo->clk_pix_main; in sti_crtc_mode_set()
67 pix_clk = compo->clk_pix_aux; in sti_crtc_mode_set()
77 if (clk_set_rate(pix_clk, rate) < 0) { in sti_crtc_mode_set()
81 if (clk_prepare_enable(pix_clk)) { in sti_crtc_mode_set()
96 clk_disable_unprepare(pix_clk); in sti_crtc_mode_set()
/linux/drivers/media/v4l2-core/
H A Dv4l2-dv-timings.c505 unsigned int pix_clk; in v4l2_detect_cvt() local
600 pix_clk = (image_width + h_blank) * hfreq; in v4l2_detect_cvt()
601 pix_clk = (pix_clk / clk_gran) * clk_gran; in v4l2_detect_cvt()
620 pix_clk = (image_width + h_blank) * hfreq; in v4l2_detect_cvt()
621 pix_clk = (pix_clk / CVT_PXL_CLK_GRAN) * CVT_PXL_CLK_GRAN; in v4l2_detect_cvt()
655 t.bt.pixelclock = pix_clk; in v4l2_detect_cvt()
725 int pix_clk; in v4l2_detect_gtf() local
787 pix_clk = (image_width + h_blank) * hfreq; in v4l2_detect_gtf()
788 pix_clk = pix_clk / GTF_PXL_CLK_GRAN * GTF_PXL_CLK_GRAN; in v4l2_detect_gtf()
819 t.bt.pixelclock = pix_clk; in v4l2_detect_gtf()
/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-dev.c25 clk_prepare_enable(dcss->pix_clk); in dcss_clocks_enable()
30 clk_disable_unprepare(dcss->pix_clk); in dcss_clocks_disable()
137 {"pix", &dcss->pix_clk}, in dcss_clks_init()
158 devm_clk_put(dcss->dev, dcss->pix_clk); in dcss_clks_release()
H A Ddcss-dev.h83 struct clk *pix_clk; member
/linux/drivers/gpu/drm/fsl-dcu/
H A Dfsl_dcu_drm_crtc.c63 clk_disable_unprepare(fsl_dev->pix_clk); in fsl_dcu_drm_crtc_atomic_disable()
72 clk_prepare_enable(fsl_dev->pix_clk); in fsl_dcu_drm_crtc_atomic_enable()
91 clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000); in fsl_dcu_drm_crtc_mode_set_nofb()
/linux/drivers/gpu/drm/bridge/
H A Dsamsung-dsim.c874 unsigned long hs_clk, byte_clk, esc_clk, pix_clk; in samsung_dsim_enable_clock() local
881 pix_clk = m->clock * 1000; in samsung_dsim_enable_clock()
887 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); in samsung_dsim_enable_clock()
1172 u64 pix_clk = m->clock * 1000; in samsung_dsim_set_display_mode() local
1174 int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk, pix_clk); in samsung_dsim_set_display_mode()
1175 int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) * byte_clk, pix_clk); in samsung_dsim_set_display_mode()
1176 int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk, pix_clk); in samsung_dsim_set_display_mode()
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_ddc.c541 uint32_t pix_clk, in write_scdc_data() argument
544 bool over_340_mhz = pix_clk > 340000 ? 1 : 0; in write_scdc_data()
/linux/include/video/
H A Dimx-ipu-v3.h
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c3697 uint32_t pix_clk = timing->pix_clk_100hz; in get_norm_pix_clk() local
3698 uint32_t normalized_pix_clk = pix_clk; in get_norm_pix_clk()
3701 pix_clk /= 2; in get_norm_pix_clk()
3706 normalized_pix_clk = pix_clk; in get_norm_pix_clk()
3709 normalized_pix_clk = (pix_clk * 30) / 24; in get_norm_pix_clk()
3712 normalized_pix_clk = (pix_clk * 36) / 24; in get_norm_pix_clk()
3715 normalized_pix_clk = (pix_clk * 42) / 24; in get_norm_pix_clk()
3718 normalized_pix_clk = (pix_clk * 48) / 24; in get_norm_pix_clk()
/linux/drivers/gpu/drm/radeon/
H A Dr100.c3170 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; in r100_bandwidth_update() local
3287 pix_clk.full = 0; in r100_bandwidth_update()
3292 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ in r100_bandwidth_update()
3293 pix_clk.full = dfixed_div(pix_clk, temp_ff); in r100_bandwidth_update()
3295 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); in r100_bandwidth_update()
3498 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); in r100_bandwidth_update()