| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 991 display_e2e_pipe_params_st *pipes) in dcn20_populate_dml_writeback_from_context() argument
1004 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
1005 pipes[pipe_cnt].dout.num_active_wb++; in dcn20_populate_dml_writeback_from_context()
1006 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
1007 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
1008 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
1009 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
1010 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
1011 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
1012 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; in dcn20_populate_dml_writeback_from_context()
[all …]
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| H A D | dcn20_fpu.h | 33 display_e2e_pipe_params_st *pipes);
37 display_e2e_pipe_params_st *pipes,
41 display_e2e_pipe_params_st *pipes,
46 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
65 enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes);
77 display_e2e_pipe_params_st *pipes,
80 dc_validate_mode, display_e2e_pipe_params_st *pipes);
87 display_e2e_pipe_params_st *pipes);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 445 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, in dcn31_zero_pipe_dcc_fraction() argument
450 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; in dcn31_zero_pipe_dcc_fraction()
451 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; in dcn31_zero_pipe_dcc_fraction()
484 display_e2e_pipe_params_st *pipes, in dcn31_calculate_wm_and_dlg_fp() argument
506 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
511 get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
513 …if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_tim… in dcn31_calculate_wm_and_dlg_fp()
523 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
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| H A D | dcn31_fpu.h | 35 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
43 display_e2e_pipe_params_st *pipes,
57 display_e2e_pipe_params_st *pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 277 display_e2e_pipe_params_st *pipes, in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
293 …dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMIN… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
335 display_e2e_pipe_params_st *pipes, in dcn32_helper_populate_phantom_dlg_params() argument
349 pipes[pipe_idx].pipe.dest.vstartup_start = in dcn32_helper_populate_phantom_dlg_params()
350 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
351 pipes[pipe_idx].pipe.dest.vupdate_offset = in dcn32_helper_populate_phantom_dlg_params()
352 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
353 pipes[pipe_idx].pipe.dest.vupdate_width = in dcn32_helper_populate_phantom_dlg_params()
354 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
355 pipes[pipe_idx].pipe.dest.vready_offset = in dcn32_helper_populate_phantom_dlg_params()
[all …]
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| /linux/sound/sparc/ |
| H A D | dbri.c | 313 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ member
769 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; in dbri_initialize()
813 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1)); in pipe_active()
833 sdp = dbri->pipes[pipe].sdp; in reset_pipe()
846 desc = dbri->pipes[pipe].first_desc; in reset_pipe()
852 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc); in reset_pipe()
854 dbri->pipes[pipe].desc = -1; in reset_pipe()
855 dbri->pipes[pipe].first_desc = -1; in reset_pipe()
882 dbri->pipes[pipe].sdp = sdp; in setup_pipe()
883 dbri->pipes[pipe].desc = -1; in setup_pipe()
[all …]
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| /linux/drivers/platform/goldfish/ |
| H A D | goldfish_pipe.c | 197 struct goldfish_pipe **pipes; member
521 pipe = dev->pipes[id]; in signalled_pipes_add_locked()
653 if (!dev->pipes[id]) in get_free_pipe_id_locked()
662 struct goldfish_pipe **pipes = in get_free_pipe_id_locked() local
663 kzalloc_objs(*pipes, new_capacity, GFP_ATOMIC); in get_free_pipe_id_locked()
664 if (!pipes) in get_free_pipe_id_locked()
666 memcpy(pipes, dev->pipes, sizeof(*pipes) * dev->pipes_capacity); in get_free_pipe_id_locked()
667 kfree(dev->pipes); in get_free_pipe_id_locked()
668 dev->pipes = pipes; in get_free_pipe_id_locked()
731 dev->pipes[id] = pipe; in goldfish_pipe_open()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 46 const display_e2e_pipe_params_st *pipes,
54 const display_e2e_pipe_params_st *pipes, in dml_get_voltage_level() argument
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
68 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()
82 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
84 recalculate_params(mode_lib, pipes, num_pipes); \
130 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
133 recalculate_params(mode_lib, pipes, num_pipes); \
209 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bytes() argument
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| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_event.c | 110 return (a->pipes[0] | a->pipes[1]) & in is_new_frame()
120 u64 evts_mask = evts->global | evts->pipes[0] | evts->pipes[1]; in komeda_print_events()
147 evt_str(&str, evts->pipes[0]); in komeda_print_events()
149 evt_str(&str, evts->pipes[1]); in komeda_print_events()
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| /linux/drivers/gpu/drm/tidss/ |
| H A D | tidss_kms.c | 142 struct pipe pipes[TIDSS_MAX_PORTS]; in tidss_dispc_modeset_init() local
199 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
200 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
201 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
226 tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, in tidss_dispc_modeset_init()
235 ret = tidss_encoder_create(tidss, pipes[i].bridge, in tidss_dispc_modeset_init()
236 pipes[i].enc_type, in tidss_dispc_modeset_init()
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| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | mpo-overview.rst | 50 For this hardware example, we have 4 pipes (if you don't know what AMD pipe
53 configuration for optimal single display output (e.g., 2 pipes per plane).
56 display - will see 4 pipes in use, 2 per plane.
204 the two displays, we need to use 2 pipes. See the example below where we avoid
207 - 1 display (1 pipe) + MPO (1 pipe), we will use two pipes
208 - 2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the
209 middle of both displays needs 2 pipes.
210 - 3 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.
217 * When ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPO
218 * When ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1650 display_e2e_pipe_params_st *pipes, in dcn31x_populate_dml_pipes_from_context() argument
1658 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); in dcn31x_populate_dml_pipes_from_context()
1661 pipes[i].pipe.src.gpuvm = 1; in dcn31x_populate_dml_pipes_from_context()
1664 pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled; in dcn31x_populate_dml_pipes_from_context()
1666 pipes[i].pipe.src.hostvm = false; in dcn31x_populate_dml_pipes_from_context()
1668 pipes[i].pipe.src.hostvm = true; in dcn31x_populate_dml_pipes_from_context()
1675 display_e2e_pipe_params_st *pipes, in dcn31_populate_dml_pipes_from_context() argument
1684 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); in dcn31_populate_dml_pipes_from_context()
1704 pipes[pipe_cnt].pipe.src.immediate_flip = true; in dcn31_populate_dml_pipes_from_context()
1705 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; in dcn31_populate_dml_pipes_from_context()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_dc_resource_mgmt.c | 142 struct dc_state *state, unsigned int plane_id, unsigned int *pipes) in find_pipes_assigned_to_plane() argument
163 pipes[num_found++] = mpc_pipe->pipe_idx; in find_pipes_assigned_to_plane()
483 static void sort_pipes_for_splitting(struct dc_plane_pipe_pool *pipes) in sort_pipes_for_splitting() argument
489 …for (odm_slice_index = 0; odm_slice_index < pipes->num_pipes_assigned_to_plane_for_odm_combine; od… in sort_pipes_for_splitting()
493 if (pipes->num_pipes_assigned_to_plane_for_mpcc_combine <= 1) in sort_pipes_for_splitting()
501 …if (pipes->pipes_assigned_to_plane[odm_slice_index][cur_index] > pipes->pipes_assigned_to_plane[od… in sort_pipes_for_splitting()
502 swap(pipes->pipes_assigned_to_plane[odm_slice_index][cur_index + 1], in sort_pipes_for_splitting()
503 pipes->pipes_assigned_to_plane[odm_slice_index][cur_index]); in sort_pipes_for_splitting()
510 if (cur_index == pipes->num_pipes_assigned_to_plane_for_mpcc_combine - 1) { in sort_pipes_for_splitting()
597 …ream(struct dml2_context *ctx, struct dc_state *state, unsigned int stream_id, unsigned int *pipes) in find_pipes_assigned_to_stream() argument
[all …]
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| /linux/net/nfc/nci/ |
| H A D | hci.c | 116 hdev->pipes[i].gate = NCI_HCI_INVALID_GATE; in nci_hci_reset_pipes()
117 hdev->pipes[i].host = NCI_HCI_INVALID_HOST; in nci_hci_reset_pipes()
127 if (ndev->hci_dev->pipes[i].host == host) { in nci_hci_reset_pipes_per_host()
128 ndev->hci_dev->pipes[i].gate = NCI_HCI_INVALID_GATE; in nci_hci_reset_pipes_per_host()
129 ndev->hci_dev->pipes[i].host = NCI_HCI_INVALID_HOST; in nci_hci_reset_pipes_per_host()
284 u8 gate = ndev->hci_dev->pipes[pipe].gate; in nci_hci_cmd_received()
313 ndev->hci_dev->pipes[new_pipe].gate = dest_gate; in nci_hci_cmd_received()
314 ndev->hci_dev->pipes[new_pipe].host = in nci_hci_cmd_received()
335 ndev->hci_dev->pipes[delete_info->pipe].gate = in nci_hci_cmd_received()
337 ndev->hci_dev->pipes[delete_info->pipe].host = in nci_hci_cmd_received()
[all …]
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| /linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 17 -- Seekable pipes
23 -- Channels, pipes, and the message channel
85 project to another (the number of data pipes needed in each direction and
90 Xillybus presents independent data streams, which resemble pipes or TCP/IP
125 possibly pressing CTRL-C as some stage, even though the xillybus_* pipes have
128 The driver and hardware are designed to behave sensibly as pipes, including:
138 device files are treated like two independent pipes (except for sharing a
144 Xillybus pipes are configured (on the IP core) to be either synchronous or
154 For FPGA to host pipes, asynchronous pipes allow data transfer from the FPGA
156 has been requested by a read() call. On synchronous pipes, only the amount
[all …]
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| /linux/tools/testing/selftests/kvm/lib/ |
| H A D | userfaultfd_util.c | 156 int pipes[2]; in uffd_setup_demand_paging() local
158 ret = pipe2((int *) &pipes, O_CLOEXEC | O_NONBLOCK); in uffd_setup_demand_paging()
162 uffd_desc->pipefds[i] = pipes[1]; in uffd_setup_demand_paging()
168 uffd_desc->reader_args[i].pipe = pipes[0]; in uffd_setup_demand_paging()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1726 display_e2e_pipe_params_st *pipes, in dcn32_enable_phantom_stream() argument
1742 …dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_id… in dcn32_enable_phantom_stream()
1753 display_e2e_pipe_params_st *pipes, in dcn32_add_phantom_pipes() argument
1763 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); in dcn32_add_phantom_pipes()
1794 display_e2e_pipe_params_st *pipes = kzalloc_objs(display_e2e_pipe_params_st, in dml1_validate() local
1807 if (!pipes) in dml1_validate()
1811 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode); in dml1_validate()
1827 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dml1_validate()
1847 kfree(pipes); in dml1_validate()
1908 display_e2e_pipe_params_st *pipes, in dcn32_populate_dml_pipes_from_context() argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1699 display_e2e_pipe_params_st *pipes, in dcn315_populate_dml_pipes_from_context() argument
1710 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); in dcn315_populate_dml_pipes_from_context()
1726 pipes[pipe_cnt].pipe.src.immediate_flip = true; in dcn315_populate_dml_pipes_from_context()
1728 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; in dcn315_populate_dml_pipes_from_context()
1729 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; in dcn315_populate_dml_pipes_from_context()
1730 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn315_populate_dml_pipes_from_context()
1731 pipes[pipe_cnt].dout.dsc_input_bpc = 0; in dcn315_populate_dml_pipes_from_context()
1733 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); in dcn315_populate_dml_pipes_from_context()
1735 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format); in dcn315_populate_dml_pipes_from_context()
1750 pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate; in dcn315_populate_dml_pipes_from_context()
[all …]
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| /linux/Documentation/filesystems/ |
| H A D | splice.rst | 2 splice and pipes
13 pipes API
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| /linux/net/nfc/hci/ |
| H A D | core.c | 42 hdev->pipes[i].gate = NFC_HCI_INVALID_GATE; in nfc_hci_reset_pipes()
43 hdev->pipes[i].dest_host = NFC_HCI_INVALID_HOST; in nfc_hci_reset_pipes()
54 if (hdev->pipes[i].dest_host != host) in nfc_hci_reset_pipes_per_host()
57 hdev->pipes[i].gate = NFC_HCI_INVALID_GATE; in nfc_hci_reset_pipes_per_host()
58 hdev->pipes[i].dest_host = NFC_HCI_INVALID_HOST; in nfc_hci_reset_pipes_per_host()
197 gate = hdev->pipes[pipe].gate; in nfc_hci_cmd_received()
218 hdev->pipes[create_info->pipe].gate = create_info->dest_gate; in nfc_hci_cmd_received()
219 hdev->pipes[create_info->pipe].dest_host = in nfc_hci_cmd_received()
240 hdev->pipes[delete_info->pipe].gate = NFC_HCI_INVALID_GATE; in nfc_hci_cmd_received()
241 hdev->pipes[delete_info->pipe].dest_host = NFC_HCI_INVALID_HOST; in nfc_hci_cmd_received()
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| /linux/tools/perf/ |
| H A D | builtin-record.c | 109 } pipes; member
1008 thread_data->pipes.msg[0] = -1; in record__thread_data_init_pipes()
1009 thread_data->pipes.msg[1] = -1; in record__thread_data_init_pipes()
1010 thread_data->pipes.ack[0] = -1; in record__thread_data_init_pipes()
1011 thread_data->pipes.ack[1] = -1; in record__thread_data_init_pipes()
1016 if (pipe(thread_data->pipes.msg)) in record__thread_data_open_pipes()
1019 if (pipe(thread_data->pipes.ack)) { in record__thread_data_open_pipes()
1020 close(thread_data->pipes.msg[0]); in record__thread_data_open_pipes()
1021 thread_data->pipes.msg[0] = -1; in record__thread_data_open_pipes()
1022 close(thread_data->pipes in record__thread_data_open_pipes()
[all...] |
| /linux/drivers/gpu/drm/vc4/tests/ |
| H A D | vc4_mock.c | 41 const struct vc4_mock_pipe_desc *pipes; member
47 .pipes = (struct vc4_mock_pipe_desc[]) { __VA_ARGS__ }, \
144 const struct vc4_mock_pipe_desc *pipe = &mock->pipes[i]; in __build_mock()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1355 display_e2e_pipe_params_st *pipes, in dcn30_populate_dml_pipes_from_context() argument
1362 dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); in dcn30_populate_dml_pipes_from_context()
1369 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth = in dcn30_populate_dml_pipes_from_context()
1377 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_populate_dml_writeback_from_context() argument
1380 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn30_populate_dml_writeback_from_context()
1410 display_e2e_pipe_params_st *pipes, in dcn30_set_mcif_arb_params() argument
1441 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j); in dcn30_set_mcif_arb_params()
1661 display_e2e_pipe_params_st *pipes, in dcn30_internal_validate_bw() argument
1675 ASSERT(pipes); in dcn30_internal_validate_bw()
1676 if (!pipes) in dcn30_internal_validate_bw()
[all …]
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| /linux/drivers/nfc/st-nci/ |
| H A D | se.c | 230 ndev->hci_dev->pipes[pipe_info[2]].gate = in st_nci_hci_load_session()
232 ndev->hci_dev->pipes[pipe_info[2]].host = in st_nci_hci_load_session()
385 u8 gate = ndev->hci_dev->pipes[pipe].gate; in st_nci_hci_event_received()
386 u8 host = ndev->hci_dev->pipes[pipe].host; in st_nci_hci_event_received()
406 u8 gate = ndev->hci_dev->pipes[pipe].gate; in st_nci_hci_cmd_received()
413 ndev->hci_dev->pipes[pipe].host != ST_NCI_UICC_HOST_ID) in st_nci_hci_cmd_received()
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| /linux/drivers/staging/media/atomisp/pci/ |
| H A D | sh_css.c | 124 struct ia_css_pipe *pipes[IA_CSS_PIPE_ID_NUM]; member
1208 assert(stream->pipes[i]); in sh_css_invalidate_shading_tables()
1209 sh_css_pipe_free_shading_table(stream->pipes[i]); in sh_css_invalidate_shading_tables()
1521 ia_css_pipeline_map(stream->pipes[i]->pipe_num, map); in map_sp_threads()
1607 main_pipe = stream->pipes[i]; in create_host_pipeline_structure()
1738 switch (stream->pipes[i]->mode) { in create_host_pipeline()
1740 err = create_host_preview_pipeline(stream->pipes[i]); in create_host_pipeline()
1743 err = create_host_video_pipeline(stream->pipes[i]); in create_host_pipeline()
1746 err = create_host_capture_pipeline(stream->pipes[i]); in create_host_pipeline()
1749 err = create_host_yuvpp_pipeline(stream->pipes[i]); in create_host_pipeline()
[all …]
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