| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 992 display_e2e_pipe_params_st *pipes) in dcn20_populate_dml_writeback_from_context() argument
1005 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
1006 pipes[pipe_cnt].dout.num_active_wb++; in dcn20_populate_dml_writeback_from_context()
1007 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
1008 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
1009 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
1010 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
1011 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
1012 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
1013 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; in dcn20_populate_dml_writeback_from_context()
[all …]
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| H A D | dcn20_fpu.h | 33 display_e2e_pipe_params_st *pipes);
37 display_e2e_pipe_params_st *pipes,
41 display_e2e_pipe_params_st *pipes,
46 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
65 bool fast_validate, display_e2e_pipe_params_st *pipes);
77 display_e2e_pipe_params_st *pipes,
80 fast_validate, display_e2e_pipe_params_st *pipes);
87 display_e2e_pipe_params_st *pipes);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 258 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_fpu_populate_dml_writeback_from_context() argument
275 pipes[pipe_cnt].dout.wb_enable = 0; in dcn30_fpu_populate_dml_writeback_from_context()
276 pipes[pipe_cnt].dout.num_active_wb = 0; in dcn30_fpu_populate_dml_writeback_from_context()
282 pipes[pipe_cnt].dout.wb_enable = 1; in dcn30_fpu_populate_dml_writeback_from_context()
283 pipes[pipe_cnt].dout.num_active_wb++; in dcn30_fpu_populate_dml_writeback_from_context()
326 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, in dcn30_fpu_populate_dml_writeback_from_context()
333 pipes[pipe_cnt].pipe.dest.htotal, in dcn30_fpu_populate_dml_writeback_from_context()
338 pipes[pipe_cnt].dout.wb = dout_wb; in dcn30_fpu_populate_dml_writeback_from_context()
349 display_e2e_pipe_params_st *pipes, in dcn30_fpu_set_mcif_arb_params() argument
358 wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; in dcn30_fpu_set_mcif_arb_params()
[all …]
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| H A D | dcn30_fpu.h | 36 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
40 display_e2e_pipe_params_st *pipes,
48 display_e2e_pipe_params_st *pipes,
68 display_e2e_pipe_params_st *pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 296 display_e2e_pipe_params_st *pipes, in calculate_wm_set_for_vlevel() argument
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
312 …wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) … in calculate_wm_set_for_vlevel()
313 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
314 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
315 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
316 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 308 display_e2e_pipe_params_st *pipes, in dcn314_populate_dml_pipes_from_context_fpu() argument
319 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); in dcn314_populate_dml_pipes_from_context_fpu()
334 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; in dcn314_populate_dml_pipes_from_context_fpu()
336 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; in dcn314_populate_dml_pipes_from_context_fpu()
340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn314_populate_dml_pipes_from_context_fpu()
341 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn314_populate_dml_pipes_from_context_fpu()
346 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn314_populate_dml_pipes_from_context_fpu()
347 max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); in dcn314_populate_dml_pipes_from_context_fpu()
348 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn314_populate_dml_pipes_from_context_fpu()
357 … pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled || dc->res_pool->hubbub->riommu_active; in dcn314_populate_dml_pipes_from_context_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 437 display_e2e_pipe_params_st *pipes, in dcn35_populate_dml_pipes_from_context_fpu() argument
446 dcn31_populate_dml_pipes_from_context(dc, context, pipes, in dcn35_populate_dml_pipes_from_context_fpu()
466 pipes[pipe_cnt].pipe.dest.vtotal = in dcn35_populate_dml_pipes_from_context_fpu()
468 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - in dcn35_populate_dml_pipes_from_context_fpu()
469 pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
472 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
473 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn35_populate_dml_pipes_from_context_fpu()
478 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn35_populate_dml_pipes_from_context_fpu()
479 max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); in dcn35_populate_dml_pipes_from_context_fpu()
480 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn35_populate_dml_pipes_from_context_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.h | 36 display_e2e_pipe_params_st *pipes,
43 display_e2e_pipe_params_st *pipes,
49 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes,
63 display_e2e_pipe_params_st *pipes,
69 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
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| H A D | dcn32_fpu.c | 277 display_e2e_pipe_params_st *pipes, in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
293 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
335 display_e2e_pipe_params_st *pipes, in dcn32_helper_populate_phantom_dlg_params() argument
349 pipes[pipe_idx].pipe.dest.vstartup_start = in dcn32_helper_populate_phantom_dlg_params()
350 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
351 pipes[pipe_idx].pipe.dest.vupdate_offset = in dcn32_helper_populate_phantom_dlg_params()
352 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
353 pipes[pipe_idx].pipe.dest.vupdate_width = in dcn32_helper_populate_phantom_dlg_params()
354 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
355 pipes[pipe_idx].pipe.dest.vready_offset = in dcn32_helper_populate_phantom_dlg_params()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 445 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, in dcn31_zero_pipe_dcc_fraction() argument
450 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; in dcn31_zero_pipe_dcc_fraction()
451 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; in dcn31_zero_pipe_dcc_fraction()
484 display_e2e_pipe_params_st *pipes, in dcn31_calculate_wm_and_dlg_fp() argument
506 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
511 get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
513 …if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_tim… in dcn31_calculate_wm_and_dlg_fp()
523 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| H A D | dcn31_fpu.h | 35 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
43 display_e2e_pipe_params_st *pipes,
57 display_e2e_pipe_params_st *pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.h | 51 display_e2e_pipe_params_st *pipes,
64 display_e2e_pipe_params_st *pipes,
71 display_e2e_pipe_params_st *pipes,
76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
80 display_e2e_pipe_params_st *pipes,
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| /linux/drivers/platform/goldfish/ |
| H A D | goldfish_pipe.c | 197 struct goldfish_pipe **pipes; member
521 pipe = dev->pipes[id]; in signalled_pipes_add_locked()
653 if (!dev->pipes[id]) in get_free_pipe_id_locked()
662 struct goldfish_pipe **pipes = in get_free_pipe_id_locked() local
663 kcalloc(new_capacity, sizeof(*pipes), GFP_ATOMIC); in get_free_pipe_id_locked()
664 if (!pipes) in get_free_pipe_id_locked()
666 memcpy(pipes, dev->pipes, sizeof(*pipes) * dev->pipes_capacity); in get_free_pipe_id_locked()
667 kfree(dev->pipes); in get_free_pipe_id_locked()
668 dev->pipes = pipes; in get_free_pipe_id_locked()
731 dev->pipes[id] = pipe; in goldfish_pipe_open()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 46 const display_e2e_pipe_params_st *pipes,
54 const display_e2e_pipe_params_st *pipes, in dml_get_voltage_level() argument
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
68 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()
82 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
84 recalculate_params(mode_lib, pipes, num_pipes); \
130 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
133 recalculate_params(mode_lib, pipes, num_pipes); \
209 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bytes() argument
[all …]
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| H A D | display_mode_lib.c | 162 display_e2e_pipe_params_st *pipes, in dml_log_pipe_params() argument
174 pipe_src = &(pipes[i].pipe.src); in dml_log_pipe_params()
175 pipe_dest = &(pipes[i].pipe.dest); in dml_log_pipe_params()
176 scale_ratio_depth = &(pipes[i].pipe.scale_ratio_depth); in dml_log_pipe_params()
177 scale_taps = &(pipes[i].pipe.scale_taps); in dml_log_pipe_params()
178 dout = &(pipes[i].dout); in dml_log_pipe_params()
179 clks_cfg = &(pipes[i].clks_cfg); in dml_log_pipe_params()
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| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_event.c | 110 return (a->pipes[0] | a->pipes[1]) & in is_new_frame()
120 u64 evts_mask = evts->global | evts->pipes[0] | evts->pipes[1]; in komeda_print_events()
147 evt_str(&str, evts->pipes[0]); in komeda_print_events()
149 evt_str(&str, evts->pipes[1]); in komeda_print_events()
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| /linux/drivers/gpu/drm/tidss/ |
| H A D | tidss_kms.c | 120 struct pipe pipes[TIDSS_MAX_PORTS]; in tidss_dispc_modeset_init() local
177 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
178 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
179 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
204 tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, in tidss_dispc_modeset_init()
213 ret = tidss_encoder_create(tidss, pipes[i].bridge, in tidss_dispc_modeset_init()
214 pipes[i].enc_type, in tidss_dispc_modeset_init()
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| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | mpo-overview.rst | 50 For this hardware example, we have 4 pipes (if you don't know what AMD pipe
53 configuration for optimal single display output (e.g., 2 pipes per plane).
56 display - will see 4 pipes in use, 2 per plane.
204 the two displays, we need to use 2 pipes. See the example below where we avoid
207 - 1 display (1 pipe) + MPO (1 pipe), we will use two pipes
208 - 2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the
209 middle of both displays needs 2 pipes.
210 - 3 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.
217 * When ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPO
218 * When ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 313 display_e2e_pipe_params_st *pipes) in dcn32_determine_det_override() argument
372 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE; in dcn32_determine_det_override()
377 pipes[i].pipe.src.det_size_override = 4 * DCN3_2_DET_SEG_SIZE; //DCN3_2_DEFAULT_DET_SIZE in dcn32_determine_det_override()
382 display_e2e_pipe_params_st *pipes) in dcn32_set_det_allocations() argument
403 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE; in dcn32_set_det_allocations()
406 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE; in dcn32_set_det_allocations()
407 pipes[0].pipe.src.unbounded_req_mode = true; in dcn32_set_det_allocations()
410 pipes[0].pipe.src.det_size_override = 320; // 5K or higher in dcn32_set_det_allocations()
414 dcn32_determine_det_override(dc, context, pipes); in dcn32_set_det_allocations()
751 display_e2e_pipe_params_st *pipes) in dcn32_update_dml_pipes_odm_policy_based_on_context() argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/link/accessories/ |
| H A D | link_dp_cts.c | 68 struct pipe_ctx *pipes[MAX_PIPES]; in dp_retrain_link_dp_test() local
77 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); in dp_retrain_link_dp_test()
80 link_set_dpms_off(pipes[i]); in dp_retrain_link_dp_test()
81 pipes[i]->link_config.dp_link_settings = *link_setting; in dp_retrain_link_dp_test()
85 pipes[i]); in dp_retrain_link_dp_test()
95 link_set_dpms_on(state, pipes[i]); in dp_retrain_link_dp_test()
134 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; in dp_test_get_audio_test_data() local
135 struct pipe_ctx *pipe_ctx = &pipes[0]; in dp_test_get_audio_test_data()
594 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; in dp_set_test_pattern() local
605 if (pipes[i].stream == NULL) in dp_set_test_pattern()
[all …]
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| /linux/net/nfc/nci/ |
| H A D | hci.c | 116 hdev->pipes[i].gate = NCI_HCI_INVALID_GATE; in nci_hci_reset_pipes()
117 hdev->pipes[i].host = NCI_HCI_INVALID_HOST; in nci_hci_reset_pipes()
127 if (ndev->hci_dev->pipes[i].host == host) { in nci_hci_reset_pipes_per_host()
128 ndev->hci_dev->pipes[i].gate = NCI_HCI_INVALID_GATE; in nci_hci_reset_pipes_per_host()
129 ndev->hci_dev->pipes[i].host = NCI_HCI_INVALID_HOST; in nci_hci_reset_pipes_per_host()
284 u8 gate = ndev->hci_dev->pipes[pipe].gate; in nci_hci_cmd_received()
313 ndev->hci_dev->pipes[new_pipe].gate = dest_gate; in nci_hci_cmd_received()
314 ndev->hci_dev->pipes[new_pipe].host = in nci_hci_cmd_received()
335 ndev->hci_dev->pipes[delete_info->pipe].gate = in nci_hci_cmd_received()
337 ndev->hci_dev->pipes[delete_info->pipe].host = in nci_hci_cmd_received()
[all …]
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| /linux/drivers/gpu/drm/arm/display/komeda/d71/ |
| H A D | d71_dev.c | 189 evts->pipes[0] |= KOMEDA_EVENT_FLIP; in d71_irq_handler()
191 evts->pipes[1] |= KOMEDA_EVENT_FLIP; in d71_irq_handler()
205 evts->pipes[0] |= get_pipeline_event(d71->pipes[0], gcu_status); in d71_irq_handler()
208 evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status); in d71_irq_handler()
228 pipe = d71->pipes[i]; in d71_enable_irq()
247 pipe = d71->pipes[i]; in d71_disable_irq()
261 struct d71_pipeline *pipe = d71->pipes[master_pipe]; in d71_on_off_vblank()
435 d71->pipes[i] = to_d71_pipeline(pipe); in d71_enum_resources()
578 malidp_write32_mask(d71->pipes[i]->lpu_addr, LPU_TBU_CONTROL, in d71_connect_iommu()
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| /linux/drivers/net/wireless/ath/ath6kl/ |
| H A D | usb.c | 70 struct ath6kl_usb_pipe pipes[ATH6KL_USB_PIPE_MAX]; member
255 ath6kl_usb_free_pipe_resources(&ar_usb->pipes[i]); in ath6kl_usb_cleanup_pipe_resources()
358 pipe = &ar_usb->pipes[pipe_num]; in ath6kl_usb_setup_pipe_resources()
474 if (ar_usb->pipes[i].ar_usb != NULL) in ath6kl_usb_flush_all()
475 usb_kill_anchored_urbs(&ar_usb->pipes[i].urb_submitted); in ath6kl_usb_flush_all()
496 ar_usb->pipes[ATH6KL_USB_PIPE_RX_DATA].urb_cnt_thresh = 1; in ath6kl_usb_start_recv_pipes()
498 ath6kl_usb_post_recv_transfers(&ar_usb->pipes[ATH6KL_USB_PIPE_RX_DATA], in ath6kl_usb_start_recv_pipes()
652 pipe = &ar_usb->pipes[i]; in ath6kl_usb_create()
708 device->pipes[i].urb_cnt_thresh = in hif_start()
709 device->pipes[i].urb_alloc / 2; in hif_start()
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| /linux/drivers/net/wireless/ath/ath10k/ |
| H A D | usb.c | 120 ath10k_usb_free_pipe_resources(ar, &ar_usb->pipes[i]); in ath10k_usb_cleanup_pipe_resources()
264 if (ar_usb->pipes[i].ar_usb) { in ath10k_usb_flush_all()
265 usb_kill_anchored_urbs(&ar_usb->pipes[i].urb_submitted); in ath10k_usb_flush_all()
266 cancel_work_sync(&ar_usb->pipes[i].io_complete_work); in ath10k_usb_flush_all()
275 ar_usb->pipes[ATH10K_USB_PIPE_RX_DATA].urb_cnt_thresh = 1; in ath10k_usb_start_recv_pipes()
278 &ar_usb->pipes[ATH10K_USB_PIPE_RX_DATA]); in ath10k_usb_start_recv_pipes()
402 ar_usb->pipes[i].urb_cnt_thresh = in ath10k_usb_hif_start()
403 ar_usb->pipes[i].urb_alloc / 2; in ath10k_usb_hif_start()
413 struct ath10k_usb_pipe *pipe = &ar_usb->pipes[pipe_id]; in ath10k_usb_hif_tx_sg()
479 return ar_usb->pipes[pipe_id].urb_cnt; in ath10k_usb_hif_get_free_queue_number()
[all …]
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| /linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 17 -- Seekable pipes
23 -- Channels, pipes, and the message channel
85 project to another (the number of data pipes needed in each direction and
90 Xillybus presents independent data streams, which resemble pipes or TCP/IP
125 possibly pressing CTRL-C as some stage, even though the xillybus_* pipes have
128 The driver and hardware are designed to behave sensibly as pipes, including:
138 device files are treated like two independent pipes (except for sharing a
144 Xillybus pipes are configured (on the IP core) to be either synchronous or
154 For FPGA to host pipes, asynchronous pipes allow data transfer from the FPGA
156 has been requested by a read() call. On synchronous pipes, only the amount
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