| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_lib.h | 57 const unsigned int pipe_idx,
75 const unsigned int pipe_idx);
80 const unsigned int pipe_idx);
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| H A D | display_mode_vba.c | 258 int pipe_idx = -1; in get_pipe_idx() local
265 pipe_idx = i; in get_pipe_idx()
269 ASSERT(pipe_idx >= 0); in get_pipe_idx()
271 return pipe_idx; in get_pipe_idx()
276 unsigned int num_pipes, unsigned int pipe_idx) in get_det_buffer_size_kbytes() argument
282 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_det_buffer_size_kbytes()
284 …dml_print("DML::%s: num_pipes=%d pipe_idx=%d plane_idx=%0d\n", __func__, num_pipes, pipe_idx, plan… in get_det_buffer_size_kbytes()
293 unsigned int num_pipes, unsigned int pipe_idx) in get_is_phantom_pipe() argument
298 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_is_phantom_pipe()
299 …nt("DML::%s: num_pipes=%d pipe_idx=%d UseMALLForPStateChange=%0d\n", __func__, num_pipes, pipe_idx, in get_is_phantom_pipe()
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| H A D | display_mode_vba.h | 173 unsigned int pipe_idx);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 488 int i, pipe_idx, total_det = 0, active_hubp_count = 0; in dcn31_calculate_wm_and_dlg_fp() local
537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
544 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
545 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn31_calculate_wm_and_dlg_fp()
548 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
549 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
551 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
552 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
553 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
554 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
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| H A D | display_rq_dlg_calc_31.h | 62 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_rq_dlg_calc_32.h | 48 const unsigned int pipe_idx);
68 const unsigned int pipe_idx);
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1653 pipe_ctx->pipe_idx, in resource_build_scaling_params()
1793 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in resource_find_free_secondary_pipe_legacy()
1796 secondary_pipe->pipe_idx = preferred_pipe_idx; in resource_find_free_secondary_pipe_legacy()
1808 secondary_pipe->pipe_idx = i; in resource_find_free_secondary_pipe_legacy()
1826 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx]; in resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master()
1828 free_pipe_idx = cur_sec_opp_head->pipe_idx; in resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master()
1851 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx]; in resource_find_free_pipe_used_in_cur_mpc_blending_tree()
1853 free_pipe_idx = cur_sec_dpp->pipe_idx; in resource_find_free_pipe_used_in_cur_mpc_blending_tree()
2012 struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx]; in resource_get_opp_heads_for_otg_master()
2037 struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx]; in resource_get_dpp_pipes_for_opp_head()
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| H A D | dc.c | 1343 pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx != in disable_dangling_plane()
1344 dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx; in disable_dangling_plane()
2497 int pipe_idx; in dc_acquire_release_mpc_3dlut() local
2507 for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) { in dc_acquire_release_mpc_3dlut()
2508 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) { in dc_acquire_release_mpc_3dlut()
2510 mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; in dc_acquire_release_mpc_3dlut()
2593 context->res_ctx.pipe_ctx[i].pipe_idx = i; in dc_post_update_surfaces_to_stream()
3828 update_dirty_rect->pipe_idx = j; in dc_dmub_update_dirty_rect()
3882 update_dirty_rect->pipe_idx = j; in build_dmub_update_dirty_rect()
6834 state->mpc.mpcc_bot_sel[i] = pipe_ctx->bottom_pipe->pipe_idx; in dc_capture_register_software_state()
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| H A D | dc_hw_sequencer.c | 336 *color = pipe_colors[top_pipe->pipe_idx]; in get_mpctree_visual_confirm_color()
2158 int pipe_idx; in hwss_wait_for_outstanding_hw_updates() local
2165 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { in hwss_wait_for_outstanding_hw_updates()
2166 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx]; in hwss_wait_for_outstanding_hw_updates()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.h | 66 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_rq_dlg_calc_20.h | 66 const unsigned int pipe_idx,
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| H A D | display_rq_dlg_calc_20v2.h | 66 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_rq_dlg_calc_314.h | 63 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.h | 62 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_trace.h | 30 trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_crtc.c | 452 u32 lm_idx, stage, i, pipe_idx, head_pipe_in_stage, lms_in_pair; in _dpu_crtc_blend_setup_mixer() local
479 pipe_idx = i + head_pipe_in_stage; in _dpu_crtc_blend_setup_mixer()
480 if (!pstate->pipe[pipe_idx].sspp) in _dpu_crtc_blend_setup_mixer()
484 set_bit(pstate->pipe[pipe_idx].sspp->idx, active_fetch); in _dpu_crtc_blend_setup_mixer()
485 set_bit(pstate->pipe[pipe_idx].sspp->idx, active_pipes); in _dpu_crtc_blend_setup_mixer()
491 &pstate->pipe[pipe_idx], i, in _dpu_crtc_blend_setup_mixer()
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| H A D | dpu_plane.c | 967 int pipe_idx; in dpu_plane_get_single_pipe_in_stage() local
969 pipe_idx = stage_index * PIPES_PER_STAGE; in dpu_plane_get_single_pipe_in_stage()
970 if (drm_rect_width(&pstate->pipe_cfg[pipe_idx].src_rect) != 0 && in dpu_plane_get_single_pipe_in_stage()
971 drm_rect_width(&pstate->pipe_cfg[pipe_idx + 1].src_rect) == 0) { in dpu_plane_get_single_pipe_in_stage()
972 *single_pipe = &pstate->pipe[pipe_idx]; in dpu_plane_get_single_pipe_in_stage()
973 *single_pipe_cfg = &pstate->pipe_cfg[pipe_idx]; in dpu_plane_get_single_pipe_in_stage()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1548 pipe_ctx[pipe_ctx->pipe_idx]; in dce110_enable_stream_timing()
1671 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); in dce110_apply_single_controller_ctx_to_hw()
1855 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; in disable_vga_and_power_gate_all_controllers()
2246 uint32_t *pipe_idx) in should_enable_fbc() argument
2270 if (pipe_ctx->pipe_idx != underlay_idx) { in should_enable_fbc()
2271 *pipe_idx = i; in should_enable_fbc()
2313 uint32_t pipe_idx = 0; in enable_fbc() local
2315 if (should_enable_fbc(dc, context, &pipe_idx)) { in enable_fbc()
2319 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in enable_fbc()
3039 pipe_ctx->pipe_idx, in dce110_program_front_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_clk_mgr.c | 524 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; in dce110_fill_display_configs()
664 pp_display_cfg->disp_configs[0].pipe_idx; in dce11_pplib_apply_display_requirements()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 1531 old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx]; in update_dsc_for_odm_change()
1552 new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx]; in update_dsc_for_odm_change()
1615 old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx]; in dcn401_add_dsc_sequence_for_odm_change()
1686 new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx]; in dcn401_add_dsc_sequence_for_odm_change()
2028 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); in dcn401_reset_back_end_for_pipe()
2483 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); in dcn401_program_front_end_for_ctx()
2978 stream_idx = top_pipe->pipe_idx; in dcn401_update_cursor_offload_pipe()
2982 p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe->pipe_idx].dcn401; in dcn401_update_cursor_offload_pipe()
3019 cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx); in dcn401_update_cursor_offload_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 1377 pipe_ctx->pipe_idx); in deallocate_mst_payload()
1464 pipe_ctx->pipe_idx); in allocate_mst_payload()
1693 pipe_ctx->pipe_idx); in update_sst_payload()
1786 pipe_ctx->pipe_idx); in link_reduce_mst_payload()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 311 pipe_ctx->pipe_idx = i; in dcn201_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 3924 uint8_t pipe_idx; member
4015 uint8_t pipe_idx; member
4066 uint8_t pipe_idx; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 769 pipe_ctx->pipe_idx); in dcn20_disable_plane()
2147 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); in dcn20_program_front_end_for_ctx()
2901 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); in dcn20_reset_back_end_for_pipe()
3196 pipe_ctx->pipe_idx = i; in dcn20_fpga_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | display_mode_core.c | 10209 dml_bool_t dml_get_is_phantom_pipe(struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx) in dml_get_is_phantom_pipe() argument
10211 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_is_phantom_pipe()
10212 …dml_print("DML::%s: pipe_idx=%d UseMALLForPStateChange=%0d\n", __func__, pipe_idx, mode_lib->ms.ca… in dml_get_is_phantom_pipe()
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