| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml_display_rq_dlg_calc.c | 41 const dml_uint_t pipe_idx) in dml_rq_dlg_get_rq_reg() argument
43 dml_uint_t plane_idx = dml_get_plane_idx(mode_lib, pipe_idx); in dml_rq_dlg_get_rq_reg()
71 dml_print("DML_DLG::%s: Calculation for pipe[%d] start\n", __func__, pipe_idx); in dml_rq_dlg_get_rq_reg()
84 dpte_group_bytes = (dml_uint_t)(dml_get_dpte_group_size_in_bytes(mode_lib, pipe_idx)); in dml_rq_dlg_get_rq_reg()
85 mpte_group_bytes = (dml_uint_t)(dml_get_vm_group_size_in_bytes(mode_lib, pipe_idx)); in dml_rq_dlg_get_rq_reg()
128 detile_buf_size_in_bytes = (dml_uint_t)(dml_get_det_buffer_size_kbytes(mode_lib, pipe_idx) * 1024); in dml_rq_dlg_get_rq_reg()
130 pte_row_height_linear = (dml_uint_t)(dml_get_dpte_row_height_linear_l(mode_lib, pipe_idx)); in dml_rq_dlg_get_rq_reg()
138 …nt_t p1_pte_row_height_linear = (dml_uint_t)(dml_get_dpte_row_height_linear_c(mode_lib, pipe_idx)); in dml_rq_dlg_get_rq_reg()
145 …_l.swath_height = (dml_uint_t)(dml_log2((dml_float_t) dml_get_swath_height_l(mode_lib, pipe_idx))); in dml_rq_dlg_get_rq_reg()
146 …_c.swath_height = (dml_uint_t)(dml_log2((dml_float_t) dml_get_swath_height_c(mode_lib, pipe_idx))); in dml_rq_dlg_get_rq_reg()
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| H A D | dml2_dc_resource_mgmt.c | 132 …_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assig… in find_master_pipe_of_plane()
155 ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[pipe->pipe_idx], in find_pipes_assigned_to_plane()
163 pipes[num_found++] = mpc_pipe->pipe_idx; in find_pipes_assigned_to_plane()
278 if (head_pipe && head_pipe->pipe_idx == i) in find_preferred_pipe_candidates()
319 if (head_pipe && head_pipe->pipe_idx == i) in find_last_resort_pipe_candidates()
331 static bool is_pipe_in_candidate_array(const unsigned int pipe_idx, in is_pipe_in_candidate_array() argument
338 if (candidate_array[i] == pipe_idx) in is_pipe_in_candidate_array()
375 pipe->pipe_idx = (uint8_t)preferred_pipe_candidates[i]; in find_more_pipes_for_stream()
376 assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx; in find_more_pipes_for_stream()
392 pipe->pipe_idx = (uint8_t)i; in find_more_pipes_for_stream()
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| H A D | display_mode_util.c | 771 dml_uint_t dml_get_plane_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx) in dml_get_plane_idx() argument
773 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_plane_idx()
779 dml_uint_t pipe_idx = 0; in dml_get_pipe_idx() local
786 pipe_idx = i; in dml_get_pipe_idx()
793 return pipe_idx; in dml_get_pipe_idx()
798 dml_uint_t pipe_idx = 0; in dml_calc_pipe_plane_mapping() local
806 pipe_plane[pipe_idx] = plane_idx; in dml_calc_pipe_plane_mapping()
807 pipe_idx++; in dml_calc_pipe_plane_mapping()
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| H A D | dml2_utils.c | 240 …rams_from_dml(struct pipe_ctx *pipe_ctx, struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx) in populate_pipe_ctx_dlg_params_from_dml() argument
253 pipe_ctx->pipe_dlg_param.vstartup_start = dml_get_vstartup_calculated(mode_lib, pipe_idx); in populate_pipe_ctx_dlg_params_from_dml()
254 pipe_ctx->pipe_dlg_param.vupdate_offset = dml_get_vupdate_offset(mode_lib, pipe_idx); in populate_pipe_ctx_dlg_params_from_dml()
255 pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx); in populate_pipe_ctx_dlg_params_from_dml()
256 pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx); in populate_pipe_ctx_dlg_params_from_dml()
308 …g.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) { in dml2_calculate_rq_and_dlg_params()
526 …_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id)) in dml2_verify_det_buffer_configuration()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 338 uint32_t i, pipe_idx; in dcn32_helper_populate_phantom_dlg_params() local
342 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_populate_phantom_dlg_params()
349 pipes[pipe_idx].pipe.dest.vstartup_start = in dcn32_helper_populate_phantom_dlg_params()
350 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
351 pipes[pipe_idx].pipe.dest.vupdate_offset = in dcn32_helper_populate_phantom_dlg_params()
352 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
353 pipes[pipe_idx].pipe.dest.vupdate_width = in dcn32_helper_populate_phantom_dlg_params()
354 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
355 pipes[pipe_idx].pipe.dest.vready_offset = in dcn32_helper_populate_phantom_dlg_params()
356 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
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| H A D | display_rq_dlg_calc_32.h | 48 const unsigned int pipe_idx);
68 const unsigned int pipe_idx);
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1365 int pipe_idx) in dcn20_acquire_dsc() argument
1369 …struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_r… in dcn20_acquire_dsc()
1376 *dsc = pool->dscs[pipe_idx]; in dcn20_acquire_dsc()
1377 res_ctx->is_dsc_acquired[pipe_idx] = true; in dcn20_acquire_dsc()
1521 int pipe_idx = next_odm_pipe->pipe_idx; in dcn20_split_stream_for_odm() local
1526 next_odm_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_odm()
1527 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1528 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1529 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1530 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_lib.h | 57 const unsigned int pipe_idx,
75 const unsigned int pipe_idx);
80 const unsigned int pipe_idx);
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| H A D | display_mode_vba.c | 258 int pipe_idx = -1; in get_pipe_idx() local
265 pipe_idx = i; in get_pipe_idx()
269 ASSERT(pipe_idx >= 0); in get_pipe_idx()
271 return pipe_idx; in get_pipe_idx()
276 unsigned int num_pipes, unsigned int pipe_idx) in get_det_buffer_size_kbytes() argument
282 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_det_buffer_size_kbytes()
284 …dml_print("DML::%s: num_pipes=%d pipe_idx=%d plane_idx=%0d\n", __func__, num_pipes, pipe_idx, plan… in get_det_buffer_size_kbytes()
293 unsigned int num_pipes, unsigned int pipe_idx) in get_is_phantom_pipe() argument
298 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_is_phantom_pipe()
299 …nt("DML::%s: num_pipes=%d pipe_idx=%d UseMALLForPStateChange=%0d\n", __func__, num_pipes, pipe_idx, in get_is_phantom_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 488 int i, pipe_idx, total_det = 0, active_hubp_count = 0; in dcn31_calculate_wm_and_dlg_fp() local
537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
544 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
545 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn31_calculate_wm_and_dlg_fp()
548 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
549 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
551 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
552 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
553 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
554 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
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| H A D | display_rq_dlg_calc_31.h | 62 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1146 int i, pipe_idx, active_hubp_count = 0; in dcn20_calculate_dlg_params() local
1179 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1184 …pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pip… in dcn20_calculate_dlg_params()
1185 …pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cn… in dcn20_calculate_dlg_params()
1186 …pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn20_calculate_dlg_params()
1187 …pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn20_calculate_dlg_params()
1195 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; in dcn20_calculate_dlg_params()
1198 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn20_calculate_dlg_params()
1199 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn20_calculate_dlg_params()
1201 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn20_calculate_dlg_params()
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| H A D | display_rq_dlg_calc_20.h | 66 const unsigned int pipe_idx,
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| H A D | display_rq_dlg_calc_20v2.h | 66 const unsigned int pipe_idx,
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| H A D | dcn20_fpu.h | 72 int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1561 int pipe_idx = sec_pipe->pipe_idx; in dcn30_split_stream_for_mpc_or_odm() local
1566 sec_pipe->pipe_idx = pipe_idx; in dcn30_split_stream_for_mpc_or_odm()
1567 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1568 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1569 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1570 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1571 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1572 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
1592 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1596 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); in dcn30_split_stream_for_mpc_or_odm()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1660 pipe_ctx->pipe_idx, in resource_build_scaling_params()
1801 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in resource_find_free_secondary_pipe_legacy()
1804 secondary_pipe->pipe_idx = preferred_pipe_idx; in resource_find_free_secondary_pipe_legacy()
1816 secondary_pipe->pipe_idx = i; in resource_find_free_secondary_pipe_legacy()
1835 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx]; in resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master()
1837 free_pipe_idx = cur_sec_opp_head->pipe_idx; in resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master()
1861 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx]; in resource_find_free_pipe_used_in_cur_mpc_blending_tree()
1863 free_pipe_idx = cur_sec_dpp->pipe_idx; in resource_find_free_pipe_used_in_cur_mpc_blending_tree()
2022 struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx]; in resource_get_opp_heads_for_otg_master()
2047 struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx]; in resource_get_dpp_pipes_for_opp_head()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 807 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
854 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
863 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()
871 pipe_idx++; in dcn21_fast_validate_bw()
878 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
885 pipe_idx++; in dcn21_fast_validate_bw()
887 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
894 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; in dcn21_fast_validate_bw()
911 …djust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); in dcn21_fast_validate_bw()
915 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 2681 cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx]; in dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe()
2740 primary_index = primary_pipe->pipe_idx; in find_idle_secondary_pipe_check_mpo()
2746 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in find_idle_secondary_pipe_check_mpo()
2748 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { in find_idle_secondary_pipe_check_mpo()
2750 secondary_pipe->pipe_idx = preferred_pipe_idx; in find_idle_secondary_pipe_check_mpo()
2761 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { in find_idle_secondary_pipe_check_mpo()
2763 secondary_pipe->pipe_idx = i; in find_idle_secondary_pipe_check_mpo()
2793 head_index = head_pipe->pipe_idx; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2795 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2796 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.h | 66 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_rq_dlg_calc_314.h | 63 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.h | 62 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_utils.c | 403 unsigned int pipe_idx = 0; in dml2_core_utils_pipe_plane_mapping() local
411 pipe_plane[pipe_idx] = plane_idx; in dml2_core_utils_pipe_plane_mapping()
412 pipe_idx++; in dml2_core_utils_pipe_plane_mapping()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1578 pipe_ctx[pipe_ctx->pipe_idx]; in dce110_enable_stream_timing()
1678 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); in dce110_apply_single_controller_ctx_to_hw()
1869 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; in disable_vga_and_power_gate_all_controllers()
2292 uint32_t *pipe_idx) in should_enable_fbc() argument
2316 if (pipe_ctx->pipe_idx != underlay_idx) { in should_enable_fbc()
2317 *pipe_idx = i; in should_enable_fbc()
2359 uint32_t pipe_idx = 0; in enable_fbc() local
2361 if (should_enable_fbc(dc, context, &pipe_idx)) { in enable_fbc()
2365 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in enable_fbc()
3099 pipe_ctx->pipe_idx, in dce110_program_front_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 1055 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
1056 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
1057 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
1058 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn201_acquire_free_pipe_for_layer()
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