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Searched refs:pipe_config (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_mst.c599 struct intel_crtc_state *pipe_config, in mst_stream_compute_config() argument
604 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in mst_stream_compute_config()
609 &pipe_config->hw.adjusted_mode; in mst_stream_compute_config()
615 if (pipe_config->fec_enable && in mst_stream_compute_config()
616 !intel_dp_supports_fec(intel_dp, connector, pipe_config)) in mst_stream_compute_config()
626 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe); in mst_stream_compute_config()
628 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in mst_stream_compute_config()
629 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in mst_stream_compute_config()
630 pipe_config->has_pch_encoder = false; in mst_stream_compute_config()
636 pipe_config, false, &limits); in mst_stream_compute_config()
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H A Dintel_dp.c1622 const struct intel_crtc_state *pipe_config) in intel_dp_source_supports_fec() argument
1631 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) in intel_dp_source_supports_fec()
1639 const struct intel_crtc_state *pipe_config) in intel_dp_supports_fec() argument
1641 return intel_dp_source_supports_fec(intel_dp, pipe_config) && in intel_dp_supports_fec()
1759 struct intel_crtc_state *pipe_config, in intel_dp_compute_link_config_wide() argument
1763 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); in intel_dp_compute_link_config_wide()
1770 intel_dp_output_format_link_bpp_x16(pipe_config->output_format, bpp); in intel_dp_compute_link_config_wide()
1782 &pipe_config->hw.adjusted_mode; in intel_dp_compute_link_config_wide()
1793 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide()
1794 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
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H A Dintel_dvo.c162 struct intel_crtc_state *pipe_config) in intel_dvo_get_config() argument
168 pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); in intel_dvo_get_config()
180 pipe_config->hw.adjusted_mode.flags |= flags; in intel_dvo_get_config()
182 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
202 const struct intel_crtc_state *pipe_config, in intel_enable_dvo() argument
210 &pipe_config->hw.mode, in intel_enable_dvo()
211 &pipe_config->hw.adjusted_mode); in intel_enable_dvo()
255 struct intel_crtc_state *pipe_config, in intel_dvo_compute_config() argument
260 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dvo_compute_config()
281 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dvo_compute_config()
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H A Dintel_display.c2854 struct intel_crtc_state *pipe_config) in intel_get_transcoder_timings() argument
2857 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_get_transcoder_timings()
2858 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_get_transcoder_timings()
2891 if (intel_pipe_is_interlaced(pipe_config)) { in intel_get_transcoder_timings()
2898 pipe_config->set_context_latency = in intel_get_transcoder_timings()
2903 pipe_config->set_context_latency; in intel_get_transcoder_timings()
2912 pipe_config->set_context_latency = in intel_get_transcoder_timings()
2917 pipe_config->min_hblank = intel_de_read(display, in intel_get_transcoder_timings()
2939 struct intel_crtc_state *pipe_config) in intel_get_pipe_src_size() argument
2946 drm_rect_init(&pipe_config->pipe_src, 0, 0, in intel_get_pipe_src_size()
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H A Dicl_dsi.c296 const struct intel_crtc_state *pipe_config) in configure_dual_link_mode() argument
305 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in configure_dual_link_mode()
321 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
701 const struct intel_crtc_state *pipe_config) in gen11_dsi_configure_transcoder() argument
705 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_configure_transcoder()
721 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { in gen11_dsi_configure_transcoder()
747 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
815 configure_dual_link_mode(encoder, pipe_config); in gen11_dsi_configure_transcoder()
1220 const struct intel_crtc_state *pipe_config, in gen11_dsi_pre_enable() argument
1224 gen11_dsi_map_pll(encoder, pipe_config); in gen11_dsi_pre_enable()
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H A Dvlv_dsi.c271 struct intel_crtc_state *pipe_config, in intel_dsi_compute_config() argument
277 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_compute_config()
281 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
282 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
288 ret = intel_pfit_compute_config(pipe_config, conn_state); in intel_dsi_compute_config()
299 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
301 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
305 pipe_config->mode_flags |= in intel_dsi_compute_config()
310 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
312 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
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H A Dintel_tv.c929 const struct intel_crtc_state *pipe_config, in intel_enable_tv() argument
935 intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc)); in intel_enable_tv()
1092 struct intel_crtc_state *pipe_config) in intel_tv_get_config() argument
1096 &pipe_config->hw.adjusted_mode; in intel_tv_get_config()
1104 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); in intel_tv_get_config()
1126 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1153 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); in intel_tv_get_config()
1169 pipe_config->mode_flags |= in intel_tv_get_config()
1191 struct intel_crtc_state *pipe_config, in intel_tv_compute_config() argument
1196 to_intel_atomic_state(pipe_config->uapi.state); in intel_tv_compute_config()
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H A Dintel_sdvo.c1282 static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) in i9xx_adjust_sdvo_tv_clock() argument
1284 struct intel_display *display = to_intel_display(pipe_config); in i9xx_adjust_sdvo_tv_clock()
1285 unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; in i9xx_adjust_sdvo_tv_clock()
1286 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
1310 pipe_config->clock_set = true; in i9xx_adjust_sdvo_tv_clock()
1358 struct intel_crtc_state *pipe_config, in intel_sdvo_compute_config() argument
1365 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_sdvo_compute_config()
1366 struct drm_display_mode *mode = &pipe_config->hw.mode; in intel_sdvo_compute_config()
1369 pipe_config->has_pch_encoder = true; in intel_sdvo_compute_config()
1370 if (!intel_link_bw_compute_pipe_bpp(pipe_config)) in intel_sdvo_compute_config()
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H A Dintel_hdcp.c2432 const struct intel_crtc_state *pipe_config, in _intel_hdcp_enable() argument
2452 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { in _intel_hdcp_enable()
2453 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; in _intel_hdcp_enable()
2454 hdcp->stream_transcoder = pipe_config->cpu_transcoder; in _intel_hdcp_enable()
2456 hdcp->cpu_transcoder = pipe_config->cpu_transcoder; in _intel_hdcp_enable()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c609 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; in populate_subvp_cmd_drr_info()
610 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping in populate_subvp_cmd_drr_info()
611 …pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for… in populate_subvp_cmd_drr_info()
642 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; in populate_subvp_cmd_drr_info()
643 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; in populate_subvp_cmd_drr_info()
644 …pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_st… in populate_subvp_cmd_drr_info()
688 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; in populate_subvp_cmd_vblank_pipe_info()
689 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - in populate_subvp_cmd_vblank_pipe_info()
691 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; in populate_subvp_cmd_vblank_pipe_info()
692 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; in populate_subvp_cmd_vblank_pipe_info()
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H A Ddc_hw_types.h407 unsigned int pipe_config; member
/linux/drivers/usb/renesas_usbhs/
H A Dpipe.c477 struct renesas_usbhs_driver_pipe_config *pipe_config = in usbhsp_setup_pipebuff() local
489 buff_size = pipe_config->bufsize; in usbhsp_setup_pipebuff()
490 bufnmb = pipe_config->bufnum; in usbhsp_setup_pipebuff()
507 struct renesas_usbhs_driver_pipe_config *pipe_config = in usbhs_pipe_config_update() local
509 u16 dblb = pipe_config->double_buf ? DBLB : 0; in usbhs_pipe_config_update()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_mem_input.c457 GRPH_PIPE_CONFIG, info->gfx8.pipe_config, in program_tiling()
474 GRPH_PIPE_CONFIG, info->gfx8.pipe_config, in program_tiling()
/linux/drivers/net/wireless/ath/ath10k/
H A Dpci.c2373 ar_pci->pipe_config, in ath10k_pci_init_config()
2483 config = &ar_pci->pipe_config[5]; in ath10k_pci_override_ce_config()
3475 ar_pci->pipe_config = kmemdup(pci_target_ce_config_wlan, in ath10k_pci_setup_resource()
3478 if (!ar_pci->pipe_config) { in ath10k_pci_setup_resource()
3506 kfree(ar_pci->pipe_config); in ath10k_pci_setup_resource()
3521 kfree(ar_pci->pipe_config); in ath10k_pci_release_resource()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_mem_input_v.c188 set_reg_field_value(value, info->gfx8.pipe_config, in program_tiling()
/linux/drivers/staging/media/atomisp/pci/
H A Dsh_css.c126 struct ia_css_pipe_config pipe_config[IA_CSS_PIPE_ID_NUM]; member
4325 struct ia_css_pipe_config *pipe_config) in sh_css_pipe_get_shading_info() argument
4340 shading_info, pipe_config); in sh_css_pipe_get_shading_info()
7455 void ia_css_pipe_config_defaults(struct ia_css_pipe_config *pipe_config) in ia_css_pipe_config_defaults() argument
7458 memcpy(pipe_config, &ia_css_pipe_default_config, sizeof(*pipe_config)); in ia_css_pipe_config_defaults()
8175 my_css_save.stream_seeds[i].pipe_config[j] = pipes[j]->config; in ia_css_stream_create()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c1799 u32 pipe_config; in dce_v8_0_crtc_do_set_base() local
1832 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1934 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); in dce_v8_0_crtc_do_set_base()
H A Ddce_v6_0.c1888 uint32_t fb_format, fb_pitch_pixels, pipe_config; in dce_v6_0_crtc_do_set_base() local
2021 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
2022 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); in dce_v6_0_crtc_do_set_base()
H A Ddce_v10_0.c1852 u32 pipe_config; in dce_v10_0_crtc_do_set_base() local
1885 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
2001 pipe_config); in dce_v10_0_crtc_do_set_base()
/linux/drivers/staging/media/atomisp/pci/runtime/binary/src/
H A Dbinary.c275 struct ia_css_pipe_config *pipe_config) /* [out] */ in ia_css_binary_get_shading_info() argument
/linux/drivers/staging/media/ipu3/
H A Dipu3-css.c1021 sp_group->pipe[pipe].pipe_config = in imgu_css_pipeline_init()
1023 sp_group->pipe[pipe].pipe_config |= IMGU_ABI_PIPE_CONFIG_ACQUIRE_ISP; in imgu_css_pipeline_init()
H A Dipu3-abi.h1781 u32 pipe_config; /* the pipe config */ member
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c210 tiling_info->gfx8.pipe_config = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h2254 } pipe_config; member