| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 993 int pipe_cnt, i; in dcn20_populate_dml_writeback_from_context() local
997 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
1004 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
1005 pipes[pipe_cnt].dout.num_active_wb++; in dcn20_populate_dml_writeback_from_context()
1006 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
1007 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
1008 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
1009 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
1010 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
1011 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
[all …]
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| H A D | dcn20_fpu.h | 38 int pipe_cnt, int i);
42 int pipe_cnt,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 446 int pipe_cnt) in dcn31_zero_pipe_dcc_fraction() argument
450 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; in dcn31_zero_pipe_dcc_fraction()
451 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; in dcn31_zero_pipe_dcc_fraction()
485 int pipe_cnt, in dcn31_calculate_wm_and_dlg_fp() argument
501 if (pipe_cnt == 0) { in dcn31_calculate_wm_and_dlg_fp()
511 get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
513 …if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_tim… in dcn31_calculate_wm_and_dlg_fp()
523 …bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
524 …state_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
525 …a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| H A D | dcn31_fpu.h | 36 int pipe_cnt);
44 int pipe_cnt,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 278 int pipe_cnt, in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
293 …dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMIN… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
336 int pipe_cnt) in dcn32_helper_populate_phantom_dlg_params() argument
350 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
352 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
354 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
356 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
471 unsigned int pipe_cnt, in dcn32_set_phantom_stream_timing() argument
515 …phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe… in dcn32_set_phantom_stream_timing()
527 phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_set_phantom_stream_timing()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1702 int i, pipe_cnt, crb_idx, crb_pipes; in dcn315_populate_dml_pipes_from_context() local
1713 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) { in dcn315_populate_dml_pipes_from_context()
1726 pipes[pipe_cnt].pipe.src.immediate_flip = true; in dcn315_populate_dml_pipes_from_context()
1728 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; in dcn315_populate_dml_pipes_from_context()
1729 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; in dcn315_populate_dml_pipes_from_context()
1730 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn315_populate_dml_pipes_from_context()
1731 pipes[pipe_cnt].dout.dsc_input_bpc = 0; in dcn315_populate_dml_pipes_from_context()
1733 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); in dcn315_populate_dml_pipes_from_context()
1735 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format); in dcn315_populate_dml_pipes_from_context()
1750 pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate; in dcn315_populate_dml_pipes_from_context()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1653 uint32_t pipe_cnt; in dcn31x_populate_dml_pipes_from_context() local
1658 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); in dcn31x_populate_dml_pipes_from_context()
1660 for (i = 0; i < pipe_cnt; i++) { in dcn31x_populate_dml_pipes_from_context()
1670 return pipe_cnt; in dcn31x_populate_dml_pipes_from_context()
1678 int i, pipe_cnt; in dcn31_populate_dml_pipes_from_context() local
1687 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_populate_dml_pipes_from_context()
1704 pipes[pipe_cnt].pipe.src.immediate_flip = true; in dcn31_populate_dml_pipes_from_context()
1705 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; in dcn31_populate_dml_pipes_from_context()
1706 pipes[pipe_cnt].pipe.src.gpuvm = true; in dcn31_populate_dml_pipes_from_context()
1707 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; in dcn31_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1727 unsigned int pipe_cnt, in dcn32_enable_phantom_stream() argument
1742 …dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_id… in dcn32_enable_phantom_stream()
1754 unsigned int pipe_cnt, in dcn32_add_phantom_pipes() argument
1763 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); in dcn32_add_phantom_pipes()
1793 int pipe_cnt = 0; in dml1_validate() local
1811 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode); in dml1_validate()
1814 if (pipe_cnt == 0) in dml1_validate()
1827 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dml1_validate()
1911 int i, pipe_cnt; in dcn32_populate_dml_pipes_from_context() local
1944 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1647 int i, pipe_cnt; in dcn316_populate_dml_pipes_from_context() local
1656 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn316_populate_dml_pipes_from_context()
1669 pipes[pipe_cnt].pipe.src.immediate_flip = true; in dcn316_populate_dml_pipes_from_context()
1671 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; in dcn316_populate_dml_pipes_from_context()
1672 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; in dcn316_populate_dml_pipes_from_context()
1673 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn316_populate_dml_pipes_from_context()
1674 pipes[pipe_cnt].dout.dsc_input_bpc = 0; in dcn316_populate_dml_pipes_from_context()
1676 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); in dcn316_populate_dml_pipes_from_context()
1679 if (pipes[pipe_cnt].dout.dsc_enable) { in dcn316_populate_dml_pipes_from_context()
1682 pipes[pipe_cnt].dout.dsc_input_bpc = 8; in dcn316_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1358 int i, pipe_cnt; in dcn30_populate_dml_pipes_from_context() local
1365 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1369 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth = in dcn30_populate_dml_pipes_from_context()
1373 return pipe_cnt; in dcn30_populate_dml_pipes_from_context()
1411 int pipe_cnt) in dcn30_set_mcif_arb_params() argument
1441 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j); in dcn30_set_mcif_arb_params()
1672 int pipe_cnt, i, pipe_idx, vlevel = 0; in dcn30_internal_validate_bw() local
1685 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); in dcn30_internal_validate_bw()
1687 if (!pipe_cnt) { in dcn30_internal_validate_bw()
1692 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.h | 39 int pipe_cnt,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_lib.h | 106 int pipe_cnt);
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| /linux/drivers/usb/host/ |
| H A D | r8a66597.h | 79 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE]; member
120 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE]; member
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| H A D | r8a66597-hcd.c | 689 if (r8a66597->pipe_cnt[min] > r8a66597->pipe_cnt[array[i]]) in get_empty_pipenum()
806 r8a66597->pipe_cnt[pipe->info.pipenum]++; in enable_r8a66597_pipe()
807 dev->pipe_cnt[pipe->info.pipenum]++; in enable_r8a66597_pipe()
868 if (!dev->pipe_cnt[pipenum]) in disable_r8a66597_pipe_all()
876 r8a66597->pipe_cnt[pipenum] -= dev->pipe_cnt[pipenum]; in disable_r8a66597_pipe_all()
877 dev->pipe_cnt[pipenum] = 0; in disable_r8a66597_pipe_all()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 807 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
815 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); in dcn21_fast_validate_bw()
817 *pipe_cnt_out = pipe_cnt; in dcn21_fast_validate_bw()
819 if (!pipe_cnt) { in dcn21_fast_validate_bw()
830 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
844 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1706 int pipe_cnt; in dcn314_populate_dml_pipes_from_context() local
1709 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode); in dcn314_populate_dml_pipes_from_context()
1712 return pipe_cnt; in dcn314_populate_dml_pipes_from_context()
1740 int pipe_cnt = 0; in dcn314_validate_bandwidth() local
1752 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false); in dcn314_validate_bandwidth()
1756 if (pipe_cnt == 0) in dcn314_validate_bandwidth()
1769 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn314_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_wrapper_fpu.c | 52 struct dml2_context *in_ctx, unsigned int pipe_cnt) in dml21_calculate_rq_and_dlg_params() argument
55 (void)pipe_cnt; in dml21_calculate_rq_and_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1635 int pipe_cnt) in dcn20_set_mcif_arb_params() argument
1664 dcn20_fpu_set_wb_arb_params(wb_arb_params, context, pipes, pipe_cnt, i); in dcn20_set_mcif_arb_params()
2067 int pipe_cnt, i, pipe_idx, vlevel; in dcn20_fast_validate_bw() local
2075 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); in dcn20_fast_validate_bw()
2077 *pipe_cnt_out = pipe_cnt; in dcn20_fast_validate_bw()
2079 if (!pipe_cnt) { in dcn20_fast_validate_bw()
2084 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn20_fast_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_utils.c | 280 …ext, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt) in dml2_calculate_rq_and_dlg_params() argument
299 for (dc_pipe_ctx_index = 0; dc_pipe_ctx_index < pipe_cnt; dc_pipe_ctx_index++) { in dml2_calculate_rq_and_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 1410 int pipe_cnt, in dcn301_calculate_wm_and_dlg() argument
1414 dcn301_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel_req); in dcn301_calculate_wm_and_dlg()
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