Home
last modified time | relevance | path

Searched refs:phyclk (Results 1 – 15 of 15) sorted by relevance

/linux/arch/arm/mach-s3c/
H A Dsetup-usb-phy-s3c64xx.c26 u32 phyclk; in s3c_usb_otgphy_init() local
31 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; in s3c_usb_otgphy_init()
37 phyclk |= S3C_PHYCLK_CLKSEL_12M; in s3c_usb_otgphy_init()
40 phyclk |= S3C_PHYCLK_CLKSEL_24M; in s3c_usb_otgphy_init()
51 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); in s3c_usb_otgphy_init()
/linux/drivers/phy/samsung/
H A Dphy-exynos5250-sata.c50 struct clk *phyclk; member
196 sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl"); in exynos_sata_phy_probe()
197 if (IS_ERR(sata_phy->phyclk)) { in exynos_sata_phy_probe()
199 ret = PTR_ERR(sata_phy->phyclk); in exynos_sata_phy_probe()
203 ret = clk_prepare_enable(sata_phy->phyclk); in exynos_sata_phy_probe()
228 clk_disable_unprepare(sata_phy->phyclk); in exynos_sata_phy_probe()
/linux/drivers/phy/freescale/
H A Dphy-fsl-samsung-hdmi.c615 struct clk *phyclk; in phy_clk_register() local
628 phyclk = devm_clk_register(dev, &phy->hw); in phy_clk_register()
629 if (IS_ERR(phyclk)) in phy_clk_register()
630 return dev_err_probe(dev, PTR_ERR(phyclk), in phy_clk_register()
633 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, phyclk); in phy_clk_register()
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi.c245 struct clk *phyclk; member
681 ret = clk_prepare_enable(inno->phyclk); in inno_hdmi_phy_power_on()
687 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_on()
703 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_off()
1064 inno->phyclk = devm_clk_register(dev, &inno->hw); in inno_hdmi_phy_clk_register()
1065 if (IS_ERR(inno->phyclk)) { in inno_hdmi_phy_clk_register()
1066 ret = PTR_ERR(inno->phyclk); in inno_hdmi_phy_clk_register()
1071 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk); in inno_hdmi_phy_clk_register()
/linux/Documentation/devicetree/bindings/net/
H A Dsti-dwmac.txt20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,flexgen.txt125 "clk-eth-ref-phyclk",
/linux/arch/arm/boot/dts/st/
H A Dstih407-pinctrl.dtsi218 phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
260 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
281 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
287 phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
/linux/arch/arm/boot/dts/rockchip/
H A Drk3188.dtsi657 clock-names = "phyclk";
665 clock-names = "phyclk";
H A Drk3066a.dtsi715 clock-names = "phyclk";
723 clock-names = "phyclk";
H A Drk322x.dtsi259 clock-names = "phyclk";
286 clock-names = "phyclk";
H A Drv1108.dtsi265 clock-names = "phyclk";
H A Drk3128.dtsi564 clock-names = "phyclk";
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3308.dtsi204 clock-names = "phyclk";
H A Drk3328.dtsi913 clock-names = "phyclk";
H A Dpx30.dtsi873 clock-names = "phyclk";