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Searched refs:phase_offset (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/dpll/zl3073x/
H A Ddpll.c55 s64 phase_offset; member
388 void *dpll_priv, s64 *phase_offset, in zl3073x_dpll_input_pin_phase_offset_get() argument
412 *phase_offset = 0; in zl3073x_dpll_input_pin_phase_offset_get()
416 ref_phase = pin->phase_offset; in zl3073x_dpll_input_pin_phase_offset_get()
438 *phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER; in zl3073x_dpll_input_pin_phase_offset_get()
1651 s64 phase_offset; in zl3073x_dpll_pin_phase_offset_check() local
1674 rc = zl3073x_read_u48(zldev, reg, &phase_offset); in zl3073x_dpll_pin_phase_offset_check()
1683 phase_offset = div_s64(sign_extend64(phase_offset, 47), 100); in zl3073x_dpll_pin_phase_offset_check()
1686 if (phase_offset != pin->phase_offset) { in zl3073x_dpll_pin_phase_offset_check()
1688 pin->label, pin->phase_offset, phase_offset); in zl3073x_dpll_pin_phase_offset_check()
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.h51 s64 phase_offset; member
84 s64 phase_offset; member
H A Dice_dpll.c1826 s64 *phase_offset, struct netlink_ext_ack *extack) in ice_dpll_phase_offset_get() argument
1835 *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; in ice_dpll_phase_offset_get()
1837 *phase_offset = p->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; in ice_dpll_phase_offset_get()
1839 *phase_offset = 0; in ice_dpll_phase_offset_get()
2488 if (d->prev_phase_offset != d->phase_offset) { in ice_dpll_notify_changes()
2489 d->prev_phase_offset = d->phase_offset; in ice_dpll_notify_changes()
2559 s64 phase_offset, tmp; in ice_dpll_pps_update_phase_offsets() local
2576 phase_offset = 0; in ice_dpll_pps_update_phase_offsets()
2578 tmp = meas[i].phase_offset[j]; in ice_dpll_pps_update_phase_offsets()
2580 phase_offset += tmp << 8 * j; in ice_dpll_pps_update_phase_offsets()
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H A Dice_ptp_hw.h365 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
H A Dice_common.c5553 u8 *dpll_state, u8 *config, s64 *phase_offset, in ice_aq_get_cgu_dpll_status() argument
5569 *phase_offset = le32_to_cpu(cmd->phase_offset_h); in ice_aq_get_cgu_dpll_status()
5570 *phase_offset <<= 32; in ice_aq_get_cgu_dpll_status()
5571 *phase_offset += le32_to_cpu(cmd->phase_offset_l); in ice_aq_get_cgu_dpll_status()
5572 *phase_offset = sign_extend64(*phase_offset, 47); in ice_aq_get_cgu_dpll_status()
H A Dice_ptp_hw.c5810 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, in ice_get_cgu_state() argument
5826 if (phase_offset) in ice_get_cgu_state()
5827 *phase_offset = hw_phase_offset; in ice_get_cgu_state()
/linux/drivers/dpll/
H A Ddpll_netlink.c346 s64 phase_offset; in dpll_msg_add_phase_offset() local
352 dpll, dpll_priv(dpll), &phase_offset, in dpll_msg_add_phase_offset()
356 if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset), in dpll_msg_add_phase_offset()
357 &phase_offset, DPLL_A_PIN_PAD)) in dpll_msg_add_phase_offset()