1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ALPHA_TSUNAMI__H__ 3 #define __ALPHA_TSUNAMI__H__ 4 5 #include <linux/types.h> 6 #include <asm/compiler.h> 7 8 /* 9 * TSUNAMI/TYPHOON are the internal names for the core logic chipset which 10 * provides memory controller and PCI access for the 21264 based systems. 11 * 12 * This file is based on: 13 * 14 * Tsunami System Programmers Manual 15 * Preliminary, Chapters 2-5 16 * 17 */ 18 19 /* XXX: Do we need to conditionalize on this? */ 20 #ifdef USE_48_BIT_KSEG 21 #define TS_BIAS 0x80000000000UL 22 #else 23 #define TS_BIAS 0x10000000000UL 24 #endif 25 26 /* 27 * CChip, DChip, and PChip registers 28 */ 29 30 typedef struct { 31 volatile unsigned long csr __attribute__((aligned(64))); 32 } tsunami_64; 33 34 typedef struct { 35 tsunami_64 csc; 36 tsunami_64 mtr; 37 tsunami_64 misc; 38 tsunami_64 mpd; 39 tsunami_64 aar0; 40 tsunami_64 aar1; 41 tsunami_64 aar2; 42 tsunami_64 aar3; 43 tsunami_64 dim0; 44 tsunami_64 dim1; 45 tsunami_64 dir0; 46 tsunami_64 dir1; 47 tsunami_64 drir; 48 tsunami_64 prben; 49 tsunami_64 iic; /* a.k.a. iic0 */ 50 tsunami_64 wdr; /* a.k.a. iic1 */ 51 tsunami_64 mpr0; 52 tsunami_64 mpr1; 53 tsunami_64 mpr2; 54 tsunami_64 mpr3; 55 tsunami_64 mctl; 56 tsunami_64 __pad1; 57 tsunami_64 ttr; 58 tsunami_64 tdr; 59 tsunami_64 dim2; 60 tsunami_64 dim3; 61 tsunami_64 dir2; 62 tsunami_64 dir3; 63 tsunami_64 iic2; 64 tsunami_64 iic3; 65 } tsunami_cchip; 66 67 typedef struct { 68 tsunami_64 dsc; 69 tsunami_64 str; 70 tsunami_64 drev; 71 } tsunami_dchip; 72 73 typedef struct { 74 tsunami_64 wsba[4]; 75 tsunami_64 wsm[4]; 76 tsunami_64 tba[4]; 77 tsunami_64 pctl; 78 tsunami_64 plat; 79 tsunami_64 reserved; 80 tsunami_64 perror; 81 tsunami_64 perrmask; 82 tsunami_64 perrset; 83 tsunami_64 tlbiv; 84 tsunami_64 tlbia; 85 tsunami_64 pmonctl; 86 tsunami_64 pmoncnt; 87 } tsunami_pchip; 88 89 #define TSUNAMI_cchip ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL)) 90 #define TSUNAMI_dchip ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL)) 91 #define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL)) 92 #define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL)) 93 extern int TSUNAMI_bootcpu; 94 95 /* 96 * TSUNAMI Pchip Error register. 97 */ 98 99 #define perror_m_lost 0x1 100 #define perror_m_serr 0x2 101 #define perror_m_perr 0x4 102 #define perror_m_dcrto 0x8 103 #define perror_m_sge 0x10 104 #define perror_m_ape 0x20 105 #define perror_m_ta 0x40 106 #define perror_m_rdpe 0x80 107 #define perror_m_nds 0x100 108 #define perror_m_uecc 0x400 109 #define perror_m_cre 0x800 110 #define perror_m_addrl 0xFFFFFFFF0000UL 111 #define perror_m_addrh 0x7000000000000UL 112 #define perror_m_cmd 0xF0000000000000UL 113 #define perror_m_syn 0xFF00000000000000UL 114 union TPchipPERROR { 115 struct { 116 unsigned int perror_v_lost : 1; 117 unsigned perror_v_serr : 1; 118 unsigned perror_v_perr : 1; 119 unsigned perror_v_dcrto : 1; 120 unsigned perror_v_sge : 1; 121 unsigned perror_v_ape : 1; 122 unsigned perror_v_ta : 1; 123 unsigned perror_v_rdpe : 1; 124 unsigned perror_v_nds : 1; 125 unsigned perror_v_reserved : 1; /* PERROR<9>: MBZ, RAZ */ 126 unsigned perror_v_uecc : 1; 127 unsigned perror_v_cre : 1; 128 unsigned perror_v_rsvd1 : 4; 129 unsigned perror_v_addrl : 32; 130 unsigned perror_v_addrh : 3; 131 unsigned perror_v_rsvd2 : 1; 132 unsigned perror_v_cmd : 4; 133 unsigned perror_v_syn : 8; 134 } perror_r_bits; 135 int perror_q_whole [2]; 136 }; 137 138 /* 139 * TSUNAMI Pchip Window Space Base Address register. 140 */ 141 #define wsba_m_ena 0x1 142 #define wsba_m_sg 0x2 143 #define wsba_m_ptp 0x4 144 #define wsba_m_addr 0xFFF00000 145 #define wmask_k_sz1gb 0x3FF00000 146 union TPchipWSBA { 147 struct { 148 unsigned wsba_v_ena : 1; 149 unsigned wsba_v_sg : 1; 150 unsigned wsba_v_ptp : 1; 151 unsigned wsba_v_rsvd1 : 17; 152 unsigned wsba_v_addr : 12; 153 unsigned wsba_v_rsvd2 : 32; 154 } wsba_r_bits; 155 int wsba_q_whole [2]; 156 }; 157 158 /* 159 * TSUNAMI Pchip Control Register 160 */ 161 #define pctl_m_fdsc 0x1 162 #define pctl_m_fbtb 0x2 163 #define pctl_m_thdis 0x4 164 #define pctl_m_chaindis 0x8 165 #define pctl_m_tgtlat 0x10 166 #define pctl_m_hole 0x20 167 #define pctl_m_mwin 0x40 168 #define pctl_m_arbena 0x80 169 #define pctl_m_prigrp 0x7F00 170 #define pctl_m_ppri 0x8000 171 #define pctl_m_rsvd1 0x30000 172 #define pctl_m_eccen 0x40000 173 #define pctl_m_padm 0x80000 174 #define pctl_m_cdqmax 0xF00000 175 #define pctl_m_rev 0xFF000000 176 #define pctl_m_crqmax 0xF00000000UL 177 #define pctl_m_ptpmax 0xF000000000UL 178 #define pctl_m_pclkx 0x30000000000UL 179 #define pctl_m_fdsdis 0x40000000000UL 180 #define pctl_m_fdwdis 0x80000000000UL 181 #define pctl_m_ptevrfy 0x100000000000UL 182 #define pctl_m_rpp 0x200000000000UL 183 #define pctl_m_pid 0xC00000000000UL 184 #define pctl_m_rsvd2 0xFFFF000000000000UL 185 186 union TPchipPCTL { 187 struct { 188 unsigned pctl_v_fdsc : 1; 189 unsigned pctl_v_fbtb : 1; 190 unsigned pctl_v_thdis : 1; 191 unsigned pctl_v_chaindis : 1; 192 unsigned pctl_v_tgtlat : 1; 193 unsigned pctl_v_hole : 1; 194 unsigned pctl_v_mwin : 1; 195 unsigned pctl_v_arbena : 1; 196 unsigned pctl_v_prigrp : 7; 197 unsigned pctl_v_ppri : 1; 198 unsigned pctl_v_rsvd1 : 2; 199 unsigned pctl_v_eccen : 1; 200 unsigned pctl_v_padm : 1; 201 unsigned pctl_v_cdqmax : 4; 202 unsigned pctl_v_rev : 8; 203 unsigned pctl_v_crqmax : 4; 204 unsigned pctl_v_ptpmax : 4; 205 unsigned pctl_v_pclkx : 2; 206 unsigned pctl_v_fdsdis : 1; 207 unsigned pctl_v_fdwdis : 1; 208 unsigned pctl_v_ptevrfy : 1; 209 unsigned pctl_v_rpp : 1; 210 unsigned pctl_v_pid : 2; 211 unsigned pctl_v_rsvd2 : 16; 212 } pctl_r_bits; 213 int pctl_q_whole [2]; 214 }; 215 216 /* 217 * TSUNAMI Pchip Error Mask Register. 218 */ 219 #define perrmask_m_lost 0x1 220 #define perrmask_m_serr 0x2 221 #define perrmask_m_perr 0x4 222 #define perrmask_m_dcrto 0x8 223 #define perrmask_m_sge 0x10 224 #define perrmask_m_ape 0x20 225 #define perrmask_m_ta 0x40 226 #define perrmask_m_rdpe 0x80 227 #define perrmask_m_nds 0x100 228 #define perrmask_m_rto 0x200 229 #define perrmask_m_uecc 0x400 230 #define perrmask_m_cre 0x800 231 #define perrmask_m_rsvd 0xFFFFFFFFFFFFF000UL 232 union TPchipPERRMASK { 233 struct { 234 unsigned int perrmask_v_lost : 1; 235 unsigned perrmask_v_serr : 1; 236 unsigned perrmask_v_perr : 1; 237 unsigned perrmask_v_dcrto : 1; 238 unsigned perrmask_v_sge : 1; 239 unsigned perrmask_v_ape : 1; 240 unsigned perrmask_v_ta : 1; 241 unsigned perrmask_v_rdpe : 1; 242 unsigned perrmask_v_nds : 1; 243 unsigned perrmask_v_rto : 1; 244 unsigned perrmask_v_uecc : 1; 245 unsigned perrmask_v_cre : 1; 246 unsigned perrmask_v_rsvd1 : 20; 247 unsigned perrmask_v_rsvd2 : 32; 248 } perrmask_r_bits; 249 int perrmask_q_whole [2]; 250 }; 251 252 /* 253 * Memory spaces: 254 */ 255 #define TSUNAMI_HOSE(h) (((unsigned long)(h)) << 33) 256 #define TSUNAMI_BASE (IDENT_ADDR + TS_BIAS) 257 258 #define TSUNAMI_MEM(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x000000000UL) 259 #define _TSUNAMI_IACK_SC(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1F8000000UL) 260 #define TSUNAMI_IO(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FC000000UL) 261 #define TSUNAMI_CONF(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FE000000UL) 262 263 #define TSUNAMI_IACK_SC _TSUNAMI_IACK_SC(0) /* hack! */ 264 265 266 /* 267 * The canonical non-remaped I/O and MEM addresses have these values 268 * subtracted out. This is arranged so that folks manipulating ISA 269 * devices can use their familiar numbers and have them map to bus 0. 270 */ 271 272 #define TSUNAMI_IO_BIAS TSUNAMI_IO(0) 273 #define TSUNAMI_MEM_BIAS TSUNAMI_MEM(0) 274 275 /* The IO address space is larger than 0xffff */ 276 #define TSUNAMI_IO_SPACE (TSUNAMI_CONF(0) - TSUNAMI_IO(0)) 277 278 /* Offset between ram physical addresses and pci64 DAC bus addresses. */ 279 #define TSUNAMI_DAC_OFFSET (1UL << 40) 280 281 /* 282 * Data structure for handling TSUNAMI machine checks: 283 */ 284 struct el_TSUNAMI_sysdata_mcheck { 285 u64 sesf; 286 u64 dir; 287 u64 misc; 288 u64 p0_perror; 289 u64 p1_perror; 290 }; 291 292 293 #ifdef __KERNEL__ 294 295 #ifndef __EXTERN_INLINE 296 #define __EXTERN_INLINE extern inline 297 #define __IO_EXTERN_INLINE 298 #endif 299 300 /* 301 * I/O functions: 302 * 303 * TSUNAMI, the 21??? PCI/memory support chipset for the EV6 (21264) 304 * can only use linear accesses to get at PCI memory and I/O spaces. 305 */ 306 307 /* 308 * Memory functions. all accesses are done through linear space. 309 */ 310 extern void __iomem *tsunami_ioportmap(unsigned long addr); 311 extern void __iomem *tsunami_ioremap(unsigned long addr, unsigned long size); tsunami_is_ioaddr(unsigned long addr)312__EXTERN_INLINE int tsunami_is_ioaddr(unsigned long addr) 313 { 314 return addr >= TSUNAMI_BASE; 315 } 316 tsunami_is_mmio(const volatile void __iomem * xaddr)317__EXTERN_INLINE int tsunami_is_mmio(const volatile void __iomem *xaddr) 318 { 319 unsigned long addr = (unsigned long) xaddr; 320 return (addr & 0x100000000UL) == 0; 321 } 322 323 #undef __IO_PREFIX 324 #define __IO_PREFIX tsunami 325 #define tsunami_trivial_rw_bw 1 326 #define tsunami_trivial_rw_lq 1 327 #define tsunami_trivial_io_bw 1 328 #define tsunami_trivial_io_lq 1 329 #define tsunami_trivial_iounmap 1 330 #include <asm/io_trivial.h> 331 332 #ifdef __IO_EXTERN_INLINE 333 #undef __EXTERN_INLINE 334 #undef __IO_EXTERN_INLINE 335 #endif 336 337 #endif /* __KERNEL__ */ 338 339 #endif /* __ALPHA_TSUNAMI__H__ */ 340