1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_CORE_H__ 7 #define __INTEL_DISPLAY_CORE_H__ 8 9 #include <linux/list.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/types.h> 13 #include <linux/wait.h> 14 #include <linux/workqueue.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_modeset_lock.h> 18 19 #include "intel_cdclk.h" 20 #include "intel_display_device.h" 21 #include "intel_display_limits.h" 22 #include "intel_display_params.h" 23 #include "intel_display_power.h" 24 #include "intel_dmc_wl.h" 25 #include "intel_dpll_mgr.h" 26 #include "intel_fbc.h" 27 #include "intel_global_state.h" 28 #include "intel_gmbus.h" 29 #include "intel_opregion.h" 30 #include "intel_pch.h" 31 #include "intel_wm_types.h" 32 33 struct drm_property; 34 struct drm_property_blob; 35 struct i915_audio_component; 36 struct i915_hdcp_arbiter; 37 struct intel_atomic_state; 38 struct intel_audio_funcs; 39 struct intel_cdclk_funcs; 40 struct intel_cdclk_vals; 41 struct intel_color_funcs; 42 struct intel_crtc; 43 struct intel_crtc_state; 44 struct intel_display_parent_interface; 45 struct intel_dmc; 46 struct intel_dpll_global_funcs; 47 struct intel_dpll_mgr; 48 struct intel_fbdev; 49 struct intel_fdi_funcs; 50 struct intel_hotplug_funcs; 51 struct intel_initial_plane_config; 52 struct intel_opregion; 53 struct intel_overlay; 54 struct task_struct; 55 56 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 57 #define I915_NUM_QGV_POINTS 8 58 59 /* Amount of PSF GV points, BSpec precisely defines this */ 60 #define I915_NUM_PSF_GV_POINTS 3 61 62 struct intel_display_funcs { 63 /* 64 * Returns the active state of the crtc, and if the crtc is active, 65 * fills out the pipe-config with the hw state. 66 */ 67 bool (*get_pipe_config)(struct intel_crtc *, 68 struct intel_crtc_state *); 69 void (*get_initial_plane_config)(struct intel_crtc *, 70 struct intel_initial_plane_config *); 71 bool (*fixup_initial_plane_config)(struct intel_crtc *crtc, 72 const struct intel_initial_plane_config *plane_config); 73 void (*crtc_enable)(struct intel_atomic_state *state, 74 struct intel_crtc *crtc); 75 void (*crtc_disable)(struct intel_atomic_state *state, 76 struct intel_crtc *crtc); 77 void (*commit_modeset_enables)(struct intel_atomic_state *state); 78 }; 79 80 /* functions used for watermark calcs for display. */ 81 struct intel_wm_funcs { 82 /* update_wm is for legacy wm management */ 83 void (*update_wm)(struct intel_display *display); 84 int (*compute_watermarks)(struct intel_atomic_state *state, 85 struct intel_crtc *crtc); 86 void (*initial_watermarks)(struct intel_atomic_state *state, 87 struct intel_crtc *crtc); 88 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 89 struct intel_crtc *crtc); 90 void (*optimize_watermarks)(struct intel_atomic_state *state, 91 struct intel_crtc *crtc); 92 int (*compute_global_watermarks)(struct intel_atomic_state *state); 93 void (*get_hw_state)(struct intel_display *display); 94 void (*sanitize)(struct intel_display *display); 95 }; 96 97 struct intel_audio_state { 98 struct intel_encoder *encoder; 99 u8 eld[MAX_ELD_BYTES]; 100 }; 101 102 struct intel_audio { 103 /* hda/i915 audio component */ 104 struct i915_audio_component *component; 105 bool component_registered; 106 /* mutex for audio/video sync */ 107 struct mutex mutex; 108 int power_refcount; 109 u32 freq_cntrl; 110 111 /* current audio state for the audio component hooks */ 112 struct intel_audio_state state[I915_MAX_TRANSCODERS]; 113 114 /* necessary resource sharing with HDMI LPE audio driver. */ 115 struct { 116 struct platform_device *platdev; 117 int irq; 118 } lpe; 119 }; 120 121 /* 122 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 123 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per 124 * dpll, because on some platforms plls share registers. 125 */ 126 struct intel_dpll_global { 127 struct mutex lock; 128 129 int num_dpll; 130 struct intel_dpll dplls[I915_NUM_PLLS]; 131 const struct intel_dpll_mgr *mgr; 132 133 struct { 134 int nssc; 135 int ssc; 136 } ref_clks; 137 138 /* 139 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id. 140 */ 141 u8 pch_ssc_use; 142 }; 143 144 struct intel_frontbuffer_tracking { 145 /* protects busy_bits */ 146 spinlock_t lock; 147 148 /* 149 * Tracking bits for delayed frontbuffer flushing due to gpu activity. 150 */ 151 unsigned busy_bits; 152 }; 153 154 struct intel_hotplug { 155 struct delayed_work hotplug_work; 156 157 const u32 *hpd, *pch_hpd; 158 159 struct { 160 unsigned long last_jiffies; 161 int count; 162 int blocked_count; 163 enum { 164 HPD_ENABLED = 0, 165 HPD_DISABLED = 1, 166 HPD_MARK_DISABLED = 2 167 } state; 168 } stats[HPD_NUM_PINS]; 169 u32 event_bits; 170 u32 retry_bits; 171 struct delayed_work reenable_work; 172 173 u32 long_hpd_pin_mask; 174 u32 short_hpd_pin_mask; 175 struct work_struct dig_port_work; 176 177 struct work_struct poll_init_work; 178 bool poll_enabled; 179 180 /* 181 * Queuing of hotplug_work, reenable_work and poll_init_work is 182 * enabled. Protected by intel_display::irq::lock. 183 */ 184 bool detection_work_enabled; 185 186 unsigned int hpd_storm_threshold; 187 /* Whether or not to count short HPD IRQs in HPD storms */ 188 u8 hpd_short_storm_enabled; 189 190 /* Last state reported by oob_hotplug_event for each encoder */ 191 unsigned long oob_hotplug_last_state; 192 193 /* 194 * if we get a HPD irq from DP and a HPD irq from non-DP 195 * the non-DP HPD could block the workqueue on a mode config 196 * mutex getting, that userspace may have taken. However 197 * userspace is waiting on the DP workqueue to run which is 198 * blocked behind the non-DP one. 199 */ 200 struct workqueue_struct *dp_wq; 201 202 /* 203 * Flag to track if long HPDs need not to be processed 204 * 205 * Some panels generate long HPDs while keep connected to the port. 206 * This can cause issues with CI tests results. In CI systems we 207 * don't expect to disconnect the panels and could ignore the long 208 * HPDs generated from the faulty panels. This flag can be used as 209 * cue to ignore the long HPDs and can be set / unset using debugfs. 210 */ 211 bool ignore_long_hpd; 212 }; 213 214 struct intel_vbt_data { 215 /* bdb version */ 216 u16 version; 217 218 /* Feature bits */ 219 unsigned int int_tv_support:1; 220 unsigned int int_crt_support:1; 221 unsigned int lvds_use_ssc:1; 222 unsigned int int_lvds_support:1; 223 unsigned int display_clock_mode:1; 224 unsigned int fdi_rx_polarity_inverted:1; 225 int lvds_ssc_freq; 226 enum drm_panel_orientation orientation; 227 228 bool override_afc_startup; 229 u8 override_afc_startup_val; 230 231 int crt_ddc_pin; 232 233 struct list_head display_devices; 234 struct list_head bdb_blocks; 235 236 struct sdvo_device_mapping { 237 u8 initialized; 238 u8 dvo_port; 239 u8 target_addr; 240 u8 dvo_wiring; 241 u8 i2c_pin; 242 u8 ddc_pin; 243 } sdvo_mappings[2]; 244 }; 245 246 struct intel_wm { 247 /* 248 * Raw watermark latency values: 249 * in 0.1us units for WM0, 250 * in 0.5us units for WM1+. 251 */ 252 /* primary */ 253 u16 pri_latency[5]; 254 /* sprite */ 255 u16 spr_latency[5]; 256 /* cursor */ 257 u16 cur_latency[5]; 258 /* 259 * Raw watermark memory latency values 260 * for SKL for all 8 levels 261 * in 1us units. 262 */ 263 u16 skl_latency[8]; 264 265 /* current hardware state */ 266 union { 267 struct ilk_wm_values hw; 268 struct vlv_wm_values vlv; 269 struct g4x_wm_values g4x; 270 }; 271 272 u8 num_levels; 273 274 /* 275 * Should be held around atomic WM register writing; also 276 * protects * intel_crtc->wm.active and 277 * crtc_state->wm.need_postvbl_update. 278 */ 279 struct mutex wm_mutex; 280 281 bool ipc_enabled; 282 }; 283 284 struct intel_display { 285 /* drm device backpointer */ 286 struct drm_device *drm; 287 288 /* Platform (and subplatform, if any) identification */ 289 struct intel_display_platforms platform; 290 291 /* Intel PCH: where the south display engine lives */ 292 enum intel_pch pch_type; 293 294 /* Parent, or core, driver functions exposed to display */ 295 const struct intel_display_parent_interface *parent; 296 297 /* list of all intel_crtcs sorted by pipe */ 298 struct list_head pipe_list; 299 300 /* Display functions */ 301 struct { 302 /* Top level crtc-ish functions */ 303 const struct intel_display_funcs *display; 304 305 /* Display CDCLK functions */ 306 const struct intel_cdclk_funcs *cdclk; 307 308 /* Display pll funcs */ 309 const struct intel_dpll_global_funcs *dpll; 310 311 /* irq display functions */ 312 const struct intel_hotplug_funcs *hotplug; 313 314 /* pm display functions */ 315 const struct intel_wm_funcs *wm; 316 317 /* fdi display functions */ 318 const struct intel_fdi_funcs *fdi; 319 320 /* Display internal color functions */ 321 const struct intel_color_funcs *color; 322 323 /* Display internal audio functions */ 324 const struct intel_audio_funcs *audio; 325 } funcs; 326 327 struct { 328 bool any_task_allowed; 329 struct task_struct *allowed_task; 330 } access; 331 332 struct { 333 /* backlight registers and fields in struct intel_panel */ 334 struct mutex lock; 335 } backlight; 336 337 struct { 338 struct intel_global_obj obj; 339 340 struct intel_bw_info { 341 /* for each QGV point */ 342 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 343 /* for each PSF GV point */ 344 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 345 /* Peak BW for each QGV point */ 346 unsigned int peakbw[I915_NUM_QGV_POINTS]; 347 u8 num_qgv_points; 348 u8 num_psf_gv_points; 349 u8 num_planes; 350 } max[6]; 351 } bw; 352 353 struct { 354 /* The current hardware cdclk configuration */ 355 struct intel_cdclk_config hw; 356 357 /* cdclk, divider, and ratio table from bspec */ 358 const struct intel_cdclk_vals *table; 359 360 struct intel_global_obj obj; 361 362 unsigned int max_cdclk_freq; 363 unsigned int max_dotclk_freq; 364 unsigned int skl_preferred_vco_freq; 365 } cdclk; 366 367 struct { 368 struct drm_property_blob *glk_linear_degamma_lut; 369 } color; 370 371 struct { 372 /* The current hardware dbuf configuration */ 373 u8 enabled_slices; 374 375 struct intel_global_obj obj; 376 } dbuf; 377 378 struct { 379 struct intel_global_obj obj; 380 } dbuf_bw; 381 382 struct { 383 /* 384 * dkl.phy_lock protects against concurrent access of the 385 * Dekel TypeC PHYs. 386 */ 387 spinlock_t phy_lock; 388 } dkl; 389 390 struct { 391 struct intel_dmc *dmc; 392 struct ref_tracker *wakeref; 393 } dmc; 394 395 struct { 396 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 397 u32 mmio_base; 398 } dsi; 399 400 struct { 401 const struct dram_info *info; 402 } dram; 403 404 struct { 405 struct intel_fbc *instances[I915_MAX_FBCS]; 406 407 /* xe3p_lpd+: FBC instance utilizing the system cache */ 408 struct sys_cache_cfg { 409 /* Protect concurrecnt access to system cache configuration */ 410 struct mutex lock; 411 enum intel_fbc_id id; 412 } sys_cache; 413 } fbc; 414 415 struct { 416 /* list of fbdev register on this device */ 417 struct intel_fbdev *fbdev; 418 } fbdev; 419 420 struct { 421 unsigned int pll_freq; 422 u32 rx_config; 423 } fdi; 424 425 struct { 426 struct list_head obj_list; 427 } global; 428 429 struct { 430 /* 431 * Base address of where the gmbus and gpio blocks are located 432 * (either on PCH or on SoC for platforms without PCH). 433 */ 434 u32 mmio_base; 435 436 /* 437 * gmbus.mutex protects against concurrent usage of the single 438 * hw gmbus controller on different i2c buses. 439 */ 440 struct mutex mutex; 441 442 struct intel_gmbus *bus[GMBUS_NUM_PINS]; 443 444 wait_queue_head_t wait_queue; 445 } gmbus; 446 447 struct { 448 struct i915_hdcp_arbiter *arbiter; 449 bool comp_added; 450 451 /* 452 * HDCP message struct for allocation of memory which can be 453 * reused when sending message to gsc cs. 454 * this is only populated post Meteorlake 455 */ 456 struct intel_hdcp_gsc_context *gsc_context; 457 /* Mutex to protect the above hdcp related values. */ 458 struct mutex hdcp_mutex; 459 } hdcp; 460 461 struct { 462 /* 463 * HTI (aka HDPORT) state read during initial hw readout. Most 464 * platforms don't have HTI, so this will just stay 0. Those 465 * that do will use this later to figure out which PLLs and PHYs 466 * are unavailable for driver usage. 467 */ 468 u32 state; 469 } hti; 470 471 struct { 472 /* Access with DISPLAY_INFO() */ 473 const struct intel_display_device_info *__device_info; 474 475 /* Access with DISPLAY_RUNTIME_INFO() */ 476 struct intel_display_runtime_info __runtime_info; 477 } info; 478 479 struct { 480 bool false_color; 481 } ips; 482 483 struct { 484 /* protects the irq masks */ 485 spinlock_t lock; 486 487 /* 488 * Most platforms treat the display irq block as an always-on 489 * power domain. vlv/chv can disable it at runtime and need 490 * special care to avoid writing any of the display block 491 * registers outside of the power domain. We defer setting up 492 * the display irqs in this case to the runtime pm. 493 */ 494 bool vlv_display_irqs_enabled; 495 496 /* For i915gm/i945gm vblank irq workaround */ 497 u8 vblank_enabled; 498 499 int vblank_enable_count; 500 bool vblank_status_last_notified; 501 502 struct work_struct vblank_notify_work; 503 504 /* 505 * Cached value of VLV/CHV IMR to avoid reads in updating the 506 * bitfield. 507 */ 508 u32 vlv_imr_mask; 509 /* 510 * Cached value of gen 5-7 DE IMR to avoid reads in updating the 511 * bitfield. 512 */ 513 u32 ilk_de_imr_mask; 514 /* 515 * Cached value of BDW+ DE pipe IMR to avoid reads in updating 516 * the bitfield. 517 */ 518 u32 de_pipe_imr_mask[I915_MAX_PIPES]; 519 u32 pipestat_irq_mask[I915_MAX_PIPES]; 520 } irq; 521 522 struct { 523 /* protected by wm.wm_mutex */ 524 u16 linetime[I915_MAX_PIPES]; 525 bool disable[I915_MAX_PIPES]; 526 } pkgc; 527 528 struct { 529 wait_queue_head_t waitqueue; 530 531 /* mutex to protect pmdemand programming sequence */ 532 struct mutex lock; 533 534 struct intel_global_obj obj; 535 } pmdemand; 536 537 struct { 538 struct i915_power_domains domains; 539 540 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 541 u32 chv_phy_control; 542 543 /* perform PHY state sanity checks? */ 544 bool chv_phy_assert[2]; 545 } power; 546 547 struct { 548 u32 mmio_base; 549 550 /* protects panel power sequencer state */ 551 struct mutex mutex; 552 } pps; 553 554 struct { 555 struct drm_property *broadcast_rgb; 556 struct drm_property *force_audio; 557 } properties; 558 559 struct { 560 unsigned long mask; 561 } quirks; 562 563 struct { 564 /* restore state for suspend/resume and display reset */ 565 struct drm_atomic_state *modeset_state; 566 struct drm_modeset_acquire_ctx reset_ctx; 567 /* modeset stuck tracking for reset */ 568 atomic_t pending_fb_pin; 569 u32 saveDSPARB; 570 u32 saveSWF0[16]; 571 u32 saveSWF1[16]; 572 u32 saveSWF3[3]; 573 u16 saveGCDGMBUS; 574 } restore; 575 576 struct { 577 enum { 578 I915_SAGV_UNKNOWN = 0, 579 I915_SAGV_DISABLED, 580 I915_SAGV_ENABLED, 581 I915_SAGV_NOT_CONTROLLED 582 } status; 583 584 u32 block_time_us; 585 } sagv; 586 587 struct { 588 /* LPT/WPT IOSF sideband protection */ 589 struct mutex lock; 590 } sbi; 591 592 struct { 593 /* 594 * DG2: Mask of PHYs that were not calibrated by the firmware 595 * and should not be used. 596 */ 597 u8 phy_failed_calibration; 598 } snps; 599 600 struct { 601 /* 602 * Shadows for CHV DPLL_MD regs to keep the state 603 * checker somewhat working in the presence hardware 604 * crappiness (can't read out DPLL_MD for pipes B & C). 605 */ 606 u32 chv_dpll_md[I915_MAX_PIPES]; 607 u32 bxt_phy_grc; 608 } state; 609 610 struct { 611 unsigned int hpll_freq; 612 unsigned int czclk_freq; 613 } vlv_clock; 614 615 struct { 616 /* ordered wq for modesets */ 617 struct workqueue_struct *modeset; 618 619 /* unbound hipri wq for page flips/plane updates */ 620 struct workqueue_struct *flip; 621 622 /* hipri wq for commit cleanups */ 623 struct workqueue_struct *cleanup; 624 625 /* unordered workqueue for all display unordered work */ 626 struct workqueue_struct *unordered; 627 } wq; 628 629 /* Grouping using named structs. Keep sorted. */ 630 struct drm_dp_tunnel_mgr *dp_tunnel_mgr; 631 struct intel_audio audio; 632 struct intel_dpll_global dpll; 633 struct intel_frontbuffer_tracking fb_tracking; 634 struct intel_hotplug hotplug; 635 struct intel_opregion *opregion; 636 struct intel_overlay *overlay; 637 struct intel_display_params params; 638 struct intel_vbt_data vbt; 639 struct intel_dmc_wl wl; 640 struct intel_wm wm; 641 642 struct work_struct psr_dc5_dc6_wa_work; 643 }; 644 645 #endif /* __INTEL_DISPLAY_CORE_H__ */ 646