xref: /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef _VEGA20_HWMGR_H_
25 #define _VEGA20_HWMGR_H_
26 
27 #include "hwmgr.h"
28 #include "smu11_driver_if.h"
29 #include "ppatomfwctrl.h"
30 
31 #define VEGA20_MAX_HARDWARE_POWERLEVELS 2
32 
33 #define WaterMarksExist  1
34 #define WaterMarksLoaded 2
35 
36 #define VG20_PSUEDO_NUM_GFXCLK_DPM_LEVELS   8
37 #define VG20_PSUEDO_NUM_SOCCLK_DPM_LEVELS   8
38 #define VG20_PSUEDO_NUM_DCEFCLK_DPM_LEVELS  8
39 #define VG20_PSUEDO_NUM_UCLK_DPM_LEVELS     4
40 
41 //OverDriver8 macro defs
42 #define AVFS_CURVE 0
43 #define OD8_HOTCURVE_TEMPERATURE 85
44 
45 #define VG20_CLOCK_MAX_DEFAULT 0xFFFF
46 
47 typedef uint32_t PP_Clock;
48 
49 enum {
50 	GNLD_DPM_PREFETCHER = 0,
51 	GNLD_DPM_GFXCLK,
52 	GNLD_DPM_UCLK,
53 	GNLD_DPM_SOCCLK,
54 	GNLD_DPM_UVD,
55 	GNLD_DPM_VCE,
56 	GNLD_ULV,
57 	GNLD_DPM_MP0CLK,
58 	GNLD_DPM_LINK,
59 	GNLD_DPM_DCEFCLK,
60 	GNLD_DS_GFXCLK,
61 	GNLD_DS_SOCCLK,
62 	GNLD_DS_LCLK,
63 	GNLD_PPT,
64 	GNLD_TDC,
65 	GNLD_THERMAL,
66 	GNLD_GFX_PER_CU_CG,
67 	GNLD_RM,
68 	GNLD_DS_DCEFCLK,
69 	GNLD_ACDC,
70 	GNLD_VR0HOT,
71 	GNLD_VR1HOT,
72 	GNLD_FW_CTF,
73 	GNLD_LED_DISPLAY,
74 	GNLD_FAN_CONTROL,
75 	GNLD_DIDT,
76 	GNLD_GFXOFF,
77 	GNLD_CG,
78 	GNLD_DPM_FCLK,
79 	GNLD_DS_FCLK,
80 	GNLD_DS_MP1CLK,
81 	GNLD_DS_MP0CLK,
82 	GNLD_XGMI,
83 	GNLD_ECC,
84 
85 	GNLD_FEATURES_MAX
86 };
87 
88 
89 #define GNLD_DPM_MAX    (GNLD_DPM_DCEFCLK + 1)
90 
91 #define SMC_DPM_FEATURES    0x30F
92 
93 struct smu_features {
94 	bool supported;
95 	bool enabled;
96 	bool allowed;
97 	uint32_t smu_feature_id;
98 	uint64_t smu_feature_bitmap;
99 };
100 
101 struct vega20_performance_level {
102 	uint32_t  soc_clock;
103 	uint32_t  gfx_clock;
104 	uint32_t  mem_clock;
105 };
106 
107 struct vega20_bacos {
108 	uint32_t                       baco_flags;
109 	/* struct vega20_performance_level  performance_level; */
110 };
111 
112 struct vega20_uvd_clocks {
113 	uint32_t  vclk;
114 	uint32_t  dclk;
115 };
116 
117 struct vega20_vce_clocks {
118 	uint32_t  evclk;
119 	uint32_t  ecclk;
120 };
121 
122 struct vega20_power_state {
123 	uint32_t                  magic;
124 	struct vega20_uvd_clocks    uvd_clks;
125 	struct vega20_vce_clocks    vce_clks;
126 	uint16_t                  performance_level_count;
127 	bool                      dc_compatible;
128 	uint32_t                  sclk_threshold;
129 	struct vega20_performance_level  performance_levels[VEGA20_MAX_HARDWARE_POWERLEVELS];
130 };
131 
132 struct vega20_dpm_level {
133 	bool		enabled;
134 	uint32_t	value;
135 	uint32_t	param1;
136 };
137 
138 #define VEGA20_MAX_DEEPSLEEP_DIVIDER_ID 5
139 #define MAX_REGULAR_DPM_NUMBER 16
140 #define MAX_PCIE_CONF 2
141 #define VEGA20_MINIMUM_ENGINE_CLOCK 2500
142 
143 struct vega20_max_sustainable_clocks {
144 	PP_Clock display_clock;
145 	PP_Clock phy_clock;
146 	PP_Clock pixel_clock;
147 	PP_Clock uclock;
148 	PP_Clock dcef_clock;
149 	PP_Clock soc_clock;
150 };
151 
152 struct vega20_dpm_state {
153 	uint32_t  soft_min_level;
154 	uint32_t  soft_max_level;
155 	uint32_t  hard_min_level;
156 	uint32_t  hard_max_level;
157 };
158 
159 struct vega20_single_dpm_table {
160 	uint32_t		count;
161 	struct vega20_dpm_state	dpm_state;
162 	struct vega20_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
163 };
164 
165 struct vega20_odn_dpm_control {
166 	uint32_t	count;
167 	uint32_t	entries[MAX_REGULAR_DPM_NUMBER];
168 };
169 
170 struct vega20_pcie_table {
171 	uint16_t count;
172 	uint8_t  pcie_gen[MAX_PCIE_CONF];
173 	uint8_t  pcie_lane[MAX_PCIE_CONF];
174 	uint32_t lclk[MAX_PCIE_CONF];
175 };
176 
177 struct vega20_dpm_table {
178 	struct vega20_single_dpm_table  soc_table;
179 	struct vega20_single_dpm_table  gfx_table;
180 	struct vega20_single_dpm_table  mem_table;
181 	struct vega20_single_dpm_table  eclk_table;
182 	struct vega20_single_dpm_table  vclk_table;
183 	struct vega20_single_dpm_table  dclk_table;
184 	struct vega20_single_dpm_table  dcef_table;
185 	struct vega20_single_dpm_table  pixel_table;
186 	struct vega20_single_dpm_table  display_table;
187 	struct vega20_single_dpm_table  phy_table;
188 	struct vega20_single_dpm_table  fclk_table;
189 	struct vega20_pcie_table        pcie_table;
190 };
191 
192 #define VEGA20_MAX_LEAKAGE_COUNT  8
193 struct vega20_leakage_voltage {
194 	uint16_t  count;
195 	uint16_t  leakage_id[VEGA20_MAX_LEAKAGE_COUNT];
196 	uint16_t  actual_voltage[VEGA20_MAX_LEAKAGE_COUNT];
197 };
198 
199 struct vega20_display_timing {
200 	uint32_t  min_clock_in_sr;
201 	uint32_t  num_existing_displays;
202 };
203 
204 struct vega20_dpmlevel_enable_mask {
205 	uint32_t  uvd_dpm_enable_mask;
206 	uint32_t  vce_dpm_enable_mask;
207 	uint32_t  samu_dpm_enable_mask;
208 	uint32_t  sclk_dpm_enable_mask;
209 	uint32_t  mclk_dpm_enable_mask;
210 };
211 
212 struct vega20_vbios_boot_state {
213 	uint8_t     uc_cooling_id;
214 	uint16_t    vddc;
215 	uint16_t    vddci;
216 	uint16_t    mvddc;
217 	uint16_t    vdd_gfx;
218 	uint32_t    gfx_clock;
219 	uint32_t    mem_clock;
220 	uint32_t    soc_clock;
221 	uint32_t    dcef_clock;
222 	uint32_t    eclock;
223 	uint32_t    dclock;
224 	uint32_t    vclock;
225 	uint32_t    fclock;
226 };
227 
228 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
229 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
230 #define DPMTABLE_UPDATE_SCLK        0x00000004
231 #define DPMTABLE_UPDATE_MCLK        0x00000008
232 #define DPMTABLE_OD_UPDATE_VDDC     0x00000010
233 #define DPMTABLE_OD_UPDATE_SCLK_MASK     0x00000020
234 #define DPMTABLE_OD_UPDATE_MCLK_MASK     0x00000040
235 
236 // To determine if sclk and mclk are in overdrive state
237 #define SCLK_MASK_OVERDRIVE_ENABLED      0x00000008
238 #define MCLK_MASK_OVERDRIVE_ENABLED      0x00000010
239 #define SOCCLK_OVERDRIVE_ENABLED         0x00000020
240 
241 struct vega20_smc_state_table {
242 	uint32_t        soc_boot_level;
243 	uint32_t        gfx_boot_level;
244 	uint32_t        dcef_boot_level;
245 	uint32_t        mem_boot_level;
246 	uint32_t        uvd_boot_level;
247 	uint32_t        vce_boot_level;
248 	uint32_t        gfx_max_level;
249 	uint32_t        mem_max_level;
250 	uint8_t         vr_hot_gpio;
251 	uint8_t         ac_dc_gpio;
252 	uint8_t         therm_out_gpio;
253 	uint8_t         therm_out_polarity;
254 	uint8_t         therm_out_mode;
255 	PPTable_t       pp_table;
256 	Watermarks_t    water_marks_table;
257 	AvfsDebugTable_t avfs_debug_table;
258 	AvfsFuseOverride_t avfs_fuse_override_table;
259 	SmuMetrics_t    smu_metrics;
260 	DriverSmuConfig_t driver_smu_config;
261 	DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
262 	OverDriveTable_t overdrive_table;
263 };
264 
265 struct vega20_mclk_latency_entries {
266 	uint32_t  frequency;
267 	uint32_t  latency;
268 };
269 
270 struct vega20_mclk_latency_table {
271 	uint32_t  count;
272 	struct vega20_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
273 };
274 
275 struct vega20_registry_data {
276 	uint64_t  disallowed_features;
277 	uint8_t   ac_dc_switch_gpio_support;
278 	uint8_t   acg_loop_support;
279 	uint8_t   clock_stretcher_support;
280 	uint8_t   db_ramping_support;
281 	uint8_t   didt_mode;
282 	uint8_t   didt_support;
283 	uint8_t   edc_didt_support;
284 	uint8_t   force_dpm_high;
285 	uint8_t   fuzzy_fan_control_support;
286 	uint8_t   mclk_dpm_key_disabled;
287 	uint8_t   od_state_in_dc_support;
288 	uint8_t   pcie_lane_override;
289 	uint8_t   pcie_speed_override;
290 	uint32_t  pcie_clock_override;
291 	uint8_t   pcie_dpm_key_disabled;
292 	uint8_t   dcefclk_dpm_key_disabled;
293 	uint8_t   prefetcher_dpm_key_disabled;
294 	uint8_t   quick_transition_support;
295 	uint8_t   regulator_hot_gpio_support;
296 	uint8_t   master_deep_sleep_support;
297 	uint8_t   gfx_clk_deep_sleep_support;
298 	uint8_t   sclk_deep_sleep_support;
299 	uint8_t   lclk_deep_sleep_support;
300 	uint8_t   dce_fclk_deep_sleep_support;
301 	uint8_t   sclk_dpm_key_disabled;
302 	uint8_t   sclk_throttle_low_notification;
303 	uint8_t   skip_baco_hardware;
304 	uint8_t   socclk_dpm_key_disabled;
305 	uint8_t   sq_ramping_support;
306 	uint8_t   tcp_ramping_support;
307 	uint8_t   td_ramping_support;
308 	uint8_t   dbr_ramping_support;
309 	uint8_t   gc_didt_support;
310 	uint8_t   psm_didt_support;
311 	uint8_t   thermal_support;
312 	uint8_t   fw_ctf_enabled;
313 	uint8_t   led_dpm_enabled;
314 	uint8_t   fan_control_support;
315 	uint8_t   ulv_support;
316 	uint8_t   od8_feature_enable;
317 	uint8_t   disable_water_mark;
318 	uint8_t   disable_workload_policy;
319 	uint32_t  force_workload_policy_mask;
320 	uint8_t   disable_3d_fs_detection;
321 	uint8_t   disable_pp_tuning;
322 	uint8_t   disable_xlpp_tuning;
323 	uint32_t  perf_ui_tuning_profile_turbo;
324 	uint32_t  perf_ui_tuning_profile_powerSave;
325 	uint32_t  perf_ui_tuning_profile_xl;
326 	uint16_t  zrpm_stop_temp;
327 	uint16_t  zrpm_start_temp;
328 	uint32_t  stable_pstate_sclk_dpm_percentage;
329 	uint8_t   fps_support;
330 	uint8_t   vr0hot;
331 	uint8_t   vr1hot;
332 	uint8_t   disable_auto_wattman;
333 	uint32_t  auto_wattman_debug;
334 	uint32_t  auto_wattman_sample_period;
335 	uint32_t  fclk_gfxclk_ratio;
336 	uint8_t   auto_wattman_threshold;
337 	uint8_t   log_avfs_param;
338 	uint8_t   enable_enginess;
339 	uint8_t   custom_fan_support;
340 	uint8_t   disable_pcc_limit_control;
341 	uint8_t   gfxoff_controlled_by_driver;
342 };
343 
344 struct vega20_odn_clock_voltage_dependency_table {
345 	uint32_t count;
346 	struct phm_ppt_v1_clock_voltage_dependency_record
347 		entries[MAX_REGULAR_DPM_NUMBER];
348 };
349 
350 struct vega20_odn_dpm_table {
351 	struct vega20_odn_dpm_control		control_gfxclk_state;
352 	struct vega20_odn_dpm_control		control_memclk_state;
353 	struct phm_odn_clock_levels		odn_core_clock_dpm_levels;
354 	struct phm_odn_clock_levels		odn_memory_clock_dpm_levels;
355 	struct vega20_odn_clock_voltage_dependency_table		vdd_dependency_on_sclk;
356 	struct vega20_odn_clock_voltage_dependency_table		vdd_dependency_on_mclk;
357 	struct vega20_odn_clock_voltage_dependency_table		vdd_dependency_on_socclk;
358 	uint32_t				odn_mclk_min_limit;
359 };
360 
361 struct vega20_odn_fan_table {
362 	uint32_t	target_fan_speed;
363 	uint32_t	target_temperature;
364 	uint32_t	min_performance_clock;
365 	uint32_t	min_fan_limit;
366 	bool		force_fan_pwm;
367 };
368 
369 struct vega20_odn_temp_table {
370 	uint16_t	target_operating_temp;
371 	uint16_t	default_target_operating_temp;
372 	uint16_t	operating_temp_min_limit;
373 	uint16_t	operating_temp_max_limit;
374 	uint16_t	operating_temp_step;
375 };
376 
377 struct vega20_odn_data {
378 	uint32_t	apply_overdrive_next_settings_mask;
379 	uint32_t	overdrive_next_state;
380 	uint32_t	overdrive_next_capabilities;
381 	uint32_t	odn_sclk_dpm_enable_mask;
382 	uint32_t	odn_mclk_dpm_enable_mask;
383 	struct vega20_odn_dpm_table	odn_dpm_table;
384 	struct vega20_odn_fan_table	odn_fan_table;
385 	struct vega20_odn_temp_table	odn_temp_table;
386 };
387 
388 enum OD8_FEATURE_ID {
389 	OD8_GFXCLK_LIMITS               = 1 << 0,
390 	OD8_GFXCLK_CURVE                = 1 << 1,
391 	OD8_UCLK_MAX                    = 1 << 2,
392 	OD8_POWER_LIMIT                 = 1 << 3,
393 	OD8_ACOUSTIC_LIMIT_SCLK         = 1 << 4,   //FanMaximumRpm
394 	OD8_FAN_SPEED_MIN               = 1 << 5,   //FanMinimumPwm
395 	OD8_TEMPERATURE_FAN             = 1 << 6,   //FanTargetTemperature
396 	OD8_TEMPERATURE_SYSTEM          = 1 << 7,   //MaxOpTemp
397 	OD8_MEMORY_TIMING_TUNE          = 1 << 8,
398 	OD8_FAN_ZERO_RPM_CONTROL        = 1 << 9
399 };
400 
401 enum OD8_SETTING_ID {
402 	OD8_SETTING_GFXCLK_FMIN = 0,
403 	OD8_SETTING_GFXCLK_FMAX,
404 	OD8_SETTING_GFXCLK_FREQ1,
405 	OD8_SETTING_GFXCLK_VOLTAGE1,
406 	OD8_SETTING_GFXCLK_FREQ2,
407 	OD8_SETTING_GFXCLK_VOLTAGE2,
408 	OD8_SETTING_GFXCLK_FREQ3,
409 	OD8_SETTING_GFXCLK_VOLTAGE3,
410 	OD8_SETTING_UCLK_FMAX,
411 	OD8_SETTING_POWER_PERCENTAGE,
412 	OD8_SETTING_FAN_ACOUSTIC_LIMIT,
413 	OD8_SETTING_FAN_MIN_SPEED,
414 	OD8_SETTING_FAN_TARGET_TEMP,
415 	OD8_SETTING_OPERATING_TEMP_MAX,
416 	OD8_SETTING_AC_TIMING,
417 	OD8_SETTING_FAN_ZERO_RPM_CONTROL,
418 	OD8_SETTING_COUNT
419 };
420 
421 struct vega20_od8_single_setting {
422 	uint32_t	feature_id;
423 	int32_t		min_value;
424 	int32_t		max_value;
425 	int32_t		current_value;
426 	int32_t		default_value;
427 };
428 
429 struct vega20_od8_settings {
430 	uint32_t	overdrive8_capabilities;
431 	struct vega20_od8_single_setting	od8_settings_array[OD8_SETTING_COUNT];
432 };
433 
434 struct vega20_hwmgr {
435 	struct vega20_dpm_table          dpm_table;
436 	struct vega20_dpm_table          golden_dpm_table;
437 	struct vega20_registry_data      registry_data;
438 	struct vega20_vbios_boot_state   vbios_boot_state;
439 	struct vega20_mclk_latency_table mclk_latency_table;
440 
441 	struct vega20_max_sustainable_clocks max_sustainable_clocks;
442 
443 	struct vega20_leakage_voltage    vddc_leakage;
444 
445 	uint32_t                           vddc_control;
446 	struct pp_atomfwctrl_voltage_table vddc_voltage_table;
447 	uint32_t                           mvdd_control;
448 	struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
449 	uint32_t                           vddci_control;
450 	struct pp_atomfwctrl_voltage_table vddci_voltage_table;
451 
452 	uint32_t                           active_auto_throttle_sources;
453 	struct vega20_bacos                bacos;
454 
455 	/* ---- General data ---- */
456 	uint8_t                           need_update_dpm_table;
457 
458 	bool                           cac_enabled;
459 	bool                           battery_state;
460 	bool                           is_tlu_enabled;
461 	bool                           avfs_exist;
462 
463 	uint32_t                       low_sclk_interrupt_threshold;
464 
465 	uint32_t                       total_active_cus;
466 
467 	uint32_t                       water_marks_bitmap;
468 
469 	struct vega20_display_timing display_timing;
470 
471 	/* ---- Vega20 Dyn Register Settings ---- */
472 
473 	uint32_t                       debug_settings;
474 	uint32_t                       lowest_uclk_reserved_for_ulv;
475 	uint32_t                       gfxclk_average_alpha;
476 	uint32_t                       socclk_average_alpha;
477 	uint32_t                       uclk_average_alpha;
478 	uint32_t                       gfx_activity_average_alpha;
479 	uint32_t                       display_voltage_mode;
480 	uint32_t                       dcef_clk_quad_eqn_a;
481 	uint32_t                       dcef_clk_quad_eqn_b;
482 	uint32_t                       dcef_clk_quad_eqn_c;
483 	uint32_t                       disp_clk_quad_eqn_a;
484 	uint32_t                       disp_clk_quad_eqn_b;
485 	uint32_t                       disp_clk_quad_eqn_c;
486 	uint32_t                       pixel_clk_quad_eqn_a;
487 	uint32_t                       pixel_clk_quad_eqn_b;
488 	uint32_t                       pixel_clk_quad_eqn_c;
489 	uint32_t                       phy_clk_quad_eqn_a;
490 	uint32_t                       phy_clk_quad_eqn_b;
491 	uint32_t                       phy_clk_quad_eqn_c;
492 
493 	/* ---- Thermal Temperature Setting ---- */
494 	struct vega20_dpmlevel_enable_mask     dpm_level_enable_mask;
495 
496 	/* ---- Power Gating States ---- */
497 	bool                           uvd_power_gated;
498 	bool                           vce_power_gated;
499 	bool                           samu_power_gated;
500 	bool                           need_long_memory_training;
501 
502 	/* Internal settings to apply the application power optimization parameters */
503 	bool                           apply_optimized_settings;
504 	uint32_t                       disable_dpm_mask;
505 
506 	/* ---- Overdrive next setting ---- */
507 	struct vega20_odn_data         odn_data;
508 	bool                           gfxclk_overdrive;
509 	bool                           memclk_overdrive;
510 
511 	/* ---- Overdrive8 Setting ---- */
512 	struct vega20_od8_settings     od8_settings;
513 
514 	/* ---- Workload Mask ---- */
515 	uint32_t                       workload_mask;
516 
517 	/* ---- SMU9 ---- */
518 	uint32_t                       smu_version;
519 	struct smu_features            smu_features[GNLD_FEATURES_MAX];
520 	struct vega20_smc_state_table  smc_state_table;
521 
522 	/* ---- Gfxoff ---- */
523 	bool                           gfxoff_allowed;
524 	uint32_t                       counter_gfxoff;
525 
526 	unsigned long                  metrics_time;
527 	SmuMetrics_t                   metrics_table;
528 	struct gpu_metrics_v1_0        gpu_metrics_table;
529 
530 	bool                           pcie_parameters_override;
531 	uint32_t                       pcie_gen_level1;
532 	uint32_t                       pcie_width_level1;
533 
534 	bool                           is_custom_profile_set;
535 };
536 
537 #define VEGA20_DPM2_NEAR_TDP_DEC                      10
538 #define VEGA20_DPM2_ABOVE_SAFE_INC                    5
539 #define VEGA20_DPM2_BELOW_SAFE_INC                    20
540 
541 #define VEGA20_DPM2_LTA_WINDOW_SIZE                   7
542 
543 #define VEGA20_DPM2_LTS_TRUNCATE                      0
544 
545 #define VEGA20_DPM2_TDP_SAFE_LIMIT_PERCENT            80
546 
547 #define VEGA20_DPM2_MAXPS_PERCENT_M                   90
548 #define VEGA20_DPM2_MAXPS_PERCENT_H                   90
549 
550 #define VEGA20_DPM2_PWREFFICIENCYRATIO_MARGIN         50
551 
552 #define VEGA20_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
553 #define VEGA20_DPM2_SQ_RAMP_MIN_POWER                 0x12
554 #define VEGA20_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
555 #define VEGA20_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
556 #define VEGA20_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
557 
558 #define VEGA20_VOLTAGE_CONTROL_NONE                   0x0
559 #define VEGA20_VOLTAGE_CONTROL_BY_GPIO                0x1
560 #define VEGA20_VOLTAGE_CONTROL_BY_SVID2               0x2
561 #define VEGA20_VOLTAGE_CONTROL_MERGED                 0x3
562 /* To convert to Q8.8 format for firmware */
563 #define VEGA20_Q88_FORMAT_CONVERSION_UNIT             256
564 
565 #define VEGA20_UNUSED_GPIO_PIN       0x7F
566 
567 #define VEGA20_THERM_OUT_MODE_DISABLE       0x0
568 #define VEGA20_THERM_OUT_MODE_THERM_ONLY    0x1
569 #define VEGA20_THERM_OUT_MODE_THERM_VRHOT   0x2
570 
571 #define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT   0xffffffff
572 #define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT    0xffffffff
573 
574 #define PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
575 #define PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
576 #define PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT      25 /* 10% * 255 = 25 */
577 #define PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT  25 /* 10% * 255 = 25 */
578 #define PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT   0xffffffff
579 #define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT         0xffffffff
580 #define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT          0xffffffff
581 
582 #define VEGA20_UMD_PSTATE_GFXCLK_LEVEL         0x3
583 #define VEGA20_UMD_PSTATE_SOCCLK_LEVEL         0x3
584 #define VEGA20_UMD_PSTATE_MCLK_LEVEL           0x2
585 #define VEGA20_UMD_PSTATE_UVDCLK_LEVEL         0x3
586 #define VEGA20_UMD_PSTATE_VCEMCLK_LEVEL        0x3
587 
588 #endif /* _VEGA20_HWMGR_H_ */
589