Searched refs:pcie_dpm_enable_mask (Results 1 – 9 of 9) sorted by relevance
112 u32 pcie_dpm_enable_mask; member
2601 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()3795 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3798 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()4140 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()4167 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()4169 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()4255 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()4257 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
594 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in vegam_populate_smc_link_level()926 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in vegam_populate_all_graphic_levels()927 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()931 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in vegam_populate_all_graphic_levels()932 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()937 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()
849 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in fiji_populate_smc_link_level()1055 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()1056 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1060 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()1061 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1066 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()
532 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in tonga_populate_smc_link_level()745 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) in tonga_populate_all_graphic_levels()748 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()749 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()754 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()755 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()761 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()
840 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in polaris10_populate_smc_link_level()1115 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()1116 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1120 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()1121 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1126 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()
789 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in iceland_populate_smc_link_level()1005 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1010 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1016 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()
1016 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
3125 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { in smu7_force_dpm_highest()3127 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; in smu7_force_dpm_highest()3270 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { in smu7_force_dpm_lowest()3272 data->dpm_level_enable_mask.pcie_dpm_enable_mask); in smu7_force_dpm_lowest()4477 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in smu7_generate_dpm_level_enable_mask()5059 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; in smu7_force_clock_level()