1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects Root Port status and schedules work.
6 *
7 * Copyright (C) 2006 Intel Corp.
8 * Tom Long Nguyen (tom.l.nguyen@intel.com)
9 * Zhang Yanmin (yanmin.zhang@intel.com)
10 *
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
12 * Andrew Patterson <andrew.patterson@hp.com>
13 */
14
15 #define pr_fmt(fmt) "AER: " fmt
16 #define dev_fmt pr_fmt
17
18 #include <linux/bitops.h>
19 #include <linux/cper.h>
20 #include <linux/dev_printk.h>
21 #include <linux/pci.h>
22 #include <linux/pci-acpi.h>
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/pm.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/delay.h>
30 #include <linux/kfifo.h>
31 #include <linux/ratelimit.h>
32 #include <linux/slab.h>
33 #include <linux/vmcore_info.h>
34 #include <acpi/apei.h>
35 #include <acpi/ghes.h>
36 #include <ras/ras_event.h>
37
38 #include "../pci.h"
39 #include "portdrv.h"
40
41 #define aer_printk(level, pdev, fmt, arg...) \
42 dev_printk(level, &(pdev)->dev, fmt, ##arg)
43
44 #define AER_ERROR_SOURCES_MAX 128
45
46 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
47 #define AER_MAX_TYPEOF_UNCOR_ERRS 32 /* as per PCI_ERR_UNCOR_STATUS*/
48
49 struct aer_err_source {
50 u32 status; /* PCI_ERR_ROOT_STATUS */
51 u32 id; /* PCI_ERR_ROOT_ERR_SRC */
52 };
53
54 struct aer_rpc {
55 struct pci_dev *rpd; /* Root Port device */
56 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX);
57 };
58
59 /* AER info for the device */
60 struct aer_info {
61
62 /*
63 * Fields for all AER capable devices. They indicate the errors
64 * "as seen by this device". Note that this may mean that if an
65 * Endpoint is causing problems, the AER counters may increment
66 * at its link partner (e.g. Root Port) because the errors will be
67 * "seen" by the link partner and not the problematic Endpoint
68 * itself (which may report all counters as 0 as it never saw any
69 * problems).
70 */
71 /* Counters for different type of correctable errors */
72 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
73 /* Counters for different type of fatal uncorrectable errors */
74 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
75 /* Counters for different type of nonfatal uncorrectable errors */
76 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
77 /* Total number of ERR_COR sent by this device */
78 u64 dev_total_cor_errs;
79 /* Total number of ERR_FATAL sent by this device */
80 u64 dev_total_fatal_errs;
81 /* Total number of ERR_NONFATAL sent by this device */
82 u64 dev_total_nonfatal_errs;
83
84 /*
85 * Fields for Root Ports & Root Complex Event Collectors only; these
86 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
87 * messages received by the Root Port / Event Collector, INCLUDING the
88 * ones that are generated internally (by the Root Port itself)
89 */
90 u64 rootport_total_cor_errs;
91 u64 rootport_total_fatal_errs;
92 u64 rootport_total_nonfatal_errs;
93
94 /* Ratelimits for errors */
95 struct ratelimit_state correctable_ratelimit;
96 struct ratelimit_state nonfatal_ratelimit;
97 };
98
99 #define AER_ANFE (PCI_ERR_UNC_UNX_COMP | \
100 PCI_ERR_UNC_ATOMEG | \
101 PCI_ERR_UNC_DMWR_BLK)
102
103 #define AER_POSSIBLE_ANFE (PCI_ERR_UNC_POISON_TLP | \
104 PCI_ERR_UNC_POISON_BLK | \
105 PCI_ERR_UNC_ECRC | \
106 PCI_ERR_UNC_UNSUP | \
107 PCI_ERR_UNC_COMP_TIME | \
108 PCI_ERR_UNC_COMP_ABORT | \
109 PCI_ERR_UNC_ACSV | \
110 PCI_ERR_UNC_TLPPRE | \
111 PCI_ERR_UNC_PCRC_CHECK)
112
113 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
114 PCI_ERR_UNC_POISON_BLK | \
115 PCI_ERR_UNC_ECRC| \
116 PCI_ERR_UNC_UNSUP| \
117 PCI_ERR_UNC_COMP_ABORT| \
118 PCI_ERR_UNC_UNX_COMP| \
119 PCI_ERR_UNC_ACSV | \
120 PCI_ERR_UNC_MCBTLP | \
121 PCI_ERR_UNC_ATOMEG | \
122 PCI_ERR_UNC_DMWR_BLK | \
123 PCI_ERR_UNC_XLAT_BLK | \
124 PCI_ERR_UNC_TLPPRE | \
125 PCI_ERR_UNC_MALF_TLP | \
126 PCI_ERR_UNC_IDE_CHECK | \
127 PCI_ERR_UNC_MISR_IDE | \
128 PCI_ERR_UNC_PCRC_CHECK)
129
130 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
131 PCI_EXP_RTCTL_SENFEE| \
132 PCI_EXP_RTCTL_SEFEE)
133 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
134 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
135 PCI_ERR_ROOT_CMD_FATAL_EN)
136 #define ERR_COR_ID(d) (d & 0xffff)
137 #define ERR_UNCOR_ID(d) (d >> 16)
138
139 #define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \
140 PCI_ERR_ROOT_COR_RCV | \
141 PCI_ERR_ROOT_MULTI_COR_RCV | \
142 PCI_ERR_ROOT_MULTI_UNCOR_RCV)
143
144 static bool pcie_aer_disable;
145 static pci_ers_result_t aer_root_reset(struct pci_dev *dev);
146
pci_no_aer(void)147 void pci_no_aer(void)
148 {
149 pcie_aer_disable = true;
150 }
151
pci_aer_available(void)152 bool pci_aer_available(void)
153 {
154 return !pcie_aer_disable && pci_msi_enabled();
155 }
156
157 #ifdef CONFIG_PCIE_ECRC
158
159 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
160 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */
161 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
162
163 static int ecrc_policy = ECRC_POLICY_DEFAULT;
164
165 static const char * const ecrc_policy_str[] = {
166 [ECRC_POLICY_DEFAULT] = "bios",
167 [ECRC_POLICY_OFF] = "off",
168 [ECRC_POLICY_ON] = "on"
169 };
170
171 /**
172 * enable_ecrc_checking - enable PCIe ECRC checking for a device
173 * @dev: the PCI device
174 *
175 * Return: 0 on success, or negative on failure.
176 */
enable_ecrc_checking(struct pci_dev * dev)177 static int enable_ecrc_checking(struct pci_dev *dev)
178 {
179 int aer = dev->aer_cap;
180 u32 reg32;
181
182 if (!aer)
183 return -ENODEV;
184
185 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
186 if (reg32 & PCI_ERR_CAP_ECRC_GENC)
187 reg32 |= PCI_ERR_CAP_ECRC_GENE;
188 if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
189 reg32 |= PCI_ERR_CAP_ECRC_CHKE;
190 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
191
192 return 0;
193 }
194
195 /**
196 * disable_ecrc_checking - disable PCIe ECRC checking for a device
197 * @dev: the PCI device
198 *
199 * Return: 0 on success, or negative on failure.
200 */
disable_ecrc_checking(struct pci_dev * dev)201 static int disable_ecrc_checking(struct pci_dev *dev)
202 {
203 int aer = dev->aer_cap;
204 u32 reg32;
205
206 if (!aer)
207 return -ENODEV;
208
209 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
210 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
211 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
212
213 return 0;
214 }
215
216 /**
217 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based
218 * on global policy
219 * @dev: the PCI device
220 */
pcie_set_ecrc_checking(struct pci_dev * dev)221 void pcie_set_ecrc_checking(struct pci_dev *dev)
222 {
223 if (!pcie_aer_is_native(dev))
224 return;
225
226 switch (ecrc_policy) {
227 case ECRC_POLICY_DEFAULT:
228 return;
229 case ECRC_POLICY_OFF:
230 disable_ecrc_checking(dev);
231 break;
232 case ECRC_POLICY_ON:
233 enable_ecrc_checking(dev);
234 break;
235 default:
236 return;
237 }
238 }
239
240 /**
241 * pcie_ecrc_get_policy - parse kernel command-line ecrc option
242 * @str: ECRC policy from kernel command line to use
243 */
pcie_ecrc_get_policy(char * str)244 void pcie_ecrc_get_policy(char *str)
245 {
246 int i;
247
248 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str);
249 if (i < 0)
250 return;
251
252 ecrc_policy = i;
253 }
254 #endif /* CONFIG_PCIE_ECRC */
255
pcie_aer_is_native(struct pci_dev * dev)256 int pcie_aer_is_native(struct pci_dev *dev)
257 {
258 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
259
260 if (!dev->aer_cap)
261 return 0;
262
263 return pcie_ports_native || host->native_aer;
264 }
265 EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "CXL");
266
pci_enable_pcie_error_reporting(struct pci_dev * dev)267 static int pci_enable_pcie_error_reporting(struct pci_dev *dev)
268 {
269 int rc;
270
271 if (!pcie_aer_is_native(dev))
272 return -EIO;
273
274 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
275 return pcibios_err_to_errno(rc);
276 }
277
pci_aer_clear_nonfatal_status(struct pci_dev * dev)278 int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
279 {
280 int aer = dev->aer_cap;
281 u32 status, sev;
282
283 if (!pcie_aer_is_native(dev))
284 return -EIO;
285
286 /* Clear status bits for ERR_NONFATAL errors only */
287 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
288 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
289 status &= ~sev;
290 if (status)
291 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
292
293 return 0;
294 }
295 EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status);
296
pci_aer_clear_fatal_status(struct pci_dev * dev)297 void pci_aer_clear_fatal_status(struct pci_dev *dev)
298 {
299 int aer = dev->aer_cap;
300 u32 status, sev;
301
302 if (!pcie_aer_is_native(dev))
303 return;
304
305 /* Clear status bits for ERR_FATAL errors only */
306 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
307 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
308 status &= sev;
309 if (status)
310 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
311 }
312
313 /**
314 * pci_aer_raw_clear_status - Clear AER error registers.
315 * @dev: the PCI device
316 *
317 * Clear AER error status registers unconditionally, regardless of
318 * whether they're owned by firmware or the OS.
319 *
320 * Return: 0 on success, or negative on failure.
321 */
pci_aer_raw_clear_status(struct pci_dev * dev)322 int pci_aer_raw_clear_status(struct pci_dev *dev)
323 {
324 int aer = dev->aer_cap;
325 u32 status;
326 int port_type;
327
328 if (!aer)
329 return -EIO;
330
331 port_type = pci_pcie_type(dev);
332 if (port_type == PCI_EXP_TYPE_ROOT_PORT ||
333 port_type == PCI_EXP_TYPE_RC_EC) {
334 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);
335 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);
336 }
337
338 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
339 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);
340
341 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
342 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
343
344 return 0;
345 }
346
pci_aer_clear_status(struct pci_dev * dev)347 int pci_aer_clear_status(struct pci_dev *dev)
348 {
349 if (!pcie_aer_is_native(dev))
350 return -EIO;
351
352 return pci_aer_raw_clear_status(dev);
353 }
354
pci_save_aer_state(struct pci_dev * dev)355 void pci_save_aer_state(struct pci_dev *dev)
356 {
357 int aer = dev->aer_cap;
358 struct pci_cap_saved_state *save_state;
359 u32 *cap;
360
361 if (!aer)
362 return;
363
364 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
365 if (!save_state)
366 return;
367
368 cap = &save_state->cap.data[0];
369 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);
370 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);
371 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
372 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);
373 if (pcie_cap_has_rtctl(dev))
374 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);
375 }
376
pci_restore_aer_state(struct pci_dev * dev)377 void pci_restore_aer_state(struct pci_dev *dev)
378 {
379 int aer = dev->aer_cap;
380 struct pci_cap_saved_state *save_state;
381 u32 *cap;
382
383 if (!aer)
384 return;
385
386 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
387 if (!save_state)
388 return;
389
390 cap = &save_state->cap.data[0];
391 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);
392 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);
393 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
394 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);
395 if (pcie_cap_has_rtctl(dev))
396 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);
397 }
398
pci_aer_init(struct pci_dev * dev)399 void pci_aer_init(struct pci_dev *dev)
400 {
401 int n;
402
403 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
404 if (!dev->aer_cap)
405 return;
406
407 dev->aer_info = kzalloc_obj(*dev->aer_info);
408 if (!dev->aer_info) {
409 dev->aer_cap = 0;
410 return;
411 }
412
413 ratelimit_state_init(&dev->aer_info->correctable_ratelimit,
414 DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST);
415 ratelimit_state_init(&dev->aer_info->nonfatal_ratelimit,
416 DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST);
417
418 /*
419 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
420 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
421 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r6.0, sec
422 * 7.8.4.9).
423 */
424 n = pcie_cap_has_rtctl(dev) ? 5 : 4;
425 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
426
427 /*
428 * Advisory Non-Fatal Errors are masked by default (PCIe r7.0, sec
429 * 7.8.4.6).
430 */
431 if (pcie_aer_is_native(dev) && dev->devcap & PCI_EXP_DEVCAP_RBER &&
432 !dev->no_aer_anfe)
433 pci_clear_and_set_config_dword(dev,
434 dev->aer_cap + PCI_ERR_COR_MASK,
435 PCI_ERR_COR_ADV_NFAT, 0);
436
437 pci_aer_clear_status(dev);
438
439 if (pci_aer_available())
440 pci_enable_pcie_error_reporting(dev);
441
442 pcie_set_ecrc_checking(dev);
443 }
444
pci_aer_exit(struct pci_dev * dev)445 void pci_aer_exit(struct pci_dev *dev)
446 {
447 kfree(dev->aer_info);
448 dev->aer_info = NULL;
449 }
450
451 #define AER_AGENT_RECEIVER 0
452 #define AER_AGENT_REQUESTER 1
453 #define AER_AGENT_COMPLETER 2
454 #define AER_AGENT_TRANSMITTER 3
455 #define AER_AGENT_COMPONENT 4
456 #define AER_AGENT_UNDEF 5
457
458 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
459 0 : PCI_ERR_UNC_COMP_TIME)
460 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
461 0 : PCI_ERR_UNC_COMP_ABORT)
462 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
463 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : \
464 (PCI_ERR_UNC_POISON_BLK|PCI_ERR_UNC_ATOMEG| \
465 PCI_ERR_UNC_DMWR_BLK|PCI_ERR_UNC_XLAT_BLK| \
466 PCI_ERR_UNC_TLPPRE))
467 #define AER_AGENT_COMPONENT_MASK(t) ((t == AER_CORRECTABLE) ? \
468 (PCI_ERR_COR_INTERNAL|PCI_ERR_COR_LOG_OVER) : \
469 (PCI_ERR_UNC_INTN|PCI_ERR_UNC_SURPDN))
470 #define AER_AGENT_UNDEF_MASK(t) ((t == AER_CORRECTABLE) ? \
471 PCI_ERR_COR_ADV_NFAT : 0)
472
473
474 #define AER_GET_AGENT(t, e) \
475 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
476 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
477 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
478 (e & AER_AGENT_COMPONENT_MASK(t)) ? AER_AGENT_COMPONENT : \
479 (e & AER_AGENT_UNDEF_MASK(t)) ? AER_AGENT_UNDEF : \
480 AER_AGENT_RECEIVER)
481
482 #define AER_PHYSICAL_LAYER_ERROR 0
483 #define AER_DATA_LINK_LAYER_ERROR 1
484 #define AER_TRANSACTION_LAYER_ERROR 2
485 #define AER_GENERAL_ERROR 3
486 #define AER_UNDEF_ERROR 4
487
488 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
489 PCI_ERR_COR_RCVR : 0)
490 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
491 (PCI_ERR_COR_BAD_TLP| \
492 PCI_ERR_COR_BAD_DLLP| \
493 PCI_ERR_COR_REP_ROLL| \
494 PCI_ERR_COR_REP_TIMER) : (PCI_ERR_UNC_DLP|PCI_ERR_UNC_SURPDN))
495 #define AER_GENERAL_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
496 (PCI_ERR_COR_INTERNAL|PCI_ERR_COR_LOG_OVER) : PCI_ERR_UNC_INTN)
497 #define AER_UNDEF_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
498 PCI_ERR_COR_ADV_NFAT : 0)
499
500 #define AER_GET_LAYER_ERROR(t, e) \
501 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
502 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
503 (e & AER_GENERAL_ERROR_MASK(t)) ? AER_GENERAL_ERROR : \
504 (e & AER_UNDEF_ERROR_MASK(t)) ? AER_UNDEF_ERROR : \
505 AER_TRANSACTION_LAYER_ERROR)
506
507 /*
508 * AER error strings
509 */
510 static const char * const aer_error_severity_string[] = {
511 "Uncorrectable (Non-Fatal)",
512 "Uncorrectable (Fatal)",
513 "Correctable"
514 };
515
516 static const char *aer_error_layer[] = {
517 "Physical Layer",
518 "Data Link Layer",
519 "Transaction Layer",
520 "General",
521 "",
522 };
523
524 static const char *aer_correctable_error_string[] = {
525 "RxErr", /* Bit Position 0 */
526 NULL,
527 NULL,
528 NULL,
529 NULL,
530 NULL,
531 "BadTLP", /* Bit Position 6 */
532 "BadDLLP", /* Bit Position 7 */
533 "Rollover", /* Bit Position 8 */
534 NULL,
535 NULL,
536 NULL,
537 "Timeout", /* Bit Position 12 */
538 "NonFatalErr", /* Bit Position 13 */
539 "CorrIntErr", /* Bit Position 14 */
540 "HeaderOF", /* Bit Position 15 */
541 NULL, /* Bit Position 16 */
542 NULL, /* Bit Position 17 */
543 NULL, /* Bit Position 18 */
544 NULL, /* Bit Position 19 */
545 NULL, /* Bit Position 20 */
546 NULL, /* Bit Position 21 */
547 NULL, /* Bit Position 22 */
548 NULL, /* Bit Position 23 */
549 NULL, /* Bit Position 24 */
550 NULL, /* Bit Position 25 */
551 NULL, /* Bit Position 26 */
552 NULL, /* Bit Position 27 */
553 NULL, /* Bit Position 28 */
554 NULL, /* Bit Position 29 */
555 NULL, /* Bit Position 30 */
556 NULL, /* Bit Position 31 */
557 };
558
559 static const char *aer_uncorrectable_error_string[] = {
560 "Undefined", /* Bit Position 0 */
561 NULL,
562 NULL,
563 NULL,
564 "DLP", /* Bit Position 4 */
565 "SDES", /* Bit Position 5 */
566 NULL,
567 NULL,
568 NULL,
569 NULL,
570 NULL,
571 NULL,
572 "TLP", /* Bit Position 12 */
573 "FCP", /* Bit Position 13 */
574 "CmpltTO", /* Bit Position 14 */
575 "CmpltAbrt", /* Bit Position 15 */
576 "UnxCmplt", /* Bit Position 16 */
577 "RxOF", /* Bit Position 17 */
578 "MalfTLP", /* Bit Position 18 */
579 "ECRC", /* Bit Position 19 */
580 "UnsupReq", /* Bit Position 20 */
581 "ACSViol", /* Bit Position 21 */
582 "UncorrIntErr", /* Bit Position 22 */
583 "BlockedTLP", /* Bit Position 23 */
584 "AtomicOpBlocked", /* Bit Position 24 */
585 "TLPBlockedErr", /* Bit Position 25 */
586 "PoisonTLPBlocked", /* Bit Position 26 */
587 "DMWrReqBlocked", /* Bit Position 27 */
588 "IDECheck", /* Bit Position 28 */
589 "MisIDETLP", /* Bit Position 29 */
590 "PCRC_CHECK", /* Bit Position 30 */
591 "TLPXlatBlocked", /* Bit Position 31 */
592 };
593
594 static const char *aer_agent_string[] = {
595 "Receiver",
596 "Requester",
597 "Completer",
598 "Transmitter",
599 "Component",
600 "",
601 };
602
603 #define aer_stats_dev_attr(name, stats_array, strings_array, \
604 total_string, total_field) \
605 static ssize_t \
606 name##_show(struct device *dev, struct device_attribute *attr, \
607 char *buf) \
608 { \
609 unsigned int i; \
610 struct pci_dev *pdev = to_pci_dev(dev); \
611 u64 *stats = pdev->aer_info->stats_array; \
612 size_t len = 0; \
613 \
614 for (i = 0; i < ARRAY_SIZE(pdev->aer_info->stats_array); i++) { \
615 if (strings_array[i]) \
616 len += sysfs_emit_at(buf, len, "%s %llu\n", \
617 strings_array[i], \
618 stats[i]); \
619 else if (stats[i]) \
620 len += sysfs_emit_at(buf, len, \
621 #stats_array "_bit[%d] %llu\n",\
622 i, stats[i]); \
623 } \
624 len += sysfs_emit_at(buf, len, "TOTAL_%s %llu\n", total_string, \
625 pdev->aer_info->total_field); \
626 return len; \
627 } \
628 static DEVICE_ATTR_RO(name)
629
630 aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs,
631 aer_correctable_error_string, "ERR_COR",
632 dev_total_cor_errs);
633 aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs,
634 aer_uncorrectable_error_string, "ERR_FATAL",
635 dev_total_fatal_errs);
636 aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs,
637 aer_uncorrectable_error_string, "ERR_NONFATAL",
638 dev_total_nonfatal_errs);
639
640 #define aer_stats_rootport_attr(name, field) \
641 static ssize_t \
642 name##_show(struct device *dev, struct device_attribute *attr, \
643 char *buf) \
644 { \
645 struct pci_dev *pdev = to_pci_dev(dev); \
646 return sysfs_emit(buf, "%llu\n", pdev->aer_info->field); \
647 } \
648 static DEVICE_ATTR_RO(name)
649
650 aer_stats_rootport_attr(aer_rootport_total_err_cor,
651 rootport_total_cor_errs);
652 aer_stats_rootport_attr(aer_rootport_total_err_fatal,
653 rootport_total_fatal_errs);
654 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal,
655 rootport_total_nonfatal_errs);
656
657 static struct attribute *aer_stats_attrs[] __ro_after_init = {
658 &dev_attr_aer_dev_correctable.attr,
659 &dev_attr_aer_dev_fatal.attr,
660 &dev_attr_aer_dev_nonfatal.attr,
661 &dev_attr_aer_rootport_total_err_cor.attr,
662 &dev_attr_aer_rootport_total_err_fatal.attr,
663 &dev_attr_aer_rootport_total_err_nonfatal.attr,
664 NULL
665 };
666
aer_stats_attrs_are_visible(struct kobject * kobj,struct attribute * a,int n)667 static umode_t aer_stats_attrs_are_visible(struct kobject *kobj,
668 struct attribute *a, int n)
669 {
670 struct device *dev = kobj_to_dev(kobj);
671 struct pci_dev *pdev = to_pci_dev(dev);
672
673 if (!pdev->aer_info)
674 return 0;
675
676 if ((a == &dev_attr_aer_rootport_total_err_cor.attr ||
677 a == &dev_attr_aer_rootport_total_err_fatal.attr ||
678 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) &&
679 ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
680 (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC)))
681 return 0;
682
683 return a->mode;
684 }
685
686 const struct attribute_group aer_stats_attr_group = {
687 .attrs = aer_stats_attrs,
688 .is_visible = aer_stats_attrs_are_visible,
689 };
690
691 /*
692 * Ratelimit interval
693 * <=0: disabled with ratelimit.interval = 0
694 * >0: enabled with ratelimit.interval in ms
695 */
696 #define aer_ratelimit_interval_attr(name, ratelimit) \
697 static ssize_t \
698 name##_show(struct device *dev, struct device_attribute *attr, \
699 char *buf) \
700 { \
701 struct pci_dev *pdev = to_pci_dev(dev); \
702 \
703 return sysfs_emit(buf, "%d\n", \
704 pdev->aer_info->ratelimit.interval); \
705 } \
706 \
707 static ssize_t \
708 name##_store(struct device *dev, struct device_attribute *attr, \
709 const char *buf, size_t count) \
710 { \
711 struct pci_dev *pdev = to_pci_dev(dev); \
712 int interval; \
713 \
714 if (!capable(CAP_SYS_ADMIN)) \
715 return -EPERM; \
716 \
717 if (kstrtoint(buf, 0, &interval) < 0) \
718 return -EINVAL; \
719 \
720 if (interval <= 0) \
721 interval = 0; \
722 else \
723 interval = msecs_to_jiffies(interval); \
724 \
725 pdev->aer_info->ratelimit.interval = interval; \
726 \
727 return count; \
728 } \
729 static DEVICE_ATTR_RW(name);
730
731 #define aer_ratelimit_burst_attr(name, ratelimit) \
732 static ssize_t \
733 name##_show(struct device *dev, struct device_attribute *attr, \
734 char *buf) \
735 { \
736 struct pci_dev *pdev = to_pci_dev(dev); \
737 \
738 return sysfs_emit(buf, "%d\n", \
739 pdev->aer_info->ratelimit.burst); \
740 } \
741 \
742 static ssize_t \
743 name##_store(struct device *dev, struct device_attribute *attr, \
744 const char *buf, size_t count) \
745 { \
746 struct pci_dev *pdev = to_pci_dev(dev); \
747 int burst; \
748 \
749 if (!capable(CAP_SYS_ADMIN)) \
750 return -EPERM; \
751 \
752 if (kstrtoint(buf, 0, &burst) < 0) \
753 return -EINVAL; \
754 \
755 pdev->aer_info->ratelimit.burst = burst; \
756 \
757 return count; \
758 } \
759 static DEVICE_ATTR_RW(name);
760
761 #define aer_ratelimit_attrs(name) \
762 aer_ratelimit_interval_attr(name##_ratelimit_interval_ms, \
763 name##_ratelimit) \
764 aer_ratelimit_burst_attr(name##_ratelimit_burst, \
765 name##_ratelimit)
766
767 aer_ratelimit_attrs(correctable)
768 aer_ratelimit_attrs(nonfatal)
769
770 static struct attribute *aer_attrs[] = {
771 &dev_attr_correctable_ratelimit_interval_ms.attr,
772 &dev_attr_correctable_ratelimit_burst.attr,
773 &dev_attr_nonfatal_ratelimit_interval_ms.attr,
774 &dev_attr_nonfatal_ratelimit_burst.attr,
775 NULL
776 };
777
aer_attrs_are_visible(struct kobject * kobj,struct attribute * a,int n)778 static umode_t aer_attrs_are_visible(struct kobject *kobj,
779 struct attribute *a, int n)
780 {
781 struct device *dev = kobj_to_dev(kobj);
782 struct pci_dev *pdev = to_pci_dev(dev);
783
784 if (!pdev->aer_info)
785 return 0;
786
787 return a->mode;
788 }
789
790 const struct attribute_group aer_attr_group = {
791 .name = "aer",
792 .attrs = aer_attrs,
793 .is_visible = aer_attrs_are_visible,
794 };
795
pci_dev_aer_stats_incr(struct pci_dev * pdev,struct aer_err_info * info)796 static void pci_dev_aer_stats_incr(struct pci_dev *pdev,
797 struct aer_err_info *info)
798 {
799 unsigned long status = info->status & ~info->mask;
800 int i, max = -1;
801 u64 *counter = NULL;
802 struct aer_info *aer_info = pdev->aer_info;
803
804 if (!aer_info)
805 return;
806
807 switch (info->severity) {
808 case AER_CORRECTABLE:
809 aer_info->dev_total_cor_errs++;
810 counter = &aer_info->dev_cor_errs[0];
811 max = AER_MAX_TYPEOF_COR_ERRS;
812 break;
813 case AER_NONFATAL:
814 aer_info->dev_total_nonfatal_errs++;
815 hwerr_log_error_type(HWERR_RECOV_PCI);
816 counter = &aer_info->dev_nonfatal_errs[0];
817 max = AER_MAX_TYPEOF_UNCOR_ERRS;
818 break;
819 case AER_FATAL:
820 aer_info->dev_total_fatal_errs++;
821 counter = &aer_info->dev_fatal_errs[0];
822 max = AER_MAX_TYPEOF_UNCOR_ERRS;
823 break;
824 }
825
826 for_each_set_bit(i, &status, max)
827 counter[i]++;
828 }
829
pci_rootport_aer_stats_incr(struct pci_dev * pdev,struct aer_err_source * e_src)830 static void pci_rootport_aer_stats_incr(struct pci_dev *pdev,
831 struct aer_err_source *e_src)
832 {
833 struct aer_info *aer_info = pdev->aer_info;
834
835 if (!aer_info)
836 return;
837
838 if (e_src->status & PCI_ERR_ROOT_COR_RCV)
839 aer_info->rootport_total_cor_errs++;
840
841 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
842 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
843 aer_info->rootport_total_fatal_errs++;
844 else
845 aer_info->rootport_total_nonfatal_errs++;
846 }
847 }
848
aer_ratelimit(struct pci_dev * dev,unsigned int severity)849 static int aer_ratelimit(struct pci_dev *dev, unsigned int severity)
850 {
851 if (!dev->aer_info)
852 return 1;
853
854 switch (severity) {
855 case AER_NONFATAL:
856 return __ratelimit(&dev->aer_info->nonfatal_ratelimit);
857 case AER_CORRECTABLE:
858 return __ratelimit(&dev->aer_info->correctable_ratelimit);
859 default:
860 return 1; /* Don't ratelimit fatal errors */
861 }
862 }
863
aer_compute_anfe_status(u16 devsta,u32 uncor_status,u32 uncor_mask,u32 uncor_severity)864 static u32 aer_compute_anfe_status(u16 devsta, u32 uncor_status,
865 u32 uncor_mask, u32 uncor_severity)
866 {
867 u32 anfe_status;
868
869 /*
870 * Uncorrectable Errors must be unmasked and have Non-Fatal severity
871 * to qualify as Advisory Non-Fatal Errors (PCIe r7.0 sec 6.2.4.3).
872 */
873 uncor_status &= ~uncor_mask & ~uncor_severity;
874
875 /* Some Non-Fatal Errors are always Advisory (PCIe r7.0 sec 6.2.7). */
876 anfe_status = uncor_status & AER_ANFE;
877
878 /*
879 * Others may be Advisory at the discretion of the detecting agent.
880 * That's impossible to discern if the agent signaled ERR_NONFATAL
881 * in addition to ERR_COR. Assume none are Advisory in that case
882 * to ensure that the Uncorrectable Error code path is taken.
883 */
884 if (!(devsta & PCI_EXP_DEVSTA_NFED))
885 anfe_status |= uncor_status & AER_POSSIBLE_ANFE;
886
887 return anfe_status;
888 }
889
aer_get_anfe_status(struct pci_dev * dev)890 static u32 aer_get_anfe_status(struct pci_dev *dev)
891 {
892 u32 uncor_status, uncor_mask, uncor_severity;
893 u16 devsta, aer = dev->aer_cap;
894
895 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &uncor_status);
896 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &uncor_mask);
897 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &uncor_severity);
898 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &devsta);
899
900 return aer_compute_anfe_status(devsta, uncor_status, uncor_mask,
901 uncor_severity);
902 }
903
tlp_header_logged(u32 status,u32 capctl)904 static bool tlp_header_logged(u32 status, u32 capctl)
905 {
906 /* Errors for which a header is always logged (PCIe r7.0 sec 6.2.7) */
907 if (status & AER_LOG_TLP_MASKS)
908 return true;
909
910 /* Completion Timeout header is only logged on capable devices */
911 if (status & PCI_ERR_UNC_COMP_TIME &&
912 capctl & PCI_ERR_CAP_COMP_TIME_LOG)
913 return true;
914
915 return false;
916 }
917
__aer_print_error(struct pci_dev * dev,struct aer_err_info * info)918 static void __aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
919 {
920 const char **strings;
921 unsigned long status = info->status & ~info->mask;
922 const char *errmsg, *agent, *layer;
923 const char *level = info->level;
924 int i;
925
926 if (info->severity == AER_CORRECTABLE)
927 strings = aer_correctable_error_string;
928 else
929 strings = aer_uncorrectable_error_string;
930
931 for_each_set_bit(i, &status, 32) {
932 errmsg = strings[i];
933 agent = aer_agent_string[AER_GET_AGENT(info->severity, BIT(i))];
934 layer = aer_error_layer[AER_GET_LAYER_ERROR(info->severity,
935 BIT(i))];
936 if (!errmsg) {
937 errmsg = "Unknown Error Bit";
938 agent = "";
939 layer = "";
940 }
941
942 aer_printk(level, dev, " [%2d] %-17s | %-11s | %-17s%s\n",
943 i, errmsg, agent, layer,
944 info->severity != AER_CORRECTABLE &&
945 info->first_error == i ? " (First)" : "");
946 }
947 }
948
aer_print_source(struct pci_dev * dev,struct aer_err_info * info,bool found)949 static void aer_print_source(struct pci_dev *dev, struct aer_err_info *info,
950 bool found)
951 {
952 u16 source = info->id;
953
954 pci_info(dev, "%s%s Error message%s from %04x:%02x:%02x.%d%s\n",
955 info->multi_error_valid ? "Multiple " : "",
956 aer_error_severity_string[info->severity],
957 info->multi_error_valid ? "s received, first one" : " received",
958 pci_domain_nr(dev->bus), PCI_BUS_NUM(source),
959 PCI_SLOT(source), PCI_FUNC(source),
960 found ? "" : " (no details found)");
961 }
962
aer_print_error(struct aer_err_info * info,int i)963 void aer_print_error(struct aer_err_info *info, int i)
964 {
965 struct pci_dev *dev;
966 const char *level = info->level;
967 const char *bus_type = aer_err_bus(info);
968
969 if (WARN_ON_ONCE(i >= AER_MAX_MULTI_ERR_DEVICES))
970 return;
971
972 dev = info->dev[i];
973
974 pci_dev_aer_stats_incr(dev, info);
975 trace_aer_event(pci_name(dev), (info->status & ~info->mask),
976 info->severity, info->tlp_header_valid &&
977 info->severity != AER_CORRECTABLE, &info->tlp,
978 bus_type);
979
980 /*
981 * For Advisory Non-Fatal Errors, record statistics and tracing
982 * even if ratelimited
983 */
984 if (!info->ratelimit_print[i])
985 goto anfe;
986
987 if (!info->status) {
988 pci_err(dev, "%s Bus Error: severity=%s (Inaccessible)\n",
989 bus_type, aer_error_severity_string[info->severity]);
990 return;
991 }
992
993 aer_printk(level, dev, "%s Bus Error: severity=%s\n",
994 bus_type, aer_error_severity_string[info->severity]);
995
996 aer_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
997 dev->vendor, dev->device, info->status, info->mask);
998
999 __aer_print_error(dev, info);
1000
1001 if (info->tlp_header_valid && info->severity != AER_CORRECTABLE)
1002 pcie_print_tlp_log(dev, &info->tlp, level, dev_fmt(" "));
1003
1004 anfe:
1005 /* Recursive invocation for Advisory Non-Fatal Errors */
1006 if (info->anfe_status && info->severity == AER_CORRECTABLE) {
1007 info->severity = AER_NONFATAL;
1008 info->status = info->anfe_status;
1009 info->mask = 0;
1010
1011 aer_print_error(info, i);
1012
1013 info->severity = AER_CORRECTABLE;
1014 }
1015 }
1016
1017 #ifdef CONFIG_ACPI_APEI_PCIEAER
cper_severity_to_aer(int cper_severity)1018 int cper_severity_to_aer(int cper_severity)
1019 {
1020 switch (cper_severity) {
1021 case CPER_SEV_RECOVERABLE:
1022 return AER_NONFATAL;
1023 case CPER_SEV_FATAL:
1024 return AER_FATAL;
1025 default:
1026 return AER_CORRECTABLE;
1027 }
1028 }
1029 EXPORT_SYMBOL_GPL(cper_severity_to_aer);
1030 #endif
1031
__pci_print_aer(struct pci_dev * dev,int aer_severity,struct aer_capability_regs * aer,bool ratelimit_print,const char * level)1032 static void __pci_print_aer(struct pci_dev *dev, int aer_severity,
1033 struct aer_capability_regs *aer,
1034 bool ratelimit_print, const char *level)
1035 {
1036 const char *bus_type, *sev;
1037 int tlp_header_valid = 0;
1038 u32 status, mask;
1039 struct aer_err_info info = {
1040 .level = level,
1041 .severity = aer_severity,
1042 .first_error = PCI_ERR_CAP_FEP(aer->cap_control),
1043 };
1044
1045 if (aer_severity == AER_CORRECTABLE) {
1046 status = aer->cor_status;
1047 mask = aer->cor_mask;
1048 sev = "cor";
1049 } else {
1050 status = aer->uncor_status;
1051 mask = aer->uncor_mask;
1052 sev = "uncor";
1053 tlp_header_valid = tlp_header_logged(status & ~mask,
1054 aer->cap_control);
1055 }
1056
1057 info.status = status;
1058 info.mask = mask;
1059 info.is_cxl = pcie_is_cxl(dev);
1060
1061 bus_type = aer_err_bus(&info);
1062
1063 pci_dev_aer_stats_incr(dev, &info);
1064 trace_aer_event(pci_name(dev), (status & ~mask), aer_severity,
1065 tlp_header_valid, &aer->header_log, bus_type);
1066
1067 /*
1068 * For Advisory Non-Fatal Errors, record statistics and tracing
1069 * even if ratelimited
1070 */
1071 if (!ratelimit_print)
1072 goto anfe;
1073
1074 aer_printk(info.level, dev,
1075 "aer_%s_status: 0x%08x, aer_%s_mask: 0x%08x\n",
1076 sev, status, sev, mask);
1077 __aer_print_error(dev, &info);
1078
1079 if (aer_severity != AER_CORRECTABLE)
1080 aer_printk(info.level, dev, "aer_uncor_severity: 0x%08x\n",
1081 aer->uncor_severity);
1082
1083 if (tlp_header_valid)
1084 pcie_print_tlp_log(dev, &aer->header_log, info.level,
1085 dev_fmt(" "));
1086
1087 anfe:
1088 /* Recursive invocation for Advisory Non-Fatal Errors */
1089 if (aer_severity == AER_CORRECTABLE &&
1090 info.status & ~info.mask & PCI_ERR_COR_ADV_NFAT) {
1091 u32 anfe_status = aer_compute_anfe_status(PCI_EXP_DEVSTA_CED,
1092 aer->uncor_status,
1093 aer->uncor_mask,
1094 aer->uncor_severity);
1095 if (anfe_status) {
1096 aer->uncor_status = anfe_status;
1097 aer->uncor_mask = 0;
1098 __pci_print_aer(dev, AER_NONFATAL, aer,
1099 ratelimit_print, level);
1100 }
1101 }
1102 }
1103
pci_print_aer(struct pci_dev * dev,int aer_severity,struct aer_capability_regs * aer)1104 void pci_print_aer(struct pci_dev *dev, int aer_severity,
1105 struct aer_capability_regs *aer)
1106 {
1107 /*
1108 * Precalculate ratelimit counter and log level so that Advisory
1109 * Non-Fatal Errors are treated like the accompanying Correctable Error
1110 */
1111 bool ratelimit_print = aer_ratelimit(dev, aer_severity);
1112 const char *level = aer_severity == AER_CORRECTABLE ? KERN_WARNING
1113 : KERN_ERR;
1114
1115 __pci_print_aer(dev, aer_severity, aer, ratelimit_print, level);
1116 }
1117 EXPORT_SYMBOL_GPL(pci_print_aer);
1118
1119 /**
1120 * add_error_device - list device to be handled
1121 * @e_info: pointer to error info
1122 * @dev: pointer to pci_dev to be added
1123 */
add_error_device(struct aer_err_info * e_info,struct pci_dev * dev)1124 static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
1125 {
1126 int i = e_info->error_dev_num;
1127
1128 if (i >= AER_MAX_MULTI_ERR_DEVICES)
1129 return -ENOSPC;
1130
1131 e_info->dev[i] = pci_dev_get(dev);
1132 e_info->error_dev_num++;
1133
1134 /*
1135 * Ratelimit AER log messages. "dev" is either the source
1136 * identified by the root's Error Source ID or it has an unmasked
1137 * error logged in its own AER Capability. Messages are emitted
1138 * when "ratelimit_print[i]" is non-zero. If we will print detail
1139 * for a downstream device, make sure we print the Error Source ID
1140 * from the root as well.
1141 */
1142 if (aer_ratelimit(dev, e_info->severity)) {
1143 e_info->ratelimit_print[i] = 1;
1144 e_info->root_ratelimit_print = 1;
1145 }
1146 return 0;
1147 }
1148
1149 /**
1150 * is_error_source - check whether the device is source of reported error
1151 * @dev: pointer to pci_dev to be checked
1152 * @e_info: pointer to reported error info
1153 */
is_error_source(struct pci_dev * dev,struct aer_err_info * e_info)1154 static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
1155 {
1156 int aer = dev->aer_cap;
1157 u32 status, mask;
1158 u16 reg16;
1159
1160 /*
1161 * When bus ID is equal to 0, it might be a bad ID
1162 * reported by Root Port.
1163 */
1164 if ((PCI_BUS_NUM(e_info->id) != 0) &&
1165 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
1166 /* Device ID match? */
1167 if (e_info->id == pci_dev_id(dev))
1168 return true;
1169
1170 /* Continue ID comparing if there is no multiple error */
1171 if (!e_info->multi_error_valid)
1172 return false;
1173 }
1174
1175 /*
1176 * When either
1177 * 1) bus ID is equal to 0. Some ports might lose the bus
1178 * ID of error source id;
1179 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
1180 * 3) There are multiple errors and prior ID comparing fails;
1181 * We check AER status registers to find possible reporter.
1182 */
1183
1184 /* Check if AER is enabled */
1185 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16);
1186 if (!(reg16 & PCI_EXP_AER_FLAGS))
1187 return false;
1188
1189 if (!aer)
1190 return false;
1191
1192 /* Check if error is recorded */
1193 if (e_info->severity == AER_CORRECTABLE) {
1194 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
1195 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
1196 } else {
1197 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
1198 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
1199 }
1200 if (status & ~mask)
1201 return true;
1202
1203 return false;
1204 }
1205
find_device_iter(struct pci_dev * dev,void * data)1206 static int find_device_iter(struct pci_dev *dev, void *data)
1207 {
1208 struct aer_err_info *e_info = (struct aer_err_info *)data;
1209
1210 if (is_error_source(dev, e_info)) {
1211 /* List this device */
1212 if (add_error_device(e_info, dev)) {
1213 /* We cannot handle more... Stop iteration */
1214 pci_err(dev, "Exceeded max supported (%d) devices with errors logged\n",
1215 AER_MAX_MULTI_ERR_DEVICES);
1216 return 1;
1217 }
1218
1219 /* If there is only a single error, stop iteration */
1220 if (!e_info->multi_error_valid)
1221 return 1;
1222 }
1223 return 0;
1224 }
1225
1226 /**
1227 * find_source_device - search through device hierarchy for source device
1228 * @parent: pointer to Root Port pci_dev data structure
1229 * @e_info: including detailed error information such as ID
1230 *
1231 * Return: true if found.
1232 *
1233 * Invoked by DPC when error is detected at the Root Port.
1234 * Caller of this function must set id, severity, and multi_error_valid of
1235 * struct aer_err_info pointed by @e_info properly. This function must fill
1236 * e_info->error_dev_num and e_info->dev[], based on the given information.
1237 */
find_source_device(struct pci_dev * parent,struct aer_err_info * e_info)1238 static bool find_source_device(struct pci_dev *parent,
1239 struct aer_err_info *e_info)
1240 {
1241 struct pci_dev *dev = parent;
1242 int result;
1243
1244 /* Must reset in this function */
1245 e_info->error_dev_num = 0;
1246
1247 /* Is Root Port an agent that sends error message? */
1248 result = find_device_iter(dev, e_info);
1249 if (result)
1250 return true;
1251
1252 if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC)
1253 pcie_walk_rcec(parent, find_device_iter, e_info);
1254 else
1255 pci_walk_bus(parent->subordinate, find_device_iter, e_info);
1256
1257 if (!e_info->error_dev_num)
1258 return false;
1259 return true;
1260 }
1261
1262 /**
1263 * pci_aer_unmask_internal_errors - unmask internal errors
1264 * @dev: pointer to the pci_dev data structure
1265 *
1266 * Unmask internal errors in the Uncorrectable and Correctable Error
1267 * Mask registers.
1268 *
1269 * Note: AER must be enabled and supported by the device which must be
1270 * checked in advance, e.g. with pcie_aer_is_native().
1271 */
pci_aer_unmask_internal_errors(struct pci_dev * dev)1272 void pci_aer_unmask_internal_errors(struct pci_dev *dev)
1273 {
1274 int aer = dev->aer_cap;
1275 u32 mask;
1276
1277 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
1278 mask &= ~PCI_ERR_UNC_INTN;
1279 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask);
1280
1281 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
1282 mask &= ~PCI_ERR_COR_INTERNAL;
1283 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
1284 }
1285
1286 /*
1287 * Internal errors are too device-specific to enable generally, however for CXL
1288 * their behavior is standardized for conveying CXL protocol errors.
1289 */
1290 EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core");
1291
1292 #ifdef CONFIG_CXL_RAS
is_aer_internal_error(struct aer_err_info * info)1293 bool is_aer_internal_error(struct aer_err_info *info)
1294 {
1295 if (info->severity == AER_CORRECTABLE)
1296 return info->status & PCI_ERR_COR_INTERNAL;
1297
1298 return info->status & PCI_ERR_UNC_INTN;
1299 }
1300 #endif
1301
1302 /**
1303 * pci_aer_handle_error - handle logging error into an event log
1304 * @dev: pointer to pci_dev data structure of error source device
1305 * @info: comprehensive error information
1306 *
1307 * Invoked when an error being detected by Root Port.
1308 */
pci_aer_handle_error(struct pci_dev * dev,struct aer_err_info * info)1309 static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info)
1310 {
1311 int aer = dev->aer_cap;
1312
1313 if (info->severity == AER_CORRECTABLE) {
1314 /*
1315 * Correctable error does not need software intervention.
1316 * No need to go through error recovery process.
1317 */
1318 if (aer) {
1319 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
1320 info->status);
1321 if (info->anfe_status)
1322 pci_write_config_dword(dev,
1323 aer + PCI_ERR_UNCOR_STATUS,
1324 info->anfe_status);
1325 }
1326 if (pcie_aer_is_native(dev)) {
1327 struct pci_driver *pdrv = dev->driver;
1328
1329 if (pdrv && pdrv->err_handler &&
1330 pdrv->err_handler->cor_error_detected)
1331 pdrv->err_handler->cor_error_detected(dev);
1332 pcie_clear_device_status(dev);
1333 }
1334 } else if (info->severity == AER_NONFATAL)
1335 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
1336 else if (info->severity == AER_FATAL)
1337 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
1338 }
1339
handle_error_source(struct pci_dev * dev,struct aer_err_info * info)1340 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
1341 {
1342 cxl_rch_handle_error(dev, info);
1343 pci_aer_handle_error(dev, info);
1344 pci_dev_put(dev);
1345 }
1346
1347 #ifdef CONFIG_ACPI_APEI_PCIEAER
1348
1349 #define AER_RECOVER_RING_SIZE 16
1350
1351 struct aer_recover_entry {
1352 u8 bus;
1353 u8 devfn;
1354 u16 domain;
1355 int severity;
1356 struct aer_capability_regs *regs;
1357 };
1358
1359 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
1360 AER_RECOVER_RING_SIZE);
1361
aer_recover_work_func(struct work_struct * work)1362 static void aer_recover_work_func(struct work_struct *work)
1363 {
1364 struct aer_capability_regs *regs;
1365 struct aer_recover_entry entry;
1366 struct pci_dev *pdev;
1367 u32 err;
1368
1369 while (kfifo_get(&aer_recover_ring, &entry)) {
1370 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
1371 entry.devfn);
1372 if (!pdev) {
1373 pr_err_ratelimited("%04x:%02x:%02x.%x: no pci_dev found\n",
1374 entry.domain, entry.bus,
1375 PCI_SLOT(entry.devfn),
1376 PCI_FUNC(entry.devfn));
1377 continue;
1378 }
1379 pci_print_aer(pdev, entry.severity, entry.regs);
1380
1381 regs = entry.regs;
1382 if (entry.severity == AER_CORRECTABLE)
1383 err = regs->cor_status & ~regs->cor_mask;
1384 else
1385 err = regs->uncor_status & ~regs->uncor_mask;
1386
1387 /*
1388 * Memory for aer_capability_regs(entry.regs) is being
1389 * allocated from the ghes_estatus_pool to protect it from
1390 * overwriting when multiple sections are present in the
1391 * error status. Thus free the same after processing the
1392 * data.
1393 */
1394 ghes_estatus_pool_region_free((unsigned long)entry.regs,
1395 sizeof(struct aer_capability_regs));
1396
1397 if (err) {
1398 if (entry.severity == AER_NONFATAL)
1399 pcie_do_recovery(pdev, pci_channel_io_normal,
1400 aer_root_reset);
1401 else if (entry.severity == AER_FATAL)
1402 pcie_do_recovery(pdev, pci_channel_io_frozen,
1403 aer_root_reset);
1404 }
1405 pci_dev_put(pdev);
1406 }
1407 }
1408
1409 /*
1410 * Mutual exclusion for writers of aer_recover_ring, reader side don't
1411 * need lock, because there is only one reader and lock is not needed
1412 * between reader and writer.
1413 */
1414 static DEFINE_SPINLOCK(aer_recover_ring_lock);
1415 static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
1416
aer_recover_queue(int domain,unsigned int bus,unsigned int devfn,int severity,struct aer_capability_regs * aer_regs)1417 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
1418 int severity, struct aer_capability_regs *aer_regs)
1419 {
1420 struct aer_recover_entry entry = {
1421 .bus = bus,
1422 .devfn = devfn,
1423 .domain = domain,
1424 .severity = severity,
1425 .regs = aer_regs,
1426 };
1427
1428 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1,
1429 &aer_recover_ring_lock))
1430 schedule_work(&aer_recover_work);
1431 else
1432 pr_err("buffer overflow in recovery for %04x:%02x:%02x.%x\n",
1433 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1434 }
1435 EXPORT_SYMBOL_GPL(aer_recover_queue);
1436 #endif
1437
aer_get_uncor_info(struct pci_dev * dev,struct aer_err_info * info,u32 status)1438 static void aer_get_uncor_info(struct pci_dev *dev, struct aer_err_info *info,
1439 u32 status)
1440 {
1441 u16 aer = dev->aer_cap;
1442 u32 aercc;
1443
1444 /* Get First Error Pointer */
1445 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &aercc);
1446 info->first_error = PCI_ERR_CAP_FEP(aercc);
1447
1448 /* Get TLP Prefix/Header Log */
1449 if (tlp_header_logged(status, aercc)) {
1450 info->tlp_header_valid = 1;
1451 pcie_read_tlp_log(dev, aer + PCI_ERR_HEADER_LOG,
1452 aer + PCI_ERR_PREFIX_LOG,
1453 aer_tlp_log_len(dev, aercc),
1454 aercc & PCI_ERR_CAP_TLP_LOG_FLIT,
1455 &info->tlp);
1456 }
1457 }
1458
1459 /**
1460 * aer_get_device_error_info - read error status from dev and store it to info
1461 * @info: pointer to structure to store the error record
1462 * @i: index into info->dev[]
1463 *
1464 * Return: 1 on success, 0 on error.
1465 *
1466 * Note that @info is reused among all error devices. Clear fields properly.
1467 */
aer_get_device_error_info(struct aer_err_info * info,int i)1468 int aer_get_device_error_info(struct aer_err_info *info, int i)
1469 {
1470 struct pci_dev *dev;
1471 int type, aer;
1472
1473 if (i >= AER_MAX_MULTI_ERR_DEVICES)
1474 return 0;
1475
1476 dev = info->dev[i];
1477 aer = dev->aer_cap;
1478 type = pci_pcie_type(dev);
1479
1480 /* Must reset in this function */
1481 info->status = 0;
1482 info->anfe_status = 0;
1483 info->tlp_header_valid = 0;
1484 info->is_cxl = pcie_is_cxl(dev);
1485
1486 /* The device might not support AER */
1487 if (!aer)
1488 return 0;
1489
1490 if (info->severity == AER_CORRECTABLE) {
1491 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,
1492 &info->status);
1493 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
1494 &info->mask);
1495 if (!(info->status & ~info->mask))
1496 return 0;
1497 if (info->status & ~info->mask & PCI_ERR_COR_ADV_NFAT) {
1498 info->anfe_status = aer_get_anfe_status(dev);
1499 aer_get_uncor_info(dev, info, info->anfe_status);
1500 }
1501 } else if (type == PCI_EXP_TYPE_ROOT_PORT ||
1502 type == PCI_EXP_TYPE_RC_EC ||
1503 type == PCI_EXP_TYPE_DOWNSTREAM ||
1504 info->severity == AER_NONFATAL) {
1505
1506 /* Link is still healthy for IO reads */
1507 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
1508 &info->status);
1509 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
1510 &info->mask);
1511 if (!(info->status & ~info->mask))
1512 return 0;
1513
1514 aer_get_uncor_info(dev, info, info->status & ~info->mask);
1515 }
1516
1517 return 1;
1518 }
1519
aer_process_err_devices(struct aer_err_info * e_info)1520 static inline void aer_process_err_devices(struct aer_err_info *e_info)
1521 {
1522 int i;
1523
1524 /* Report all before handling them, to not lose records by reset etc. */
1525 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1526 if (aer_get_device_error_info(e_info, i))
1527 aer_print_error(e_info, i);
1528 }
1529 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1530 if (aer_get_device_error_info(e_info, i))
1531 handle_error_source(e_info->dev[i], e_info);
1532 }
1533 }
1534
1535 /**
1536 * aer_isr_one_error_type - consume a Correctable or Uncorrectable Error
1537 * detected by Root Port or RCEC
1538 * @root: pointer to Root Port or RCEC that signaled AER interrupt
1539 * @info: pointer to AER error info
1540 */
aer_isr_one_error_type(struct pci_dev * root,struct aer_err_info * info)1541 static void aer_isr_one_error_type(struct pci_dev *root,
1542 struct aer_err_info *info)
1543 {
1544 bool found;
1545
1546 found = find_source_device(root, info);
1547
1548 /*
1549 * If we're going to log error messages, we've already set
1550 * "info->root_ratelimit_print" and "info->ratelimit_print[i]" to
1551 * non-zero (which enables printing) because this is either an
1552 * ERR_FATAL or we found a device with an error logged in its AER
1553 * Capability.
1554 *
1555 * If we didn't find the Error Source device, at least log the
1556 * Requester ID from the ERR_* Message received by the Root Port or
1557 * RCEC, ratelimited by the RP or RCEC.
1558 */
1559 if (info->root_ratelimit_print ||
1560 (!found && aer_ratelimit(root, info->severity)))
1561 aer_print_source(root, info, found);
1562
1563 if (found)
1564 aer_process_err_devices(info);
1565 }
1566
1567 /**
1568 * aer_isr_one_error - consume error(s) signaled by an AER interrupt from
1569 * Root Port or RCEC
1570 * @root: pointer to Root Port or RCEC that signaled AER interrupt
1571 * @e_src: pointer to an error source
1572 */
aer_isr_one_error(struct pci_dev * root,struct aer_err_source * e_src)1573 static void aer_isr_one_error(struct pci_dev *root,
1574 struct aer_err_source *e_src)
1575 {
1576 u32 status = e_src->status;
1577
1578 pci_rootport_aer_stats_incr(root, e_src);
1579
1580 /*
1581 * There is a possibility that both correctable error and
1582 * uncorrectable error being logged. Report correctable error first.
1583 */
1584 if (status & PCI_ERR_ROOT_COR_RCV) {
1585 int multi = status & PCI_ERR_ROOT_MULTI_COR_RCV;
1586 struct aer_err_info e_info = {
1587 .id = ERR_COR_ID(e_src->id),
1588 .severity = AER_CORRECTABLE,
1589 .level = KERN_WARNING,
1590 .multi_error_valid = multi ? 1 : 0,
1591 };
1592
1593 aer_isr_one_error_type(root, &e_info);
1594 }
1595
1596 if (status & PCI_ERR_ROOT_UNCOR_RCV) {
1597 int fatal = status & PCI_ERR_ROOT_FATAL_RCV;
1598 int multi = status & PCI_ERR_ROOT_MULTI_UNCOR_RCV;
1599 struct aer_err_info e_info = {
1600 .id = ERR_UNCOR_ID(e_src->id),
1601 .severity = fatal ? AER_FATAL : AER_NONFATAL,
1602 .level = KERN_ERR,
1603 .multi_error_valid = multi ? 1 : 0,
1604 };
1605
1606 aer_isr_one_error_type(root, &e_info);
1607 }
1608 }
1609
1610 /**
1611 * aer_isr - consume errors detected by Root Port
1612 * @irq: IRQ assigned to Root Port
1613 * @context: pointer to Root Port data structure
1614 *
1615 * Invoked, as DPC, when Root Port records new detected error
1616 */
aer_isr(int irq,void * context)1617 static irqreturn_t aer_isr(int irq, void *context)
1618 {
1619 struct pcie_device *dev = (struct pcie_device *)context;
1620 struct aer_rpc *rpc = get_service_data(dev);
1621 struct aer_err_source e_src;
1622
1623 if (kfifo_is_empty(&rpc->aer_fifo))
1624 return IRQ_NONE;
1625
1626 while (kfifo_get(&rpc->aer_fifo, &e_src))
1627 aer_isr_one_error(rpc->rpd, &e_src);
1628 return IRQ_HANDLED;
1629 }
1630
1631 /**
1632 * aer_irq - Root Port's ISR
1633 * @irq: IRQ assigned to Root Port
1634 * @context: pointer to Root Port data structure
1635 *
1636 * Invoked when Root Port detects AER messages.
1637 */
aer_irq(int irq,void * context)1638 static irqreturn_t aer_irq(int irq, void *context)
1639 {
1640 struct pcie_device *pdev = (struct pcie_device *)context;
1641 struct aer_rpc *rpc = get_service_data(pdev);
1642 struct pci_dev *rp = rpc->rpd;
1643 int aer = rp->aer_cap;
1644 struct aer_err_source e_src = {};
1645
1646 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);
1647 if (!(e_src.status & AER_ERR_STATUS_MASK))
1648 return IRQ_NONE;
1649
1650 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
1651 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);
1652
1653 if (!kfifo_put(&rpc->aer_fifo, e_src))
1654 return IRQ_HANDLED;
1655
1656 return IRQ_WAKE_THREAD;
1657 }
1658
aer_enable_irq(struct pci_dev * pdev)1659 static void aer_enable_irq(struct pci_dev *pdev)
1660 {
1661 int aer = pdev->aer_cap;
1662 u32 reg32;
1663
1664 /* Enable Root Port's interrupt in response to error messages */
1665 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1666 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1667 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1668 }
1669
aer_disable_irq(struct pci_dev * pdev)1670 static void aer_disable_irq(struct pci_dev *pdev)
1671 {
1672 int aer = pdev->aer_cap;
1673 u32 reg32;
1674
1675 /* Disable Root Port's interrupt in response to error messages */
1676 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1677 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1678 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1679 }
1680
clear_status_iter(struct pci_dev * dev,void * data)1681 static int clear_status_iter(struct pci_dev *dev, void *data)
1682 {
1683 u16 devctl;
1684
1685 /* Skip if pci_enable_pcie_error_reporting() hasn't been called yet */
1686 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &devctl);
1687 if (!(devctl & PCI_EXP_AER_FLAGS))
1688 return 0;
1689
1690 pci_aer_clear_status(dev);
1691 pcie_clear_device_status(dev);
1692 return 0;
1693 }
1694
1695 /**
1696 * aer_enable_rootport - enable Root Port's interrupts when receiving messages
1697 * @rpc: pointer to a Root Port data structure
1698 *
1699 * Invoked when PCIe bus loads AER service driver.
1700 */
aer_enable_rootport(struct aer_rpc * rpc)1701 static void aer_enable_rootport(struct aer_rpc *rpc)
1702 {
1703 struct pci_dev *pdev = rpc->rpd;
1704 int aer = pdev->aer_cap;
1705 u16 reg16;
1706 u32 reg32;
1707
1708 /* Clear PCIe Capability's Device Status */
1709 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16);
1710 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
1711
1712 /* Disable system error generation in response to error messages */
1713 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
1714 SYSTEM_ERROR_INTR_ON_MESG_MASK);
1715
1716 /* Clear error status of this Root Port or RCEC */
1717 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1718 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1719
1720 /* Clear error status of agents reporting to this Root Port or RCEC */
1721 if (reg32 & AER_ERR_STATUS_MASK) {
1722 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_EC)
1723 pcie_walk_rcec(pdev, clear_status_iter, NULL);
1724 else if (pdev->subordinate)
1725 pci_walk_bus(pdev->subordinate, clear_status_iter,
1726 NULL);
1727 }
1728
1729 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32);
1730 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);
1731 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32);
1732 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);
1733
1734 aer_enable_irq(pdev);
1735 }
1736
1737 /**
1738 * aer_disable_rootport - disable Root Port's interrupts when receiving messages
1739 * @rpc: pointer to a Root Port data structure
1740 *
1741 * Invoked when PCIe bus unloads AER service driver.
1742 */
aer_disable_rootport(struct aer_rpc * rpc)1743 static void aer_disable_rootport(struct aer_rpc *rpc)
1744 {
1745 struct pci_dev *pdev = rpc->rpd;
1746 int aer = pdev->aer_cap;
1747 u32 reg32;
1748
1749 aer_disable_irq(pdev);
1750
1751 /* Clear Root's error status reg */
1752 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1753 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1754 }
1755
1756 /**
1757 * aer_remove - clean up resources
1758 * @dev: pointer to the pcie_dev data structure
1759 *
1760 * Invoked when PCI Express bus unloads or AER probe fails.
1761 */
aer_remove(struct pcie_device * dev)1762 static void aer_remove(struct pcie_device *dev)
1763 {
1764 struct aer_rpc *rpc = get_service_data(dev);
1765
1766 aer_disable_rootport(rpc);
1767 }
1768
1769 /**
1770 * aer_probe - initialize resources
1771 * @dev: pointer to the pcie_dev data structure
1772 *
1773 * Invoked when PCI Express bus loads AER service driver.
1774 */
aer_probe(struct pcie_device * dev)1775 static int aer_probe(struct pcie_device *dev)
1776 {
1777 int status;
1778 struct aer_rpc *rpc;
1779 struct device *device = &dev->device;
1780 struct pci_dev *port = dev->port;
1781
1782 BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) <
1783 AER_MAX_TYPEOF_COR_ERRS);
1784 BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) <
1785 AER_MAX_TYPEOF_UNCOR_ERRS);
1786
1787 /* Limit to Root Ports or Root Complex Event Collectors */
1788 if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) &&
1789 (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT))
1790 return -ENODEV;
1791
1792 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
1793 if (!rpc)
1794 return -ENOMEM;
1795
1796 rpc->rpd = port;
1797 INIT_KFIFO(rpc->aer_fifo);
1798 set_service_data(dev, rpc);
1799
1800 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr,
1801 IRQF_SHARED, "aerdrv", dev);
1802 if (status) {
1803 pci_err(port, "request AER IRQ %d failed\n", dev->irq);
1804 return status;
1805 }
1806
1807 cxl_rch_enable_rcec(port);
1808 aer_enable_rootport(rpc);
1809 pci_info(port, "enabled with IRQ %d\n", dev->irq);
1810 return 0;
1811 }
1812
aer_suspend(struct pcie_device * dev)1813 static int aer_suspend(struct pcie_device *dev)
1814 {
1815 struct aer_rpc *rpc = get_service_data(dev);
1816
1817 aer_disable_rootport(rpc);
1818 return 0;
1819 }
1820
aer_resume(struct pcie_device * dev)1821 static int aer_resume(struct pcie_device *dev)
1822 {
1823 struct aer_rpc *rpc = get_service_data(dev);
1824
1825 aer_enable_rootport(rpc);
1826 return 0;
1827 }
1828
1829 /**
1830 * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP
1831 * @dev: pointer to Root Port, RCEC, or RCiEP
1832 *
1833 * Invoked by Port Bus driver when performing reset.
1834 */
aer_root_reset(struct pci_dev * dev)1835 static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
1836 {
1837 int type = pci_pcie_type(dev);
1838 struct pci_dev *root;
1839 int aer;
1840 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
1841 u32 reg32;
1842 int rc;
1843
1844 /*
1845 * Only Root Ports and RCECs have AER Root Command and Root Status
1846 * registers. If "dev" is an RCiEP, the relevant registers are in
1847 * the RCEC.
1848 */
1849 if (type == PCI_EXP_TYPE_RC_END)
1850 root = dev->rcec;
1851 else
1852 root = pcie_find_root_port(dev);
1853
1854 /*
1855 * If the platform retained control of AER, an RCiEP may not have
1856 * an RCEC visible to us, so dev->rcec ("root") may be NULL. In
1857 * that case, firmware is responsible for these registers.
1858 */
1859 aer = root ? root->aer_cap : 0;
1860
1861 if ((host->native_aer || pcie_ports_native) && aer)
1862 aer_disable_irq(root);
1863
1864 if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) {
1865 rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET);
1866 if (!rc)
1867 pci_info(dev, "has been reset\n");
1868 else
1869 pci_info(dev, "not reset (no FLR support: %d)\n", rc);
1870 } else {
1871 rc = pci_bus_error_reset(dev);
1872 pci_info(dev, "%s Port link has been reset (%d)\n",
1873 pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc);
1874 }
1875
1876 if ((host->native_aer || pcie_ports_native) && aer) {
1877 /* Clear Root Error Status */
1878 pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32);
1879 pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32);
1880
1881 aer_enable_irq(root);
1882 }
1883
1884 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1885 }
1886
1887 static struct pcie_port_service_driver aerdriver = {
1888 .name = "aer",
1889 .port_type = PCIE_ANY_PORT,
1890 .service = PCIE_PORT_SERVICE_AER,
1891
1892 .probe = aer_probe,
1893 .suspend = aer_suspend,
1894 .resume = aer_resume,
1895 .remove = aer_remove,
1896 };
1897
1898 /**
1899 * pcie_aer_init - register AER service driver
1900 *
1901 * Invoked when AER service driver is loaded.
1902 */
pcie_aer_init(void)1903 int __init pcie_aer_init(void)
1904 {
1905 if (!pci_aer_available())
1906 return -ENXIO;
1907 return pcie_port_service_register(&aerdriver);
1908 }
1909