1 #ifndef __src_nvidia_inc_kernel_gpu_gsp_gsp_static_config_h__ 2 #define __src_nvidia_inc_kernel_gpu_gsp_gsp_static_config_h__ 3 #include <nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h> 4 #include <nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h> 5 #include <nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h> 6 #include <nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h> 7 #include <nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h> 8 #include <nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h> 9 #include <nvrm/535.113.01/nvidia/generated/g_chipset_nvoc.h> 10 #include <nvrm/535.113.01/nvidia/generated/g_gpu_nvoc.h> 11 #include <nvrm/535.113.01/nvidia/inc/kernel/gpu/gpu_acpi_data.h> 12 #include <nvrm/535.113.01/nvidia/inc/kernel/gpu/nvbitmask.h> 13 #include <nvrm/535.113.01/nvidia/kernel/inc/vgpu/rpc_headers.h> 14 15 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ 16 17 /* 18 * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 19 * SPDX-License-Identifier: MIT 20 * 21 * Permission is hereby granted, free of charge, to any person obtaining a 22 * copy of this software and associated documentation files (the "Software"), 23 * to deal in the Software without restriction, including without limitation 24 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 25 * and/or sell copies of the Software, and to permit persons to whom the 26 * Software is furnished to do so, subject to the following conditions: 27 * 28 * The above copyright notice and this permission notice shall be included in 29 * all copies or substantial portions of the Software. 30 * 31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 32 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 33 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 34 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 35 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 36 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 37 * DEALINGS IN THE SOFTWARE. 38 */ 39 40 typedef struct GSP_VF_INFO 41 { 42 NvU32 totalVFs; 43 NvU32 firstVFOffset; 44 NvU64 FirstVFBar0Address; 45 NvU64 FirstVFBar1Address; 46 NvU64 FirstVFBar2Address; 47 NvBool b64bitBar0; 48 NvBool b64bitBar1; 49 NvBool b64bitBar2; 50 } GSP_VF_INFO; 51 52 typedef struct GspSMInfo_t 53 { 54 NvU32 version; 55 NvU32 regBankCount; 56 NvU32 regBankRegCount; 57 NvU32 maxWarpsPerSM; 58 NvU32 maxThreadsPerWarp; 59 NvU32 geomGsObufEntries; 60 NvU32 geomXbufEntries; 61 NvU32 maxSPPerSM; 62 NvU32 rtCoreCount; 63 } GspSMInfo; 64 65 typedef struct GspStaticConfigInfo_t 66 { 67 NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE]; 68 NV2080_CTRL_GPU_GET_GID_INFO_PARAMS gidInfo; 69 NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS gpcInfo; 70 NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS tpcInfo[MAX_GPC_COUNT]; 71 NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS zcullInfo[MAX_GPC_COUNT]; 72 NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo; 73 NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams; 74 COMPUTE_BRANDING_TYPE computeBranding; 75 76 NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps; 77 NvU32 sriovMaxGfid; 78 79 NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX]; 80 81 GspSMInfo SM_info; 82 83 NvBool poisonFuseEnabled; 84 85 NvU64 fb_length; 86 NvU32 fbio_mask; 87 NvU32 fb_bus_width; 88 NvU32 fb_ram_type; 89 NvU32 fbp_mask; 90 NvU32 l2_cache_size; 91 92 NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; 93 NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; 94 95 NvU8 gpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 96 NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 97 NvU16 gpuNameString_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 98 NvBool bGpuInternalSku; 99 NvBool bIsQuadroGeneric; 100 NvBool bIsQuadroAd; 101 NvBool bIsNvidiaNvs; 102 NvBool bIsVgx; 103 NvBool bGeforceSmb; 104 NvBool bIsTitan; 105 NvBool bIsTesla; 106 NvBool bIsMobile; 107 NvBool bIsGc6Rtd3Allowed; 108 NvBool bIsGcOffRtd3Allowed; 109 NvBool bIsGcoffLegacyAllowed; 110 111 NvU64 bar1PdeBase; 112 NvU64 bar2PdeBase; 113 114 NvBool bVbiosValid; 115 NvU32 vbiosSubVendor; 116 NvU32 vbiosSubDevice; 117 118 NvBool bPageRetirementSupported; 119 120 NvBool bSplitVasBetweenServerClientRm; 121 122 NvBool bClRootportNeedsNosnoopWAR; 123 124 VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads; 125 VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution; 126 NvU64 displaylessMaxPixels; 127 128 // Client handle for internal RMAPI control. 129 NvHandle hInternalClient; 130 131 // Device handle for internal RMAPI control. 132 NvHandle hInternalDevice; 133 134 // Subdevice handle for internal RMAPI control. 135 NvHandle hInternalSubdevice; 136 137 NvBool bSelfHostedMode; 138 NvBool bAtsSupported; 139 140 NvBool bIsGpuUefi; 141 } GspStaticConfigInfo; 142 143 typedef struct GspSystemInfo 144 { 145 NvU64 gpuPhysAddr; 146 NvU64 gpuPhysFbAddr; 147 NvU64 gpuPhysInstAddr; 148 NvU64 nvDomainBusDeviceFunc; 149 NvU64 simAccessBufPhysAddr; 150 NvU64 pcieAtomicsOpMask; 151 NvU64 consoleMemSize; 152 NvU64 maxUserVa; 153 NvU32 pciConfigMirrorBase; 154 NvU32 pciConfigMirrorSize; 155 NvU8 oorArch; 156 NvU64 clPdbProperties; 157 NvU32 Chipset; 158 NvBool bGpuBehindBridge; 159 NvBool bMnocAvailable; 160 NvBool bUpstreamL0sUnsupported; 161 NvBool bUpstreamL1Unsupported; 162 NvBool bUpstreamL1PorSupported; 163 NvBool bUpstreamL1PorMobileOnly; 164 NvU8 upstreamAddressValid; 165 BUSINFO FHBBusInfo; 166 BUSINFO chipsetIDInfo; 167 ACPI_METHOD_DATA acpiMethodData; 168 NvU32 hypervisorType; 169 NvBool bIsPassthru; 170 NvU64 sysTimerOffsetNs; 171 GSP_VF_INFO gspVFInfo; 172 } GspSystemInfo; 173 174 #endif 175