1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
3
4 #include <linux/module.h>
5 #include <linux/of.h>
6 #include <linux/platform_device.h>
7
8 #include "pinctrl-msm.h"
9
10 static const char * const sm8150_tiles[] = {
11 "north",
12 "south",
13 "east",
14 "west"
15 };
16
17 enum {
18 NORTH,
19 SOUTH,
20 EAST,
21 WEST
22 };
23
24 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
25 { \
26 .grp = PINCTRL_PINGROUP("gpio" #id, \
27 gpio##id##_pins, \
28 ARRAY_SIZE(gpio##id##_pins)), \
29 .funcs = (int[]){ \
30 msm_mux_gpio, /* gpio mode */ \
31 msm_mux_##f1, \
32 msm_mux_##f2, \
33 msm_mux_##f3, \
34 msm_mux_##f4, \
35 msm_mux_##f5, \
36 msm_mux_##f6, \
37 msm_mux_##f7, \
38 msm_mux_##f8, \
39 msm_mux_##f9 \
40 }, \
41 .nfuncs = 10, \
42 .ctl_reg = 0x1000 * id, \
43 .io_reg = 0x1000 * id + 0x4, \
44 .intr_cfg_reg = 0x1000 * id + 0x8, \
45 .intr_status_reg = 0x1000 * id + 0xc, \
46 .tile = _tile, \
47 .mux_bit = 2, \
48 .pull_bit = 0, \
49 .drv_bit = 6, \
50 .oe_bit = 9, \
51 .in_bit = 0, \
52 .out_bit = 1, \
53 .intr_enable_bit = 0, \
54 .intr_status_bit = 0, \
55 .intr_target_bit = 5, \
56 .intr_target_kpss_val = 3, \
57 .intr_raw_status_bit = 4, \
58 .intr_polarity_bit = 1, \
59 .intr_detection_bit = 2, \
60 .intr_detection_width = 2, \
61 }
62
63 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
64 { \
65 .grp = PINCTRL_PINGROUP(#pg_name, \
66 pg_name##_pins, \
67 ARRAY_SIZE(pg_name##_pins)), \
68 .ctl_reg = ctl, \
69 .io_reg = 0, \
70 .intr_cfg_reg = 0, \
71 .intr_status_reg = 0, \
72 .tile = NORTH, \
73 .mux_bit = -1, \
74 .pull_bit = pull, \
75 .drv_bit = drv, \
76 .oe_bit = -1, \
77 .in_bit = -1, \
78 .out_bit = -1, \
79 .intr_enable_bit = -1, \
80 .intr_status_bit = -1, \
81 .intr_target_bit = -1, \
82 .intr_raw_status_bit = -1, \
83 .intr_polarity_bit = -1, \
84 .intr_detection_bit = -1, \
85 .intr_detection_width = -1, \
86 }
87
88 #define UFS_RESET(pg_name, offset) \
89 { \
90 .grp = PINCTRL_PINGROUP(#pg_name, \
91 pg_name##_pins, \
92 ARRAY_SIZE(pg_name##_pins)), \
93 .ctl_reg = offset, \
94 .io_reg = offset + 0x4, \
95 .intr_cfg_reg = 0, \
96 .intr_status_reg = 0, \
97 .tile = SOUTH, \
98 .mux_bit = -1, \
99 .pull_bit = 3, \
100 .drv_bit = 0, \
101 .oe_bit = -1, \
102 .in_bit = -1, \
103 .out_bit = 0, \
104 .intr_enable_bit = -1, \
105 .intr_status_bit = -1, \
106 .intr_target_bit = -1, \
107 .intr_raw_status_bit = -1, \
108 .intr_polarity_bit = -1, \
109 .intr_detection_bit = -1, \
110 .intr_detection_width = -1, \
111 }
112
113 static const struct pinctrl_pin_desc sm8150_pins[] = {
114 PINCTRL_PIN(0, "GPIO_0"),
115 PINCTRL_PIN(1, "GPIO_1"),
116 PINCTRL_PIN(2, "GPIO_2"),
117 PINCTRL_PIN(3, "GPIO_3"),
118 PINCTRL_PIN(4, "GPIO_4"),
119 PINCTRL_PIN(5, "GPIO_5"),
120 PINCTRL_PIN(6, "GPIO_6"),
121 PINCTRL_PIN(7, "GPIO_7"),
122 PINCTRL_PIN(8, "GPIO_8"),
123 PINCTRL_PIN(9, "GPIO_9"),
124 PINCTRL_PIN(10, "GPIO_10"),
125 PINCTRL_PIN(11, "GPIO_11"),
126 PINCTRL_PIN(12, "GPIO_12"),
127 PINCTRL_PIN(13, "GPIO_13"),
128 PINCTRL_PIN(14, "GPIO_14"),
129 PINCTRL_PIN(15, "GPIO_15"),
130 PINCTRL_PIN(16, "GPIO_16"),
131 PINCTRL_PIN(17, "GPIO_17"),
132 PINCTRL_PIN(18, "GPIO_18"),
133 PINCTRL_PIN(19, "GPIO_19"),
134 PINCTRL_PIN(20, "GPIO_20"),
135 PINCTRL_PIN(21, "GPIO_21"),
136 PINCTRL_PIN(22, "GPIO_22"),
137 PINCTRL_PIN(23, "GPIO_23"),
138 PINCTRL_PIN(24, "GPIO_24"),
139 PINCTRL_PIN(25, "GPIO_25"),
140 PINCTRL_PIN(26, "GPIO_26"),
141 PINCTRL_PIN(27, "GPIO_27"),
142 PINCTRL_PIN(28, "GPIO_28"),
143 PINCTRL_PIN(29, "GPIO_29"),
144 PINCTRL_PIN(30, "GPIO_30"),
145 PINCTRL_PIN(31, "GPIO_31"),
146 PINCTRL_PIN(32, "GPIO_32"),
147 PINCTRL_PIN(33, "GPIO_33"),
148 PINCTRL_PIN(34, "GPIO_34"),
149 PINCTRL_PIN(35, "GPIO_35"),
150 PINCTRL_PIN(36, "GPIO_36"),
151 PINCTRL_PIN(37, "GPIO_37"),
152 PINCTRL_PIN(38, "GPIO_38"),
153 PINCTRL_PIN(39, "GPIO_39"),
154 PINCTRL_PIN(40, "GPIO_40"),
155 PINCTRL_PIN(41, "GPIO_41"),
156 PINCTRL_PIN(42, "GPIO_42"),
157 PINCTRL_PIN(43, "GPIO_43"),
158 PINCTRL_PIN(44, "GPIO_44"),
159 PINCTRL_PIN(45, "GPIO_45"),
160 PINCTRL_PIN(46, "GPIO_46"),
161 PINCTRL_PIN(47, "GPIO_47"),
162 PINCTRL_PIN(48, "GPIO_48"),
163 PINCTRL_PIN(49, "GPIO_49"),
164 PINCTRL_PIN(50, "GPIO_50"),
165 PINCTRL_PIN(51, "GPIO_51"),
166 PINCTRL_PIN(52, "GPIO_52"),
167 PINCTRL_PIN(53, "GPIO_53"),
168 PINCTRL_PIN(54, "GPIO_54"),
169 PINCTRL_PIN(55, "GPIO_55"),
170 PINCTRL_PIN(56, "GPIO_56"),
171 PINCTRL_PIN(57, "GPIO_57"),
172 PINCTRL_PIN(58, "GPIO_58"),
173 PINCTRL_PIN(59, "GPIO_59"),
174 PINCTRL_PIN(60, "GPIO_60"),
175 PINCTRL_PIN(61, "GPIO_61"),
176 PINCTRL_PIN(62, "GPIO_62"),
177 PINCTRL_PIN(63, "GPIO_63"),
178 PINCTRL_PIN(64, "GPIO_64"),
179 PINCTRL_PIN(65, "GPIO_65"),
180 PINCTRL_PIN(66, "GPIO_66"),
181 PINCTRL_PIN(67, "GPIO_67"),
182 PINCTRL_PIN(68, "GPIO_68"),
183 PINCTRL_PIN(69, "GPIO_69"),
184 PINCTRL_PIN(70, "GPIO_70"),
185 PINCTRL_PIN(71, "GPIO_71"),
186 PINCTRL_PIN(72, "GPIO_72"),
187 PINCTRL_PIN(73, "GPIO_73"),
188 PINCTRL_PIN(74, "GPIO_74"),
189 PINCTRL_PIN(75, "GPIO_75"),
190 PINCTRL_PIN(76, "GPIO_76"),
191 PINCTRL_PIN(77, "GPIO_77"),
192 PINCTRL_PIN(78, "GPIO_78"),
193 PINCTRL_PIN(79, "GPIO_79"),
194 PINCTRL_PIN(80, "GPIO_80"),
195 PINCTRL_PIN(81, "GPIO_81"),
196 PINCTRL_PIN(82, "GPIO_82"),
197 PINCTRL_PIN(83, "GPIO_83"),
198 PINCTRL_PIN(84, "GPIO_84"),
199 PINCTRL_PIN(85, "GPIO_85"),
200 PINCTRL_PIN(86, "GPIO_86"),
201 PINCTRL_PIN(87, "GPIO_87"),
202 PINCTRL_PIN(88, "GPIO_88"),
203 PINCTRL_PIN(89, "GPIO_89"),
204 PINCTRL_PIN(90, "GPIO_90"),
205 PINCTRL_PIN(91, "GPIO_91"),
206 PINCTRL_PIN(92, "GPIO_92"),
207 PINCTRL_PIN(93, "GPIO_93"),
208 PINCTRL_PIN(94, "GPIO_94"),
209 PINCTRL_PIN(95, "GPIO_95"),
210 PINCTRL_PIN(96, "GPIO_96"),
211 PINCTRL_PIN(97, "GPIO_97"),
212 PINCTRL_PIN(98, "GPIO_98"),
213 PINCTRL_PIN(99, "GPIO_99"),
214 PINCTRL_PIN(100, "GPIO_100"),
215 PINCTRL_PIN(101, "GPIO_101"),
216 PINCTRL_PIN(102, "GPIO_102"),
217 PINCTRL_PIN(103, "GPIO_103"),
218 PINCTRL_PIN(104, "GPIO_104"),
219 PINCTRL_PIN(105, "GPIO_105"),
220 PINCTRL_PIN(106, "GPIO_106"),
221 PINCTRL_PIN(107, "GPIO_107"),
222 PINCTRL_PIN(108, "GPIO_108"),
223 PINCTRL_PIN(109, "GPIO_109"),
224 PINCTRL_PIN(110, "GPIO_110"),
225 PINCTRL_PIN(111, "GPIO_111"),
226 PINCTRL_PIN(112, "GPIO_112"),
227 PINCTRL_PIN(113, "GPIO_113"),
228 PINCTRL_PIN(114, "GPIO_114"),
229 PINCTRL_PIN(115, "GPIO_115"),
230 PINCTRL_PIN(116, "GPIO_116"),
231 PINCTRL_PIN(117, "GPIO_117"),
232 PINCTRL_PIN(118, "GPIO_118"),
233 PINCTRL_PIN(119, "GPIO_119"),
234 PINCTRL_PIN(120, "GPIO_120"),
235 PINCTRL_PIN(121, "GPIO_121"),
236 PINCTRL_PIN(122, "GPIO_122"),
237 PINCTRL_PIN(123, "GPIO_123"),
238 PINCTRL_PIN(124, "GPIO_124"),
239 PINCTRL_PIN(125, "GPIO_125"),
240 PINCTRL_PIN(126, "GPIO_126"),
241 PINCTRL_PIN(127, "GPIO_127"),
242 PINCTRL_PIN(128, "GPIO_128"),
243 PINCTRL_PIN(129, "GPIO_129"),
244 PINCTRL_PIN(130, "GPIO_130"),
245 PINCTRL_PIN(131, "GPIO_131"),
246 PINCTRL_PIN(132, "GPIO_132"),
247 PINCTRL_PIN(133, "GPIO_133"),
248 PINCTRL_PIN(134, "GPIO_134"),
249 PINCTRL_PIN(135, "GPIO_135"),
250 PINCTRL_PIN(136, "GPIO_136"),
251 PINCTRL_PIN(137, "GPIO_137"),
252 PINCTRL_PIN(138, "GPIO_138"),
253 PINCTRL_PIN(139, "GPIO_139"),
254 PINCTRL_PIN(140, "GPIO_140"),
255 PINCTRL_PIN(141, "GPIO_141"),
256 PINCTRL_PIN(142, "GPIO_142"),
257 PINCTRL_PIN(143, "GPIO_143"),
258 PINCTRL_PIN(144, "GPIO_144"),
259 PINCTRL_PIN(145, "GPIO_145"),
260 PINCTRL_PIN(146, "GPIO_146"),
261 PINCTRL_PIN(147, "GPIO_147"),
262 PINCTRL_PIN(148, "GPIO_148"),
263 PINCTRL_PIN(149, "GPIO_149"),
264 PINCTRL_PIN(150, "GPIO_150"),
265 PINCTRL_PIN(151, "GPIO_151"),
266 PINCTRL_PIN(152, "GPIO_152"),
267 PINCTRL_PIN(153, "GPIO_153"),
268 PINCTRL_PIN(154, "GPIO_154"),
269 PINCTRL_PIN(155, "GPIO_155"),
270 PINCTRL_PIN(156, "GPIO_156"),
271 PINCTRL_PIN(157, "GPIO_157"),
272 PINCTRL_PIN(158, "GPIO_158"),
273 PINCTRL_PIN(159, "GPIO_159"),
274 PINCTRL_PIN(160, "GPIO_160"),
275 PINCTRL_PIN(161, "GPIO_161"),
276 PINCTRL_PIN(162, "GPIO_162"),
277 PINCTRL_PIN(163, "GPIO_163"),
278 PINCTRL_PIN(164, "GPIO_164"),
279 PINCTRL_PIN(165, "GPIO_165"),
280 PINCTRL_PIN(166, "GPIO_166"),
281 PINCTRL_PIN(167, "GPIO_167"),
282 PINCTRL_PIN(168, "GPIO_168"),
283 PINCTRL_PIN(169, "GPIO_169"),
284 PINCTRL_PIN(170, "GPIO_170"),
285 PINCTRL_PIN(171, "GPIO_171"),
286 PINCTRL_PIN(172, "GPIO_172"),
287 PINCTRL_PIN(173, "GPIO_173"),
288 PINCTRL_PIN(174, "GPIO_174"),
289 PINCTRL_PIN(175, "UFS_RESET"),
290 PINCTRL_PIN(176, "SDC2_CLK"),
291 PINCTRL_PIN(177, "SDC2_CMD"),
292 PINCTRL_PIN(178, "SDC2_DATA"),
293 };
294
295 #define DECLARE_MSM_GPIO_PINS(pin) \
296 static const unsigned int gpio##pin##_pins[] = { pin }
297 DECLARE_MSM_GPIO_PINS(0);
298 DECLARE_MSM_GPIO_PINS(1);
299 DECLARE_MSM_GPIO_PINS(2);
300 DECLARE_MSM_GPIO_PINS(3);
301 DECLARE_MSM_GPIO_PINS(4);
302 DECLARE_MSM_GPIO_PINS(5);
303 DECLARE_MSM_GPIO_PINS(6);
304 DECLARE_MSM_GPIO_PINS(7);
305 DECLARE_MSM_GPIO_PINS(8);
306 DECLARE_MSM_GPIO_PINS(9);
307 DECLARE_MSM_GPIO_PINS(10);
308 DECLARE_MSM_GPIO_PINS(11);
309 DECLARE_MSM_GPIO_PINS(12);
310 DECLARE_MSM_GPIO_PINS(13);
311 DECLARE_MSM_GPIO_PINS(14);
312 DECLARE_MSM_GPIO_PINS(15);
313 DECLARE_MSM_GPIO_PINS(16);
314 DECLARE_MSM_GPIO_PINS(17);
315 DECLARE_MSM_GPIO_PINS(18);
316 DECLARE_MSM_GPIO_PINS(19);
317 DECLARE_MSM_GPIO_PINS(20);
318 DECLARE_MSM_GPIO_PINS(21);
319 DECLARE_MSM_GPIO_PINS(22);
320 DECLARE_MSM_GPIO_PINS(23);
321 DECLARE_MSM_GPIO_PINS(24);
322 DECLARE_MSM_GPIO_PINS(25);
323 DECLARE_MSM_GPIO_PINS(26);
324 DECLARE_MSM_GPIO_PINS(27);
325 DECLARE_MSM_GPIO_PINS(28);
326 DECLARE_MSM_GPIO_PINS(29);
327 DECLARE_MSM_GPIO_PINS(30);
328 DECLARE_MSM_GPIO_PINS(31);
329 DECLARE_MSM_GPIO_PINS(32);
330 DECLARE_MSM_GPIO_PINS(33);
331 DECLARE_MSM_GPIO_PINS(34);
332 DECLARE_MSM_GPIO_PINS(35);
333 DECLARE_MSM_GPIO_PINS(36);
334 DECLARE_MSM_GPIO_PINS(37);
335 DECLARE_MSM_GPIO_PINS(38);
336 DECLARE_MSM_GPIO_PINS(39);
337 DECLARE_MSM_GPIO_PINS(40);
338 DECLARE_MSM_GPIO_PINS(41);
339 DECLARE_MSM_GPIO_PINS(42);
340 DECLARE_MSM_GPIO_PINS(43);
341 DECLARE_MSM_GPIO_PINS(44);
342 DECLARE_MSM_GPIO_PINS(45);
343 DECLARE_MSM_GPIO_PINS(46);
344 DECLARE_MSM_GPIO_PINS(47);
345 DECLARE_MSM_GPIO_PINS(48);
346 DECLARE_MSM_GPIO_PINS(49);
347 DECLARE_MSM_GPIO_PINS(50);
348 DECLARE_MSM_GPIO_PINS(51);
349 DECLARE_MSM_GPIO_PINS(52);
350 DECLARE_MSM_GPIO_PINS(53);
351 DECLARE_MSM_GPIO_PINS(54);
352 DECLARE_MSM_GPIO_PINS(55);
353 DECLARE_MSM_GPIO_PINS(56);
354 DECLARE_MSM_GPIO_PINS(57);
355 DECLARE_MSM_GPIO_PINS(58);
356 DECLARE_MSM_GPIO_PINS(59);
357 DECLARE_MSM_GPIO_PINS(60);
358 DECLARE_MSM_GPIO_PINS(61);
359 DECLARE_MSM_GPIO_PINS(62);
360 DECLARE_MSM_GPIO_PINS(63);
361 DECLARE_MSM_GPIO_PINS(64);
362 DECLARE_MSM_GPIO_PINS(65);
363 DECLARE_MSM_GPIO_PINS(66);
364 DECLARE_MSM_GPIO_PINS(67);
365 DECLARE_MSM_GPIO_PINS(68);
366 DECLARE_MSM_GPIO_PINS(69);
367 DECLARE_MSM_GPIO_PINS(70);
368 DECLARE_MSM_GPIO_PINS(71);
369 DECLARE_MSM_GPIO_PINS(72);
370 DECLARE_MSM_GPIO_PINS(73);
371 DECLARE_MSM_GPIO_PINS(74);
372 DECLARE_MSM_GPIO_PINS(75);
373 DECLARE_MSM_GPIO_PINS(76);
374 DECLARE_MSM_GPIO_PINS(77);
375 DECLARE_MSM_GPIO_PINS(78);
376 DECLARE_MSM_GPIO_PINS(79);
377 DECLARE_MSM_GPIO_PINS(80);
378 DECLARE_MSM_GPIO_PINS(81);
379 DECLARE_MSM_GPIO_PINS(82);
380 DECLARE_MSM_GPIO_PINS(83);
381 DECLARE_MSM_GPIO_PINS(84);
382 DECLARE_MSM_GPIO_PINS(85);
383 DECLARE_MSM_GPIO_PINS(86);
384 DECLARE_MSM_GPIO_PINS(87);
385 DECLARE_MSM_GPIO_PINS(88);
386 DECLARE_MSM_GPIO_PINS(89);
387 DECLARE_MSM_GPIO_PINS(90);
388 DECLARE_MSM_GPIO_PINS(91);
389 DECLARE_MSM_GPIO_PINS(92);
390 DECLARE_MSM_GPIO_PINS(93);
391 DECLARE_MSM_GPIO_PINS(94);
392 DECLARE_MSM_GPIO_PINS(95);
393 DECLARE_MSM_GPIO_PINS(96);
394 DECLARE_MSM_GPIO_PINS(97);
395 DECLARE_MSM_GPIO_PINS(98);
396 DECLARE_MSM_GPIO_PINS(99);
397 DECLARE_MSM_GPIO_PINS(100);
398 DECLARE_MSM_GPIO_PINS(101);
399 DECLARE_MSM_GPIO_PINS(102);
400 DECLARE_MSM_GPIO_PINS(103);
401 DECLARE_MSM_GPIO_PINS(104);
402 DECLARE_MSM_GPIO_PINS(105);
403 DECLARE_MSM_GPIO_PINS(106);
404 DECLARE_MSM_GPIO_PINS(107);
405 DECLARE_MSM_GPIO_PINS(108);
406 DECLARE_MSM_GPIO_PINS(109);
407 DECLARE_MSM_GPIO_PINS(110);
408 DECLARE_MSM_GPIO_PINS(111);
409 DECLARE_MSM_GPIO_PINS(112);
410 DECLARE_MSM_GPIO_PINS(113);
411 DECLARE_MSM_GPIO_PINS(114);
412 DECLARE_MSM_GPIO_PINS(115);
413 DECLARE_MSM_GPIO_PINS(116);
414 DECLARE_MSM_GPIO_PINS(117);
415 DECLARE_MSM_GPIO_PINS(118);
416 DECLARE_MSM_GPIO_PINS(119);
417 DECLARE_MSM_GPIO_PINS(120);
418 DECLARE_MSM_GPIO_PINS(121);
419 DECLARE_MSM_GPIO_PINS(122);
420 DECLARE_MSM_GPIO_PINS(123);
421 DECLARE_MSM_GPIO_PINS(124);
422 DECLARE_MSM_GPIO_PINS(125);
423 DECLARE_MSM_GPIO_PINS(126);
424 DECLARE_MSM_GPIO_PINS(127);
425 DECLARE_MSM_GPIO_PINS(128);
426 DECLARE_MSM_GPIO_PINS(129);
427 DECLARE_MSM_GPIO_PINS(130);
428 DECLARE_MSM_GPIO_PINS(131);
429 DECLARE_MSM_GPIO_PINS(132);
430 DECLARE_MSM_GPIO_PINS(133);
431 DECLARE_MSM_GPIO_PINS(134);
432 DECLARE_MSM_GPIO_PINS(135);
433 DECLARE_MSM_GPIO_PINS(136);
434 DECLARE_MSM_GPIO_PINS(137);
435 DECLARE_MSM_GPIO_PINS(138);
436 DECLARE_MSM_GPIO_PINS(139);
437 DECLARE_MSM_GPIO_PINS(140);
438 DECLARE_MSM_GPIO_PINS(141);
439 DECLARE_MSM_GPIO_PINS(142);
440 DECLARE_MSM_GPIO_PINS(143);
441 DECLARE_MSM_GPIO_PINS(144);
442 DECLARE_MSM_GPIO_PINS(145);
443 DECLARE_MSM_GPIO_PINS(146);
444 DECLARE_MSM_GPIO_PINS(147);
445 DECLARE_MSM_GPIO_PINS(148);
446 DECLARE_MSM_GPIO_PINS(149);
447 DECLARE_MSM_GPIO_PINS(150);
448 DECLARE_MSM_GPIO_PINS(151);
449 DECLARE_MSM_GPIO_PINS(152);
450 DECLARE_MSM_GPIO_PINS(153);
451 DECLARE_MSM_GPIO_PINS(154);
452 DECLARE_MSM_GPIO_PINS(155);
453 DECLARE_MSM_GPIO_PINS(156);
454 DECLARE_MSM_GPIO_PINS(157);
455 DECLARE_MSM_GPIO_PINS(158);
456 DECLARE_MSM_GPIO_PINS(159);
457 DECLARE_MSM_GPIO_PINS(160);
458 DECLARE_MSM_GPIO_PINS(161);
459 DECLARE_MSM_GPIO_PINS(162);
460 DECLARE_MSM_GPIO_PINS(163);
461 DECLARE_MSM_GPIO_PINS(164);
462 DECLARE_MSM_GPIO_PINS(165);
463 DECLARE_MSM_GPIO_PINS(166);
464 DECLARE_MSM_GPIO_PINS(167);
465 DECLARE_MSM_GPIO_PINS(168);
466 DECLARE_MSM_GPIO_PINS(169);
467 DECLARE_MSM_GPIO_PINS(170);
468 DECLARE_MSM_GPIO_PINS(171);
469 DECLARE_MSM_GPIO_PINS(172);
470 DECLARE_MSM_GPIO_PINS(173);
471 DECLARE_MSM_GPIO_PINS(174);
472
473 static const unsigned int ufs_reset_pins[] = { 175 };
474 static const unsigned int sdc2_clk_pins[] = { 176 };
475 static const unsigned int sdc2_cmd_pins[] = { 177 };
476 static const unsigned int sdc2_data_pins[] = { 178 };
477
478 enum sm8150_functions {
479 msm_mux_adsp_ext,
480 msm_mux_agera_pll,
481 msm_mux_aoss_cti,
482 msm_mux_atest_char,
483 msm_mux_atest_char0,
484 msm_mux_atest_char1,
485 msm_mux_atest_char2,
486 msm_mux_atest_char3,
487 msm_mux_atest_usb1,
488 msm_mux_atest_usb2,
489 msm_mux_atest_usb10,
490 msm_mux_atest_usb11,
491 msm_mux_atest_usb12,
492 msm_mux_atest_usb13,
493 msm_mux_atest_usb20,
494 msm_mux_atest_usb21,
495 msm_mux_atest_usb22,
496 msm_mux_atest_usb23,
497 msm_mux_audio_ref,
498 msm_mux_btfm_slimbus,
499 msm_mux_cam_mclk,
500 msm_mux_cci_async,
501 msm_mux_cci_i2c,
502 msm_mux_cci_timer0,
503 msm_mux_cci_timer1,
504 msm_mux_cci_timer2,
505 msm_mux_cci_timer3,
506 msm_mux_cci_timer4,
507 msm_mux_cri_trng,
508 msm_mux_cri_trng0,
509 msm_mux_cri_trng1,
510 msm_mux_dbg_out,
511 msm_mux_ddr_bist,
512 msm_mux_ddr_pxi0,
513 msm_mux_ddr_pxi1,
514 msm_mux_ddr_pxi2,
515 msm_mux_ddr_pxi3,
516 msm_mux_edp_hot,
517 msm_mux_edp_lcd,
518 msm_mux_emac_phy,
519 msm_mux_emac_pps,
520 msm_mux_gcc_gp1,
521 msm_mux_gcc_gp2,
522 msm_mux_gcc_gp3,
523 msm_mux_gpio,
524 msm_mux_jitter_bist,
525 msm_mux_hs1_mi2s,
526 msm_mux_hs2_mi2s,
527 msm_mux_hs3_mi2s,
528 msm_mux_lpass_slimbus,
529 msm_mux_mdp_vsync,
530 msm_mux_mdp_vsync0,
531 msm_mux_mdp_vsync1,
532 msm_mux_mdp_vsync2,
533 msm_mux_mdp_vsync3,
534 msm_mux_mss_lte,
535 msm_mux_m_voc,
536 msm_mux_nav_pps,
537 msm_mux_pa_indicator,
538 msm_mux_pci_e0,
539 msm_mux_pci_e1,
540 msm_mux_phase_flag,
541 msm_mux_pll_bist,
542 msm_mux_pll_bypassnl,
543 msm_mux_pll_reset,
544 msm_mux_pri_mi2s,
545 msm_mux_pri_mi2s_ws,
546 msm_mux_prng_rosc,
547 msm_mux_qdss,
548 msm_mux_qdss_cti,
549 msm_mux_qlink_enable,
550 msm_mux_qlink_request,
551 msm_mux_qspi0,
552 msm_mux_qspi1,
553 msm_mux_qspi2,
554 msm_mux_qspi3,
555 msm_mux_qspi_clk,
556 msm_mux_qspi_cs,
557 msm_mux_qua_mi2s,
558 msm_mux_qup0,
559 msm_mux_qup1,
560 msm_mux_qup2,
561 msm_mux_qup3,
562 msm_mux_qup4,
563 msm_mux_qup5,
564 msm_mux_qup6,
565 msm_mux_qup7,
566 msm_mux_qup8,
567 msm_mux_qup9,
568 msm_mux_qup10,
569 msm_mux_qup11,
570 msm_mux_qup12,
571 msm_mux_qup13,
572 msm_mux_qup14,
573 msm_mux_qup15,
574 msm_mux_qup16,
575 msm_mux_qup17,
576 msm_mux_qup18,
577 msm_mux_qup19,
578 msm_mux_qup_l4,
579 msm_mux_qup_l5,
580 msm_mux_qup_l6,
581 msm_mux_rgmii,
582 msm_mux_sdc4,
583 msm_mux_sd_write,
584 msm_mux_sec_mi2s,
585 msm_mux_spkr_i2s,
586 msm_mux_sp_cmu,
587 msm_mux_ter_mi2s,
588 msm_mux_tgu_ch0,
589 msm_mux_tgu_ch2,
590 msm_mux_tgu_ch1,
591 msm_mux_tgu_ch3,
592 msm_mux_tsense_pwm1,
593 msm_mux_tsense_pwm2,
594 msm_mux_tsif1,
595 msm_mux_tsif2,
596 msm_mux_uim1,
597 msm_mux_uim2,
598 msm_mux_uim_batt,
599 msm_mux_usb2phy_ac,
600 msm_mux_usb_phy,
601 msm_mux_vfr_1,
602 msm_mux_vsense_trigger,
603 msm_mux_wlan1_adc1,
604 msm_mux_wlan1_adc0,
605 msm_mux_wlan2_adc1,
606 msm_mux_wlan2_adc0,
607 msm_mux_wmss_reset,
608 msm_mux__,
609 };
610
611 static const char * const phase_flag_groups[] = {
612 "gpio18", "gpio19", "gpio20", "gpio55", "gpio56",
613 "gpio57", "gpio59", "gpio64", "gpio68", "gpio76",
614 "gpio79", "gpio80", "gpio90", "gpio91", "gpio92",
615 "gpio93", "gpio94", "gpio96", "gpio114", "gpio115",
616 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120",
617 "gpio121", "gpio122", "gpio126", "gpio127", "gpio128",
618 "gpio144", "gpio145",
619 };
620
621 static const char * const emac_pps_groups[] = {
622 "gpio81",
623 };
624
625 static const char * const qup12_groups[] = {
626 "gpio83", "gpio84", "gpio85", "gpio86",
627 };
628
629 static const char * const qup16_groups[] = {
630 "gpio83", "gpio84", "gpio85", "gpio86",
631 };
632
633 static const char * const tsif1_groups[] = {
634 "gpio88", "gpio89", "gpio90", "gpio91", "gpio97",
635 };
636
637 static const char * const qup8_groups[] = {
638 "gpio88", "gpio89", "gpio90", "gpio91",
639 };
640
641 static const char * const qspi_cs_groups[] = {
642 "gpio88", "gpio94",
643 };
644
645 static const char * const tgu_ch3_groups[] = {
646 "gpio88",
647 };
648
649 static const char * const qspi0_groups[] = {
650 "gpio89",
651 };
652
653 static const char * const mdp_vsync0_groups[] = {
654 "gpio89",
655 };
656
657 static const char * const mdp_vsync1_groups[] = {
658 "gpio89",
659 };
660
661 static const char * const mdp_vsync2_groups[] = {
662 "gpio89",
663 };
664
665 static const char * const mdp_vsync3_groups[] = {
666 "gpio89",
667 };
668
669 static const char * const tgu_ch0_groups[] = {
670 "gpio89",
671 };
672
673 static const char * const qspi1_groups[] = {
674 "gpio90",
675 };
676
677 static const char * const sdc4_groups[] = {
678 "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
679 };
680
681 static const char * const tgu_ch1_groups[] = {
682 "gpio90",
683 };
684
685 static const char * const wlan1_adc1_groups[] = {
686 "gpio90",
687 };
688
689 static const char * const qspi2_groups[] = {
690 "gpio91",
691 };
692
693 static const char * const vfr_1_groups[] = {
694 "gpio91",
695 };
696
697 static const char * const tgu_ch2_groups[] = {
698 "gpio91",
699 };
700
701 static const char * const wlan1_adc0_groups[] = {
702 "gpio91",
703 };
704
705 static const char * const tsif2_groups[] = {
706 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
707 };
708
709 static const char * const qup11_groups[] = {
710 "gpio92", "gpio93", "gpio94", "gpio95",
711 };
712
713 static const char * const qspi_clk_groups[] = {
714 "gpio92",
715 };
716
717 static const char * const wlan2_adc1_groups[] = {
718 "gpio92",
719 };
720
721 static const char * const qspi3_groups[] = {
722 "gpio93",
723 };
724
725 static const char * const wlan2_adc0_groups[] = {
726 "gpio93",
727 };
728
729 static const char * const sd_write_groups[] = {
730 "gpio97",
731 };
732
733 static const char * const qup7_groups[] = {
734 "gpio98", "gpio99", "gpio100", "gpio101",
735 };
736
737 static const char * const ddr_bist_groups[] = {
738 "gpio98", "gpio99", "gpio145", "gpio146",
739 };
740
741 static const char * const ddr_pxi3_groups[] = {
742 "gpio98", "gpio101",
743 };
744
745 static const char * const atest_usb13_groups[] = {
746 "gpio99",
747 };
748
749 static const char * const ddr_pxi1_groups[] = {
750 "gpio99", "gpio100",
751 };
752
753 static const char * const pll_bypassnl_groups[] = {
754 "gpio100",
755 };
756
757 static const char * const atest_usb12_groups[] = {
758 "gpio100",
759 };
760
761 static const char * const pll_reset_groups[] = {
762 "gpio101",
763 };
764
765 static const char * const pci_e1_groups[] = {
766 "gpio102", "gpio103",
767 };
768
769 static const char * const uim2_groups[] = {
770 "gpio105", "gpio106", "gpio107", "gpio108",
771 };
772
773 static const char * const uim1_groups[] = {
774 "gpio109", "gpio110", "gpio111", "gpio112",
775 };
776
777 static const char * const uim_batt_groups[] = {
778 "gpio113",
779 };
780
781 static const char * const usb2phy_ac_groups[] = {
782 "gpio113", "gpio123",
783 };
784
785 static const char * const aoss_cti_groups[] = {
786 "gpio113",
787 };
788
789 static const char * const qup1_groups[] = {
790 "gpio114", "gpio115", "gpio116", "gpio117",
791 };
792
793 static const char * const rgmii_groups[] = {
794 "gpio4", "gpio5", "gpio6", "gpio7", "gpio59",
795 "gpio114", "gpio115", "gpio116", "gpio117",
796 "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
797 };
798
799 static const char * const adsp_ext_groups[] = {
800 "gpio115",
801 };
802
803 static const char * const qup5_groups[] = {
804 "gpio119", "gpio120", "gpio121", "gpio122",
805 };
806
807 static const char * const atest_usb22_groups[] = {
808 "gpio123",
809 };
810
811 static const char * const emac_phy_groups[] = {
812 "gpio124",
813 };
814
815 static const char * const hs3_mi2s_groups[] = {
816 "gpio125", "gpio165", "gpio166", "gpio167", "gpio168",
817 };
818
819 static const char * const sec_mi2s_groups[] = {
820 "gpio126", "gpio127", "gpio128", "gpio129", "gpio130",
821 };
822
823 static const char * const qup2_groups[] = {
824 "gpio126", "gpio127", "gpio128", "gpio129",
825 };
826
827 static const char * const jitter_bist_groups[] = {
828 "gpio129",
829 };
830
831 static const char * const atest_usb21_groups[] = {
832 "gpio129",
833 };
834
835 static const char * const pll_bist_groups[] = {
836 "gpio130",
837 };
838
839 static const char * const atest_usb20_groups[] = {
840 "gpio130",
841 };
842
843 static const char * const atest_char0_groups[] = {
844 "gpio130",
845 };
846
847 static const char * const ter_mi2s_groups[] = {
848 "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
849 };
850
851 static const char * const gcc_gp1_groups[] = {
852 "gpio131", "gpio136",
853 };
854
855 static const char * const atest_char1_groups[] = {
856 "gpio133",
857 };
858
859 static const char * const atest_char2_groups[] = {
860 "gpio134",
861 };
862
863 static const char * const atest_char3_groups[] = {
864 "gpio135",
865 };
866
867 static const char * const qua_mi2s_groups[] = {
868 "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141",
869 "gpio142",
870 };
871
872 static const char * const pri_mi2s_groups[] = {
873 "gpio143", "gpio144", "gpio146", "gpio147",
874 };
875
876 static const char * const qup3_groups[] = {
877 "gpio144", "gpio145", "gpio146", "gpio147",
878 };
879
880 static const char * const ddr_pxi0_groups[] = {
881 "gpio144", "gpio145",
882 };
883
884 static const char * const pri_mi2s_ws_groups[] = {
885 "gpio145",
886 };
887
888 static const char * const vsense_trigger_groups[] = {
889 "gpio145",
890 };
891
892 static const char * const atest_usb1_groups[] = {
893 "gpio145",
894 };
895
896 static const char * const atest_usb11_groups[] = {
897 "gpio146",
898 };
899
900 static const char * const ddr_pxi2_groups[] = {
901 "gpio146", "gpio147",
902 };
903
904 static const char * const dbg_out_groups[] = {
905 "gpio147",
906 };
907
908 static const char * const atest_usb10_groups[] = {
909 "gpio147",
910 };
911
912 static const char * const spkr_i2s_groups[] = {
913 "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
914 };
915
916 static const char * const audio_ref_groups[] = {
917 "gpio148",
918 };
919
920 static const char * const lpass_slimbus_groups[] = {
921 "gpio149", "gpio150", "gpio151", "gpio152",
922 };
923
924 static const char * const tsense_pwm1_groups[] = {
925 "gpio150",
926 };
927
928 static const char * const tsense_pwm2_groups[] = {
929 "gpio150",
930 };
931
932 static const char * const btfm_slimbus_groups[] = {
933 "gpio153", "gpio154",
934 };
935
936 static const char * const hs1_mi2s_groups[] = {
937 "gpio155", "gpio156", "gpio157", "gpio158", "gpio159",
938 };
939
940 static const char * const cri_trng0_groups[] = {
941 "gpio159",
942 };
943
944 static const char * const hs2_mi2s_groups[] = {
945 "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
946 };
947
948 static const char * const cri_trng1_groups[] = {
949 "gpio160",
950 };
951
952 static const char * const cri_trng_groups[] = {
953 "gpio161",
954 };
955
956 static const char * const sp_cmu_groups[] = {
957 "gpio162",
958 };
959
960 static const char * const prng_rosc_groups[] = {
961 "gpio163",
962 };
963
964 static const char * const qup0_groups[] = {
965 "gpio0", "gpio1", "gpio2", "gpio3",
966 };
967
968 static const char * const gpio_groups[] = {
969 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
970 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
971 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
972 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
973 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
974 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
975 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
976 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
977 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
978 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
979 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
980 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
981 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
982 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
983 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
984 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
985 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
986 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
987 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
988 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
989 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
990 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
991 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
992 "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
993 "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
994 "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
995 "gpio171", "gpio172", "gpio173", "gpio174",
996 };
997
998 static const char * const qup6_groups[] = {
999 "gpio4", "gpio5", "gpio6", "gpio7",
1000 };
1001
1002 static const char * const qup_l6_groups[] = {
1003 "gpio6", "gpio34", "gpio97", "gpio123",
1004 };
1005
1006 static const char * const qup_l5_groups[] = {
1007 "gpio7", "gpio33", "gpio82", "gpio96",
1008 };
1009
1010 static const char * const mdp_vsync_groups[] = {
1011 "gpio8", "gpio9", "gpio10", "gpio81", "gpio82",
1012 };
1013
1014 static const char * const edp_lcd_groups[] = {
1015 "gpio9",
1016 };
1017
1018 static const char * const qup10_groups[] = {
1019 "gpio9", "gpio10", "gpio11", "gpio12",
1020 };
1021
1022 static const char * const m_voc_groups[] = {
1023 "gpio10",
1024 };
1025
1026 static const char * const edp_hot_groups[] = {
1027 "gpio10",
1028 };
1029
1030 static const char * const cam_mclk_groups[] = {
1031 "gpio13", "gpio14", "gpio15", "gpio16",
1032 };
1033
1034 static const char * const qdss_groups[] = {
1035 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
1036 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
1037 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
1038 "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
1039 "gpio33", "gpio39", "gpio40", "gpio41", "gpio42",
1040 "gpio47", "gpio48", "gpio83", "gpio117", "gpio118",
1041 "gpio119", "gpio120", "gpio121", "gpio132",
1042 "gpio133", "gpio134",
1043 };
1044
1045 static const char * const cci_i2c_groups[] = {
1046 "gpio17", "gpio18", "gpio19", "gpio20", "gpio31", "gpio32", "gpio33",
1047 "gpio34",
1048 };
1049
1050 static const char * const cci_timer0_groups[] = {
1051 "gpio21",
1052 };
1053
1054 static const char * const gcc_gp2_groups[] = {
1055 "gpio21", "gpio137",
1056 };
1057
1058 static const char * const cci_timer1_groups[] = {
1059 "gpio22",
1060 };
1061
1062 static const char * const gcc_gp3_groups[] = {
1063 "gpio22", "gpio138",
1064 };
1065
1066 static const char * const cci_timer2_groups[] = {
1067 "gpio23",
1068 };
1069
1070 static const char * const qup18_groups[] = {
1071 "gpio23", "gpio24", "gpio25", "gpio26",
1072 };
1073
1074 static const char * const cci_timer3_groups[] = {
1075 "gpio24",
1076 };
1077
1078 static const char * const cci_async_groups[] = {
1079 "gpio24", "gpio25", "gpio26",
1080 };
1081
1082 static const char * const cci_timer4_groups[] = {
1083 "gpio25",
1084 };
1085
1086 static const char * const qup15_groups[] = {
1087 "gpio27", "gpio28", "gpio29", "gpio30",
1088 };
1089
1090 static const char * const pci_e0_groups[] = {
1091 "gpio35", "gpio36",
1092 };
1093
1094 static const char * const qup_l4_groups[] = {
1095 "gpio37", "gpio59", "gpio81", "gpio95",
1096 };
1097
1098 static const char * const agera_pll_groups[] = {
1099 "gpio37",
1100 };
1101
1102 static const char * const usb_phy_groups[] = {
1103 "gpio38",
1104 };
1105
1106 static const char * const qup9_groups[] = {
1107 "gpio39", "gpio40", "gpio41", "gpio42",
1108 };
1109
1110 static const char * const qup13_groups[] = {
1111 "gpio43", "gpio44", "gpio45", "gpio46",
1112 };
1113
1114 static const char * const qdss_cti_groups[] = {
1115 "gpio45", "gpio46", "gpio49", "gpio50", "gpio56", "gpio57", "gpio58",
1116 "gpio58",
1117 };
1118
1119 static const char * const qup14_groups[] = {
1120 "gpio47", "gpio48", "gpio49", "gpio50",
1121 };
1122
1123 static const char * const qup4_groups[] = {
1124 "gpio51", "gpio52", "gpio53", "gpio54",
1125 };
1126
1127 static const char * const qup17_groups[] = {
1128 "gpio55", "gpio56", "gpio57", "gpio58",
1129 };
1130
1131 static const char * const qup19_groups[] = {
1132 "gpio55", "gpio56", "gpio57", "gpio58",
1133 };
1134
1135 static const char * const atest_char_groups[] = {
1136 "gpio59",
1137 };
1138
1139 static const char * const nav_pps_groups[] = {
1140 "gpio60", "gpio60", "gpio76", "gpio76", "gpio77", "gpio77", "gpio81",
1141 "gpio81", "gpio82", "gpio82",
1142 };
1143
1144 static const char * const atest_usb2_groups[] = {
1145 "gpio60",
1146 };
1147
1148 static const char * const qlink_request_groups[] = {
1149 "gpio61",
1150 };
1151
1152 static const char * const qlink_enable_groups[] = {
1153 "gpio62",
1154 };
1155
1156 static const char * const wmss_reset_groups[] = {
1157 "gpio63",
1158 };
1159
1160 static const char * const atest_usb23_groups[] = {
1161 "gpio63",
1162 };
1163
1164 static const char * const pa_indicator_groups[] = {
1165 "gpio68",
1166 };
1167
1168 static const char * const mss_lte_groups[] = {
1169 "gpio69", "gpio70",
1170 };
1171
1172 static const struct pinfunction sm8150_functions[] = {
1173 MSM_PIN_FUNCTION(adsp_ext),
1174 MSM_PIN_FUNCTION(agera_pll),
1175 MSM_PIN_FUNCTION(aoss_cti),
1176 MSM_PIN_FUNCTION(ddr_pxi2),
1177 MSM_PIN_FUNCTION(atest_char),
1178 MSM_PIN_FUNCTION(atest_char0),
1179 MSM_PIN_FUNCTION(atest_char1),
1180 MSM_PIN_FUNCTION(atest_char2),
1181 MSM_PIN_FUNCTION(atest_char3),
1182 MSM_PIN_FUNCTION(audio_ref),
1183 MSM_PIN_FUNCTION(atest_usb1),
1184 MSM_PIN_FUNCTION(atest_usb2),
1185 MSM_PIN_FUNCTION(atest_usb10),
1186 MSM_PIN_FUNCTION(atest_usb11),
1187 MSM_PIN_FUNCTION(atest_usb12),
1188 MSM_PIN_FUNCTION(atest_usb13),
1189 MSM_PIN_FUNCTION(atest_usb20),
1190 MSM_PIN_FUNCTION(atest_usb21),
1191 MSM_PIN_FUNCTION(atest_usb22),
1192 MSM_PIN_FUNCTION(atest_usb23),
1193 MSM_PIN_FUNCTION(btfm_slimbus),
1194 MSM_PIN_FUNCTION(cam_mclk),
1195 MSM_PIN_FUNCTION(cci_async),
1196 MSM_PIN_FUNCTION(cci_i2c),
1197 MSM_PIN_FUNCTION(cci_timer0),
1198 MSM_PIN_FUNCTION(cci_timer1),
1199 MSM_PIN_FUNCTION(cci_timer2),
1200 MSM_PIN_FUNCTION(cci_timer3),
1201 MSM_PIN_FUNCTION(cci_timer4),
1202 MSM_PIN_FUNCTION(cri_trng),
1203 MSM_PIN_FUNCTION(cri_trng0),
1204 MSM_PIN_FUNCTION(cri_trng1),
1205 MSM_PIN_FUNCTION(dbg_out),
1206 MSM_PIN_FUNCTION(ddr_bist),
1207 MSM_PIN_FUNCTION(ddr_pxi0),
1208 MSM_PIN_FUNCTION(ddr_pxi1),
1209 MSM_PIN_FUNCTION(ddr_pxi3),
1210 MSM_PIN_FUNCTION(edp_hot),
1211 MSM_PIN_FUNCTION(edp_lcd),
1212 MSM_PIN_FUNCTION(emac_phy),
1213 MSM_PIN_FUNCTION(emac_pps),
1214 MSM_PIN_FUNCTION(gcc_gp1),
1215 MSM_PIN_FUNCTION(gcc_gp2),
1216 MSM_PIN_FUNCTION(gcc_gp3),
1217 MSM_GPIO_PIN_FUNCTION(gpio),
1218 MSM_PIN_FUNCTION(hs1_mi2s),
1219 MSM_PIN_FUNCTION(hs2_mi2s),
1220 MSM_PIN_FUNCTION(hs3_mi2s),
1221 MSM_PIN_FUNCTION(jitter_bist),
1222 MSM_PIN_FUNCTION(lpass_slimbus),
1223 MSM_PIN_FUNCTION(mdp_vsync),
1224 MSM_PIN_FUNCTION(mdp_vsync0),
1225 MSM_PIN_FUNCTION(mdp_vsync1),
1226 MSM_PIN_FUNCTION(mdp_vsync2),
1227 MSM_PIN_FUNCTION(mdp_vsync3),
1228 MSM_PIN_FUNCTION(mss_lte),
1229 MSM_PIN_FUNCTION(m_voc),
1230 MSM_PIN_FUNCTION(nav_pps),
1231 MSM_PIN_FUNCTION(pa_indicator),
1232 MSM_PIN_FUNCTION(pci_e0),
1233 MSM_PIN_FUNCTION(phase_flag),
1234 MSM_PIN_FUNCTION(pll_bypassnl),
1235 MSM_PIN_FUNCTION(pll_bist),
1236 MSM_PIN_FUNCTION(pci_e1),
1237 MSM_PIN_FUNCTION(pll_reset),
1238 MSM_PIN_FUNCTION(pri_mi2s),
1239 MSM_PIN_FUNCTION(pri_mi2s_ws),
1240 MSM_PIN_FUNCTION(prng_rosc),
1241 MSM_PIN_FUNCTION(qdss),
1242 MSM_PIN_FUNCTION(qdss_cti),
1243 MSM_PIN_FUNCTION(qlink_request),
1244 MSM_PIN_FUNCTION(qlink_enable),
1245 MSM_PIN_FUNCTION(qspi0),
1246 MSM_PIN_FUNCTION(qspi1),
1247 MSM_PIN_FUNCTION(qspi2),
1248 MSM_PIN_FUNCTION(qspi3),
1249 MSM_PIN_FUNCTION(qspi_clk),
1250 MSM_PIN_FUNCTION(qspi_cs),
1251 MSM_PIN_FUNCTION(qua_mi2s),
1252 MSM_PIN_FUNCTION(qup0),
1253 MSM_PIN_FUNCTION(qup1),
1254 MSM_PIN_FUNCTION(qup2),
1255 MSM_PIN_FUNCTION(qup3),
1256 MSM_PIN_FUNCTION(qup4),
1257 MSM_PIN_FUNCTION(qup5),
1258 MSM_PIN_FUNCTION(qup6),
1259 MSM_PIN_FUNCTION(qup7),
1260 MSM_PIN_FUNCTION(qup8),
1261 MSM_PIN_FUNCTION(qup9),
1262 MSM_PIN_FUNCTION(qup10),
1263 MSM_PIN_FUNCTION(qup11),
1264 MSM_PIN_FUNCTION(qup12),
1265 MSM_PIN_FUNCTION(qup13),
1266 MSM_PIN_FUNCTION(qup14),
1267 MSM_PIN_FUNCTION(qup15),
1268 MSM_PIN_FUNCTION(qup16),
1269 MSM_PIN_FUNCTION(qup17),
1270 MSM_PIN_FUNCTION(qup18),
1271 MSM_PIN_FUNCTION(qup19),
1272 MSM_PIN_FUNCTION(qup_l4),
1273 MSM_PIN_FUNCTION(qup_l5),
1274 MSM_PIN_FUNCTION(qup_l6),
1275 MSM_PIN_FUNCTION(rgmii),
1276 MSM_PIN_FUNCTION(sdc4),
1277 MSM_PIN_FUNCTION(sd_write),
1278 MSM_PIN_FUNCTION(sec_mi2s),
1279 MSM_PIN_FUNCTION(spkr_i2s),
1280 MSM_PIN_FUNCTION(sp_cmu),
1281 MSM_PIN_FUNCTION(ter_mi2s),
1282 MSM_PIN_FUNCTION(tgu_ch0),
1283 MSM_PIN_FUNCTION(tgu_ch1),
1284 MSM_PIN_FUNCTION(tgu_ch2),
1285 MSM_PIN_FUNCTION(tgu_ch3),
1286 MSM_PIN_FUNCTION(tsense_pwm1),
1287 MSM_PIN_FUNCTION(tsense_pwm2),
1288 MSM_PIN_FUNCTION(tsif1),
1289 MSM_PIN_FUNCTION(tsif2),
1290 MSM_PIN_FUNCTION(uim1),
1291 MSM_PIN_FUNCTION(uim2),
1292 MSM_PIN_FUNCTION(uim_batt),
1293 MSM_PIN_FUNCTION(usb2phy_ac),
1294 MSM_PIN_FUNCTION(usb_phy),
1295 MSM_PIN_FUNCTION(vfr_1),
1296 MSM_PIN_FUNCTION(vsense_trigger),
1297 MSM_PIN_FUNCTION(wlan1_adc0),
1298 MSM_PIN_FUNCTION(wlan1_adc1),
1299 MSM_PIN_FUNCTION(wlan2_adc0),
1300 MSM_PIN_FUNCTION(wlan2_adc1),
1301 MSM_PIN_FUNCTION(wmss_reset),
1302 };
1303
1304 /*
1305 * Every pin is maintained as a single group, and missing or non-existing pin
1306 * would be maintained as dummy group to synchronize pin group index with
1307 * pin descriptor registered with pinctrl core.
1308 * Clients would not be able to request these dummy pin groups.
1309 */
1310 static const struct msm_pingroup sm8150_groups[] = {
1311 [0] = PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _),
1312 [1] = PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _),
1313 [2] = PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _),
1314 [3] = PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _),
1315 [4] = PINGROUP(4, SOUTH, qup6, rgmii, _, _, _, _, _, _, _),
1316 [5] = PINGROUP(5, SOUTH, qup6, rgmii, _, _, _, _, _, _, _),
1317 [6] = PINGROUP(6, SOUTH, qup6, rgmii, qup_l6, _, _, _, _, _, _),
1318 [7] = PINGROUP(7, SOUTH, qup6, rgmii, qup_l5, _, _, _, _, _, _),
1319 [8] = PINGROUP(8, NORTH, mdp_vsync, _, _, _, _, _, _, _, _),
1320 [9] = PINGROUP(9, NORTH, mdp_vsync, edp_lcd, qup10, _, _, _, _, _, _),
1321 [10] = PINGROUP(10, NORTH, mdp_vsync, m_voc, edp_hot, qup10, _, _, _, _, _),
1322 [11] = PINGROUP(11, NORTH, qup10, _, _, _, _, _, _, _, _),
1323 [12] = PINGROUP(12, NORTH, qup10, _, _, _, _, _, _, _, _),
1324 [13] = PINGROUP(13, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
1325 [14] = PINGROUP(14, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
1326 [15] = PINGROUP(15, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
1327 [16] = PINGROUP(16, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
1328 [17] = PINGROUP(17, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
1329 [18] = PINGROUP(18, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
1330 [19] = PINGROUP(19, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
1331 [20] = PINGROUP(20, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
1332 [21] = PINGROUP(21, EAST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _),
1333 [22] = PINGROUP(22, EAST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _),
1334 [23] = PINGROUP(23, EAST, cci_timer2, qup18, qdss, _, _, _, _, _, _),
1335 [24] = PINGROUP(24, EAST, cci_timer3, cci_async, qup18, qdss, _, _, _, _, _),
1336 [25] = PINGROUP(25, EAST, cci_timer4, cci_async, qup18, qdss, _, _, _, _, _),
1337 [26] = PINGROUP(26, EAST, cci_async, qup18, qdss, _, _, _, _, _, _),
1338 [27] = PINGROUP(27, EAST, qup15, _, qdss, _, _, _, _, _, _),
1339 [28] = PINGROUP(28, EAST, qup15, qdss, _, _, _, _, _, _, _),
1340 [29] = PINGROUP(29, EAST, qup15, qdss, _, _, _, _, _, _, _),
1341 [30] = PINGROUP(30, EAST, qup15, qdss, _, _, _, _, _, _, _),
1342 [31] = PINGROUP(31, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
1343 [32] = PINGROUP(32, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
1344 [33] = PINGROUP(33, NORTH, cci_i2c, qup_l5, qdss, _, _, _, _, _, _),
1345 [34] = PINGROUP(34, NORTH, cci_i2c, qup_l6, _, _, _, _, _, _, _),
1346 [35] = PINGROUP(35, NORTH, pci_e0, _, _, _, _, _, _, _, _),
1347 [36] = PINGROUP(36, NORTH, pci_e0, _, _, _, _, _, _, _, _),
1348 [37] = PINGROUP(37, NORTH, qup_l4, agera_pll, _, _, _, _, _, _, _),
1349 [38] = PINGROUP(38, SOUTH, usb_phy, _, _, _, _, _, _, _, _),
1350 [39] = PINGROUP(39, NORTH, qup9, qdss, _, _, _, _, _, _, _),
1351 [40] = PINGROUP(40, NORTH, qup9, qdss, _, _, _, _, _, _, _),
1352 [41] = PINGROUP(41, NORTH, qup9, qdss, _, _, _, _, _, _, _),
1353 [42] = PINGROUP(42, NORTH, qup9, qdss, _, _, _, _, _, _, _),
1354 [43] = PINGROUP(43, EAST, qup13, _, _, _, _, _, _, _, _),
1355 [44] = PINGROUP(44, EAST, qup13, _, _, _, _, _, _, _, _),
1356 [45] = PINGROUP(45, EAST, qup13, qdss_cti, _, _, _, _, _, _, _),
1357 [46] = PINGROUP(46, EAST, qup13, qdss_cti, _, _, _, _, _, _, _),
1358 [47] = PINGROUP(47, EAST, qup14, qdss, _, _, _, _, _, _, _),
1359 [48] = PINGROUP(48, EAST, qup14, qdss, _, _, _, _, _, _, _),
1360 [49] = PINGROUP(49, EAST, qup14, _, qdss_cti, _, _, _, _, _, _),
1361 [50] = PINGROUP(50, EAST, qup14, qdss_cti, _, _, _, _, _, _, _),
1362 [51] = PINGROUP(51, SOUTH, qup4, _, _, _, _, _, _, _, _),
1363 [52] = PINGROUP(52, SOUTH, qup4, _, _, _, _, _, _, _, _),
1364 [53] = PINGROUP(53, SOUTH, qup4, _, _, _, _, _, _, _, _),
1365 [54] = PINGROUP(54, SOUTH, qup4, _, _, _, _, _, _, _, _),
1366 [55] = PINGROUP(55, SOUTH, qup17, qup19, phase_flag, _, _, _, _, _, _),
1367 [56] = PINGROUP(56, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
1368 [57] = PINGROUP(57, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
1369 [58] = PINGROUP(58, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
1370 [59] = PINGROUP(59, SOUTH, rgmii, qup_l4, phase_flag, _, atest_char, _, _, _, _),
1371 [60] = PINGROUP(60, SOUTH, _, nav_pps, nav_pps, atest_usb2, _, _, _, _, _),
1372 [61] = PINGROUP(61, SOUTH, qlink_request, _, _, _, _, _, _, _, _),
1373 [62] = PINGROUP(62, SOUTH, qlink_enable, _, _, _, _, _, _, _, _),
1374 [63] = PINGROUP(63, SOUTH, wmss_reset, atest_usb23, _, _, _, _, _, _, _),
1375 [64] = PINGROUP(64, SOUTH, _, phase_flag, _, _, _, _, _, _, _),
1376 [65] = PINGROUP(65, SOUTH, _, _, _, _, _, _, _, _, _),
1377 [66] = PINGROUP(66, SOUTH, _, _, _, _, _, _, _, _, _),
1378 [67] = PINGROUP(67, SOUTH, _, _, _, _, _, _, _, _, _),
1379 [68] = PINGROUP(68, SOUTH, _, pa_indicator, phase_flag, _, _, _, _, _, _),
1380 [69] = PINGROUP(69, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
1381 [70] = PINGROUP(70, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
1382 [71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _),
1383 [72] = PINGROUP(72, SOUTH, _, _, _, _, _, _, _, _, _),
1384 [73] = PINGROUP(73, SOUTH, _, _, _, _, _, _, _, _, _),
1385 [74] = PINGROUP(74, SOUTH, _, _, _, _, _, _, _, _, _),
1386 [75] = PINGROUP(75, SOUTH, _, _, _, _, _, _, _, _, _),
1387 [76] = PINGROUP(76, SOUTH, _, _, _, nav_pps, nav_pps, phase_flag, _, _, _),
1388 [77] = PINGROUP(77, SOUTH, _, _, _, nav_pps, nav_pps, _, _, _, _),
1389 [78] = PINGROUP(78, SOUTH, _, _, _, _, _, _, _, _, _),
1390 [79] = PINGROUP(79, SOUTH, _, _, phase_flag, _, _, _, _, _, _),
1391 [80] = PINGROUP(80, SOUTH, _, _, phase_flag, _, _, _, _, _, _),
1392 [81] = PINGROUP(81, SOUTH, _, _, _, nav_pps, nav_pps, qup_l4, mdp_vsync, emac_pps, _),
1393 [82] = PINGROUP(82, SOUTH, _, _, _, nav_pps, nav_pps, qup_l5, mdp_vsync, _, _),
1394 [83] = PINGROUP(83, NORTH, qup12, qup16, _, qdss, _, _, _, _, _),
1395 [84] = PINGROUP(84, NORTH, qup12, qup16, _, _, _, _, _, _, _),
1396 [85] = PINGROUP(85, NORTH, qup12, qup16, _, _, _, _, _, _, _),
1397 [86] = PINGROUP(86, NORTH, qup12, qup16, _, _, _, _, _, _, _),
1398 [87] = PINGROUP(87, EAST, _, _, _, _, _, _, _, _, _),
1399 [88] = PINGROUP(88, NORTH, tsif1, qup8, qspi_cs, tgu_ch3, _, _, _, _, _),
1400 [89] = PINGROUP(89, NORTH, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _),
1401 [90] = PINGROUP(90, NORTH, tsif1, qup8, qspi1, sdc4, phase_flag, tgu_ch1, _, _, wlan1_adc1),
1402 [91] = PINGROUP(91, NORTH, tsif1, qup8, qspi2, sdc4, vfr_1, phase_flag, tgu_ch2, _, _),
1403 [92] = PINGROUP(92, NORTH, tsif2, qup11, qspi_clk, sdc4, phase_flag, _, wlan2_adc1, _, _),
1404 [93] = PINGROUP(93, NORTH, tsif2, qup11, qspi3, sdc4, phase_flag, _, wlan2_adc0, _, _),
1405 [94] = PINGROUP(94, NORTH, tsif2, qup11, qspi_cs, sdc4, phase_flag, _, _, _, _),
1406 [95] = PINGROUP(95, NORTH, tsif2, qup11, sdc4, qup_l4, _, _, _, _, _),
1407 [96] = PINGROUP(96, NORTH, tsif2, qup_l5, phase_flag, _, _, _, _, _, _),
1408 [97] = PINGROUP(97, NORTH, sd_write, tsif1, qup_l6, _, _, _, _, _, _),
1409 [98] = PINGROUP(98, SOUTH, qup7, ddr_bist, ddr_pxi3, _, _, _, _, _, _),
1410 [99] = PINGROUP(99, SOUTH, qup7, ddr_bist, atest_usb13, ddr_pxi1, _, _, _, _, _),
1411 [100] = PINGROUP(100, SOUTH, qup7, pll_bypassnl, atest_usb12, ddr_pxi1, _, _, _, _, _),
1412 [101] = PINGROUP(101, SOUTH, qup7, pll_reset, ddr_pxi3, _, _, _, _, _, _),
1413 [102] = PINGROUP(102, NORTH, pci_e1, _, _, _, _, _, _, _, _),
1414 [103] = PINGROUP(103, NORTH, pci_e1, _, _, _, _, _, _, _, _),
1415 [104] = PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _),
1416 [105] = PINGROUP(105, WEST, uim2, _, _, _, _, _, _, _, _),
1417 [106] = PINGROUP(106, WEST, uim2, _, _, _, _, _, _, _, _),
1418 [107] = PINGROUP(107, WEST, uim2, _, _, _, _, _, _, _, _),
1419 [108] = PINGROUP(108, WEST, uim2, _, _, _, _, _, _, _, _),
1420 [109] = PINGROUP(109, WEST, uim1, _, _, _, _, _, _, _, _),
1421 [110] = PINGROUP(110, WEST, uim1, _, _, _, _, _, _, _, _),
1422 [111] = PINGROUP(111, WEST, uim1, _, _, _, _, _, _, _, _),
1423 [112] = PINGROUP(112, WEST, uim1, _, _, _, _, _, _, _, _),
1424 [113] = PINGROUP(113, WEST, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _),
1425 [114] = PINGROUP(114, SOUTH, qup1, rgmii, phase_flag, _, _, _, _, _, _),
1426 [115] = PINGROUP(115, SOUTH, qup1, rgmii, phase_flag, adsp_ext, _, _, _, _, _),
1427 [116] = PINGROUP(116, SOUTH, qup1, rgmii, phase_flag, _, _, _, _, _, _),
1428 [117] = PINGROUP(117, SOUTH, qup1, rgmii, phase_flag, _, qdss, _, _, _, _),
1429 [118] = PINGROUP(118, SOUTH, rgmii, phase_flag, _, qdss, _, _, _, _, _),
1430 [119] = PINGROUP(119, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
1431 [120] = PINGROUP(120, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
1432 [121] = PINGROUP(121, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
1433 [122] = PINGROUP(122, SOUTH, qup5, rgmii, phase_flag, _, _, _, _, _, _),
1434 [123] = PINGROUP(123, SOUTH, usb2phy_ac, qup_l6, atest_usb22, _, _, _, _, _, _),
1435 [124] = PINGROUP(124, SOUTH, emac_phy, _, _, _, _, _, _, _, _),
1436 [125] = PINGROUP(125, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
1437 [126] = PINGROUP(126, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
1438 [127] = PINGROUP(127, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
1439 [128] = PINGROUP(128, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
1440 [129] = PINGROUP(129, SOUTH, sec_mi2s, qup2, jitter_bist, atest_usb21, _, _, _, _, _),
1441 [130] = PINGROUP(130, SOUTH, sec_mi2s, pll_bist, atest_usb20, atest_char0, _, _, _, _, _),
1442 [131] = PINGROUP(131, SOUTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1443 [132] = PINGROUP(132, SOUTH, ter_mi2s, _, qdss, _, _, _, _, _, _),
1444 [133] = PINGROUP(133, SOUTH, ter_mi2s, qdss, atest_char1, _, _, _, _, _, _),
1445 [134] = PINGROUP(134, SOUTH, ter_mi2s, qdss, atest_char2, _, _, _, _, _, _),
1446 [135] = PINGROUP(135, SOUTH, ter_mi2s, atest_char3, _, _, _, _, _, _, _),
1447 [136] = PINGROUP(136, SOUTH, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1448 [137] = PINGROUP(137, SOUTH, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _),
1449 [138] = PINGROUP(138, SOUTH, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _),
1450 [139] = PINGROUP(139, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
1451 [140] = PINGROUP(140, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
1452 [141] = PINGROUP(141, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
1453 [142] = PINGROUP(142, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
1454 [143] = PINGROUP(143, SOUTH, pri_mi2s, _, _, _, _, _, _, _, _),
1455 [144] = PINGROUP(144, SOUTH, pri_mi2s, qup3, phase_flag, _, ddr_pxi0, _, _, _, _),
1456 [145] = PINGROUP(145, SOUTH, pri_mi2s_ws, qup3, phase_flag, ddr_bist, _, vsense_trigger, atest_usb1, ddr_pxi0, _),
1457 [146] = PINGROUP(146, SOUTH, pri_mi2s, qup3, ddr_bist, atest_usb11, ddr_pxi2, _, _, _, _),
1458 [147] = PINGROUP(147, SOUTH, pri_mi2s, qup3, dbg_out, atest_usb10, ddr_pxi2, _, _, _, _),
1459 [148] = PINGROUP(148, SOUTH, spkr_i2s, audio_ref, _, _, _, _, _, _, _),
1460 [149] = PINGROUP(149, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
1461 [150] = PINGROUP(150, SOUTH, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _),
1462 [151] = PINGROUP(151, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
1463 [152] = PINGROUP(152, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
1464 [153] = PINGROUP(153, SOUTH, btfm_slimbus, _, _, _, _, _, _, _, _),
1465 [154] = PINGROUP(154, SOUTH, btfm_slimbus, _, _, _, _, _, _, _, _),
1466 [155] = PINGROUP(155, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
1467 [156] = PINGROUP(156, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
1468 [157] = PINGROUP(157, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
1469 [158] = PINGROUP(158, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
1470 [159] = PINGROUP(159, WEST, hs1_mi2s, cri_trng0, _, _, _, _, _, _, _),
1471 [160] = PINGROUP(160, WEST, hs2_mi2s, cri_trng1, _, _, _, _, _, _, _),
1472 [161] = PINGROUP(161, WEST, hs2_mi2s, cri_trng, _, _, _, _, _, _, _),
1473 [162] = PINGROUP(162, WEST, hs2_mi2s, sp_cmu, _, _, _, _, _, _, _),
1474 [163] = PINGROUP(163, WEST, hs2_mi2s, prng_rosc, _, _, _, _, _, _, _),
1475 [164] = PINGROUP(164, WEST, hs2_mi2s, _, _, _, _, _, _, _, _),
1476 [165] = PINGROUP(165, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
1477 [166] = PINGROUP(166, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
1478 [167] = PINGROUP(167, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
1479 [168] = PINGROUP(168, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
1480 [169] = PINGROUP(169, NORTH, _, _, _, _, _, _, _, _, _),
1481 [170] = PINGROUP(170, NORTH, _, _, _, _, _, _, _, _, _),
1482 [171] = PINGROUP(171, NORTH, _, _, _, _, _, _, _, _, _),
1483 [172] = PINGROUP(172, NORTH, _, _, _, _, _, _, _, _, _),
1484 [173] = PINGROUP(173, NORTH, _, _, _, _, _, _, _, _, _),
1485 [174] = PINGROUP(174, NORTH, _, _, _, _, _, _, _, _, _),
1486 [175] = UFS_RESET(ufs_reset, 0xB6000),
1487 [176] = SDC_QDSD_PINGROUP(sdc2_clk, 0xB2000, 14, 6),
1488 [177] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xB2000, 11, 3),
1489 [178] = SDC_QDSD_PINGROUP(sdc2_data, 0xB2000, 9, 0),
1490 };
1491
1492 static const struct msm_gpio_wakeirq_map sm8150_pdc_map[] = {
1493 { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 },
1494 { 12, 104 }, { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 },
1495 { 30, 39 }, { 36, 43 }, { 37, 44 }, { 38, 30 }, { 39, 118 },
1496 { 41, 47 }, { 42, 48 }, { 46, 50 }, { 47, 49 },
1497 { 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 },
1498 { 53, 54 }, { 54, 55 }, { 55, 56 }, { 56, 57 }, { 58, 58 },
1499 { 60, 60 }, { 61, 61 }, { 68, 62 }, { 70, 63 }, { 76, 71 },
1500 { 77, 66 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 },
1501 { 88, 117 }, { 90, 69 }, { 91, 70 }, { 93, 75 },
1502 { 95, 72 }, { 96, 73 }, { 97, 74 }, { 101, 40 }, { 103, 77 },
1503 { 104, 78 }, { 108, 79 }, { 112, 80 }, { 113, 81 }, { 114, 82 },
1504 { 117, 85 }, { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 },
1505 { 122, 90 }, { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 },
1506 { 132, 105 }, { 133, 83 }, { 134, 36 }, { 136, 97 }, { 142, 103 },
1507 { 144, 115 }, { 147, 102 }, { 150, 107 },
1508 { 152, 108 }, { 153, 109 }
1509 };
1510
1511 static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
1512 .pins = sm8150_pins,
1513 .npins = ARRAY_SIZE(sm8150_pins),
1514 .functions = sm8150_functions,
1515 .nfunctions = ARRAY_SIZE(sm8150_functions),
1516 .groups = sm8150_groups,
1517 .ngroups = ARRAY_SIZE(sm8150_groups),
1518 .ngpios = 176,
1519 .tiles = sm8150_tiles,
1520 .ntiles = ARRAY_SIZE(sm8150_tiles),
1521 .wakeirq_map = sm8150_pdc_map,
1522 .nwakeirq_map = ARRAY_SIZE(sm8150_pdc_map),
1523 .wakeirq_dual_edge_errata = true,
1524 };
1525
sm8150_pinctrl_probe(struct platform_device * pdev)1526 static int sm8150_pinctrl_probe(struct platform_device *pdev)
1527 {
1528 return msm_pinctrl_probe(pdev, &sm8150_pinctrl);
1529 }
1530
1531 static const struct of_device_id sm8150_pinctrl_of_match[] = {
1532 { .compatible = "qcom,sm8150-pinctrl", },
1533 { },
1534 };
1535
1536 static struct platform_driver sm8150_pinctrl_driver = {
1537 .driver = {
1538 .name = "sm8150-pinctrl",
1539 .of_match_table = sm8150_pinctrl_of_match,
1540 },
1541 .probe = sm8150_pinctrl_probe,
1542 };
1543
sm8150_pinctrl_init(void)1544 static int __init sm8150_pinctrl_init(void)
1545 {
1546 return platform_driver_register(&sm8150_pinctrl_driver);
1547 }
1548 arch_initcall(sm8150_pinctrl_init);
1549
sm8150_pinctrl_exit(void)1550 static void __exit sm8150_pinctrl_exit(void)
1551 {
1552 platform_driver_unregister(&sm8150_pinctrl_driver);
1553 }
1554 module_exit(sm8150_pinctrl_exit);
1555
1556 MODULE_DESCRIPTION("QTI sm8150 pinctrl driver");
1557 MODULE_LICENSE("GPL v2");
1558 MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match);
1559