1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40 #include <linux/dmi.h>
41
42 #ifdef CONFIG_X86
43 /* for snoop control */
44 #include <asm/set_memory.h>
45 #include <asm/cpufeature.h>
46 #endif
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include <sound/hdaudio.h>
50 #include <sound/hda_i915.h>
51 #include <sound/intel-dsp-config.h>
52 #include <linux/vgaarb.h>
53 #include <linux/vga_switcheroo.h>
54 #include <linux/apple-gmux.h>
55 #include <linux/firmware.h>
56 #include <sound/hda_codec.h>
57 #include "intel.h"
58
59 #define CREATE_TRACE_POINTS
60 #include "intel_trace.h"
61
62 /* position fix mode */
63 enum {
64 POS_FIX_AUTO,
65 POS_FIX_LPIB,
66 POS_FIX_POSBUF,
67 POS_FIX_VIACOMBO,
68 POS_FIX_COMBO,
69 POS_FIX_SKL,
70 POS_FIX_FIFO,
71 };
72
73 /* Defines for ATI HD Audio support in SB450 south bridge */
74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
76
77 /* Defines for Nvidia HDA support */
78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
80 #define NVIDIA_HDA_ISTRM_COH 0x4d
81 #define NVIDIA_HDA_OSTRM_COH 0x4c
82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
83
84 /* Defines for Intel SCH HDA snoop control */
85 #define INTEL_HDA_CGCTL 0x48
86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
87 #define INTEL_SCH_HDA_DEVC 0x78
88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
89
90 /* max number of SDs */
91 /* ICH, ATI and VIA have 4 playback and 4 capture */
92 #define ICH6_NUM_CAPTURE 4
93 #define ICH6_NUM_PLAYBACK 4
94
95 /* ULI has 6 playback and 5 capture */
96 #define ULI_NUM_CAPTURE 5
97 #define ULI_NUM_PLAYBACK 6
98
99 /* ATI HDMI may have up to 8 playbacks and 0 capture */
100 #define ATIHDMI_NUM_CAPTURE 0
101 #define ATIHDMI_NUM_PLAYBACK 8
102
103
104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
107 static char *model[SNDRV_CARDS];
108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
111 static int probe_only[SNDRV_CARDS];
112 static int jackpoll_ms[SNDRV_CARDS];
113 static int single_cmd = -1;
114 static int enable_msi = -1;
115 #ifdef CONFIG_SND_HDA_PATCH_LOADER
116 static char *patch[SNDRV_CARDS];
117 #endif
118 #ifdef CONFIG_SND_HDA_INPUT_BEEP
119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
120 CONFIG_SND_HDA_INPUT_BEEP_MODE};
121 #endif
122 static bool dmic_detect = 1;
123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
124
125 module_param_array(index, int, NULL, 0444);
126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
127 module_param_array(id, charp, NULL, 0444);
128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
129 module_param_array(enable, bool, NULL, 0444);
130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
131 module_param_array(model, charp, NULL, 0444);
132 MODULE_PARM_DESC(model, "Use the given board model.");
133 module_param_array(position_fix, int, NULL, 0444);
134 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
136 module_param_array(bdl_pos_adj, int, NULL, 0644);
137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
138 module_param_array(probe_mask, int, NULL, 0444);
139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
140 module_param_array(probe_only, int, NULL, 0444);
141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
142 module_param_array(jackpoll_ms, int, NULL, 0444);
143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
144 module_param(single_cmd, bint, 0444);
145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
146 "(for debugging only).");
147 module_param(enable_msi, bint, 0444);
148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
149 #ifdef CONFIG_SND_HDA_PATCH_LOADER
150 module_param_array(patch, charp, NULL, 0444);
151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
152 #endif
153 #ifdef CONFIG_SND_HDA_INPUT_BEEP
154 module_param_array(beep_mode, bool, NULL, 0444);
155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
156 "(0=off, 1=on) (default=1).");
157 #endif
158 module_param(dmic_detect, bool, 0444);
159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
160 "(0=off, 1=on) (default=1); "
161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
162 module_param(ctl_dev_id, bool, 0444);
163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
164
165 #ifdef CONFIG_PM
166 static int param_set_xint(const char *val, const struct kernel_param *kp);
167 static const struct kernel_param_ops param_ops_xint = {
168 .set = param_set_xint,
169 .get = param_get_int,
170 };
171 #define param_check_xint param_check_int
172
173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
174 module_param(power_save, xint, 0644);
175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
176 "(in second, 0 = disable).");
177
178 static int pm_blacklist = -1;
179 module_param(pm_blacklist, bint, 0644);
180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
181
182 /* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
186 static bool power_save_controller = 1;
187 module_param(power_save_controller, bool, 0644);
188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
189 #else /* CONFIG_PM */
190 #define power_save 0
191 #define pm_blacklist 0
192 #define power_save_controller false
193 #endif /* CONFIG_PM */
194
195 static int align_buffer_size = -1;
196 module_param(align_buffer_size, bint, 0644);
197 MODULE_PARM_DESC(align_buffer_size,
198 "Force buffer and period sizes to be multiple of 128 bytes.");
199
200 #ifdef CONFIG_X86
201 static int hda_snoop = -1;
202 module_param_named(snoop, hda_snoop, bint, 0444);
203 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
204 #else
205 #define hda_snoop true
206 #endif
207
208
209 MODULE_LICENSE("GPL");
210 MODULE_DESCRIPTION("Intel HDA driver");
211
212 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
213 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
214 #define SUPPORT_VGA_SWITCHEROO
215 #endif
216 #endif
217
218
219 /*
220 */
221
222 /* driver types */
223 enum {
224 AZX_DRIVER_ICH,
225 AZX_DRIVER_PCH,
226 AZX_DRIVER_SCH,
227 AZX_DRIVER_SKL,
228 AZX_DRIVER_HDMI,
229 AZX_DRIVER_ATI,
230 AZX_DRIVER_ATIHDMI,
231 AZX_DRIVER_ATIHDMI_NS,
232 AZX_DRIVER_GFHDMI,
233 AZX_DRIVER_VIA,
234 AZX_DRIVER_SIS,
235 AZX_DRIVER_ULI,
236 AZX_DRIVER_NVIDIA,
237 AZX_DRIVER_TERA,
238 AZX_DRIVER_CTX,
239 AZX_DRIVER_CTHDA,
240 AZX_DRIVER_CMEDIA,
241 AZX_DRIVER_ZHAOXIN,
242 AZX_DRIVER_ZHAOXINHDMI,
243 AZX_DRIVER_LOONGSON,
244 AZX_DRIVER_GENERIC,
245 AZX_NUM_DRIVERS, /* keep this as last entry */
246 };
247
248 #define azx_get_snoop_type(chip) \
249 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
250 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
251
252 /* quirks for old Intel chipsets */
253 #define AZX_DCAPS_INTEL_ICH \
254 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
255
256 /* quirks for Intel PCH */
257 #define AZX_DCAPS_INTEL_PCH_BASE \
258 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
259 AZX_DCAPS_SNOOP_TYPE(SCH))
260
261 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
262 #define AZX_DCAPS_INTEL_PCH_NOPM \
263 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
264
265 /* PCH for HSW/BDW; with runtime PM */
266 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
267 #define AZX_DCAPS_INTEL_PCH \
268 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
269
270 /* HSW HDMI */
271 #define AZX_DCAPS_INTEL_HASWELL \
272 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
273 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
274 AZX_DCAPS_SNOOP_TYPE(SCH))
275
276 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
277 #define AZX_DCAPS_INTEL_BROADWELL \
278 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
279 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
280 AZX_DCAPS_SNOOP_TYPE(SCH))
281
282 #define AZX_DCAPS_INTEL_BAYTRAIL \
283 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
284
285 #define AZX_DCAPS_INTEL_BRASWELL \
286 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
287 AZX_DCAPS_I915_COMPONENT)
288
289 #define AZX_DCAPS_INTEL_SKYLAKE \
290 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
291 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
292
293 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
294
295 #define AZX_DCAPS_INTEL_LNL \
296 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS)
297
298 #define AZX_DCAPS_INTEL_NVL \
299 (AZX_DCAPS_INTEL_LNL & ~AZX_DCAPS_NO_ALIGN_BUFSIZE)
300
301 /* quirks for ATI SB / AMD Hudson */
302 #define AZX_DCAPS_PRESET_ATI_SB \
303 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
304 AZX_DCAPS_SNOOP_TYPE(ATI))
305
306 /* quirks for ATI/AMD HDMI */
307 #define AZX_DCAPS_PRESET_ATI_HDMI \
308 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
309 AZX_DCAPS_NO_MSI64)
310
311 /* quirks for ATI HDMI with snoop off */
312 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
313 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
314
315 /* quirks for AMD SB */
316 #define AZX_DCAPS_PRESET_AMD_SB \
317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
318 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
319 AZX_DCAPS_RETRY_PROBE)
320
321 /* quirks for Nvidia */
322 #define AZX_DCAPS_PRESET_NVIDIA \
323 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
324 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
325
326 #define AZX_DCAPS_PRESET_CTHDA \
327 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
328 AZX_DCAPS_NO_64BIT |\
329 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
330
331 /*
332 * vga_switcheroo support
333 */
334 #ifdef SUPPORT_VGA_SWITCHEROO
335 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
336 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
337 #else
338 #define use_vga_switcheroo(chip) 0
339 #define needs_eld_notify_link(chip) false
340 #endif
341
342 static const char * const driver_short_names[] = {
343 [AZX_DRIVER_ICH] = "HDA Intel",
344 [AZX_DRIVER_PCH] = "HDA Intel PCH",
345 [AZX_DRIVER_SCH] = "HDA Intel MID",
346 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
347 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
348 [AZX_DRIVER_ATI] = "HDA ATI SB",
349 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
350 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
351 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
352 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
353 [AZX_DRIVER_SIS] = "HDA SIS966",
354 [AZX_DRIVER_ULI] = "HDA ULI M5461",
355 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
356 [AZX_DRIVER_TERA] = "HDA Teradici",
357 [AZX_DRIVER_CTX] = "HDA Creative",
358 [AZX_DRIVER_CTHDA] = "HDA Creative",
359 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
360 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
361 [AZX_DRIVER_ZHAOXINHDMI] = "HDA Zhaoxin HDMI",
362 [AZX_DRIVER_LOONGSON] = "HDA Loongson",
363 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
364 };
365
366 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
367 static void set_default_power_save(struct azx *chip);
368
369 /*
370 * initialize the PCI registers
371 */
372 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)373 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
374 unsigned char mask, unsigned char val)
375 {
376 unsigned char data;
377
378 pci_read_config_byte(pci, reg, &data);
379 data &= ~mask;
380 data |= (val & mask);
381 pci_write_config_byte(pci, reg, data);
382 }
383
azx_init_pci(struct azx * chip)384 static void azx_init_pci(struct azx *chip)
385 {
386 int snoop_type = azx_get_snoop_type(chip);
387
388 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
389 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
390 * Ensuring these bits are 0 clears playback static on some HD Audio
391 * codecs.
392 * The PCI register TCSEL is defined in the Intel manuals.
393 */
394 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
395 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
396 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
397 }
398
399 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
400 * we need to enable snoop.
401 */
402 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
403 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
404 azx_snoop(chip));
405 update_pci_byte(chip->pci,
406 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
407 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
408 }
409
410 /* For NVIDIA HDA, enable snoop */
411 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
412 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
413 azx_snoop(chip));
414 update_pci_byte(chip->pci,
415 NVIDIA_HDA_TRANSREG_ADDR,
416 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
417 update_pci_byte(chip->pci,
418 NVIDIA_HDA_ISTRM_COH,
419 0x01, NVIDIA_HDA_ENABLE_COHBIT);
420 update_pci_byte(chip->pci,
421 NVIDIA_HDA_OSTRM_COH,
422 0x01, NVIDIA_HDA_ENABLE_COHBIT);
423 }
424
425 /* Enable SCH/PCH snoop if needed */
426 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
427 unsigned short snoop;
428 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
429 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
430 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
431 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
432 if (!azx_snoop(chip))
433 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
434 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
435 pci_read_config_word(chip->pci,
436 INTEL_SCH_HDA_DEVC, &snoop);
437 }
438 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
439 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
440 "Disabled" : "Enabled");
441 }
442 }
443
444 /*
445 * In BXT-P A0, HD-Audio DMA requests is later than expected,
446 * and makes an audio stream sensitive to system latencies when
447 * 24/32 bits are playing.
448 * Adjusting threshold of DMA fifo to force the DMA request
449 * sooner to improve latency tolerance at the expense of power.
450 */
bxt_reduce_dma_latency(struct azx * chip)451 static void bxt_reduce_dma_latency(struct azx *chip)
452 {
453 u32 val;
454
455 val = azx_readl(chip, VS_EM4L);
456 val &= (0x3 << 20);
457 azx_writel(chip, VS_EM4L, val);
458 }
459
460 /*
461 * ML_LCAP bits:
462 * bit 0: 6 MHz Supported
463 * bit 1: 12 MHz Supported
464 * bit 2: 24 MHz Supported
465 * bit 3: 48 MHz Supported
466 * bit 4: 96 MHz Supported
467 * bit 5: 192 MHz Supported
468 */
intel_get_lctl_scf(struct azx * chip)469 static int intel_get_lctl_scf(struct azx *chip)
470 {
471 struct hdac_bus *bus = azx_bus(chip);
472 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
473 u32 val, t;
474 int i;
475
476 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
477
478 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
479 t = preferred_bits[i];
480 if (val & (1 << t))
481 return t;
482 }
483
484 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
485 return 0;
486 }
487
intel_ml_lctl_set_power(struct azx * chip,int state)488 static int intel_ml_lctl_set_power(struct azx *chip, int state)
489 {
490 struct hdac_bus *bus = azx_bus(chip);
491 u32 val;
492 int timeout;
493
494 /*
495 * Changes to LCTL.SCF are only needed for the first multi-link dealing
496 * with external codecs
497 */
498 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
499 val &= ~AZX_ML_LCTL_SPA;
500 val |= state << AZX_ML_LCTL_SPA_SHIFT;
501 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
502 /* wait for CPA */
503 timeout = 50;
504 while (timeout) {
505 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
506 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
507 return 0;
508 timeout--;
509 udelay(10);
510 }
511
512 return -1;
513 }
514
intel_init_lctl(struct azx * chip)515 static void intel_init_lctl(struct azx *chip)
516 {
517 struct hdac_bus *bus = azx_bus(chip);
518 u32 val;
519 int ret;
520
521 /* 0. check lctl register value is correct or not */
522 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
523 /* only perform additional configurations if the SCF is initially based on 6MHz */
524 if ((val & AZX_ML_LCTL_SCF) != 0)
525 return;
526
527 /*
528 * Before operating on SPA, CPA must match SPA.
529 * Any deviation may result in undefined behavior.
530 */
531 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
532 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
533 return;
534
535 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
536 ret = intel_ml_lctl_set_power(chip, 0);
537 udelay(100);
538 if (ret)
539 goto set_spa;
540
541 /* 2. update SCF to select an audio clock different from 6MHz */
542 val &= ~AZX_ML_LCTL_SCF;
543 val |= intel_get_lctl_scf(chip);
544 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
545
546 set_spa:
547 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
548 intel_ml_lctl_set_power(chip, 1);
549 udelay(100);
550 }
551
hda_intel_init_chip(struct azx * chip,bool full_reset)552 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
553 {
554 struct hdac_bus *bus = azx_bus(chip);
555 struct pci_dev *pci = chip->pci;
556 u32 val;
557
558 snd_hdac_set_codec_wakeup(bus, true);
559 if (chip->driver_type == AZX_DRIVER_SKL) {
560 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
561 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
562 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
563 }
564 azx_init_chip(chip, full_reset);
565 if (chip->driver_type == AZX_DRIVER_SKL) {
566 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
567 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
568 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
569 }
570
571 snd_hdac_set_codec_wakeup(bus, false);
572
573 /* reduce dma latency to avoid noise */
574 if (HDA_CONTROLLER_IS_APL(pci))
575 bxt_reduce_dma_latency(chip);
576
577 if (bus->mlcap != NULL)
578 intel_init_lctl(chip);
579 }
580
581 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)582 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
583 unsigned int pos)
584 {
585 struct snd_pcm_substream *substream = azx_dev->core.substream;
586 int stream = substream->stream;
587 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
588 int delay;
589
590 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
591 delay = pos - lpib_pos;
592 else
593 delay = lpib_pos - pos;
594 if (delay < 0) {
595 if (delay >= azx_dev->core.delay_negative_threshold)
596 delay = 0;
597 else
598 delay += azx_dev->core.bufsize;
599 }
600
601 if (delay >= azx_dev->core.period_bytes) {
602 dev_info(chip->card->dev,
603 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
604 delay, azx_dev->core.period_bytes);
605 delay = 0;
606 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
607 chip->get_delay[stream] = NULL;
608 }
609
610 return bytes_to_frames(substream->runtime, delay);
611 }
612
613 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
614
615 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)616 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
617 {
618 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
619 int ok;
620
621 ok = azx_position_ok(chip, azx_dev);
622 if (ok == 1) {
623 azx_dev->irq_pending = 0;
624 return ok;
625 } else if (ok == 0) {
626 /* bogus IRQ, process it later */
627 azx_dev->irq_pending = 1;
628 schedule_work(&hda->irq_pending_work);
629 }
630 return 0;
631 }
632
633 #define display_power(chip, enable) \
634 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
635
636 /*
637 * Check whether the current DMA position is acceptable for updating
638 * periods. Returns non-zero if it's OK.
639 *
640 * Many HD-audio controllers appear pretty inaccurate about
641 * the update-IRQ timing. The IRQ is issued before actually the
642 * data is processed. So, we need to process it afterwords in a
643 * workqueue.
644 *
645 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
646 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)647 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
648 {
649 struct snd_pcm_substream *substream = azx_dev->core.substream;
650 struct snd_pcm_runtime *runtime = substream->runtime;
651 int stream = substream->stream;
652 u32 wallclk;
653 unsigned int pos;
654 snd_pcm_uframes_t hwptr, target;
655
656 /*
657 * The value of the WALLCLK register is always 0
658 * on the Loongson controller, so we return directly.
659 */
660 if (chip->driver_type == AZX_DRIVER_LOONGSON)
661 return 1;
662
663 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
664 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
665 return -1; /* bogus (too early) interrupt */
666
667 if (chip->get_position[stream])
668 pos = chip->get_position[stream](chip, azx_dev);
669 else { /* use the position buffer as default */
670 pos = azx_get_pos_posbuf(chip, azx_dev);
671 if (!pos || pos == (u32)-1) {
672 dev_info(chip->card->dev,
673 "Invalid position buffer, using LPIB read method instead.\n");
674 chip->get_position[stream] = azx_get_pos_lpib;
675 if (chip->get_position[0] == azx_get_pos_lpib &&
676 chip->get_position[1] == azx_get_pos_lpib)
677 azx_bus(chip)->use_posbuf = false;
678 pos = azx_get_pos_lpib(chip, azx_dev);
679 chip->get_delay[stream] = NULL;
680 } else {
681 chip->get_position[stream] = azx_get_pos_posbuf;
682 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
683 chip->get_delay[stream] = azx_get_delay_from_lpib;
684 }
685 }
686
687 if (pos >= azx_dev->core.bufsize)
688 pos = 0;
689
690 if (WARN_ONCE(!azx_dev->core.period_bytes,
691 "hda-intel: zero azx_dev->period_bytes"))
692 return -1; /* this shouldn't happen! */
693 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
694 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
695 /* NG - it's below the first next period boundary */
696 return chip->bdl_pos_adj ? 0 : -1;
697 azx_dev->core.start_wallclk += wallclk;
698
699 if (azx_dev->core.no_period_wakeup)
700 return 1; /* OK, no need to check period boundary */
701
702 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
703 return 1; /* OK, already in hwptr updating process */
704
705 /* check whether the period gets really elapsed */
706 pos = bytes_to_frames(runtime, pos);
707 hwptr = runtime->hw_ptr_base + pos;
708 if (hwptr < runtime->status->hw_ptr)
709 hwptr += runtime->buffer_size;
710 target = runtime->hw_ptr_interrupt + runtime->period_size;
711 if (hwptr < target) {
712 /* too early wakeup, process it later */
713 return chip->bdl_pos_adj ? 0 : -1;
714 }
715
716 return 1; /* OK, it's fine */
717 }
718
719 /*
720 * The work for pending PCM period updates.
721 */
azx_irq_pending_work(struct work_struct * work)722 static void azx_irq_pending_work(struct work_struct *work)
723 {
724 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
725 struct azx *chip = &hda->chip;
726 struct hdac_bus *bus = azx_bus(chip);
727 struct hdac_stream *s;
728 int pending, ok;
729
730 if (!hda->irq_pending_warned) {
731 dev_info(chip->card->dev,
732 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
733 chip->card->number);
734 hda->irq_pending_warned = 1;
735 }
736
737 for (;;) {
738 pending = 0;
739 spin_lock_irq(&bus->reg_lock);
740 list_for_each_entry(s, &bus->stream_list, list) {
741 struct azx_dev *azx_dev = stream_to_azx_dev(s);
742 if (!azx_dev->irq_pending ||
743 !s->substream ||
744 !s->running)
745 continue;
746 ok = azx_position_ok(chip, azx_dev);
747 if (ok > 0) {
748 azx_dev->irq_pending = 0;
749 spin_unlock(&bus->reg_lock);
750 snd_pcm_period_elapsed(s->substream);
751 spin_lock(&bus->reg_lock);
752 } else if (ok < 0) {
753 pending = 0; /* too early */
754 } else
755 pending++;
756 }
757 spin_unlock_irq(&bus->reg_lock);
758 if (!pending)
759 return;
760 msleep(1);
761 }
762 }
763
764 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)765 static void azx_clear_irq_pending(struct azx *chip)
766 {
767 struct hdac_bus *bus = azx_bus(chip);
768 struct hdac_stream *s;
769
770 guard(spinlock_irq)(&bus->reg_lock);
771 list_for_each_entry(s, &bus->stream_list, list) {
772 struct azx_dev *azx_dev = stream_to_azx_dev(s);
773 azx_dev->irq_pending = 0;
774 }
775 }
776
azx_acquire_irq(struct azx * chip,int do_disconnect)777 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
778 {
779 struct hdac_bus *bus = azx_bus(chip);
780 int ret;
781
782 if (!chip->msi || pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_MSI) < 0) {
783 ret = pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_INTX);
784 if (ret < 0)
785 return ret;
786 chip->msi = 0;
787 }
788
789 if (request_irq(chip->pci->irq, azx_interrupt,
790 chip->msi ? 0 : IRQF_SHARED,
791 chip->card->irq_descr, chip)) {
792 dev_err(chip->card->dev,
793 "unable to grab IRQ %d, disabling device\n",
794 chip->pci->irq);
795 if (do_disconnect)
796 snd_card_disconnect(chip->card);
797 return -1;
798 }
799 bus->irq = chip->pci->irq;
800 chip->card->sync_irq = bus->irq;
801 return 0;
802 }
803
804 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)805 static unsigned int azx_via_get_position(struct azx *chip,
806 struct azx_dev *azx_dev)
807 {
808 unsigned int link_pos, mini_pos, bound_pos;
809 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
810 unsigned int fifo_size;
811
812 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
813 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
814 /* Playback, no problem using link position */
815 return link_pos;
816 }
817
818 /* Capture */
819 /* For new chipset,
820 * use mod to get the DMA position just like old chipset
821 */
822 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
823 mod_dma_pos %= azx_dev->core.period_bytes;
824
825 fifo_size = azx_stream(azx_dev)->fifo_size;
826
827 if (azx_dev->insufficient) {
828 /* Link position never gather than FIFO size */
829 if (link_pos <= fifo_size)
830 return 0;
831
832 azx_dev->insufficient = 0;
833 }
834
835 if (link_pos <= fifo_size)
836 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
837 else
838 mini_pos = link_pos - fifo_size;
839
840 /* Find nearest previous boudary */
841 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
842 mod_link_pos = link_pos % azx_dev->core.period_bytes;
843 if (mod_link_pos >= fifo_size)
844 bound_pos = link_pos - mod_link_pos;
845 else if (mod_dma_pos >= mod_mini_pos)
846 bound_pos = mini_pos - mod_mini_pos;
847 else {
848 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
849 if (bound_pos >= azx_dev->core.bufsize)
850 bound_pos = 0;
851 }
852
853 /* Calculate real DMA position we want */
854 return bound_pos + mod_dma_pos;
855 }
856
857 #define AMD_FIFO_SIZE 32
858
859 /* get the current DMA position with FIFO size correction */
azx_get_pos_fifo(struct azx * chip,struct azx_dev * azx_dev)860 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
861 {
862 struct snd_pcm_substream *substream = azx_dev->core.substream;
863 struct snd_pcm_runtime *runtime = substream->runtime;
864 unsigned int pos, delay;
865
866 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
867 if (!runtime)
868 return pos;
869
870 runtime->delay = AMD_FIFO_SIZE;
871 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
872 if (azx_dev->insufficient) {
873 if (pos < delay) {
874 delay = pos;
875 runtime->delay = bytes_to_frames(runtime, pos);
876 } else {
877 azx_dev->insufficient = 0;
878 }
879 }
880
881 /* correct the DMA position for capture stream */
882 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
883 if (pos < delay)
884 pos += azx_dev->core.bufsize;
885 pos -= delay;
886 }
887
888 return pos;
889 }
890
azx_get_delay_from_fifo(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)891 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
892 unsigned int pos)
893 {
894 struct snd_pcm_substream *substream = azx_dev->core.substream;
895
896 /* just read back the calculated value in the above */
897 return substream->runtime->delay;
898 }
899
__azx_shutdown_chip(struct azx * chip,bool skip_link_reset)900 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
901 {
902 azx_stop_chip(chip);
903 if (!skip_link_reset)
904 azx_enter_link_reset(chip);
905 azx_clear_irq_pending(chip);
906 display_power(chip, false);
907 }
908
909 static DEFINE_MUTEX(card_list_lock);
910 static LIST_HEAD(card_list);
911
azx_shutdown_chip(struct azx * chip)912 static void azx_shutdown_chip(struct azx *chip)
913 {
914 __azx_shutdown_chip(chip, false);
915 }
916
azx_add_card_list(struct azx * chip)917 static void azx_add_card_list(struct azx *chip)
918 {
919 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
920
921 guard(mutex)(&card_list_lock);
922 list_add(&hda->list, &card_list);
923 }
924
azx_del_card_list(struct azx * chip)925 static void azx_del_card_list(struct azx *chip)
926 {
927 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
928
929 guard(mutex)(&card_list_lock);
930 list_del_init(&hda->list);
931 }
932
933 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)934 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp)
935 {
936 struct hda_intel *hda;
937 struct azx *chip;
938 int prev = power_save;
939 int ret = param_set_int(val, kp);
940
941 if (ret || prev == power_save)
942 return ret;
943
944 if (pm_blacklist > 0)
945 return 0;
946
947 guard(mutex)(&card_list_lock);
948 list_for_each_entry(hda, &card_list, list) {
949 chip = &hda->chip;
950 if (!hda->probe_continued || chip->disabled ||
951 hda->runtime_pm_disabled)
952 continue;
953 snd_hda_set_power_save(&chip->bus, power_save * 1000);
954 }
955 return 0;
956 }
957
958 /*
959 * power management
960 */
azx_is_pm_ready(struct snd_card * card)961 static bool azx_is_pm_ready(struct snd_card *card)
962 {
963 struct azx *chip;
964 struct hda_intel *hda;
965
966 if (!card)
967 return false;
968 chip = card->private_data;
969 hda = container_of(chip, struct hda_intel, chip);
970 if (chip->disabled || hda->init_failed || !chip->running)
971 return false;
972 return true;
973 }
974
__azx_runtime_resume(struct azx * chip)975 static void __azx_runtime_resume(struct azx *chip)
976 {
977 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
978 struct hdac_bus *bus = azx_bus(chip);
979 struct hda_codec *codec;
980 int status;
981
982 display_power(chip, true);
983 if (hda->need_i915_power)
984 snd_hdac_i915_set_bclk(bus);
985
986 /* Read STATESTS before controller reset */
987 status = azx_readw(chip, STATESTS);
988
989 azx_init_pci(chip);
990 hda_intel_init_chip(chip, true);
991
992 /* Avoid codec resume if runtime resume is for system suspend */
993 if (!chip->pm_prepared) {
994 list_for_each_codec(codec, &chip->bus) {
995 if (codec->relaxed_resume)
996 continue;
997
998 if (codec->forced_resume || (status & (1 << codec->addr)))
999 pm_request_resume(hda_codec_dev(codec));
1000 }
1001 }
1002
1003 /* power down again for link-controlled chips */
1004 if (!hda->need_i915_power)
1005 display_power(chip, false);
1006 }
1007
azx_prepare(struct device * dev)1008 static int azx_prepare(struct device *dev)
1009 {
1010 struct snd_card *card = dev_get_drvdata(dev);
1011 struct azx *chip;
1012
1013 if (!azx_is_pm_ready(card))
1014 return 0;
1015
1016 chip = card->private_data;
1017 chip->pm_prepared = 1;
1018 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1019
1020 flush_work(&azx_bus(chip)->unsol_work);
1021
1022 /* HDA controller always requires different WAKEEN for runtime suspend
1023 * and system suspend, so don't use direct-complete here.
1024 */
1025 return 0;
1026 }
1027
azx_complete(struct device * dev)1028 static void azx_complete(struct device *dev)
1029 {
1030 struct snd_card *card = dev_get_drvdata(dev);
1031 struct azx *chip;
1032
1033 if (!azx_is_pm_ready(card))
1034 return;
1035
1036 chip = card->private_data;
1037 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1038 chip->pm_prepared = 0;
1039 }
1040
azx_suspend(struct device * dev)1041 static int azx_suspend(struct device *dev)
1042 {
1043 struct snd_card *card = dev_get_drvdata(dev);
1044 struct azx *chip;
1045
1046 if (!azx_is_pm_ready(card))
1047 return 0;
1048
1049 chip = card->private_data;
1050 azx_shutdown_chip(chip);
1051
1052 trace_azx_suspend(chip);
1053 return 0;
1054 }
1055
azx_resume(struct device * dev)1056 static int azx_resume(struct device *dev)
1057 {
1058 struct snd_card *card = dev_get_drvdata(dev);
1059 struct azx *chip;
1060
1061 if (!azx_is_pm_ready(card))
1062 return 0;
1063
1064 chip = card->private_data;
1065
1066 __azx_runtime_resume(chip);
1067
1068 trace_azx_resume(chip);
1069 return 0;
1070 }
1071
1072 /* put codec down to D3 at hibernation for Intel SKL+;
1073 * otherwise BIOS may still access the codec and screw up the driver
1074 */
azx_freeze_noirq(struct device * dev)1075 static int azx_freeze_noirq(struct device *dev)
1076 {
1077 struct snd_card *card = dev_get_drvdata(dev);
1078 struct azx *chip = card->private_data;
1079 struct pci_dev *pci = to_pci_dev(dev);
1080
1081 if (!azx_is_pm_ready(card))
1082 return 0;
1083 if (chip->driver_type == AZX_DRIVER_SKL)
1084 pci_set_power_state(pci, PCI_D3hot);
1085
1086 return 0;
1087 }
1088
azx_thaw_noirq(struct device * dev)1089 static int azx_thaw_noirq(struct device *dev)
1090 {
1091 struct snd_card *card = dev_get_drvdata(dev);
1092 struct azx *chip = card->private_data;
1093 struct pci_dev *pci = to_pci_dev(dev);
1094
1095 if (!azx_is_pm_ready(card))
1096 return 0;
1097 if (chip->driver_type == AZX_DRIVER_SKL)
1098 pci_set_power_state(pci, PCI_D0);
1099
1100 return 0;
1101 }
1102
azx_runtime_suspend(struct device * dev)1103 static int azx_runtime_suspend(struct device *dev)
1104 {
1105 struct snd_card *card = dev_get_drvdata(dev);
1106 struct azx *chip;
1107
1108 if (!azx_is_pm_ready(card))
1109 return 0;
1110 chip = card->private_data;
1111
1112 /* enable controller wake up event */
1113 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1114
1115 azx_shutdown_chip(chip);
1116 trace_azx_runtime_suspend(chip);
1117 return 0;
1118 }
1119
azx_runtime_resume(struct device * dev)1120 static int azx_runtime_resume(struct device *dev)
1121 {
1122 struct snd_card *card = dev_get_drvdata(dev);
1123 struct azx *chip;
1124
1125 if (!azx_is_pm_ready(card))
1126 return 0;
1127 chip = card->private_data;
1128 __azx_runtime_resume(chip);
1129
1130 /* disable controller Wake Up event*/
1131 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1132
1133 trace_azx_runtime_resume(chip);
1134 return 0;
1135 }
1136
azx_runtime_idle(struct device * dev)1137 static int azx_runtime_idle(struct device *dev)
1138 {
1139 struct snd_card *card = dev_get_drvdata(dev);
1140 struct azx *chip;
1141 struct hda_intel *hda;
1142
1143 if (!card)
1144 return 0;
1145
1146 chip = card->private_data;
1147 hda = container_of(chip, struct hda_intel, chip);
1148 if (chip->disabled || hda->init_failed)
1149 return 0;
1150
1151 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1152 azx_bus(chip)->codec_powered || !chip->running)
1153 return -EBUSY;
1154
1155 /* ELD notification gets broken when HD-audio bus is off */
1156 if (needs_eld_notify_link(chip))
1157 return -EBUSY;
1158
1159 return 0;
1160 }
1161
1162 static const struct dev_pm_ops azx_pm = {
1163 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1164 .prepare = pm_sleep_ptr(azx_prepare),
1165 .complete = pm_sleep_ptr(azx_complete),
1166 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq),
1167 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq),
1168 RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1169 };
1170
1171
1172 static int azx_probe_continue(struct azx *chip);
1173
1174 #ifdef SUPPORT_VGA_SWITCHEROO
1175 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1176
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1177 static void azx_vs_set_state(struct pci_dev *pci,
1178 enum vga_switcheroo_state state)
1179 {
1180 struct snd_card *card = pci_get_drvdata(pci);
1181 struct azx *chip = card->private_data;
1182 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1183 struct hda_codec *codec;
1184 bool disabled;
1185
1186 wait_for_completion(&hda->probe_wait);
1187 if (hda->init_failed)
1188 return;
1189
1190 disabled = (state == VGA_SWITCHEROO_OFF);
1191 if (chip->disabled == disabled)
1192 return;
1193
1194 if (!hda->probe_continued) {
1195 chip->disabled = disabled;
1196 if (!disabled) {
1197 dev_info(chip->card->dev,
1198 "Start delayed initialization\n");
1199 if (azx_probe_continue(chip) < 0)
1200 dev_err(chip->card->dev, "initialization error\n");
1201 }
1202 } else {
1203 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1204 disabled ? "Disabling" : "Enabling");
1205 if (disabled) {
1206 list_for_each_codec(codec, &chip->bus) {
1207 pm_runtime_suspend(hda_codec_dev(codec));
1208 pm_runtime_disable(hda_codec_dev(codec));
1209 }
1210 pm_runtime_suspend(card->dev);
1211 pm_runtime_disable(card->dev);
1212 /* when we get suspended by vga_switcheroo we end up in D3cold,
1213 * however we have no ACPI handle, so pci/acpi can't put us there,
1214 * put ourselves there */
1215 pci->current_state = PCI_D3cold;
1216 chip->disabled = true;
1217 if (snd_hda_lock_devices(&chip->bus))
1218 dev_warn(chip->card->dev,
1219 "Cannot lock devices!\n");
1220 } else {
1221 snd_hda_unlock_devices(&chip->bus);
1222 chip->disabled = false;
1223 pm_runtime_enable(card->dev);
1224 list_for_each_codec(codec, &chip->bus) {
1225 pm_runtime_enable(hda_codec_dev(codec));
1226 pm_runtime_resume(hda_codec_dev(codec));
1227 }
1228 }
1229 }
1230 }
1231
azx_vs_can_switch(struct pci_dev * pci)1232 static bool azx_vs_can_switch(struct pci_dev *pci)
1233 {
1234 struct snd_card *card = pci_get_drvdata(pci);
1235 struct azx *chip = card->private_data;
1236 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1237
1238 wait_for_completion(&hda->probe_wait);
1239 if (hda->init_failed)
1240 return false;
1241 if (chip->disabled || !hda->probe_continued)
1242 return true;
1243 if (snd_hda_lock_devices(&chip->bus))
1244 return false;
1245 snd_hda_unlock_devices(&chip->bus);
1246 return true;
1247 }
1248
1249 /*
1250 * The discrete GPU cannot power down unless the HDA controller runtime
1251 * suspends, so activate runtime PM on codecs even if power_save == 0.
1252 */
setup_vga_switcheroo_runtime_pm(struct azx * chip)1253 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1254 {
1255 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1256 struct hda_codec *codec;
1257
1258 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1259 list_for_each_codec(codec, &chip->bus)
1260 codec->auto_runtime_pm = 1;
1261 /* reset the power save setup */
1262 if (chip->running)
1263 set_default_power_save(chip);
1264 }
1265 }
1266
azx_vs_gpu_bound(struct pci_dev * pci,enum vga_switcheroo_client_id client_id)1267 static void azx_vs_gpu_bound(struct pci_dev *pci,
1268 enum vga_switcheroo_client_id client_id)
1269 {
1270 struct snd_card *card = pci_get_drvdata(pci);
1271 struct azx *chip = card->private_data;
1272
1273 if (client_id == VGA_SWITCHEROO_DIS)
1274 chip->bus.keep_power = 0;
1275 setup_vga_switcheroo_runtime_pm(chip);
1276 }
1277
init_vga_switcheroo(struct azx * chip)1278 static void init_vga_switcheroo(struct azx *chip)
1279 {
1280 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1281 struct pci_dev *p = get_bound_vga(chip->pci);
1282 struct pci_dev *parent;
1283 if (p) {
1284 dev_info(chip->card->dev,
1285 "Handle vga_switcheroo audio client\n");
1286 hda->use_vga_switcheroo = 1;
1287
1288 /* cleared in either gpu_bound op or codec probe, or when its
1289 * upstream port has _PR3 (i.e. dGPU).
1290 */
1291 parent = pci_upstream_bridge(p);
1292 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1293 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1294 pci_dev_put(p);
1295 }
1296 }
1297
1298 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1299 .set_gpu_state = azx_vs_set_state,
1300 .can_switch = azx_vs_can_switch,
1301 .gpu_bound = azx_vs_gpu_bound,
1302 };
1303
register_vga_switcheroo(struct azx * chip)1304 static int register_vga_switcheroo(struct azx *chip)
1305 {
1306 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1307 struct pci_dev *p;
1308 int err;
1309
1310 if (!hda->use_vga_switcheroo)
1311 return 0;
1312
1313 p = get_bound_vga(chip->pci);
1314 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1315 pci_dev_put(p);
1316
1317 if (err < 0)
1318 return err;
1319 hda->vga_switcheroo_registered = 1;
1320
1321 return 0;
1322 }
1323 #else
1324 #define init_vga_switcheroo(chip) /* NOP */
1325 #define register_vga_switcheroo(chip) 0
1326 #define check_hdmi_disabled(pci) false
1327 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1328 #endif /* SUPPORT_VGA_SWITCHER */
1329
1330 /*
1331 * destructor
1332 */
azx_free(struct azx * chip)1333 static void azx_free(struct azx *chip)
1334 {
1335 struct pci_dev *pci = chip->pci;
1336 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1337 struct hdac_bus *bus = azx_bus(chip);
1338
1339 if (hda->freed)
1340 return;
1341
1342 if (azx_has_pm_runtime(chip) && chip->running) {
1343 pm_runtime_get_noresume(&pci->dev);
1344 pm_runtime_forbid(&pci->dev);
1345 pm_runtime_dont_use_autosuspend(&pci->dev);
1346 }
1347
1348 chip->running = 0;
1349
1350 azx_del_card_list(chip);
1351
1352 hda->init_failed = 1; /* to be sure */
1353 complete_all(&hda->probe_wait);
1354
1355 if (use_vga_switcheroo(hda)) {
1356 if (chip->disabled && hda->probe_continued)
1357 snd_hda_unlock_devices(&chip->bus);
1358 if (hda->vga_switcheroo_registered) {
1359 vga_switcheroo_unregister_client(chip->pci);
1360
1361 /* Some GPUs don't have sound, and azx_first_init fails,
1362 * leaving the device probed but non-functional. As long
1363 * as it's probed, the PCI subsystem keeps its runtime
1364 * PM status as active. Force it to suspended (as we
1365 * actually stop the chip) to allow GPU to suspend via
1366 * vga_switcheroo, and print a warning.
1367 */
1368 dev_warn(&pci->dev, "GPU sound probed, but not operational: please add a quirk to driver_denylist\n");
1369 pm_runtime_disable(&pci->dev);
1370 pm_runtime_set_suspended(&pci->dev);
1371 pm_runtime_enable(&pci->dev);
1372 }
1373 }
1374
1375 if (bus->chip_init) {
1376 azx_clear_irq_pending(chip);
1377 azx_stop_all_streams(chip);
1378 azx_stop_chip(chip);
1379 }
1380
1381 if (bus->irq >= 0)
1382 free_irq(bus->irq, (void*)chip);
1383
1384 azx_free_stream_pages(chip);
1385 azx_free_streams(chip);
1386 snd_hdac_bus_exit(bus);
1387
1388 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1389 release_firmware(chip->fw);
1390 #endif
1391 display_power(chip, false);
1392
1393 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1394 snd_hdac_i915_exit(bus);
1395
1396 hda->freed = 1;
1397 }
1398
azx_dev_disconnect(struct snd_device * device)1399 static int azx_dev_disconnect(struct snd_device *device)
1400 {
1401 struct azx *chip = device->device_data;
1402 struct hdac_bus *bus = azx_bus(chip);
1403
1404 chip->bus.shutdown = 1;
1405 cancel_work_sync(&bus->unsol_work);
1406
1407 return 0;
1408 }
1409
azx_dev_free(struct snd_device * device)1410 static int azx_dev_free(struct snd_device *device)
1411 {
1412 azx_free(device->device_data);
1413 return 0;
1414 }
1415
1416 #ifdef SUPPORT_VGA_SWITCHEROO
1417 #ifdef CONFIG_ACPI
1418 /* ATPX is in the integrated GPU's namespace */
atpx_present(void)1419 static bool atpx_present(void)
1420 {
1421 struct pci_dev *pdev = NULL;
1422 acpi_handle dhandle, atpx_handle;
1423 acpi_status status;
1424
1425 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
1426 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
1427 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
1428 continue;
1429
1430 dhandle = ACPI_HANDLE(&pdev->dev);
1431 if (dhandle) {
1432 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1433 if (ACPI_SUCCESS(status)) {
1434 pci_dev_put(pdev);
1435 return true;
1436 }
1437 }
1438 }
1439 return false;
1440 }
1441 #else
atpx_present(void)1442 static bool atpx_present(void)
1443 {
1444 return false;
1445 }
1446 #endif
1447
1448 /*
1449 * Check of disabled HDMI controller by vga_switcheroo
1450 */
get_bound_vga(struct pci_dev * pci)1451 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1452 {
1453 struct pci_dev *p;
1454
1455 /* check only discrete GPU */
1456 switch (pci->vendor) {
1457 case PCI_VENDOR_ID_ATI:
1458 case PCI_VENDOR_ID_AMD:
1459 if (pci->devfn == 1) {
1460 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1461 pci->bus->number, 0);
1462 if (p) {
1463 /* ATPX is in the integrated GPU's ACPI namespace
1464 * rather than the dGPU's namespace. However,
1465 * the dGPU is the one who is involved in
1466 * vgaswitcheroo.
1467 */
1468 if (pci_is_display(p) &&
1469 (atpx_present() || apple_gmux_detect(NULL, NULL)))
1470 return p;
1471 pci_dev_put(p);
1472 }
1473 }
1474 break;
1475 case PCI_VENDOR_ID_NVIDIA:
1476 if (pci->devfn == 1) {
1477 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1478 pci->bus->number, 0);
1479 if (p) {
1480 if (pci_is_display(p))
1481 return p;
1482 pci_dev_put(p);
1483 }
1484 }
1485 break;
1486 }
1487 return NULL;
1488 }
1489
check_hdmi_disabled(struct pci_dev * pci)1490 static bool check_hdmi_disabled(struct pci_dev *pci)
1491 {
1492 bool vga_inactive = false;
1493 struct pci_dev *p = get_bound_vga(pci);
1494
1495 if (p) {
1496 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1497 vga_inactive = true;
1498 pci_dev_put(p);
1499 }
1500 return vga_inactive;
1501 }
1502 #endif /* SUPPORT_VGA_SWITCHEROO */
1503
1504 /*
1505 * allow/deny-listing for position_fix
1506 */
1507 static const struct snd_pci_quirk position_fix_list[] = {
1508 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1509 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1510 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1511 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1512 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1517 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1518 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1519 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1520 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1521 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1522 {}
1523 };
1524
check_position_fix(struct azx * chip,int fix)1525 static int check_position_fix(struct azx *chip, int fix)
1526 {
1527 const struct snd_pci_quirk *q;
1528
1529 switch (fix) {
1530 case POS_FIX_AUTO:
1531 case POS_FIX_LPIB:
1532 case POS_FIX_POSBUF:
1533 case POS_FIX_VIACOMBO:
1534 case POS_FIX_COMBO:
1535 case POS_FIX_SKL:
1536 case POS_FIX_FIFO:
1537 return fix;
1538 }
1539
1540 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1541 if (q) {
1542 dev_info(chip->card->dev,
1543 "position_fix set to %d for device %04x:%04x\n",
1544 q->value, q->subvendor, q->subdevice);
1545 return q->value;
1546 }
1547
1548 /* Check VIA/ATI HD Audio Controller exist */
1549 if (chip->driver_type == AZX_DRIVER_VIA) {
1550 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1551 return POS_FIX_VIACOMBO;
1552 }
1553 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1554 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1555 return POS_FIX_FIFO;
1556 }
1557 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1558 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1559 return POS_FIX_LPIB;
1560 }
1561 if (chip->driver_type == AZX_DRIVER_SKL) {
1562 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1563 return POS_FIX_SKL;
1564 }
1565 return POS_FIX_AUTO;
1566 }
1567
assign_position_fix(struct azx * chip,int fix)1568 static void assign_position_fix(struct azx *chip, int fix)
1569 {
1570 static const azx_get_pos_callback_t callbacks[] = {
1571 [POS_FIX_AUTO] = NULL,
1572 [POS_FIX_LPIB] = azx_get_pos_lpib,
1573 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1574 [POS_FIX_VIACOMBO] = azx_via_get_position,
1575 [POS_FIX_COMBO] = azx_get_pos_lpib,
1576 [POS_FIX_SKL] = azx_get_pos_posbuf,
1577 [POS_FIX_FIFO] = azx_get_pos_fifo,
1578 };
1579
1580 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1581
1582 /* combo mode uses LPIB only for playback */
1583 if (fix == POS_FIX_COMBO)
1584 chip->get_position[1] = NULL;
1585
1586 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1587 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1588 chip->get_delay[0] = chip->get_delay[1] =
1589 azx_get_delay_from_lpib;
1590 }
1591
1592 if (fix == POS_FIX_FIFO)
1593 chip->get_delay[0] = chip->get_delay[1] =
1594 azx_get_delay_from_fifo;
1595 }
1596
1597 /*
1598 * deny-lists for probe_mask
1599 */
1600 static const struct snd_pci_quirk probe_mask_list[] = {
1601 /* Thinkpad often breaks the controller communication when accessing
1602 * to the non-working (or non-existing) modem codec slot.
1603 */
1604 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1605 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1606 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1607 /* broken BIOS */
1608 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1609 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1610 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1611 /* forced codec slots */
1612 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1613 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1614 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1615 /* WinFast VP200 H (Teradici) user reported broken communication */
1616 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1617 {}
1618 };
1619
1620 #define AZX_FORCE_CODEC_MASK 0x100
1621
check_probe_mask(struct azx * chip,int dev)1622 static void check_probe_mask(struct azx *chip, int dev)
1623 {
1624 const struct snd_pci_quirk *q;
1625
1626 chip->codec_probe_mask = probe_mask[dev];
1627 if (chip->codec_probe_mask == -1) {
1628 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1629 if (q) {
1630 dev_info(chip->card->dev,
1631 "probe_mask set to 0x%x for device %04x:%04x\n",
1632 q->value, q->subvendor, q->subdevice);
1633 chip->codec_probe_mask = q->value;
1634 }
1635 }
1636
1637 /* check forced option */
1638 if (chip->codec_probe_mask != -1 &&
1639 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1640 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1641 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1642 (int)azx_bus(chip)->codec_mask);
1643 }
1644 }
1645
1646 /*
1647 * allow/deny-list for enable_msi
1648 */
1649 static const struct snd_pci_quirk msi_deny_list[] = {
1650 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1651 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1652 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1653 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1654 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1655 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1656 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1657 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1658 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1659 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1660 {}
1661 };
1662
check_msi(struct azx * chip)1663 static void check_msi(struct azx *chip)
1664 {
1665 const struct snd_pci_quirk *q;
1666
1667 if (enable_msi >= 0) {
1668 chip->msi = !!enable_msi;
1669 return;
1670 }
1671 chip->msi = 1; /* enable MSI as default */
1672 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1673 if (q) {
1674 dev_info(chip->card->dev,
1675 "msi for device %04x:%04x set to %d\n",
1676 q->subvendor, q->subdevice, q->value);
1677 chip->msi = q->value;
1678 return;
1679 }
1680
1681 /* NVidia chipsets seem to cause troubles with MSI */
1682 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1683 dev_info(chip->card->dev, "Disabling MSI\n");
1684 chip->msi = 0;
1685 }
1686 }
1687
1688 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1689 static void azx_check_snoop_available(struct azx *chip)
1690 {
1691 int snoop = hda_snoop;
1692
1693 if (snoop >= 0) {
1694 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1695 snoop ? "snoop" : "non-snoop");
1696 chip->snoop = snoop;
1697 chip->uc_buffer = !snoop;
1698 return;
1699 }
1700
1701 snoop = true;
1702 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1703 chip->driver_type == AZX_DRIVER_VIA) {
1704 /* force to non-snoop mode for a new VIA controller
1705 * when BIOS is set
1706 */
1707 u8 val;
1708 pci_read_config_byte(chip->pci, 0x42, &val);
1709 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1710 chip->pci->revision == 0x20))
1711 snoop = false;
1712 }
1713
1714 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1715 snoop = false;
1716
1717 chip->snoop = snoop;
1718 if (!snoop) {
1719 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1720 /* C-Media requires non-cached pages only for CORB/RIRB */
1721 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1722 chip->uc_buffer = true;
1723 }
1724 }
1725
azx_probe_work(struct work_struct * work)1726 static void azx_probe_work(struct work_struct *work)
1727 {
1728 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1729 azx_probe_continue(&hda->chip);
1730 }
1731
default_bdl_pos_adj(struct azx * chip)1732 static int default_bdl_pos_adj(struct azx *chip)
1733 {
1734 /* some exceptions: Atoms seem problematic with value 1 */
1735 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1736 switch (chip->pci->device) {
1737 case PCI_DEVICE_ID_INTEL_HDA_BYT:
1738 case PCI_DEVICE_ID_INTEL_HDA_BSW:
1739 return 32;
1740 case PCI_DEVICE_ID_INTEL_HDA_APL:
1741 return 64;
1742 }
1743 }
1744
1745 switch (chip->driver_type) {
1746 /*
1747 * increase the bdl size for Glenfly Gpus for hardware
1748 * limitation on hdac interrupt interval
1749 */
1750 case AZX_DRIVER_GFHDMI:
1751 return 128;
1752 case AZX_DRIVER_ICH:
1753 case AZX_DRIVER_PCH:
1754 return 1;
1755 case AZX_DRIVER_ZHAOXINHDMI:
1756 return 128;
1757 case AZX_DRIVER_NVIDIA:
1758 return 64;
1759 default:
1760 return 32;
1761 }
1762 }
1763
1764 /*
1765 * constructor
1766 */
1767 static const struct hda_controller_ops pci_hda_ops;
1768
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1769 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1770 int dev, unsigned int driver_caps,
1771 struct azx **rchip)
1772 {
1773 static const struct snd_device_ops ops = {
1774 .dev_disconnect = azx_dev_disconnect,
1775 .dev_free = azx_dev_free,
1776 };
1777 struct hda_intel *hda;
1778 struct azx *chip;
1779 int err;
1780
1781 *rchip = NULL;
1782
1783 err = pcim_enable_device(pci);
1784 if (err < 0)
1785 return err;
1786
1787 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1788 if (!hda)
1789 return -ENOMEM;
1790
1791 chip = &hda->chip;
1792 mutex_init(&chip->open_mutex);
1793 chip->card = card;
1794 chip->pci = pci;
1795 chip->ops = &pci_hda_ops;
1796 chip->driver_caps = driver_caps;
1797 chip->driver_type = driver_caps & 0xff;
1798 check_msi(chip);
1799 chip->dev_index = dev;
1800 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1801 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1802 INIT_LIST_HEAD(&chip->pcm_list);
1803 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1804 INIT_LIST_HEAD(&hda->list);
1805 init_vga_switcheroo(chip);
1806 init_completion(&hda->probe_wait);
1807
1808 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1809
1810 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1811 chip->fallback_to_single_cmd = 1;
1812 else /* explicitly set to single_cmd or not */
1813 chip->single_cmd = single_cmd;
1814
1815 azx_check_snoop_available(chip);
1816
1817 if (bdl_pos_adj[dev] < 0)
1818 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1819 else
1820 chip->bdl_pos_adj = bdl_pos_adj[dev];
1821
1822 err = azx_bus_init(chip, model[dev]);
1823 if (err < 0)
1824 return err;
1825
1826 /* use the non-cached pages in non-snoop mode */
1827 if (!azx_snoop(chip))
1828 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC;
1829
1830 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1831 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1832 chip->bus.core.needs_damn_long_delay = 1;
1833 }
1834
1835 check_probe_mask(chip, dev);
1836
1837 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1838 if (err < 0) {
1839 dev_err(card->dev, "Error creating device [card]!\n");
1840 azx_free(chip);
1841 return err;
1842 }
1843
1844 /* continue probing in work context as may trigger request module */
1845 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1846
1847 *rchip = chip;
1848
1849 return 0;
1850 }
1851
azx_first_init(struct azx * chip)1852 static int azx_first_init(struct azx *chip)
1853 {
1854 int dev = chip->dev_index;
1855 struct pci_dev *pci = chip->pci;
1856 struct snd_card *card = chip->card;
1857 struct hdac_bus *bus = azx_bus(chip);
1858 int err;
1859 unsigned short gcap;
1860 unsigned int dma_bits = 64;
1861
1862 #if BITS_PER_LONG != 64
1863 /* Fix up base address on ULI M5461 */
1864 if (chip->driver_type == AZX_DRIVER_ULI) {
1865 u16 tmp3;
1866 pci_read_config_word(pci, 0x40, &tmp3);
1867 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1868 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1869 }
1870 #endif
1871 /*
1872 * Fix response write request not synced to memory when handle
1873 * hdac interrupt on Glenfly Gpus
1874 */
1875 if (chip->driver_type == AZX_DRIVER_GFHDMI)
1876 bus->polling_mode = 1;
1877
1878 if (chip->driver_type == AZX_DRIVER_LOONGSON) {
1879 bus->polling_mode = 1;
1880 bus->not_use_interrupts = 1;
1881 bus->access_sdnctl_in_dword = 1;
1882 if (!chip->jackpoll_interval)
1883 chip->jackpoll_interval = msecs_to_jiffies(1500);
1884 }
1885
1886 if (chip->driver_type == AZX_DRIVER_ZHAOXINHDMI)
1887 bus->polling_mode = 1;
1888
1889 bus->remap_addr = pcim_iomap_region(pci, 0, "ICH HD audio");
1890 if (IS_ERR(bus->remap_addr))
1891 return PTR_ERR(bus->remap_addr);
1892
1893 bus->addr = pci_resource_start(pci, 0);
1894
1895 if (chip->driver_type == AZX_DRIVER_SKL)
1896 snd_hdac_bus_parse_capabilities(bus);
1897
1898 /*
1899 * Some Intel CPUs has always running timer (ART) feature and
1900 * controller may have Global time sync reporting capability, so
1901 * check both of these before declaring synchronized time reporting
1902 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1903 */
1904 chip->gts_present = false;
1905
1906 #ifdef CONFIG_X86
1907 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1908 chip->gts_present = true;
1909 #endif
1910
1911 pci_set_master(pci);
1912
1913 gcap = azx_readw(chip, GCAP);
1914 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1915
1916 /* AMD devices support 40 or 48bit DMA, take the safe one */
1917 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1918 dma_bits = 40;
1919
1920 /* disable SB600 64bit support for safety */
1921 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1922 struct pci_dev *p_smbus;
1923 dma_bits = 40;
1924 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1925 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1926 NULL);
1927 if (p_smbus) {
1928 if (p_smbus->revision < 0x30)
1929 gcap &= ~AZX_GCAP_64OK;
1930 pci_dev_put(p_smbus);
1931 }
1932 }
1933
1934 /* NVidia hardware normally only supports up to 40 bits of DMA */
1935 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1936 dma_bits = 40;
1937
1938 /* disable 64bit DMA address on some devices */
1939 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1940 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1941 gcap &= ~AZX_GCAP_64OK;
1942 }
1943
1944 /* disable buffer size rounding to 128-byte multiples if supported */
1945 if (align_buffer_size >= 0)
1946 chip->align_buffer_size = !!align_buffer_size;
1947 else {
1948 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1949 chip->align_buffer_size = 0;
1950 else
1951 chip->align_buffer_size = 1;
1952 }
1953
1954 /* allow 64bit DMA address if supported by H/W */
1955 if (!(gcap & AZX_GCAP_64OK))
1956 dma_bits = 32;
1957 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1958 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1959 dma_set_max_seg_size(&pci->dev, UINT_MAX);
1960
1961 if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1962 dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits);
1963 pci->msi_addr_mask = DMA_BIT_MASK(dma_bits);
1964 }
1965
1966 /* read number of streams from GCAP register instead of using
1967 * hardcoded value
1968 */
1969 chip->capture_streams = (gcap >> 8) & 0x0f;
1970 chip->playback_streams = (gcap >> 12) & 0x0f;
1971 if (!chip->playback_streams && !chip->capture_streams) {
1972 /* gcap didn't give any info, switching to old method */
1973
1974 switch (chip->driver_type) {
1975 case AZX_DRIVER_ULI:
1976 chip->playback_streams = ULI_NUM_PLAYBACK;
1977 chip->capture_streams = ULI_NUM_CAPTURE;
1978 break;
1979 case AZX_DRIVER_ATIHDMI:
1980 case AZX_DRIVER_ATIHDMI_NS:
1981 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1982 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1983 break;
1984 case AZX_DRIVER_GFHDMI:
1985 case AZX_DRIVER_ZHAOXINHDMI:
1986 case AZX_DRIVER_GENERIC:
1987 default:
1988 chip->playback_streams = ICH6_NUM_PLAYBACK;
1989 chip->capture_streams = ICH6_NUM_CAPTURE;
1990 break;
1991 }
1992 }
1993 chip->capture_index_offset = 0;
1994 chip->playback_index_offset = chip->capture_streams;
1995 chip->num_streams = chip->playback_streams + chip->capture_streams;
1996
1997 /* sanity check for the SDxCTL.STRM field overflow */
1998 if (chip->num_streams > 15 &&
1999 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2000 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2001 "forcing separate stream tags", chip->num_streams);
2002 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2003 }
2004
2005 /* initialize streams */
2006 err = azx_init_streams(chip);
2007 if (err < 0)
2008 return err;
2009
2010 err = azx_alloc_stream_pages(chip);
2011 if (err < 0)
2012 return err;
2013
2014 /* initialize chip */
2015 azx_init_pci(chip);
2016
2017 snd_hdac_i915_set_bclk(bus);
2018
2019 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2020
2021 /* codec detection */
2022 if (!azx_bus(chip)->codec_mask) {
2023 dev_err(card->dev, "no codecs found!\n");
2024 /* keep running the rest for the runtime PM */
2025 }
2026
2027 if (azx_acquire_irq(chip, 0) < 0)
2028 return -EBUSY;
2029
2030 strscpy(card->driver, "HDA-Intel");
2031 strscpy(card->shortname, driver_short_names[chip->driver_type],
2032 sizeof(card->shortname));
2033 snprintf(card->longname, sizeof(card->longname),
2034 "%s at 0x%lx irq %i",
2035 card->shortname, bus->addr, bus->irq);
2036
2037 return 0;
2038 }
2039
2040 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2041 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)2042 static void azx_firmware_cb(const struct firmware *fw, void *context)
2043 {
2044 struct snd_card *card = context;
2045 struct azx *chip = card->private_data;
2046
2047 if (fw)
2048 chip->fw = fw;
2049 else
2050 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2051 if (!chip->disabled) {
2052 /* continue probing */
2053 azx_probe_continue(chip);
2054 }
2055 }
2056 #endif
2057
disable_msi_reset_irq(struct azx * chip)2058 static int disable_msi_reset_irq(struct azx *chip)
2059 {
2060 struct hdac_bus *bus = azx_bus(chip);
2061 int err;
2062
2063 free_irq(bus->irq, chip);
2064 bus->irq = -1;
2065 chip->card->sync_irq = -1;
2066 pci_free_irq_vectors(chip->pci);
2067 chip->msi = 0;
2068 err = azx_acquire_irq(chip, 1);
2069 if (err < 0)
2070 return err;
2071
2072 return 0;
2073 }
2074
2075 /* Denylist for skipping the whole probe:
2076 * some HD-audio PCI entries are exposed without any codecs, and such devices
2077 * should be ignored from the beginning.
2078 */
2079 static const struct pci_device_id driver_denylist[] = {
2080 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2081 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2082 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2083 {}
2084 };
2085
2086 static struct pci_device_id driver_denylist_ideapad_z570[] = {
2087 { PCI_DEVICE_SUB(0x10de, 0x0bea, 0x0000, 0x0000) }, /* NVIDIA GF108 HDA */
2088 {}
2089 };
2090
2091 static struct pci_device_id driver_denylist_msi_x870e[] = {
2092 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1462, 0xee59) }, /* MSI X870E Tomahawk WiFi */
2093 {}
2094 };
2095
2096 /* DMI-based denylist, to be used when:
2097 * - PCI subsystem IDs are zero, impossible to distinguish from valid sound cards.
2098 * - Different modifications of the same laptop use different GPU models.
2099 */
2100 static const struct dmi_system_id driver_denylist_dmi[] = {
2101 {
2102 /* No HDA in NVIDIA DGPU. BIOS disables it, but quirk_nvidia_hda() reenables. */
2103 .matches = {
2104 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2105 DMI_MATCH(DMI_PRODUCT_VERSION, "Ideapad Z570"),
2106 },
2107 .driver_data = &driver_denylist_ideapad_z570,
2108 },
2109 {
2110 /* PCI device matching alone incorrectly matches some laptops */
2111 .matches = {
2112 DMI_MATCH(DMI_BOARD_VENDOR, "Micro-Star International Co., Ltd."),
2113 DMI_MATCH(DMI_BOARD_NAME, "MAG X870E TOMAHAWK WIFI (MS-7E59)"),
2114 },
2115 .driver_data = &driver_denylist_msi_x870e,
2116 },
2117 {}
2118 };
2119
2120 static const struct hda_controller_ops pci_hda_ops = {
2121 .disable_msi_reset_irq = disable_msi_reset_irq,
2122 .position_check = azx_position_check,
2123 };
2124
2125 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2126
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2127 static int azx_probe(struct pci_dev *pci,
2128 const struct pci_device_id *pci_id)
2129 {
2130 const struct dmi_system_id *dmi;
2131 struct snd_card *card;
2132 struct hda_intel *hda;
2133 struct azx *chip;
2134 bool schedule_probe;
2135 int dev;
2136 int err;
2137
2138 if (pci_match_id(driver_denylist, pci)) {
2139 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2140 return -ENODEV;
2141 }
2142
2143 dmi = dmi_first_match(driver_denylist_dmi);
2144 if (dmi && pci_match_id(dmi->driver_data, pci)) {
2145 dev_info(&pci->dev, "Skipping the device on the DMI denylist\n");
2146 return -ENODEV;
2147 }
2148
2149 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
2150 if (dev >= SNDRV_CARDS)
2151 return -ENODEV;
2152 if (!enable[dev]) {
2153 set_bit(dev, probed_devs);
2154 return -ENOENT;
2155 }
2156
2157 /*
2158 * stop probe if another Intel's DSP driver should be activated
2159 */
2160 if (dmic_detect) {
2161 err = snd_intel_dsp_driver_probe(pci);
2162 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2163 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2164 return -ENODEV;
2165 }
2166 } else {
2167 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2168 }
2169
2170 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2171 0, &card);
2172 if (err < 0) {
2173 dev_err(&pci->dev, "Error creating card!\n");
2174 return err;
2175 }
2176
2177 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2178 if (err < 0)
2179 goto out_free;
2180 card->private_data = chip;
2181 hda = container_of(chip, struct hda_intel, chip);
2182
2183 pci_set_drvdata(pci, card);
2184
2185 #ifdef CONFIG_SND_HDA_I915
2186 /* bind with i915 if needed */
2187 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2188 err = snd_hdac_i915_init(azx_bus(chip));
2189 if (err < 0) {
2190 if (err == -EPROBE_DEFER)
2191 goto out_free;
2192
2193 /* if the controller is bound only with HDMI/DP
2194 * (for HSW and BDW), we need to abort the probe;
2195 * for other chips, still continue probing as other
2196 * codecs can be on the same link.
2197 */
2198 if (HDA_CONTROLLER_IN_GPU(pci)) {
2199 dev_err_probe(card->dev, err,
2200 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2201
2202 goto out_free;
2203 } else {
2204 /* don't bother any longer */
2205 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2206 }
2207 }
2208
2209 /* HSW/BDW controllers need this power */
2210 if (HDA_CONTROLLER_IN_GPU(pci))
2211 hda->need_i915_power = true;
2212 }
2213 #else
2214 if (HDA_CONTROLLER_IN_GPU(pci))
2215 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2216 #endif
2217
2218 err = register_vga_switcheroo(chip);
2219 if (err < 0) {
2220 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2221 goto out_free;
2222 }
2223
2224 if (check_hdmi_disabled(pci)) {
2225 dev_info(card->dev, "VGA controller is disabled\n");
2226 dev_info(card->dev, "Delaying initialization\n");
2227 chip->disabled = true;
2228 }
2229
2230 schedule_probe = !chip->disabled;
2231
2232 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2233 if (patch[dev] && *patch[dev]) {
2234 dev_info(card->dev, "Applying patch firmware '%s'\n",
2235 patch[dev]);
2236 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2237 &pci->dev, GFP_KERNEL, card,
2238 azx_firmware_cb);
2239 if (err < 0)
2240 goto out_free;
2241 schedule_probe = false; /* continued in azx_firmware_cb() */
2242 }
2243 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2244
2245 if (schedule_probe)
2246 schedule_delayed_work(&hda->probe_work, 0);
2247
2248 set_bit(dev, probed_devs);
2249 if (chip->disabled)
2250 complete_all(&hda->probe_wait);
2251 return 0;
2252
2253 out_free:
2254 pci_set_drvdata(pci, NULL);
2255 snd_card_free(card);
2256 return err;
2257 }
2258
2259 /* On some boards setting power_save to a non 0 value leads to clicking /
2260 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2261 * figure out how to avoid these sounds, but that is not always feasible.
2262 * So we keep a list of devices where we disable powersaving as its known
2263 * to causes problems on these devices.
2264 */
2265 static const struct snd_pci_quirk power_save_denylist[] = {
2266 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2267 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2268 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2269 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2270 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2271 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2272 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2273 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2274 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2275 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2276 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2277 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2278 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2279 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2280 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2281 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2282 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2283 /* https://bugs.launchpad.net/bugs/1821663 */
2284 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2285 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2286 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2287 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2288 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2289 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
2290 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2291 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2292 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2293 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2294 /* https://bugs.launchpad.net/bugs/1821663 */
2295 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2296 /* KONTRON SinglePC may cause a stall at runtime resume */
2297 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
2298 /* Dell ALC3271 */
2299 SND_PCI_QUIRK(0x1028, 0x0962, "Dell ALC3271", 0),
2300 /* https://bugzilla.kernel.org/show_bug.cgi?id=220210 */
2301 SND_PCI_QUIRK(0x17aa, 0x5079, "Lenovo Thinkpad E15", 0),
2302 {}
2303 };
2304
set_default_power_save(struct azx * chip)2305 static void set_default_power_save(struct azx *chip)
2306 {
2307 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2308 int val = power_save;
2309
2310 if (pm_blacklist < 0) {
2311 const struct snd_pci_quirk *q;
2312
2313 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2314 if (q && val) {
2315 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2316 q->subvendor, q->subdevice);
2317 val = 0;
2318 hda->runtime_pm_disabled = 1;
2319 }
2320 } else if (pm_blacklist > 0) {
2321 dev_info(chip->card->dev, "Forcing power_save to 0 via option\n");
2322 val = 0;
2323 }
2324 snd_hda_set_power_save(&chip->bus, val * 1000);
2325 }
2326
2327 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2328 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2329 [AZX_DRIVER_NVIDIA] = 8,
2330 [AZX_DRIVER_TERA] = 1,
2331 };
2332
azx_probe_continue(struct azx * chip)2333 static int azx_probe_continue(struct azx *chip)
2334 {
2335 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2336 struct hdac_bus *bus = azx_bus(chip);
2337 struct pci_dev *pci = chip->pci;
2338 int dev = chip->dev_index;
2339 int err;
2340
2341 if (chip->disabled || hda->init_failed)
2342 return -EIO;
2343 if (hda->probe_retry)
2344 goto probe_retry;
2345
2346 to_hda_bus(bus)->bus_probing = 1;
2347 hda->probe_continued = 1;
2348
2349 /* Request display power well for the HDA controller or codec. For
2350 * Haswell/Broadwell, both the display HDA controller and codec need
2351 * this power. For other platforms, like Baytrail/Braswell, only the
2352 * display codec needs the power and it can be released after probe.
2353 */
2354 display_power(chip, true);
2355
2356 err = azx_first_init(chip);
2357 if (err < 0)
2358 goto out_free;
2359
2360 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2361 chip->beep_mode = beep_mode[dev];
2362 #endif
2363
2364 chip->ctl_dev_id = ctl_dev_id;
2365
2366 /* create codec instances */
2367 if (bus->codec_mask) {
2368 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2369 if (err < 0)
2370 goto out_free;
2371 }
2372
2373 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2374 if (chip->fw) {
2375 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2376 chip->fw->data);
2377 if (err < 0)
2378 goto out_free;
2379 }
2380 #endif
2381
2382 probe_retry:
2383 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2384 err = azx_codec_configure(chip);
2385 if (err) {
2386 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2387 ++hda->probe_retry < 60) {
2388 schedule_delayed_work(&hda->probe_work,
2389 msecs_to_jiffies(1000));
2390 return 0; /* keep things up */
2391 }
2392 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2393 goto out_free;
2394 }
2395 }
2396
2397 err = snd_card_register(chip->card);
2398 if (err < 0)
2399 goto out_free;
2400
2401 setup_vga_switcheroo_runtime_pm(chip);
2402
2403 chip->running = 1;
2404 azx_add_card_list(chip);
2405
2406 set_default_power_save(chip);
2407
2408 if (azx_has_pm_runtime(chip)) {
2409 pm_runtime_use_autosuspend(&pci->dev);
2410 pm_runtime_allow(&pci->dev);
2411 pm_runtime_put_autosuspend(&pci->dev);
2412 }
2413
2414 out_free:
2415 if (err < 0) {
2416 pci_set_drvdata(pci, NULL);
2417 snd_card_free(chip->card);
2418 return err;
2419 }
2420
2421 if (!hda->need_i915_power)
2422 display_power(chip, false);
2423 complete_all(&hda->probe_wait);
2424 to_hda_bus(bus)->bus_probing = 0;
2425 hda->probe_retry = 0;
2426 return 0;
2427 }
2428
azx_remove(struct pci_dev * pci)2429 static void azx_remove(struct pci_dev *pci)
2430 {
2431 struct snd_card *card = pci_get_drvdata(pci);
2432 struct azx *chip;
2433 struct hda_intel *hda;
2434
2435 if (card) {
2436 /* cancel the pending probing work */
2437 chip = card->private_data;
2438 hda = container_of(chip, struct hda_intel, chip);
2439 /* FIXME: below is an ugly workaround.
2440 * Both device_release_driver() and driver_probe_device()
2441 * take *both* the device's and its parent's lock before
2442 * calling the remove() and probe() callbacks. The codec
2443 * probe takes the locks of both the codec itself and its
2444 * parent, i.e. the PCI controller dev. Meanwhile, when
2445 * the PCI controller is unbound, it takes its lock, too
2446 * ==> ouch, a deadlock!
2447 * As a workaround, we unlock temporarily here the controller
2448 * device during cancel_work_sync() call.
2449 */
2450 device_unlock(&pci->dev);
2451 cancel_delayed_work_sync(&hda->probe_work);
2452 device_lock(&pci->dev);
2453
2454 clear_bit(chip->dev_index, probed_devs);
2455 pci_set_drvdata(pci, NULL);
2456 snd_card_free(card);
2457 }
2458 }
2459
azx_shutdown(struct pci_dev * pci)2460 static void azx_shutdown(struct pci_dev *pci)
2461 {
2462 struct snd_card *card = pci_get_drvdata(pci);
2463 struct azx *chip;
2464
2465 if (!card)
2466 return;
2467 chip = card->private_data;
2468 if (chip && chip->running)
2469 __azx_shutdown_chip(chip, true);
2470 }
2471
2472 /* PCI IDs */
2473 static const struct pci_device_id azx_ids[] = {
2474 /* CPT */
2475 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2476 /* PBG */
2477 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2478 /* Panther Point */
2479 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2480 /* Lynx Point */
2481 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2482 /* 9 Series */
2483 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2484 /* Wellsburg */
2485 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2486 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2487 /* Lewisburg */
2488 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2489 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2490 /* Lynx Point-LP */
2491 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2492 /* Lynx Point-LP */
2493 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2494 /* Wildcat Point-LP */
2495 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2496 /* Skylake (Sunrise Point) */
2497 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2498 /* Skylake-LP (Sunrise Point-LP) */
2499 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2500 /* Kabylake */
2501 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2502 /* Kabylake-LP */
2503 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2504 /* Kabylake-H */
2505 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2506 /* Coffelake */
2507 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2508 /* Cannonlake */
2509 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2510 /* CometLake-LP */
2511 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2512 /* CometLake-H */
2513 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2514 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2515 /* CometLake-S */
2516 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2517 /* CometLake-R */
2518 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2519 /* Icelake */
2520 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2521 /* Icelake-H */
2522 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2523 /* Jasperlake */
2524 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2525 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2526 /* Tigerlake */
2527 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2528 /* Tigerlake-H */
2529 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2530 /* DG1 */
2531 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2532 /* DG2 */
2533 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2534 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2535 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2536 /* Alderlake-S */
2537 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2538 /* Alderlake-P */
2539 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2540 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2541 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2542 /* Alderlake-M */
2543 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2544 /* Alderlake-N */
2545 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2546 /* Elkhart Lake */
2547 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2548 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2549 /* Raptor Lake */
2550 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2551 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2552 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2553 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2554 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2555 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2556 /* Battlemage */
2557 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2558 /* Lunarlake-P */
2559 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2560 /* Arrow Lake-S */
2561 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2562 /* Arrow Lake */
2563 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2564 /* Panther Lake */
2565 { PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2566 /* Panther Lake-H */
2567 { PCI_DEVICE_DATA(INTEL, HDA_PTL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2568 /* Wildcat Lake */
2569 { PCI_DEVICE_DATA(INTEL, HDA_WCL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2570 /* Nova Lake */
2571 { PCI_DEVICE_DATA(INTEL, HDA_NVL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_NVL) },
2572 { PCI_DEVICE_DATA(INTEL, HDA_NVL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_NVL) },
2573 /* Apollolake (Broxton-P) */
2574 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2575 /* Gemini-Lake */
2576 { PCI_DEVICE_DATA(INTEL, HDA_GLK, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2577 /* Haswell */
2578 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2579 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2580 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2581 /* Broadwell */
2582 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) },
2583 /* 5 Series/3400 */
2584 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2585 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2586 /* Poulsbo */
2587 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2588 AZX_DCAPS_POSFIX_LPIB) },
2589 /* Oaktrail */
2590 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) },
2591 /* BayTrail */
2592 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) },
2593 /* Braswell */
2594 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) },
2595 /* ICH6 */
2596 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2597 /* ICH7 */
2598 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2599 /* ESB2 */
2600 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2601 /* ICH8 */
2602 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2603 /* ICH9 */
2604 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2605 /* ICH9 */
2606 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2607 /* ICH10 */
2608 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2609 /* ICH10 */
2610 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2611 /* Generic Intel */
2612 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2613 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2614 .class_mask = 0xffffff,
2615 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2616 /* ATI SB 450/600/700/800/900 */
2617 { PCI_VDEVICE(ATI, 0x437b),
2618 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2619 { PCI_VDEVICE(ATI, 0x4383),
2620 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2621 /* AMD Hudson */
2622 { PCI_VDEVICE(AMD, 0x780d),
2623 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2624 /* AMD, X370 & co */
2625 { PCI_VDEVICE(AMD, 0x1457),
2626 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2627 /* AMD, X570 & co */
2628 { PCI_VDEVICE(AMD, 0x1487),
2629 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2630 /* AMD Stoney */
2631 { PCI_VDEVICE(AMD, 0x157a),
2632 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2633 AZX_DCAPS_PM_RUNTIME },
2634 /* AMD Raven */
2635 { PCI_VDEVICE(AMD, 0x15e3),
2636 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2637 /* ATI HDMI */
2638 { PCI_VDEVICE(ATI, 0x0002),
2639 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2640 AZX_DCAPS_PM_RUNTIME },
2641 { PCI_VDEVICE(ATI, 0x1308),
2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2643 { PCI_VDEVICE(ATI, 0x157a),
2644 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2645 { PCI_VDEVICE(ATI, 0x15b3),
2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2647 { PCI_VDEVICE(ATI, 0x793b),
2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2649 { PCI_VDEVICE(ATI, 0x7919),
2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2651 { PCI_VDEVICE(ATI, 0x960f),
2652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2653 { PCI_VDEVICE(ATI, 0x970f),
2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2655 { PCI_VDEVICE(ATI, 0x9840),
2656 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2657 { PCI_VDEVICE(ATI, 0xaa00),
2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2659 { PCI_VDEVICE(ATI, 0xaa08),
2660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2661 { PCI_VDEVICE(ATI, 0xaa10),
2662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2663 { PCI_VDEVICE(ATI, 0xaa18),
2664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2665 { PCI_VDEVICE(ATI, 0xaa20),
2666 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2667 { PCI_VDEVICE(ATI, 0xaa28),
2668 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2669 { PCI_VDEVICE(ATI, 0xaa30),
2670 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2671 { PCI_VDEVICE(ATI, 0xaa38),
2672 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2673 { PCI_VDEVICE(ATI, 0xaa40),
2674 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2675 { PCI_VDEVICE(ATI, 0xaa48),
2676 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2677 { PCI_VDEVICE(ATI, 0xaa50),
2678 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2679 { PCI_VDEVICE(ATI, 0xaa58),
2680 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2681 { PCI_VDEVICE(ATI, 0xaa60),
2682 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2683 { PCI_VDEVICE(ATI, 0xaa68),
2684 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2685 { PCI_VDEVICE(ATI, 0xaa80),
2686 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2687 { PCI_VDEVICE(ATI, 0xaa88),
2688 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2689 { PCI_VDEVICE(ATI, 0xaa90),
2690 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2691 { PCI_VDEVICE(ATI, 0xaa98),
2692 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2693 { PCI_VDEVICE(ATI, 0x9902),
2694 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2695 { PCI_VDEVICE(ATI, 0xaaa0),
2696 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2697 { PCI_VDEVICE(ATI, 0xaaa8),
2698 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2699 { PCI_VDEVICE(ATI, 0xaab0),
2700 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2701 { PCI_VDEVICE(ATI, 0xaac0),
2702 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2703 AZX_DCAPS_PM_RUNTIME },
2704 { PCI_VDEVICE(ATI, 0xaac8),
2705 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2706 AZX_DCAPS_PM_RUNTIME },
2707 { PCI_VDEVICE(ATI, 0xaad8),
2708 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2709 AZX_DCAPS_PM_RUNTIME },
2710 { PCI_VDEVICE(ATI, 0xaae0),
2711 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2712 AZX_DCAPS_PM_RUNTIME },
2713 { PCI_VDEVICE(ATI, 0xaae8),
2714 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2715 AZX_DCAPS_PM_RUNTIME },
2716 { PCI_VDEVICE(ATI, 0xaaf0),
2717 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2718 AZX_DCAPS_PM_RUNTIME },
2719 { PCI_VDEVICE(ATI, 0xaaf8),
2720 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2721 AZX_DCAPS_PM_RUNTIME },
2722 { PCI_VDEVICE(ATI, 0xab00),
2723 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2724 AZX_DCAPS_PM_RUNTIME },
2725 { PCI_VDEVICE(ATI, 0xab08),
2726 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2727 AZX_DCAPS_PM_RUNTIME },
2728 { PCI_VDEVICE(ATI, 0xab10),
2729 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2730 AZX_DCAPS_PM_RUNTIME },
2731 { PCI_VDEVICE(ATI, 0xab18),
2732 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2733 AZX_DCAPS_PM_RUNTIME },
2734 { PCI_VDEVICE(ATI, 0xab20),
2735 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2736 AZX_DCAPS_PM_RUNTIME },
2737 { PCI_VDEVICE(ATI, 0xab28),
2738 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2739 AZX_DCAPS_PM_RUNTIME },
2740 { PCI_VDEVICE(ATI, 0xab30),
2741 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2742 AZX_DCAPS_PM_RUNTIME },
2743 { PCI_VDEVICE(ATI, 0xab38),
2744 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2745 AZX_DCAPS_PM_RUNTIME },
2746 { PCI_VDEVICE(ATI, 0xab40),
2747 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2748 AZX_DCAPS_PM_RUNTIME },
2749 /* GLENFLY */
2750 { PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID),
2751 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2752 .class_mask = 0xffffff,
2753 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2754 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2755 /* VIA VT8251/VT8237A */
2756 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA },
2757 /* VIA GFX VT7122/VX900 */
2758 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2759 /* VIA GFX VT6122/VX11 */
2760 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2761 /* SIS966 */
2762 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },
2763 /* ULI M5461 */
2764 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI },
2765 /* NVIDIA MCP */
2766 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2767 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2768 .class_mask = 0xffffff,
2769 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2770 /* Teradici */
2771 { PCI_DEVICE(0x6549, 0x1200),
2772 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2773 { PCI_DEVICE(0x6549, 0x2200),
2774 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2775 /* Creative X-Fi (CA0110-IBG) */
2776 /* CTHDA chips */
2777 { PCI_VDEVICE(CREATIVE, 0x0010),
2778 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2779 { PCI_VDEVICE(CREATIVE, 0x0012),
2780 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2781 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2782 /* the following entry conflicts with snd-ctxfi driver,
2783 * as ctxfi driver mutates from HD-audio to native mode with
2784 * a special command sequence.
2785 */
2786 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2787 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2788 .class_mask = 0xffffff,
2789 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2790 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2791 #else
2792 /* this entry seems still valid -- i.e. without emu20kx chip */
2793 { PCI_VDEVICE(CREATIVE, 0x0009),
2794 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2795 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2796 #endif
2797 /* CM8888 */
2798 { PCI_VDEVICE(CMEDIA, 0x5011),
2799 .driver_data = AZX_DRIVER_CMEDIA |
2800 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2801 /* Vortex86MX */
2802 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2803 /* VMware HDAudio */
2804 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2805 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2806 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2807 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2808 .class_mask = 0xffffff,
2809 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2810 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2811 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2812 .class_mask = 0xffffff,
2813 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2814 /* Zhaoxin */
2815 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2816 { PCI_VDEVICE(ZHAOXIN, 0x9141),
2817 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2818 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2819 { PCI_VDEVICE(ZHAOXIN, 0x9142),
2820 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2821 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2822 { PCI_VDEVICE(ZHAOXIN, 0x9144),
2823 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2824 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2825 { PCI_VDEVICE(ZHAOXIN, 0x9145),
2826 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2827 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2828 { PCI_VDEVICE(ZHAOXIN, 0x9146),
2829 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2830 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2831 /* Loongson HDAudio*/
2832 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),
2833 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL },
2834 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),
2835 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL },
2836 { 0, }
2837 };
2838 MODULE_DEVICE_TABLE(pci, azx_ids);
2839
2840 /* pci_driver definition */
2841 static struct pci_driver azx_driver = {
2842 .name = KBUILD_MODNAME,
2843 .id_table = azx_ids,
2844 .probe = azx_probe,
2845 .remove = azx_remove,
2846 .shutdown = azx_shutdown,
2847 .driver = {
2848 .pm = pm_ptr(&azx_pm),
2849 },
2850 };
2851
2852 module_pci_driver(azx_driver);
2853