1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries 4 * Copyright 2016 Microsemi Corporation 5 * Copyright 2014-2015 PMC-Sierra, Inc. 6 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 15 * NON INFRINGEMENT. See the GNU General Public License for more details. 16 * 17 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com 18 * 19 */ 20 #ifndef HPSA_CMD_H 21 #define HPSA_CMD_H 22 23 #include <linux/compiler.h> 24 25 #include <linux/build_bug.h> /* static_assert */ 26 #include <linux/stddef.h> /* offsetof */ 27 28 /* general boundary defintions */ 29 #define SENSEINFOBYTES 32 /* may vary between hbas */ 30 #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */ 31 #define HPSA_SG_CHAIN 0x80000000 32 #define HPSA_SG_LAST 0x40000000 33 #define MAXREPLYQS 256 34 35 /* Command Status value */ 36 #define CMD_SUCCESS 0x0000 37 #define CMD_TARGET_STATUS 0x0001 38 #define CMD_DATA_UNDERRUN 0x0002 39 #define CMD_DATA_OVERRUN 0x0003 40 #define CMD_INVALID 0x0004 41 #define CMD_PROTOCOL_ERR 0x0005 42 #define CMD_HARDWARE_ERR 0x0006 43 #define CMD_CONNECTION_LOST 0x0007 44 #define CMD_ABORTED 0x0008 45 #define CMD_ABORT_FAILED 0x0009 46 #define CMD_UNSOLICITED_ABORT 0x000A 47 #define CMD_TIMEOUT 0x000B 48 #define CMD_UNABORTABLE 0x000C 49 #define CMD_TMF_STATUS 0x000D 50 #define CMD_IOACCEL_DISABLED 0x000E 51 #define CMD_CTLR_LOCKUP 0xffff 52 /* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec 53 * it is a value defined by the driver that commands can be marked 54 * with when a controller lockup has been detected by the driver 55 */ 56 57 /* TMF function status values */ 58 #define CISS_TMF_COMPLETE 0x00 59 #define CISS_TMF_INVALID_FRAME 0x02 60 #define CISS_TMF_NOT_SUPPORTED 0x04 61 #define CISS_TMF_FAILED 0x05 62 #define CISS_TMF_SUCCESS 0x08 63 #define CISS_TMF_WRONG_LUN 0x09 64 #define CISS_TMF_OVERLAPPED_TAG 0x0a 65 66 /* transfer direction */ 67 #define XFER_NONE 0x00 68 #define XFER_WRITE 0x01 69 #define XFER_READ 0x02 70 #define XFER_RSVD 0x03 71 72 /* task attribute */ 73 #define ATTR_UNTAGGED 0x00 74 #define ATTR_SIMPLE 0x04 75 #define ATTR_HEADOFQUEUE 0x05 76 #define ATTR_ORDERED 0x06 77 #define ATTR_ACA 0x07 78 79 /* cdb type */ 80 #define TYPE_CMD 0x00 81 #define TYPE_MSG 0x01 82 #define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */ 83 84 /* Message Types */ 85 #define HPSA_TASK_MANAGEMENT 0x00 86 #define HPSA_RESET 0x01 87 #define HPSA_SCAN 0x02 88 #define HPSA_NOOP 0x03 89 90 #define HPSA_CTLR_RESET_TYPE 0x00 91 #define HPSA_BUS_RESET_TYPE 0x01 92 #define HPSA_TARGET_RESET_TYPE 0x03 93 #define HPSA_LUN_RESET_TYPE 0x04 94 #define HPSA_NEXUS_RESET_TYPE 0x05 95 96 /* Task Management Functions */ 97 #define HPSA_TMF_ABORT_TASK 0x00 98 #define HPSA_TMF_ABORT_TASK_SET 0x01 99 #define HPSA_TMF_CLEAR_ACA 0x02 100 #define HPSA_TMF_CLEAR_TASK_SET 0x03 101 #define HPSA_TMF_QUERY_TASK 0x04 102 #define HPSA_TMF_QUERY_TASK_SET 0x05 103 #define HPSA_TMF_QUERY_ASYNCEVENT 0x06 104 105 106 107 /* config space register offsets */ 108 #define CFG_VENDORID 0x00 109 #define CFG_DEVICEID 0x02 110 #define CFG_I2OBAR 0x10 111 #define CFG_MEM1BAR 0x14 112 113 /* i2o space register offsets */ 114 #define I2O_IBDB_SET 0x20 115 #define I2O_IBDB_CLEAR 0x70 116 #define I2O_INT_STATUS 0x30 117 #define I2O_INT_MASK 0x34 118 #define I2O_IBPOST_Q 0x40 119 #define I2O_OBPOST_Q 0x44 120 #define I2O_DMA1_CFG 0x214 121 122 /* Configuration Table */ 123 #define CFGTBL_ChangeReq 0x00000001l 124 #define CFGTBL_AccCmds 0x00000001l 125 #define DOORBELL_CTLR_RESET 0x00000004l 126 #define DOORBELL_CTLR_RESET2 0x00000020l 127 #define DOORBELL_CLEAR_EVENTS 0x00000040l 128 #define DOORBELL_GENERATE_CHKPT 0x00000080l 129 130 #define CFGTBL_Trans_Simple 0x00000002l 131 #define CFGTBL_Trans_Performant 0x00000004l 132 #define CFGTBL_Trans_io_accel1 0x00000080l 133 #define CFGTBL_Trans_io_accel2 0x00000100l 134 #define CFGTBL_Trans_use_short_tags 0x20000000l 135 #define CFGTBL_Trans_enable_directed_msix (1 << 30) 136 137 #define CFGTBL_BusType_Ultra2 0x00000001l 138 #define CFGTBL_BusType_Ultra3 0x00000002l 139 #define CFGTBL_BusType_Fibre1G 0x00000100l 140 #define CFGTBL_BusType_Fibre2G 0x00000200l 141 142 /* VPD Inquiry types */ 143 #define HPSA_INQUIRY_FAILED 0x02 144 #define HPSA_VPD_SUPPORTED_PAGES 0x00 145 #define HPSA_VPD_LV_DEVICE_ID 0x83 146 #define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1 147 #define HPSA_VPD_LV_IOACCEL_STATUS 0xC2 148 #define HPSA_VPD_LV_STATUS 0xC3 149 #define HPSA_VPD_HEADER_SZ 4 150 151 /* Logical volume states */ 152 #define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff 153 #define HPSA_LV_OK 0x0 154 #define HPSA_LV_FAILED 0x01 155 #define HPSA_LV_NOT_AVAILABLE 0x0b 156 #define HPSA_LV_UNDERGOING_ERASE 0x0F 157 #define HPSA_LV_UNDERGOING_RPI 0x12 158 #define HPSA_LV_PENDING_RPI 0x13 159 #define HPSA_LV_ENCRYPTED_NO_KEY 0x14 160 #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15 161 #define HPSA_LV_UNDERGOING_ENCRYPTION 0x16 162 #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17 163 #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18 164 #define HPSA_LV_PENDING_ENCRYPTION 0x19 165 #define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A 166 167 struct vals32 { 168 u32 lower; 169 u32 upper; 170 }; 171 172 union u64bit { 173 struct vals32 val32; 174 u64 val; 175 }; 176 177 /* FIXME this is a per controller value (barf!) */ 178 #define HPSA_MAX_LUN 1024 179 #define HPSA_MAX_PHYS_LUN 1024 180 #define MAX_EXT_TARGETS 32 181 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \ 182 MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */ 183 184 /* SCSI-3 Commands */ 185 #define HPSA_INQUIRY 0x12 186 struct InquiryData { 187 u8 data_byte[36]; 188 } __packed; 189 190 #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ 191 #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 192 #define HPSA_REPORT_PHYS_EXTENDED 0x02 193 #define HPSA_CISS_READ 0xc0 /* CISS Read */ 194 #define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */ 195 196 #define RAID_MAP_MAX_ENTRIES 256 197 198 struct raid_map_disk_data { 199 u32 ioaccel_handle; /**< Handle to access this disk via the 200 * I/O accelerator */ 201 u8 xor_mult[2]; /**< XOR multipliers for this position, 202 * valid for data disks only */ 203 u8 reserved[2]; 204 } __packed; 205 206 struct raid_map_data { 207 __le32 structure_size; /* Size of entire structure in bytes */ 208 __le32 volume_blk_size; /* bytes / block in the volume */ 209 __le64 volume_blk_cnt; /* logical blocks on the volume */ 210 u8 phys_blk_shift; /* Shift factor to convert between 211 * units of logical blocks and physical 212 * disk blocks */ 213 u8 parity_rotation_shift; /* Shift factor to convert between units 214 * of logical stripes and physical 215 * stripes */ 216 __le16 strip_size; /* blocks used on each disk / stripe */ 217 __le64 disk_starting_blk; /* First disk block used in volume */ 218 __le64 disk_blk_cnt; /* disk blocks used by volume / disk */ 219 __le16 data_disks_per_row; /* data disk entries / row in the map */ 220 __le16 metadata_disks_per_row;/* mirror/parity disk entries / row 221 * in the map */ 222 __le16 row_cnt; /* rows in each layout map */ 223 __le16 layout_map_count; /* layout maps (1 map per mirror/parity 224 * group) */ 225 __le16 flags; /* Bit 0 set if encryption enabled */ 226 #define RAID_MAP_FLAG_ENCRYPT_ON 0x01 227 __le16 dekindex; /* Data encryption key index. */ 228 u8 reserved[16]; 229 struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES]; 230 } __packed; 231 232 struct ReportLUNdata { 233 u8 LUNListLength[4]; 234 u8 extended_response_flag; 235 u8 reserved[3]; 236 u8 LUN[HPSA_MAX_LUN][8]; 237 } __packed; 238 239 struct ext_report_lun_entry { 240 u8 lunid[8]; 241 #define MASKED_DEVICE(x) ((x)[3] & 0xC0) 242 #define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F) 243 #define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6]) 244 #define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \ 245 GET_BMIC_LEVEL_TWO_TARGET((lunid))) 246 u8 wwid[8]; 247 u8 device_type; 248 u8 device_flags; 249 u8 lun_count; /* multi-lun device, how many luns */ 250 u8 redundant_paths; 251 u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */ 252 } __packed; 253 254 struct ReportExtendedLUNdata { 255 u8 LUNListLength[4]; 256 u8 extended_response_flag; 257 u8 reserved[3]; 258 struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN]; 259 } __packed; 260 261 struct SenseSubsystem_info { 262 u8 reserved[36]; 263 u8 portname[8]; 264 u8 reserved1[1108]; 265 } __packed; 266 267 /* BMIC commands */ 268 #define BMIC_READ 0x26 269 #define BMIC_WRITE 0x27 270 #define BMIC_CACHE_FLUSH 0xc2 271 #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ 272 #define BMIC_FLASH_FIRMWARE 0xF7 273 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 274 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 275 #define BMIC_IDENTIFY_CONTROLLER 0x11 276 #define BMIC_SET_DIAG_OPTIONS 0xF4 277 #define BMIC_SENSE_DIAG_OPTIONS 0xF5 278 #define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x80000000 279 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 280 #define BMIC_SENSE_STORAGE_BOX_PARAMS 0x65 281 282 /* Command List Structure */ 283 union SCSI3Addr { 284 struct { 285 u8 Dev; 286 u8 Bus:6; 287 u8 Mode:2; /* b00 */ 288 } PeripDev; 289 struct { 290 u8 DevLSB; 291 u8 DevMSB:6; 292 u8 Mode:2; /* b01 */ 293 } LogDev; 294 struct { 295 u8 Dev:5; 296 u8 Bus:3; 297 u8 Targ:6; 298 u8 Mode:2; /* b10 */ 299 } LogUnit; 300 } __packed; 301 302 struct PhysDevAddr { 303 u32 TargetId:24; 304 u32 Bus:6; 305 u32 Mode:2; 306 /* 2 level target device addr */ 307 union SCSI3Addr Target[2]; 308 } __packed; 309 310 struct LogDevAddr { 311 u32 VolId:30; 312 u32 Mode:2; 313 u8 reserved[4]; 314 } __packed; 315 316 union LUNAddr { 317 u8 LunAddrBytes[8]; 318 union SCSI3Addr SCSI3Lun[4]; 319 struct PhysDevAddr PhysDev; 320 struct LogDevAddr LogDev; 321 } __packed; 322 323 struct CommandListHeader { 324 u8 ReplyQueue; 325 u8 SGList; 326 __le16 SGTotal; 327 __le64 tag; 328 union LUNAddr LUN; 329 } __packed; 330 331 struct RequestBlock { 332 u8 CDBLen; 333 /* 334 * type_attr_dir: 335 * type: low 3 bits 336 * attr: middle 3 bits 337 * dir: high 2 bits 338 */ 339 u8 type_attr_dir; 340 #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\ 341 (((a) & 0x07) << 3) |\ 342 ((t) & 0x07)) 343 #define GET_TYPE(tad) ((tad) & 0x07) 344 #define GET_ATTR(tad) (((tad) >> 3) & 0x07) 345 #define GET_DIR(tad) (((tad) >> 6) & 0x03) 346 u16 Timeout; 347 u8 CDB[16]; 348 } __packed; 349 350 struct ErrDescriptor { 351 __le64 Addr; 352 __le32 Len; 353 } __packed; 354 355 struct SGDescriptor { 356 __le64 Addr; 357 __le32 Len; 358 __le32 Ext; 359 } __packed; 360 361 union MoreErrInfo { 362 struct { 363 u8 Reserved[3]; 364 u8 Type; 365 u32 ErrorInfo; 366 } Common_Info; 367 struct { 368 u8 Reserved[2]; 369 u8 offense_size; /* size of offending entry */ 370 u8 offense_num; /* byte # of offense 0-base */ 371 u32 offense_value; 372 } Invalid_Cmd; 373 } __packed; 374 375 struct ErrorInfo { 376 u8 ScsiStatus; 377 u8 SenseLen; 378 u16 CommandStatus; 379 u32 ResidualCnt; 380 union MoreErrInfo MoreErrInfo; 381 u8 SenseInfo[SENSEINFOBYTES]; 382 } __packed; 383 /* Command types */ 384 #define CMD_IOCTL_PEND 0x01 385 #define CMD_SCSI 0x03 386 #define CMD_IOACCEL1 0x04 387 #define CMD_IOACCEL2 0x05 388 #define IOACCEL2_TMF 0x06 389 390 #define DIRECT_LOOKUP_SHIFT 4 391 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1)) 392 393 #define HPSA_ERROR_BIT 0x02 394 struct ctlr_info; /* defined in hpsa.h */ 395 /* The size of this structure needs to be divisible by 128 396 * on all architectures. The low 4 bits of the addresses 397 * are used as follows: 398 * 399 * bit 0: to device, used to indicate "performant mode" command 400 * from device, indidcates error status. 401 * bit 1-3: to device, indicates block fetch table entry for 402 * reducing DMA in fetching commands from host memory. 403 */ 404 405 #define COMMANDLIST_ALIGNMENT 128 406 struct CommandList { 407 struct CommandListHeader Header; 408 struct RequestBlock Request; 409 struct ErrDescriptor ErrDesc; 410 struct SGDescriptor SG[SG_ENTRIES_IN_CMD]; 411 /* information associated with the command */ 412 u32 busaddr; /* physical addr of this record */ 413 struct ErrorInfo *err_info; /* pointer to the allocated mem */ 414 struct ctlr_info *h; 415 int cmd_type; 416 long cmdindex; 417 struct completion *waiting; 418 struct scsi_cmnd *scsi_cmd; 419 struct work_struct work; 420 421 /* 422 * For commands using either of the two "ioaccel" paths to 423 * bypass the RAID stack and go directly to the physical disk 424 * phys_disk is a pointer to the hpsa_scsi_dev_t to which the 425 * i/o is destined. We need to store that here because the command 426 * may potentially encounter TASK SET FULL and need to be resubmitted 427 * For "normal" i/o's not using the "ioaccel" paths, phys_disk is 428 * not used. 429 */ 430 struct hpsa_scsi_dev_t *phys_disk; 431 432 bool retry_pending; 433 struct hpsa_scsi_dev_t *device; 434 atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */ 435 } __aligned(COMMANDLIST_ALIGNMENT); 436 437 /* 438 * Make sure our embedded atomic variable is aligned. Otherwise we break atomic 439 * operations on architectures that don't support unaligned atomics like IA64. 440 * 441 * The assert guards against reintroductin against unwanted __packed to 442 * the struct CommandList. 443 */ 444 static_assert(offsetof(struct CommandList, refcount) % __alignof__(atomic_t) == 0); 445 446 /* Max S/G elements in I/O accelerator command */ 447 #define IOACCEL1_MAXSGENTRIES 24 448 #define IOACCEL2_MAXSGENTRIES 28 449 450 /* 451 * Structure for I/O accelerator (mode 1) commands. 452 * Note that this structure must be 128-byte aligned in size. 453 */ 454 #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 455 struct io_accel1_cmd { 456 __le16 dev_handle; /* 0x00 - 0x01 */ 457 u8 reserved1; /* 0x02 */ 458 u8 function; /* 0x03 */ 459 u8 reserved2[8]; /* 0x04 - 0x0B */ 460 u32 err_info; /* 0x0C - 0x0F */ 461 u8 reserved3[2]; /* 0x10 - 0x11 */ 462 u8 err_info_len; /* 0x12 */ 463 u8 reserved4; /* 0x13 */ 464 u8 sgl_offset; /* 0x14 */ 465 u8 reserved5[7]; /* 0x15 - 0x1B */ 466 __le32 transfer_len; /* 0x1C - 0x1F */ 467 u8 reserved6[4]; /* 0x20 - 0x23 */ 468 __le16 io_flags; /* 0x24 - 0x25 */ 469 u8 reserved7[14]; /* 0x26 - 0x33 */ 470 u8 LUN[8]; /* 0x34 - 0x3B */ 471 __le32 control; /* 0x3C - 0x3F */ 472 u8 CDB[16]; /* 0x40 - 0x4F */ 473 u8 reserved8[16]; /* 0x50 - 0x5F */ 474 __le16 host_context_flags; /* 0x60 - 0x61 */ 475 __le16 timeout_sec; /* 0x62 - 0x63 */ 476 u8 ReplyQueue; /* 0x64 */ 477 u8 reserved9[3]; /* 0x65 - 0x67 */ 478 __le64 tag; /* 0x68 - 0x6F */ 479 __le64 host_addr; /* 0x70 - 0x77 */ 480 u8 CISS_LUN[8]; /* 0x78 - 0x7F */ 481 struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES]; 482 } __packed __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT); 483 484 #define IOACCEL1_FUNCTION_SCSIIO 0x00 485 #define IOACCEL1_SGLOFFSET 32 486 487 #define IOACCEL1_IOFLAGS_IO_REQ 0x4000 488 #define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F 489 #define IOACCEL1_IOFLAGS_CDBLEN_MAX 16 490 491 #define IOACCEL1_CONTROL_NODATAXFER 0x00000000 492 #define IOACCEL1_CONTROL_DATA_OUT 0x01000000 493 #define IOACCEL1_CONTROL_DATA_IN 0x02000000 494 #define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800 495 #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11 496 #define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000 497 #define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100 498 #define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200 499 #define IOACCEL1_CONTROL_ACA 0x00000400 500 501 #define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013 502 503 #define IOACCEL1_BUSADDR_CMDTYPE 0x00000060 504 505 struct ioaccel2_sg_element { 506 __le64 address; 507 __le32 length; 508 u8 reserved[3]; 509 u8 chain_indicator; 510 #define IOACCEL2_CHAIN 0x80 511 #define IOACCEL2_LAST_SG 0x40 512 } __packed; 513 514 /* 515 * SCSI Response Format structure for IO Accelerator Mode 2 516 */ 517 struct io_accel2_scsi_response { 518 u8 IU_type; 519 #define IOACCEL2_IU_TYPE_SRF 0x60 520 u8 reserved1[3]; 521 u8 req_id[4]; /* request identifier */ 522 u8 reserved2[4]; 523 u8 serv_response; /* service response */ 524 #define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000 525 #define IOACCEL2_SERV_RESPONSE_FAILURE 0x001 526 #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002 527 #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003 528 #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004 529 #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005 530 u8 status; /* status */ 531 #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00 532 #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02 533 #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08 534 #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18 535 #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28 536 #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40 537 #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E 538 #define IOACCEL2_STATUS_SR_IO_ERROR 0x01 539 #define IOACCEL2_STATUS_SR_IO_ABORTED 0x02 540 #define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE 0x03 541 #define IOACCEL2_STATUS_SR_INVALID_DEVICE 0x04 542 #define IOACCEL2_STATUS_SR_UNDERRUN 0x51 543 #define IOACCEL2_STATUS_SR_OVERRUN 0x75 544 u8 data_present; /* low 2 bits */ 545 #define IOACCEL2_NO_DATAPRESENT 0x000 546 #define IOACCEL2_RESPONSE_DATAPRESENT 0x001 547 #define IOACCEL2_SENSE_DATA_PRESENT 0x002 548 #define IOACCEL2_RESERVED 0x003 549 u8 sense_data_len; /* sense/response data length */ 550 u8 resid_cnt[4]; /* residual count */ 551 u8 sense_data_buff[32]; /* sense/response data buffer */ 552 } __packed; 553 554 /* 555 * Structure for I/O accelerator (mode 2 or m2) commands. 556 * Note that this structure must be 128-byte aligned in size. 557 */ 558 #define IOACCEL2_COMMANDLIST_ALIGNMENT 128 559 struct io_accel2_cmd { 560 u8 IU_type; /* IU Type */ 561 u8 direction; /* direction, memtype, and encryption */ 562 #define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */ 563 #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */ 564 /* 0b=PCIe, 1b=DDR */ 565 #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */ 566 /* 0=off, 1=on */ 567 u8 reply_queue; /* Reply Queue ID */ 568 u8 reserved1; /* Reserved */ 569 __le32 scsi_nexus; /* Device Handle */ 570 __le32 Tag; /* cciss tag, lower 4 bytes only */ 571 __le32 tweak_lower; /* Encryption tweak, lower 4 bytes */ 572 u8 cdb[16]; /* SCSI Command Descriptor Block */ 573 u8 cciss_lun[8]; /* 8 byte SCSI address */ 574 __le32 data_len; /* Total bytes to transfer */ 575 u8 cmd_priority_task_attr; /* priority and task attrs */ 576 #define IOACCEL2_PRIORITY_MASK 0x78 577 #define IOACCEL2_ATTR_MASK 0x07 578 u8 sg_count; /* Number of sg elements */ 579 __le16 dekindex; /* Data encryption key index */ 580 __le64 err_ptr; /* Error Pointer */ 581 __le32 err_len; /* Error Length*/ 582 __le32 tweak_upper; /* Encryption tweak, upper 4 bytes */ 583 struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES]; 584 struct io_accel2_scsi_response error_data; 585 } __packed __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); 586 587 /* 588 * defines for Mode 2 command struct 589 * FIXME: this can't be all I need mfm 590 */ 591 #define IOACCEL2_IU_TYPE 0x40 592 #define IOACCEL2_IU_TMF_TYPE 0x41 593 #define IOACCEL2_DIR_NO_DATA 0x00 594 #define IOACCEL2_DIR_DATA_IN 0x01 595 #define IOACCEL2_DIR_DATA_OUT 0x02 596 #define IOACCEL2_TMF_ABORT 0x01 597 /* 598 * SCSI Task Management Request format for Accelerator Mode 2 599 */ 600 struct hpsa_tmf_struct { 601 u8 iu_type; /* Information Unit Type */ 602 u8 reply_queue; /* Reply Queue ID */ 603 u8 tmf; /* Task Management Function */ 604 u8 reserved1; /* byte 3 Reserved */ 605 __le32 it_nexus; /* SCSI I-T Nexus */ 606 u8 lun_id[8]; /* LUN ID for TMF request */ 607 __le64 tag; /* cciss tag associated w/ request */ 608 __le64 abort_tag; /* cciss tag of SCSI cmd or TMF to abort */ 609 __le64 error_ptr; /* Error Pointer */ 610 __le32 error_len; /* Error Length */ 611 } __packed __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); 612 613 /* Configuration Table Structure */ 614 struct HostWrite { 615 __le32 TransportRequest; 616 __le32 command_pool_addr_hi; 617 __le32 CoalIntDelay; 618 __le32 CoalIntCount; 619 } __packed; 620 621 #define SIMPLE_MODE 0x02 622 #define PERFORMANT_MODE 0x04 623 #define MEMQ_MODE 0x08 624 #define IOACCEL_MODE_1 0x80 625 626 #define DRIVER_SUPPORT_UA_ENABLE 0x00000001 627 628 struct CfgTable { 629 u8 Signature[4]; 630 __le32 SpecValence; 631 __le32 TransportSupport; 632 __le32 TransportActive; 633 struct HostWrite HostWrite; 634 __le32 CmdsOutMax; 635 __le32 BusTypes; 636 __le32 TransMethodOffset; 637 u8 ServerName[16]; 638 __le32 HeartBeat; 639 __le32 driver_support; 640 #define ENABLE_SCSI_PREFETCH 0x100 641 #define ENABLE_UNIT_ATTN 0x01 642 __le32 MaxScatterGatherElements; 643 __le32 MaxLogicalUnits; 644 __le32 MaxPhysicalDevices; 645 __le32 MaxPhysicalDrivesPerLogicalUnit; 646 __le32 MaxPerformantModeCommands; 647 __le32 MaxBlockFetch; 648 __le32 PowerConservationSupport; 649 __le32 PowerConservationEnable; 650 __le32 TMFSupportFlags; 651 u8 TMFTagMask[8]; 652 u8 reserved[0x78 - 0x70]; 653 __le32 misc_fw_support; /* offset 0x78 */ 654 #define MISC_FW_DOORBELL_RESET 0x02 655 #define MISC_FW_DOORBELL_RESET2 0x010 656 #define MISC_FW_RAID_OFFLOAD_BASIC 0x020 657 #define MISC_FW_EVENT_NOTIFY 0x080 658 u8 driver_version[32]; 659 __le32 max_cached_write_size; 660 u8 driver_scratchpad[16]; 661 __le32 max_error_info_length; 662 __le32 io_accel_max_embedded_sg_count; 663 __le32 io_accel_request_size_offset; 664 __le32 event_notify; 665 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30) 666 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31) 667 __le32 clear_event_notify; 668 } __packed; 669 670 #define NUM_BLOCKFETCH_ENTRIES 8 671 struct TransTable_struct { 672 __le32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; 673 __le32 RepQSize; 674 __le32 RepQCount; 675 __le32 RepQCtrAddrLow32; 676 __le32 RepQCtrAddrHigh32; 677 #define MAX_REPLY_QUEUES 64 678 struct vals32 RepQAddr[MAX_REPLY_QUEUES]; 679 } __packed; 680 681 struct hpsa_pci_info { 682 unsigned char bus; 683 unsigned char dev_fn; 684 unsigned short domain; 685 u32 board_id; 686 } __packed; 687 688 struct bmic_identify_controller { 689 u8 configured_logical_drive_count; /* offset 0 */ 690 u8 pad1[153]; 691 __le16 extended_logical_unit_count; /* offset 154 */ 692 u8 pad2[136]; 693 u8 controller_mode; /* offset 292 */ 694 u8 pad3[32]; 695 } __packed; 696 697 698 struct bmic_identify_physical_device { 699 u8 scsi_bus; /* SCSI Bus number on controller */ 700 u8 scsi_id; /* SCSI ID on this bus */ 701 __le16 block_size; /* sector size in bytes */ 702 __le32 total_blocks; /* number for sectors on drive */ 703 __le32 reserved_blocks; /* controller reserved (RIS) */ 704 u8 model[40]; /* Physical Drive Model */ 705 u8 serial_number[40]; /* Drive Serial Number */ 706 u8 firmware_revision[8]; /* drive firmware revision */ 707 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ 708 u8 compaq_drive_stamp; /* 0 means drive not stamped */ 709 u8 last_failure_reason; 710 #define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG 0x01 711 #define BMIC_LAST_FAILURE_ERROR_ERASING_RIS 0x02 712 #define BMIC_LAST_FAILURE_ERROR_SAVING_RIS 0x03 713 #define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND 0x04 714 #define BMIC_LAST_FAILURE_MARK_BAD_FAILED 0x05 715 #define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP 0x06 716 #define BMIC_LAST_FAILURE_TIMEOUT 0x07 717 #define BMIC_LAST_FAILURE_AUTOSENSE_FAILED 0x08 718 #define BMIC_LAST_FAILURE_MEDIUM_ERROR_1 0x09 719 #define BMIC_LAST_FAILURE_MEDIUM_ERROR_2 0x0a 720 #define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE 0x0b 721 #define BMIC_LAST_FAILURE_NOT_READY 0x0c 722 #define BMIC_LAST_FAILURE_HARDWARE_ERROR 0x0d 723 #define BMIC_LAST_FAILURE_ABORTED_COMMAND 0x0e 724 #define BMIC_LAST_FAILURE_WRITE_PROTECTED 0x0f 725 #define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER 0x10 726 #define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR 0x11 727 #define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG 0x12 728 #define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED 0x13 729 #define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG 0x14 730 #define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED 0x15 731 #define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED 0x16 732 #define BMIC_LAST_FAILURE_INQUIRY_FAILED 0x17 733 #define BMIC_LAST_FAILURE_NON_DISK_DEVICE 0x18 734 #define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED 0x19 735 #define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE 0x1a 736 #define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED 0x1b 737 #define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED 0x1c 738 #define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP 0x1d 739 #define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED 0x1e 740 #define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR 0x1f 741 #define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS 0x20 742 #define BMIC_LAST_FAILURE_WRONG_REPLACE 0x21 743 #define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED 0x22 744 #define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED 0x23 745 #define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE 0x24 746 #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG 0x25 747 #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG 0x26 748 #define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED 0x27 749 #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY 0x28 750 #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED 0x29 751 #define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY 0x2a 752 #define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED 0x2b 753 754 #define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED 0x37 755 #define BMIC_LAST_FAILURE_PHY_RESET_FAILED 0x38 756 #define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE 0x40 757 #define BMIC_LAST_FAILURE_KC_VOLUME_FAILED 0x41 758 #define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT 0x42 759 #define BMIC_LAST_FAILURE_OFFLINE_ERASE 0x80 760 #define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL 0x81 761 #define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX 0x82 762 #define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE 0x83 763 764 u8 flags; 765 u8 more_flags; 766 u8 scsi_lun; /* SCSI LUN for phys drive */ 767 u8 yet_more_flags; 768 u8 even_more_flags; 769 __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */ 770 u8 phys_connector[2]; /* connector number on controller */ 771 u8 phys_box_on_bus; /* phys enclosure this drive resides */ 772 u8 phys_bay_in_box; /* phys drv bay this drive resides */ 773 __le32 rpm; /* Drive rotational speed in rpm */ 774 u8 device_type; /* type of drive */ 775 #define BMIC_DEVICE_TYPE_CONTROLLER 0x07 776 777 u8 sata_version; /* only valid when drive_type is SATA */ 778 __le64 big_total_block_count; 779 __le64 ris_starting_lba; 780 __le32 ris_size; 781 u8 wwid[20]; 782 u8 controller_phy_map[32]; 783 __le16 phy_count; 784 u8 phy_connected_dev_type[256]; 785 u8 phy_to_drive_bay_num[256]; 786 __le16 phy_to_attached_dev_index[256]; 787 u8 box_index; 788 u8 reserved; 789 __le16 extra_physical_drive_flags; 790 #define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \ 791 (idphydrv->extra_physical_drive_flags & (1 << 10)) 792 u8 negotiated_link_rate[256]; 793 u8 phy_to_phy_map[256]; 794 u8 redundant_path_present_map; 795 u8 redundant_path_failure_map; 796 u8 active_path_number; 797 __le16 alternate_paths_phys_connector[8]; 798 u8 alternate_paths_phys_box_on_port[8]; 799 u8 multi_lun_device_lun_count; 800 u8 minimum_good_fw_revision[8]; 801 u8 unique_inquiry_bytes[20]; 802 u8 current_temperature_degreesC; 803 u8 temperature_threshold_degreesC; 804 u8 max_temperature_degreesC; 805 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */ 806 __le16 current_queue_depth_limit; 807 u8 reserved_switch_stuff[60]; 808 __le16 power_on_hours; /* valid only if gas gauge supported */ 809 __le16 percent_endurance_used; /* valid only if gas gauge supported. */ 810 #define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \ 811 ((idphydrv->percent_endurance_used & 0x80) || \ 812 (idphydrv->percent_endurance_used > 10000)) 813 u8 drive_authentication; 814 #define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \ 815 (idphydrv->drive_authentication == 0x80) 816 u8 smart_carrier_authentication; 817 #define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \ 818 (idphydrv->smart_carrier_authentication != 0x0) 819 #define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \ 820 (idphydrv->smart_carrier_authentication == 0x01) 821 u8 smart_carrier_app_fw_version; 822 u8 smart_carrier_bootloader_fw_version; 823 u8 sanitize_support_flags; 824 u8 drive_key_flags; 825 u8 encryption_key_name[64]; 826 __le32 misc_drive_flags; 827 __le16 dek_index; 828 __le16 hba_drive_encryption_flags; 829 __le16 max_overwrite_time; 830 __le16 max_block_erase_time; 831 __le16 max_crypto_erase_time; 832 u8 device_connector_info[5]; 833 u8 connector_name[8][8]; 834 u8 page_83_id[16]; 835 u8 max_link_rate[256]; 836 u8 neg_phys_link_rate[256]; 837 u8 box_conn_name[8]; 838 } __packed __attribute((aligned(512))); 839 840 struct bmic_sense_subsystem_info { 841 u8 primary_slot_number; 842 u8 reserved[3]; 843 u8 chasis_serial_number[32]; 844 u8 primary_world_wide_id[8]; 845 u8 primary_array_serial_number[32]; /* NULL terminated */ 846 u8 primary_cache_serial_number[32]; /* NULL terminated */ 847 u8 reserved_2[8]; 848 u8 secondary_array_serial_number[32]; 849 u8 secondary_cache_serial_number[32]; 850 u8 pad[332]; 851 } __packed; 852 853 struct bmic_sense_storage_box_params { 854 u8 reserved[36]; 855 u8 inquiry_valid; 856 u8 reserved_1[68]; 857 u8 phys_box_on_port; 858 u8 reserved_2[22]; 859 u16 connection_info; 860 u8 reserver_3[84]; 861 u8 phys_connector[2]; 862 u8 reserved_4[296]; 863 } __packed; 864 865 #endif /* HPSA_CMD_H */ 866