1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__ 27 #define __DAL_TIMING_GENERATOR_TYPES_H__ 28 29 #include "hw_shared.h" 30 31 struct dc_bios; 32 33 /* Contains CRTC vertical/horizontal pixel counters */ 34 struct crtc_position { 35 int32_t vertical_count; 36 int32_t horizontal_count; 37 int32_t nominal_vcount; 38 }; 39 40 struct dcp_gsl_params { 41 int gsl_group; 42 int gsl_master; 43 }; 44 45 struct gsl_params { 46 int gsl0_en; 47 int gsl1_en; 48 int gsl2_en; 49 int gsl_master_en; 50 int gsl_master_mode; 51 int master_update_lock_gsl_en; 52 int gsl_window_start_x; 53 int gsl_window_end_x; 54 int gsl_window_start_y; 55 int gsl_window_end_y; 56 }; 57 58 /* define the structure of Dynamic Refresh Mode */ 59 struct drr_params { 60 uint32_t vertical_total_min; 61 uint32_t vertical_total_max; 62 uint32_t vertical_total_mid; 63 uint32_t vertical_total_mid_frame_num; 64 bool immediate_flip; 65 }; 66 67 struct long_vtotal_params { 68 uint32_t vertical_total_min; 69 uint32_t vertical_total_max; 70 uint32_t vertical_blank_start; 71 }; 72 73 #define LEFT_EYE_3D_PRIMARY_SURFACE 1 74 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0 75 76 enum crtc_state { 77 CRTC_STATE_VBLANK = 0, 78 CRTC_STATE_VACTIVE 79 }; 80 81 struct vupdate_keepout_params { 82 int start_offset; 83 int end_offset; 84 int enable; 85 }; 86 87 struct crtc_stereo_flags { 88 uint8_t PROGRAM_STEREO : 1; 89 uint8_t PROGRAM_POLARITY : 1; 90 uint8_t RIGHT_EYE_POLARITY : 1; 91 uint8_t FRAME_PACKED : 1; 92 uint8_t DISABLE_STEREO_DP_SYNC : 1; 93 }; 94 95 enum crc_selection { 96 /* Order must match values expected by hardware */ 97 UNION_WINDOW_A_B = 0, 98 UNION_WINDOW_A_NOT_B, 99 UNION_WINDOW_NOT_A_B, 100 UNION_WINDOW_NOT_A_NOT_B, 101 INTERSECT_WINDOW_A_B, 102 INTERSECT_WINDOW_A_NOT_B, 103 INTERSECT_WINDOW_NOT_A_B, 104 INTERSECT_WINDOW_NOT_A_NOT_B, 105 }; 106 107 enum otg_out_mux_dest { 108 OUT_MUX_DIO = 0, 109 OUT_MUX_HPO_DP = 2, 110 }; 111 112 enum h_timing_div_mode { 113 H_TIMING_NO_DIV, 114 H_TIMING_DIV_BY2, 115 H_TIMING_RESERVED, 116 H_TIMING_DIV_BY4, 117 }; 118 119 enum timing_synchronization_type { 120 NOT_SYNCHRONIZABLE, 121 TIMING_SYNCHRONIZABLE, 122 VBLANK_SYNCHRONIZABLE 123 }; 124 125 enum crc_poly_mode { 126 CRC_POLY_MODE_16, 127 CRC_POLY_MODE_32, 128 CRC_POLY_MODE_MAX, 129 }; 130 131 struct crc_params { 132 /* Regions used to calculate CRC*/ 133 uint16_t windowa_x_start; 134 uint16_t windowa_x_end; 135 uint16_t windowa_y_start; 136 uint16_t windowa_y_end; 137 138 uint16_t windowb_x_start; 139 uint16_t windowb_x_end; 140 uint16_t windowb_y_start; 141 uint16_t windowb_y_end; 142 143 enum crc_selection selection; 144 145 uint8_t dsc_mode; 146 uint8_t odm_mode; 147 148 bool continuous_mode; 149 bool enable; 150 151 uint8_t crc_eng_inst; 152 bool reset; 153 enum crc_poly_mode crc_poly_mode; 154 }; 155 156 struct dcn_otg_state { 157 uint32_t v_blank_start; 158 uint32_t v_blank_end; 159 uint32_t v_sync_a_pol; 160 uint32_t v_total; 161 uint32_t v_total_max; 162 uint32_t v_total_min; 163 uint32_t v_total_min_sel; 164 uint32_t v_total_max_sel; 165 uint32_t v_sync_a_start; 166 uint32_t v_sync_a_end; 167 uint32_t h_blank_start; 168 uint32_t h_blank_end; 169 uint32_t h_sync_a_start; 170 uint32_t h_sync_a_end; 171 uint32_t h_sync_a_pol; 172 uint32_t h_total; 173 uint32_t underflow_occurred_status; 174 uint32_t otg_enabled; 175 uint32_t blank_enabled; 176 uint32_t vertical_interrupt1_en; 177 uint32_t vertical_interrupt1_line; 178 uint32_t vertical_interrupt2_en; 179 uint32_t vertical_interrupt2_line; 180 uint32_t vertical_interrupt2_dest; 181 uint32_t otg_master_update_lock; 182 uint32_t otg_double_buffer_control; 183 }; 184 185 struct dcn_optc_reg_state { 186 uint32_t optc_bytes_per_pixel; 187 uint32_t optc_data_format_control; 188 uint32_t optc_data_source_select; 189 uint32_t optc_input_clock_control; 190 uint32_t optc_input_global_control; 191 uint32_t optc_input_spare_register; 192 uint32_t optc_memory_config; 193 uint32_t optc_rsmu_underflow; 194 uint32_t optc_underflow_threshold; 195 uint32_t optc_width_control; 196 197 uint32_t otg_3d_structure_control; 198 uint32_t otg_clock_control; 199 uint32_t otg_control; 200 uint32_t otg_count_control; 201 uint32_t otg_count_reset; 202 uint32_t otg_crc_cntl; 203 uint32_t otg_crc_sig_blue_control_mask; 204 uint32_t otg_crc_sig_red_green_mask; 205 uint32_t otg_crc0_data_b; 206 uint32_t otg_crc0_data_rg; 207 uint32_t otg_crc0_windowa_x_control; 208 uint32_t otg_crc0_windowa_x_control_readback; 209 uint32_t otg_crc0_windowa_y_control; 210 uint32_t otg_crc0_windowa_y_control_readback; 211 uint32_t otg_crc0_windowb_x_control; 212 uint32_t otg_crc0_windowb_x_control_readback; 213 uint32_t otg_crc0_windowb_y_control; 214 uint32_t otg_crc0_windowb_y_control_readback; 215 uint32_t otg_crc1_data_b; 216 uint32_t otg_crc1_data_rg; 217 uint32_t otg_crc1_windowa_x_control; 218 uint32_t otg_crc1_windowa_x_control_readback; 219 uint32_t otg_crc1_windowa_y_control; 220 uint32_t otg_crc1_windowa_y_control_readback; 221 uint32_t otg_crc1_windowb_x_control; 222 uint32_t otg_crc1_windowb_x_control_readback; 223 uint32_t otg_crc1_windowb_y_control; 224 uint32_t otg_crc1_windowb_y_control_readback; 225 uint32_t otg_crc2_data_b; 226 uint32_t otg_crc2_data_rg; 227 uint32_t otg_crc3_data_b; 228 uint32_t otg_crc3_data_rg; 229 uint32_t otg_dlpc_control; 230 uint32_t otg_double_buffer_control; 231 uint32_t otg_drr_control2; 232 uint32_t otg_drr_control; 233 uint32_t otg_drr_timing_int_status; 234 uint32_t otg_drr_trigger_window; 235 uint32_t otg_drr_v_total_change; 236 uint32_t otg_drr_v_total_reach_range; 237 uint32_t otg_dsc_start_position; 238 uint32_t otg_force_count_now_cntl; 239 uint32_t otg_global_control0; 240 uint32_t otg_global_control1; 241 uint32_t otg_global_control2; 242 uint32_t otg_global_control3; 243 uint32_t otg_global_control4; 244 uint32_t otg_global_sync_status; 245 uint32_t otg_gsl_control; 246 uint32_t otg_gsl_vsync_gap; 247 uint32_t otg_gsl_window_x; 248 uint32_t otg_gsl_window_y; 249 uint32_t otg_h_blank_start_end; 250 uint32_t otg_h_sync_a; 251 uint32_t otg_h_sync_a_cntl; 252 uint32_t otg_h_timing_cntl; 253 uint32_t otg_h_total; 254 uint32_t otg_interlace_control; 255 uint32_t otg_interlace_status; 256 uint32_t otg_interrupt_control; 257 uint32_t otg_long_vblank_status; 258 uint32_t otg_m_const_dto0; 259 uint32_t otg_m_const_dto1; 260 uint32_t otg_manual_force_vsync_next_line; 261 uint32_t otg_master_en; 262 uint32_t otg_master_update_lock; 263 uint32_t otg_master_update_mode; 264 uint32_t otg_nom_vert_position; 265 uint32_t otg_pipe_update_status; 266 uint32_t otg_pixel_data_readback0; 267 uint32_t otg_pixel_data_readback1; 268 uint32_t otg_request_control; 269 uint32_t otg_snapshot_control; 270 uint32_t otg_snapshot_frame; 271 uint32_t otg_snapshot_position; 272 uint32_t otg_snapshot_status; 273 uint32_t otg_spare_register; 274 uint32_t otg_static_screen_control; 275 uint32_t otg_status; 276 uint32_t otg_status_frame_count; 277 uint32_t otg_status_hv_count; 278 uint32_t otg_status_position; 279 uint32_t otg_status_vf_count; 280 uint32_t otg_stereo_control; 281 uint32_t otg_stereo_force_next_eye; 282 uint32_t otg_stereo_status; 283 uint32_t otg_trig_manual_control; 284 uint32_t otg_triga_cntl; 285 uint32_t otg_triga_manual_trig; 286 uint32_t otg_trigb_cntl; 287 uint32_t otg_trigb_manual_trig; 288 uint32_t otg_update_lock; 289 uint32_t otg_v_blank_start_end; 290 uint32_t otg_v_count_stop_control; 291 uint32_t otg_v_count_stop_control2; 292 uint32_t otg_v_sync_a; 293 uint32_t otg_v_sync_a_cntl; 294 uint32_t otg_v_total; 295 uint32_t otg_v_total_control; 296 uint32_t otg_v_total_int_status; 297 uint32_t otg_v_total_max; 298 uint32_t otg_v_total_mid; 299 uint32_t otg_v_total_min; 300 uint32_t otg_vert_sync_control; 301 uint32_t otg_vertical_interrupt0_control; 302 uint32_t otg_vertical_interrupt0_position; 303 uint32_t otg_vertical_interrupt1_control; 304 uint32_t otg_vertical_interrupt1_position; 305 uint32_t otg_vertical_interrupt2_control; 306 uint32_t otg_vertical_interrupt2_position; 307 uint32_t otg_vready_param; 308 uint32_t otg_vstartup_param; 309 uint32_t otg_vsync_nom_int_status; 310 uint32_t otg_vupdate_keepout; 311 uint32_t otg_vupdate_param; 312 }; 313 314 /** 315 * struct timing_generator - Entry point to Output Timing Generator feature. 316 */ 317 struct timing_generator { 318 /** 319 * @funcs: Timing generator control functions 320 */ 321 const struct timing_generator_funcs *funcs; 322 struct dc_bios *bp; 323 struct dc_context *ctx; 324 int inst; 325 }; 326 327 struct dc_crtc_timing; 328 329 struct drr_params; 330 331 /** 332 * struct timing_generator_funcs - Control timing generator on a given device. 333 */ 334 struct timing_generator_funcs { 335 bool (*validate_timing)(struct timing_generator *tg, 336 const struct dc_crtc_timing *timing); 337 void (*program_timing)(struct timing_generator *tg, 338 const struct dc_crtc_timing *timing, 339 int vready_offset, 340 int vstartup_start, 341 int vupdate_offset, 342 int vupdate_width, 343 int pstate_keepout, 344 const enum signal_type signal, 345 bool use_vbios 346 ); 347 void (*setup_vertical_interrupt0)( 348 struct timing_generator *optc, 349 uint32_t start_line, 350 uint32_t end_line); 351 void (*setup_vertical_interrupt1)( 352 struct timing_generator *optc, 353 uint32_t start_line); 354 void (*setup_vertical_interrupt2)( 355 struct timing_generator *optc, 356 uint32_t start_line); 357 358 bool (*enable_crtc)(struct timing_generator *tg); 359 bool (*disable_crtc)(struct timing_generator *tg); 360 void (*phantom_crtc_post_enable)(struct timing_generator *tg); 361 void (*disable_phantom_crtc)(struct timing_generator *tg); 362 bool (*immediate_disable_crtc)(struct timing_generator *tg); 363 bool (*is_counter_moving)(struct timing_generator *tg); 364 void (*get_position)(struct timing_generator *tg, 365 struct crtc_position *position); 366 367 uint32_t (*get_frame_count)(struct timing_generator *tg); 368 void (*get_scanoutpos)( 369 struct timing_generator *tg, 370 uint32_t *v_blank_start, 371 uint32_t *v_blank_end, 372 uint32_t *h_position, 373 uint32_t *v_position); 374 bool (*get_otg_active_size)(struct timing_generator *optc, 375 uint32_t *otg_active_width, 376 uint32_t *otg_active_height); 377 bool (*is_matching_timing)(struct timing_generator *tg, 378 const struct dc_crtc_timing *otg_timing); 379 void (*set_early_control)(struct timing_generator *tg, 380 uint32_t early_cntl); 381 void (*wait_for_state)(struct timing_generator *tg, 382 enum crtc_state state); 383 void (*set_blank)(struct timing_generator *tg, 384 bool enable_blanking); 385 bool (*is_blanked)(struct timing_generator *tg); 386 void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color); 387 void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color); 388 void (*set_colors)(struct timing_generator *tg, 389 const struct tg_color *blank_color, 390 const struct tg_color *overscan_color); 391 392 void (*disable_vga)(struct timing_generator *tg); 393 bool (*did_triggered_reset_occur)(struct timing_generator *tg); 394 void (*setup_global_swap_lock)(struct timing_generator *tg, 395 const struct dcp_gsl_params *gsl_params); 396 void (*unlock)(struct timing_generator *tg); 397 void (*lock)(struct timing_generator *tg); 398 void (*lock_doublebuffer_disable)(struct timing_generator *tg); 399 void (*lock_doublebuffer_enable)(struct timing_generator *tg); 400 void(*triplebuffer_unlock)(struct timing_generator *tg); 401 void(*triplebuffer_lock)(struct timing_generator *tg); 402 void (*enable_reset_trigger)(struct timing_generator *tg, 403 int source_tg_inst); 404 void (*enable_crtc_reset)(struct timing_generator *tg, 405 int source_tg_inst, 406 struct crtc_trigger_info *crtc_tp); 407 void (*disable_reset_trigger)(struct timing_generator *tg); 408 void (*tear_down_global_swap_lock)(struct timing_generator *tg); 409 void (*enable_advanced_request)(struct timing_generator *tg, 410 bool enable, const struct dc_crtc_timing *timing); 411 void (*set_drr)(struct timing_generator *tg, const struct drr_params *params); 412 void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max); 413 void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate); 414 void (*set_static_screen_control)(struct timing_generator *tg, 415 uint32_t event_triggers, 416 uint32_t num_frames); 417 void (*set_test_pattern)( 418 struct timing_generator *tg, 419 enum controller_dp_test_pattern test_pattern, 420 enum dc_color_depth color_depth); 421 422 bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); 423 424 void (*program_global_sync)(struct timing_generator *tg, 425 int vready_offset, 426 int vstartup_start, 427 int vupdate_offset, 428 int vupdate_width, 429 int pstate_keepout); 430 void (*enable_optc_clock)(struct timing_generator *tg, bool enable); 431 void (*program_stereo)(struct timing_generator *tg, 432 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); 433 bool (*is_stereo_left_eye)(struct timing_generator *tg); 434 435 void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable); 436 437 void (*tg_init)(struct timing_generator *tg); 438 bool (*is_tg_enabled)(struct timing_generator *tg); 439 bool (*is_optc_underflow_occurred)(struct timing_generator *tg); 440 void (*clear_optc_underflow)(struct timing_generator *tg); 441 442 void (*set_dwb_source)(struct timing_generator *optc, 443 uint32_t dwb_pipe_inst); 444 445 void (*get_optc_source)(struct timing_generator *optc, 446 uint32_t *num_of_input_segments, 447 uint32_t *seg0_src_sel, 448 uint32_t *seg1_src_sel); 449 bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing); 450 451 /** 452 * Configure CRCs for the given timing generator. Return false if TG is 453 * not on. 454 */ 455 bool (*configure_crc)(struct timing_generator *tg, 456 const struct crc_params *params); 457 458 /** 459 * @get_crc: Get CRCs for the given timing generator. Return false if 460 * CRCs are not enabled (via configure_crc). 461 */ 462 bool (*get_crc)(struct timing_generator *tg, uint8_t idx, 463 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); 464 465 void (*program_manual_trigger)(struct timing_generator *optc); 466 void (*setup_manual_trigger)(struct timing_generator *optc); 467 bool (*get_hw_timing)(struct timing_generator *optc, 468 struct dc_crtc_timing *hw_crtc_timing); 469 470 void (*set_vtg_params)(struct timing_generator *optc, 471 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); 472 473 void (*set_dsc_config)(struct timing_generator *optc, 474 enum optc_dsc_mode dsc_mode, 475 uint32_t dsc_bytes_per_pixel, 476 uint32_t dsc_slice_width); 477 void (*get_dsc_status)(struct timing_generator *optc, 478 uint32_t *dsc_mode); 479 void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); 480 481 /** 482 * @set_odm_combine: Set up the ODM block to read from the correct 483 * OPP(s) and turn on/off ODM memory. 484 */ 485 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, 486 int segment_width, int last_segment_width); 487 void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments); 488 void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode); 489 void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); 490 void (*set_gsl_source_select)(struct timing_generator *optc, 491 int group_idx, 492 uint32_t gsl_ready_signal); 493 void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest); 494 void (*set_drr_trigger_window)(struct timing_generator *optc, 495 uint32_t window_start, uint32_t window_end); 496 void (*set_vtotal_change_limit)(struct timing_generator *optc, 497 uint32_t limit); 498 void (*align_vblanks)(struct timing_generator *master_optc, 499 struct timing_generator *slave_optc, 500 uint32_t master_pixel_clock_100Hz, 501 uint32_t slave_pixel_clock_100Hz, 502 uint8_t master_clock_divider, 503 uint8_t slave_clock_divider); 504 bool (*validate_vmin_vmax)(struct timing_generator *optc, 505 int vmin, int vmax); 506 bool (*validate_vtotal_change_limit)(struct timing_generator *optc, 507 uint32_t vtotal_change_limit); 508 509 void (*init_odm)(struct timing_generator *tg); 510 void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg); 511 void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params); 512 void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg); 513 void (*wait_otg_disable)(struct timing_generator *optc); 514 bool (*get_optc_double_buffer_pending)(struct timing_generator *tg); 515 bool (*get_otg_double_buffer_pending)(struct timing_generator *tg); 516 bool (*get_pipe_update_pending)(struct timing_generator *tg); 517 void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable); 518 bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked); 519 void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s); 520 void (*optc_read_reg_state)(struct timing_generator *tg, struct dcn_optc_reg_state *optc_reg_state); 521 }; 522 523 #endif 524