| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| H A D | dcn20_mpc.c | 75 int opp_id, in mpc2_set_denorm() argument
107 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc2_set_denorm()
113 int opp_id, in mpc2_set_denorm_clamp() argument
118 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc2_set_denorm_clamp()
121 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc2_set_denorm_clamp()
124 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc2_set_denorm_clamp()
133 int opp_id, in mpc2_set_output_csc() argument
142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
170 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_output_csc()
171 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_output_csc()
[all …]
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| H A D | dcn20_mpc.h | 284 int opp_id,
289 int opp_id,
294 int opp_id,
300 int opp_id,
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/ |
| H A D | dcn30_optc.c | 218 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc3_set_odm_combine() argument
241 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc3_set_odm_combine()
246 …memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (o… in optc3_set_odm_combine()
256 OPTC_SEG0_SRC_SEL, opp_id[0], in optc3_set_odm_combine()
257 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc3_set_odm_combine()
261 OPTC_SEG0_SRC_SEL, opp_id[0], in optc3_set_odm_combine()
262 OPTC_SEG1_SRC_SEL, opp_id[1], in optc3_set_odm_combine()
263 OPTC_SEG2_SRC_SEL, opp_id[2], in optc3_set_odm_combine()
264 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc3_set_odm_combine()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/ |
| H A D | dcn35_optc.c | 58 static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc35_set_odm_combine() argument
81 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc35_set_odm_combine()
83 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc35_set_odm_combine()
94 OPTC_SEG0_SRC_SEL, opp_id[0], in optc35_set_odm_combine()
95 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc35_set_odm_combine()
99 OPTC_SEG0_SRC_SEL, opp_id[0], in optc35_set_odm_combine()
100 OPTC_SEG1_SRC_SEL, opp_id[1], in optc35_set_odm_combine()
101 OPTC_SEG2_SRC_SEL, opp_id[2], in optc35_set_odm_combine()
102 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc35_set_odm_combine()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_mpc.c | 44 int opp_id, in mpc201_set_out_rate_control() argument
51 REG_UPDATE_2(MUX[opp_id], in mpc201_set_out_rate_control()
56 REG_UPDATE_3(MUX[opp_id], in mpc201_set_out_rate_control()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
| H A D | dcn20_optc.c | 181 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument
202 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc2_set_odm_combine()
210 OPTC_SEG0_SRC_SEL, opp_id[0], in optc2_set_odm_combine()
211 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc2_set_odm_combine()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 874 …block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp-… in hwss_build_fast_sequence()
881 …block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.op… in hwss_build_fast_sequence()
1501 int opp_id, in hwss_add_mpc_set_output_csc() argument
1507 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.opp_id = opp_id; in hwss_add_mpc_set_output_csc()
1520 int opp_id, in hwss_add_mpc_set_ocsc_default() argument
1526 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.opp_id = opp_id; in hwss_add_mpc_set_ocsc_default()
1990 int opp_id = params->set_output_csc_params.opp_id; in hwss_set_output_csc() local
1996 opp_id, in hwss_set_output_csc()
2004 int opp_id = params->set_ocsc_default_params.opp_id; in hwss_set_ocsc_default() local
2010 opp_id, in hwss_set_ocsc_default()
[all …]
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| H A D | dc_resource.c | 3809 if (s.opp_id < MAX_OPP) in acquire_resource_from_hw_enabled_state()
3810 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; in acquire_resource_from_hw_enabled_state()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 132 int opp_id; member
139 int opp_id; member
724 int opp_id; member
1114 uint16_t *matrix, int opp_id);
1638 struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode);
1641 struct mpc *mpc, int opp_id, enum dc_color_space colorspace, enum mpc_output_csc_mode ocsc_mode);
2007 int opp_id);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 301 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn201_init_hw()
320 hubp->opp_id = OPP_ID_INVALID; in dcn201_init_hw()
524 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.c | 152 hubp201->base.opp_id = OPP_ID_INVALID; in dcn201_hubp_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.h | 53 int opp_id);
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| H A D | dcn20_hwseq.c | 173 if (s.opp_id != 0xf) in dcn20_log_color_state()
175 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn20_log_color_state()
990 int opp_id) in dcn20_program_output_csc() argument
1002 opp_id, in dcn20_program_output_csc()
1008 opp_id, in dcn20_program_output_csc()
1814 hubp->opp_id); in dcn20_update_dchubp_dpp()
3001 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn20_update_mpcc()
3177 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn20_fpga_init_hw()
3196 hubp->opp_id = OPP_ID_INVALID; in dcn20_fpga_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 543 if (s.opp_id != 0xf) in dcn10_log_color_state()
545 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn10_log_color_state()
566 if (s.opp_id != 0xf) { in dcn10_log_color_state()
601 if (s.opp_id != 0xf) in dcn10_log_color_state()
1526 int opp_id = hubp->opp_id; in dcn10_plane_atomic_disable() local
1534 if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL) in dcn10_plane_atomic_disable()
1677 hubp->opp_id = OPP_ID_INVALID; in dcn10_init_pipes()
1680 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn10_init_pipes()
2830 int opp_id) in dcn10_program_output_csc() argument
2961 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn10_update_mpcc()
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| /linux/Documentation/arch/arm/omap/ |
| H A D | omap_pm.rst | 127 7. `(*pdata->dsp_set_min_opp)(u8 opp_id)`
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | timing_generator.h | 485 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| H A D | dcn10_hubp.c | 66 hubp->opp_id = OPP_ID_INVALID; in hubp1_set_blank()
1417 hubp1->base.opp_id = OPP_ID_INVALID; in dcn10_hubp_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 188 if (s.opp_id != 0xf) in dcn30_log_color_state()
194 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn30_log_color_state()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| H A D | dcn30_hubp.c | 674 hubp2->base.opp_id = OPP_ID_INVALID; in hubp3_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| H A D | dcn20_hubp.c | 959 hubp->opp_id = OPP_ID_INVALID; in hubp2_set_blank()
1721 hubp2->base.opp_id = OPP_ID_INVALID; in hubp2_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 729 hubp->opp_id = OPP_ID_INVALID; in dcn35_init_pipes()
732 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn35_init_pipes()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| H A D | dcn401_hubp.c | 1091 hubp2->base.opp_id = OPP_ID_INVALID; in hubp401_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 3715 pipe_ctx->stream->csc_color_matrix.matrix, hubp->opp_id); in dcn401_update_dchubp_dpp_sequence()
3846 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn401_update_mpcc_sequence()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 3095 int opp_id) in program_output_csc() argument
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