/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn10/ |
H A D | dcn10_mpc.c | 149 unsigned int opp_id; in mpc1_is_mpcc_idle() local 153 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle() 155 if (top_sel == 0xf && opp_id == 0xf && idle) in mpc1_is_mpcc_idle() 237 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane() 240 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id); in mpc1_insert_plane() 246 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); in mpc1_insert_plane() 302 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); in mpc1_remove_mpcc() 306 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); in mpc1_remove_mpcc() 375 int opp_id; in mpc1_mpc_init() local 387 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { in mpc1_mpc_init() [all …]
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H A D | dcn10_mpc.h | 201 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock); 203 unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/ |
H A D | dcn314_optc.c | 50 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc314_set_odm_combine() argument 73 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc314_set_odm_combine() 75 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc314_set_odm_combine() 86 OPTC_SEG0_SRC_SEL, opp_id[0], in optc314_set_odm_combine() 87 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc314_set_odm_combine() 91 OPTC_SEG0_SRC_SEL, opp_id[0], in optc314_set_odm_combine() 92 OPTC_SEG1_SRC_SEL, opp_id[1], in optc314_set_odm_combine() 93 OPTC_SEG2_SRC_SEL, opp_id[2], in optc314_set_odm_combine() 94 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc314_set_odm_combine()
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/ |
H A D | dcn31_optc.c | 43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc31_set_odm_combine() argument 59 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc31_set_odm_combine() 61 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc31_set_odm_combine() 74 OPTC_SEG0_SRC_SEL, opp_id[0], in optc31_set_odm_combine() 75 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc31_set_odm_combine() 79 OPTC_SEG0_SRC_SEL, opp_id[0], in optc31_set_odm_combine() 80 OPTC_SEG1_SRC_SEL, opp_id[1], in optc31_set_odm_combine() 81 OPTC_SEG2_SRC_SEL, opp_id[2], in optc31_set_odm_combine() 82 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc31_set_odm_combine()
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/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
H A D | dcn20_mpc.c | 75 int opp_id, in mpc2_set_denorm() argument 107 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc2_set_denorm() 113 int opp_id, in mpc2_set_denorm_clamp() argument 118 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc2_set_denorm_clamp() 121 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc2_set_denorm_clamp() 124 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc2_set_denorm_clamp() 133 int opp_id, in mpc2_set_output_csc() argument 142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc() 170 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_output_csc() 171 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_output_csc() [all …]
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H A D | dcn20_mpc.h | 284 int opp_id, 289 int opp_id, 294 int opp_id, 300 int opp_id,
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/ |
H A D | dcn401_optc.c | 57 static uint32_t decide_odm_mem_bit_map(int *opp_id, int opp_cnt, int h_active) in decide_odm_mem_bit_map() argument 67 first_preferred_memory_for_opp[opp_id[i]] = true; in decide_odm_mem_bit_map() 75 second_preferred_memory_for_opp[opp_id[i]] = true; in decide_odm_mem_bit_map() 104 static void optc401_set_odm_combine(struct timing_generator *optc, int *opp_id, in optc401_set_odm_combine() argument 110 opp_id, opp_cnt, h_active); in optc401_set_odm_combine() 119 OPTC_SEG0_SRC_SEL, opp_id[0], in optc401_set_odm_combine() 120 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc401_set_odm_combine() 130 OPTC_SEG0_SRC_SEL, opp_id[0], in optc401_set_odm_combine() 131 OPTC_SEG1_SRC_SEL, opp_id[1], in optc401_set_odm_combine() 132 OPTC_SEG2_SRC_SEL, opp_id[2]); in optc401_set_odm_combine() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | mpc.h | 270 int opp_id; member 288 uint32_t opp_id; member 447 int opp_id, 602 int opp_id, 621 int opp_id, 641 int opp_id, 663 int opp_id, 780 int opp_id, 903 int opp_id);
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H A D | hubp.h | 108 int opp_id; member
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H A D | timing_generator.h | 317 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/ |
H A D | dcn35_optc.c | 58 static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc35_set_odm_combine() argument 81 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc35_set_odm_combine() 83 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc35_set_odm_combine() 94 OPTC_SEG0_SRC_SEL, opp_id[0], in optc35_set_odm_combine() 95 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc35_set_odm_combine() 99 OPTC_SEG0_SRC_SEL, opp_id[0], in optc35_set_odm_combine() 100 OPTC_SEG1_SRC_SEL, opp_id[1], in optc35_set_odm_combine() 101 OPTC_SEG2_SRC_SEL, opp_id[2], in optc35_set_odm_combine() 102 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc35_set_odm_combine()
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/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/ |
H A D | dcn30_mpc.c | 50 int opp_id; in mpc3_mpc_init() local 54 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { in mpc3_mpc_init() 55 if (REG(MUX[opp_id])) in mpc3_mpc_init() 57 REG_UPDATE_2(MUX[opp_id], MPC_OUT_RATE_CONTROL_DISABLE, in mpc3_mpc_init() 374 int opp_id, in mpc3_set_denorm() argument 407 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc3_set_denorm() 413 int opp_id, in mpc3_set_denorm_clamp() argument 419 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc3_set_denorm_clamp() 422 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc3_set_denorm_clamp() 425 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc3_set_denorm_clamp() [all …]
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H A D | dcn30_mpc.h | 1032 int opp_id, 1037 int opp_id, 1042 int opp_id, 1048 int opp_id,
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/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
H A D | dcn201_mpc.c | 44 int opp_id, in mpc201_set_out_rate_control() argument 51 REG_UPDATE_2(MUX[opp_id], in mpc201_set_out_rate_control() 56 REG_UPDATE_3(MUX[opp_id], in mpc201_set_out_rate_control()
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
H A D | dcn20_optc.c | 181 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument 202 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc2_set_odm_combine() 210 OPTC_SEG0_SRC_SEL, opp_id[0], in optc2_set_odm_combine() 211 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc2_set_odm_combine()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/ |
H A D | hw_sequencer.h | 126 int opp_id; member 133 int opp_id; member 312 uint16_t *matrix, int opp_id);
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn31/ |
H A D | dcn31_hubp.c | 115 hubp2->base.opp_id = OPP_ID_INVALID; in hubp31_construct()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
H A D | dcn201_hwseq.c | 298 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn201_init_hw() 317 hubp->opp_id = OPP_ID_INVALID; in dcn201_init_hw() 521 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc()
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
H A D | dcn201_hubp.c | 150 hubp201->base.opp_id = OPP_ID_INVALID; in dcn201_hubp_construct()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
H A D | dcn20_hwseq.h | 53 int opp_id);
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn32/ |
H A D | dcn32_hubp.c | 221 hubp2->base.opp_id = OPP_ID_INVALID; in hubp32_construct()
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn35/ |
H A D | dcn35_hubp.c | 235 hubp2->base.opp_id = OPP_ID_INVALID; in hubp35_construct()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
H A D | dcn10_hwseq.h | 68 int opp_id);
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H A D | dcn10_hwseq.c | 380 if (s.opp_id != 0xf) in dcn10_log_color_state() 382 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn10_log_color_state() 1309 int opp_id = hubp->opp_id; in dcn10_plane_atomic_disable() local 1317 if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL) in dcn10_plane_atomic_disable() 1459 hubp->opp_id = OPP_ID_INVALID; in dcn10_init_pipes() 1462 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn10_init_pipes() 2617 int opp_id) in dcn10_program_output_csc() argument 2749 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn10_update_mpcc()
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/linux/Documentation/arch/arm/omap/ |
H A D | omap_pm.rst | 127 7. `(*pdata->dsp_set_min_opp)(u8 opp_id)`
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