1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2024 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_QUERY_ROCE_CC_GEN2 0x6UL 44 #define TLV_TYPE_MODIFY_ROCE_CC_GEN2 0x7UL 45 #define TLV_TYPE_QUERY_ROCE_CC_GEN1_EXT 0x8UL 46 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1_EXT 0x9UL 47 #define TLV_TYPE_QUERY_ROCE_CC_GEN2_EXT 0xaUL 48 #define TLV_TYPE_MODIFY_ROCE_CC_GEN2_EXT 0xbUL 49 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 50 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 51 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 52 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 53 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 54 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 55 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 56 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 57 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 58 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 59 60 61 /* tlv (size:64b/8B) */ 62 struct tlv { 63 __le16 cmd_discr; 64 u8 reserved_8b; 65 u8 flags; 66 #define TLV_FLAGS_MORE 0x1UL 67 #define TLV_FLAGS_MORE_LAST 0x0UL 68 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 69 #define TLV_FLAGS_REQUIRED 0x2UL 70 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 71 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 72 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 73 __le16 tlv_type; 74 __le16 length; 75 }; 76 77 /* input (size:128b/16B) */ 78 struct input { 79 __le16 req_type; 80 __le16 cmpl_ring; 81 __le16 seq_id; 82 __le16 target_id; 83 __le64 resp_addr; 84 }; 85 86 /* output (size:64b/8B) */ 87 struct output { 88 __le16 error_code; 89 __le16 req_type; 90 __le16 seq_id; 91 __le16 resp_len; 92 }; 93 94 /* hwrm_short_input (size:128b/16B) */ 95 struct hwrm_short_input { 96 __le16 req_type; 97 __le16 signature; 98 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 99 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 100 __le16 target_id; 101 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 102 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 103 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 104 __le16 size; 105 __le64 req_addr; 106 }; 107 108 /* cmd_nums (size:64b/8B) */ 109 struct cmd_nums { 110 __le16 req_type; 111 #define HWRM_VER_GET 0x0UL 112 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 113 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 114 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 115 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 116 #define HWRM_FUNC_VF_CFG 0xfUL 117 #define HWRM_RESERVED1 0x10UL 118 #define HWRM_FUNC_RESET 0x11UL 119 #define HWRM_FUNC_GETFID 0x12UL 120 #define HWRM_FUNC_VF_ALLOC 0x13UL 121 #define HWRM_FUNC_VF_FREE 0x14UL 122 #define HWRM_FUNC_QCAPS 0x15UL 123 #define HWRM_FUNC_QCFG 0x16UL 124 #define HWRM_FUNC_CFG 0x17UL 125 #define HWRM_FUNC_QSTATS 0x18UL 126 #define HWRM_FUNC_CLR_STATS 0x19UL 127 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 128 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 129 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 130 #define HWRM_FUNC_DRV_RGTR 0x1dUL 131 #define HWRM_FUNC_DRV_QVER 0x1eUL 132 #define HWRM_FUNC_BUF_RGTR 0x1fUL 133 #define HWRM_PORT_PHY_CFG 0x20UL 134 #define HWRM_PORT_MAC_CFG 0x21UL 135 #define HWRM_PORT_TS_QUERY 0x22UL 136 #define HWRM_PORT_QSTATS 0x23UL 137 #define HWRM_PORT_LPBK_QSTATS 0x24UL 138 #define HWRM_PORT_CLR_STATS 0x25UL 139 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 140 #define HWRM_PORT_PHY_QCFG 0x27UL 141 #define HWRM_PORT_MAC_QCFG 0x28UL 142 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 143 #define HWRM_PORT_PHY_QCAPS 0x2aUL 144 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 145 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 146 #define HWRM_PORT_LED_CFG 0x2dUL 147 #define HWRM_PORT_LED_QCFG 0x2eUL 148 #define HWRM_PORT_LED_QCAPS 0x2fUL 149 #define HWRM_QUEUE_QPORTCFG 0x30UL 150 #define HWRM_QUEUE_QCFG 0x31UL 151 #define HWRM_QUEUE_CFG 0x32UL 152 #define HWRM_FUNC_VLAN_CFG 0x33UL 153 #define HWRM_FUNC_VLAN_QCFG 0x34UL 154 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 155 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 156 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 157 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 158 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 159 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 160 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 161 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 162 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 163 #define HWRM_VNIC_ALLOC 0x40UL 164 #define HWRM_VNIC_FREE 0x41UL 165 #define HWRM_VNIC_CFG 0x42UL 166 #define HWRM_VNIC_QCFG 0x43UL 167 #define HWRM_VNIC_TPA_CFG 0x44UL 168 #define HWRM_VNIC_TPA_QCFG 0x45UL 169 #define HWRM_VNIC_RSS_CFG 0x46UL 170 #define HWRM_VNIC_RSS_QCFG 0x47UL 171 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 172 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 173 #define HWRM_VNIC_QCAPS 0x4aUL 174 #define HWRM_VNIC_UPDATE 0x4bUL 175 #define HWRM_RING_ALLOC 0x50UL 176 #define HWRM_RING_FREE 0x51UL 177 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 178 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 179 #define HWRM_RING_AGGINT_QCAPS 0x54UL 180 #define HWRM_RING_SCHQ_ALLOC 0x55UL 181 #define HWRM_RING_SCHQ_CFG 0x56UL 182 #define HWRM_RING_SCHQ_FREE 0x57UL 183 #define HWRM_RING_RESET 0x5eUL 184 #define HWRM_RING_GRP_ALLOC 0x60UL 185 #define HWRM_RING_GRP_FREE 0x61UL 186 #define HWRM_RING_CFG 0x62UL 187 #define HWRM_RING_QCFG 0x63UL 188 #define HWRM_RESERVED5 0x64UL 189 #define HWRM_RESERVED6 0x65UL 190 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 191 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 192 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 193 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 194 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 195 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 196 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 197 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 198 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 199 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 200 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG 0x88UL 201 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG 0x89UL 202 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG 0x8aUL 203 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG 0x8bUL 204 #define HWRM_QUEUE_QCAPS 0x8cUL 205 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG 0x8dUL 206 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG 0x8eUL 207 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG 0x8fUL 208 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 209 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 210 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 211 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 212 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 213 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 214 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 215 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 216 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 217 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 218 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 219 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 220 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 221 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 222 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 223 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 224 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 225 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 226 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG 0xa3UL 227 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 228 #define HWRM_STAT_CTX_ALLOC 0xb0UL 229 #define HWRM_STAT_CTX_FREE 0xb1UL 230 #define HWRM_STAT_CTX_QUERY 0xb2UL 231 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 232 #define HWRM_PORT_QSTATS_EXT 0xb4UL 233 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 234 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 235 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 236 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 237 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 238 #define HWRM_RESERVED7 0xbaUL 239 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 240 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 241 #define HWRM_PORT_ECN_QSTATS 0xbdUL 242 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 243 #define HWRM_FW_LIVEPATCH 0xbfUL 244 #define HWRM_FW_RESET 0xc0UL 245 #define HWRM_FW_QSTATUS 0xc1UL 246 #define HWRM_FW_HEALTH_CHECK 0xc2UL 247 #define HWRM_FW_SYNC 0xc3UL 248 #define HWRM_FW_STATE_QCAPS 0xc4UL 249 #define HWRM_FW_STATE_QUIESCE 0xc5UL 250 #define HWRM_FW_STATE_BACKUP 0xc6UL 251 #define HWRM_FW_STATE_RESTORE 0xc7UL 252 #define HWRM_FW_SET_TIME 0xc8UL 253 #define HWRM_FW_GET_TIME 0xc9UL 254 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 255 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 256 #define HWRM_FW_IPC_MAILBOX 0xccUL 257 #define HWRM_FW_ECN_CFG 0xcdUL 258 #define HWRM_FW_ECN_QCFG 0xceUL 259 #define HWRM_FW_SECURE_CFG 0xcfUL 260 #define HWRM_EXEC_FWD_RESP 0xd0UL 261 #define HWRM_REJECT_FWD_RESP 0xd1UL 262 #define HWRM_FWD_RESP 0xd2UL 263 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 264 #define HWRM_OEM_CMD 0xd4UL 265 #define HWRM_PORT_PRBS_TEST 0xd5UL 266 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 267 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 268 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 269 #define HWRM_PORT_DSC_DUMP 0xd9UL 270 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 271 #define HWRM_PORT_EP_TX_CFG 0xdbUL 272 #define HWRM_PORT_CFG 0xdcUL 273 #define HWRM_PORT_QCFG 0xddUL 274 #define HWRM_PORT_MAC_QCAPS 0xdfUL 275 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 276 #define HWRM_REG_POWER_QUERY 0xe1UL 277 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 278 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 279 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 280 #define HWRM_WOL_FILTER_FREE 0xf1UL 281 #define HWRM_WOL_FILTER_QCFG 0xf2UL 282 #define HWRM_WOL_REASON_QCFG 0xf3UL 283 #define HWRM_CFA_METER_QCAPS 0xf4UL 284 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 285 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 286 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 287 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 288 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 289 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 290 #define HWRM_CFA_VFR_ALLOC 0xfdUL 291 #define HWRM_CFA_VFR_FREE 0xfeUL 292 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 293 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 294 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 295 #define HWRM_CFA_FLOW_ALLOC 0x103UL 296 #define HWRM_CFA_FLOW_FREE 0x104UL 297 #define HWRM_CFA_FLOW_FLUSH 0x105UL 298 #define HWRM_CFA_FLOW_STATS 0x106UL 299 #define HWRM_CFA_FLOW_INFO 0x107UL 300 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 301 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 302 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 303 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 304 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 305 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 306 #define HWRM_CFA_PAIR_FREE 0x10eUL 307 #define HWRM_CFA_PAIR_INFO 0x10fUL 308 #define HWRM_FW_IPC_MSG 0x110UL 309 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 310 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 311 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 312 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 313 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 314 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 315 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 316 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 317 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 318 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 319 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 320 #define HWRM_CFA_COUNTER_CFG 0x11cUL 321 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 322 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 323 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 324 #define HWRM_CFA_EEM_QCAPS 0x120UL 325 #define HWRM_CFA_EEM_CFG 0x121UL 326 #define HWRM_CFA_EEM_QCFG 0x122UL 327 #define HWRM_CFA_EEM_OP 0x123UL 328 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 329 #define HWRM_CFA_TFLIB 0x125UL 330 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 331 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 332 #define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL 333 #define HWRM_CFA_TLS_FILTER_FREE 0x129UL 334 #define HWRM_CFA_RELEASE_AFM_FUNC 0x12aUL 335 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 336 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 337 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 338 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 339 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 340 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 341 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 342 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 343 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 344 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 345 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 346 #define HWRM_ENGINE_QG_QUERY 0x13dUL 347 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 348 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 349 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 350 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 351 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 352 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 353 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 354 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 355 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 356 #define HWRM_ENGINE_SG_QUERY 0x147UL 357 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 358 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 359 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 360 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 361 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 362 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 363 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 364 #define HWRM_ENGINE_STATS_QUERY 0x157UL 365 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 366 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 367 #define HWRM_ENGINE_RQ_FREE 0x15fUL 368 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 369 #define HWRM_ENGINE_CQ_FREE 0x161UL 370 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 371 #define HWRM_ENGINE_NQ_FREE 0x163UL 372 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 373 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 374 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 375 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 376 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 377 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 378 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 379 #define HWRM_FUNC_VF_BW_CFG 0x195UL 380 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 381 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 382 #define HWRM_FUNC_QSTATS_EXT 0x198UL 383 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 384 #define HWRM_FUNC_SPD_CFG 0x19aUL 385 #define HWRM_FUNC_SPD_QCFG 0x19bUL 386 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 387 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 388 #define HWRM_FUNC_PTP_CFG 0x19eUL 389 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 390 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 391 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 392 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 393 #define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL 394 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL 395 #define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL 396 #define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL 397 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL 398 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL 399 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL 400 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL 401 #define HWRM_FUNC_SYNCE_CFG 0x1abUL 402 #define HWRM_FUNC_SYNCE_QCFG 0x1acUL 403 #define HWRM_FUNC_KEY_CTX_FREE 0x1adUL 404 #define HWRM_FUNC_LAG_MODE_CFG 0x1aeUL 405 #define HWRM_FUNC_LAG_MODE_QCFG 0x1afUL 406 #define HWRM_FUNC_LAG_CREATE 0x1b0UL 407 #define HWRM_FUNC_LAG_UPDATE 0x1b1UL 408 #define HWRM_FUNC_LAG_FREE 0x1b2UL 409 #define HWRM_FUNC_LAG_QCFG 0x1b3UL 410 #define HWRM_FUNC_TIMEDTX_PACING_RATE_ADD 0x1c2UL 411 #define HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE 0x1c3UL 412 #define HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY 0x1c4UL 413 #define HWRM_SELFTEST_QLIST 0x200UL 414 #define HWRM_SELFTEST_EXEC 0x201UL 415 #define HWRM_SELFTEST_IRQ 0x202UL 416 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 417 #define HWRM_PCIE_QSTATS 0x204UL 418 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 419 #define HWRM_MFG_TIMERS_QUERY 0x206UL 420 #define HWRM_MFG_OTP_CFG 0x207UL 421 #define HWRM_MFG_OTP_QCFG 0x208UL 422 #define HWRM_MFG_HDMA_TEST 0x209UL 423 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 424 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 425 #define HWRM_MFG_SOC_IMAGE 0x20cUL 426 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 427 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE 0x20eUL 428 #define HWRM_MFG_PARAM_CRITICAL_DATA_READ 0x20fUL 429 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH 0x210UL 430 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 431 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 432 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 433 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 434 #define HWRM_MFG_PSOC_QSTATUS 0x215UL 435 #define HWRM_MFG_SELFTEST_QLIST 0x216UL 436 #define HWRM_MFG_SELFTEST_EXEC 0x217UL 437 #define HWRM_STAT_GENERIC_QSTATS 0x218UL 438 #define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL 439 #define HWRM_STAT_DB_ERROR_QSTATS 0x21aUL 440 #define HWRM_MFG_TESTS 0x21bUL 441 #define HWRM_PORT_POE_CFG 0x230UL 442 #define HWRM_PORT_POE_QCFG 0x231UL 443 #define HWRM_UDCC_QCAPS 0x258UL 444 #define HWRM_UDCC_CFG 0x259UL 445 #define HWRM_UDCC_QCFG 0x25aUL 446 #define HWRM_UDCC_SESSION_CFG 0x25bUL 447 #define HWRM_UDCC_SESSION_QCFG 0x25cUL 448 #define HWRM_UDCC_SESSION_QUERY 0x25dUL 449 #define HWRM_UDCC_COMP_CFG 0x25eUL 450 #define HWRM_UDCC_COMP_QCFG 0x25fUL 451 #define HWRM_UDCC_COMP_QUERY 0x260UL 452 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS 0x261UL 453 #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG 0x262UL 454 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG 0x263UL 455 #define HWRM_TF 0x2bcUL 456 #define HWRM_TF_VERSION_GET 0x2bdUL 457 #define HWRM_TF_SESSION_OPEN 0x2c6UL 458 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 459 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 460 #define HWRM_TF_SESSION_CLOSE 0x2caUL 461 #define HWRM_TF_SESSION_QCFG 0x2cbUL 462 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 463 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 464 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 465 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 466 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 467 #define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL 468 #define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL 469 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 470 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 471 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 472 #define HWRM_TF_EM_INSERT 0x2eaUL 473 #define HWRM_TF_EM_DELETE 0x2ebUL 474 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 475 #define HWRM_TF_EM_MOVE 0x2edUL 476 #define HWRM_TF_TCAM_SET 0x2f8UL 477 #define HWRM_TF_TCAM_GET 0x2f9UL 478 #define HWRM_TF_TCAM_MOVE 0x2faUL 479 #define HWRM_TF_TCAM_FREE 0x2fbUL 480 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 481 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 482 #define HWRM_TF_IF_TBL_SET 0x2feUL 483 #define HWRM_TF_IF_TBL_GET 0x2ffUL 484 #define HWRM_TF_RESC_USAGE_SET 0x300UL 485 #define HWRM_TF_RESC_USAGE_QUERY 0x301UL 486 #define HWRM_TF_TBL_TYPE_ALLOC 0x302UL 487 #define HWRM_TF_TBL_TYPE_FREE 0x303UL 488 #define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL 489 #define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL 490 #define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL 491 #define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL 492 #define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL 493 #define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL 494 #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL 495 #define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL 496 #define HWRM_TFC_SESSION_ID_ALLOC 0x388UL 497 #define HWRM_TFC_SESSION_FID_ADD 0x389UL 498 #define HWRM_TFC_SESSION_FID_REM 0x38aUL 499 #define HWRM_TFC_IDENT_ALLOC 0x38bUL 500 #define HWRM_TFC_IDENT_FREE 0x38cUL 501 #define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL 502 #define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL 503 #define HWRM_TFC_IDX_TBL_SET 0x38fUL 504 #define HWRM_TFC_IDX_TBL_GET 0x390UL 505 #define HWRM_TFC_IDX_TBL_FREE 0x391UL 506 #define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL 507 #define HWRM_TFC_TCAM_SET 0x393UL 508 #define HWRM_TFC_TCAM_GET 0x394UL 509 #define HWRM_TFC_TCAM_ALLOC 0x395UL 510 #define HWRM_TFC_TCAM_ALLOC_SET 0x396UL 511 #define HWRM_TFC_TCAM_FREE 0x397UL 512 #define HWRM_TFC_IF_TBL_SET 0x398UL 513 #define HWRM_TFC_IF_TBL_GET 0x399UL 514 #define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL 515 #define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL 516 #define HWRM_TFC_GLOBAL_ID_FREE 0x39cUL 517 #define HWRM_SV 0x400UL 518 #define HWRM_DBG_SERDES_TEST 0xff0eUL 519 #define HWRM_DBG_LOG_BUFFER_FLUSH 0xff0fUL 520 #define HWRM_DBG_READ_DIRECT 0xff10UL 521 #define HWRM_DBG_READ_INDIRECT 0xff11UL 522 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 523 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 524 #define HWRM_DBG_DUMP 0xff14UL 525 #define HWRM_DBG_ERASE_NVM 0xff15UL 526 #define HWRM_DBG_CFG 0xff16UL 527 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 528 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 529 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 530 #define HWRM_DBG_FW_CLI 0xff1aUL 531 #define HWRM_DBG_I2C_CMD 0xff1bUL 532 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 533 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 534 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 535 #define HWRM_DBG_DRV_TRACE 0xff1fUL 536 #define HWRM_DBG_QCAPS 0xff20UL 537 #define HWRM_DBG_QCFG 0xff21UL 538 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 539 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 540 #define HWRM_DBG_USEQ_FREE 0xff24UL 541 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 542 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 543 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 544 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 545 #define HWRM_DBG_USEQ_RUN 0xff29UL 546 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 547 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 548 #define HWRM_DBG_COREDUMP_CAPTURE 0xff2cUL 549 #define HWRM_DBG_PTRACE 0xff2dUL 550 #define HWRM_DBG_SIM_CABLE_STATE 0xff2eUL 551 #define HWRM_NVM_GET_VPD_FIELD_INFO 0xffeaUL 552 #define HWRM_NVM_SET_VPD_FIELD_INFO 0xffebUL 553 #define HWRM_NVM_DEFRAG 0xffecUL 554 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 555 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 556 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 557 #define HWRM_NVM_FLUSH 0xfff0UL 558 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 559 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 560 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 561 #define HWRM_NVM_MODIFY 0xfff4UL 562 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 563 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 564 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 565 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 566 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 567 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 568 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 569 #define HWRM_NVM_RAW_DUMP 0xfffcUL 570 #define HWRM_NVM_READ 0xfffdUL 571 #define HWRM_NVM_WRITE 0xfffeUL 572 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 573 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 574 __le16 unused_0[3]; 575 }; 576 577 /* ret_codes (size:64b/8B) */ 578 struct ret_codes { 579 __le16 error_code; 580 #define HWRM_ERR_CODE_SUCCESS 0x0UL 581 #define HWRM_ERR_CODE_FAIL 0x1UL 582 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 583 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 584 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 585 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 586 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 587 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 588 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 589 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 590 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 591 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 592 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 593 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 594 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 595 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 596 #define HWRM_ERR_CODE_BUSY 0x10UL 597 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 598 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 599 #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT 0x13UL 600 #define HWRM_ERR_CODE_SECURE_SOC_ERROR 0x14UL 601 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 602 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 603 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 604 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 605 __le16 unused_0[3]; 606 }; 607 608 /* hwrm_err_output (size:128b/16B) */ 609 struct hwrm_err_output { 610 __le16 error_code; 611 __le16 req_type; 612 __le16 seq_id; 613 __le16 resp_len; 614 __le32 opaque_0; 615 __le16 opaque_1; 616 u8 cmd_err; 617 u8 valid; 618 }; 619 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 620 #define HWRM_MAX_REQ_LEN 128 621 #define HWRM_MAX_RESP_LEN 704 622 #define HW_HASH_INDEX_SIZE 0x80 623 #define HW_HASH_KEY_SIZE 40 624 #define HWRM_RESP_VALID_KEY 1 625 #define HWRM_TARGET_ID_BONO 0xFFF8 626 #define HWRM_TARGET_ID_KONG 0xFFF9 627 #define HWRM_TARGET_ID_APE 0xFFFA 628 #define HWRM_TARGET_ID_TOOLS 0xFFFD 629 #define HWRM_VERSION_MAJOR 1 630 #define HWRM_VERSION_MINOR 10 631 #define HWRM_VERSION_UPDATE 3 632 #define HWRM_VERSION_RSVD 85 633 #define HWRM_VERSION_STR "1.10.3.85" 634 635 /* hwrm_ver_get_input (size:192b/24B) */ 636 struct hwrm_ver_get_input { 637 __le16 req_type; 638 __le16 cmpl_ring; 639 __le16 seq_id; 640 __le16 target_id; 641 __le64 resp_addr; 642 u8 hwrm_intf_maj; 643 u8 hwrm_intf_min; 644 u8 hwrm_intf_upd; 645 u8 unused_0[5]; 646 }; 647 648 /* hwrm_ver_get_output (size:1408b/176B) */ 649 struct hwrm_ver_get_output { 650 __le16 error_code; 651 __le16 req_type; 652 __le16 seq_id; 653 __le16 resp_len; 654 u8 hwrm_intf_maj_8b; 655 u8 hwrm_intf_min_8b; 656 u8 hwrm_intf_upd_8b; 657 u8 hwrm_intf_rsvd_8b; 658 u8 hwrm_fw_maj_8b; 659 u8 hwrm_fw_min_8b; 660 u8 hwrm_fw_bld_8b; 661 u8 hwrm_fw_rsvd_8b; 662 u8 mgmt_fw_maj_8b; 663 u8 mgmt_fw_min_8b; 664 u8 mgmt_fw_bld_8b; 665 u8 mgmt_fw_rsvd_8b; 666 u8 netctrl_fw_maj_8b; 667 u8 netctrl_fw_min_8b; 668 u8 netctrl_fw_bld_8b; 669 u8 netctrl_fw_rsvd_8b; 670 __le32 dev_caps_cfg; 671 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 672 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 673 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 674 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 675 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 676 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 677 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 678 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 679 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 680 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 681 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 682 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 683 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 684 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 685 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 686 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 687 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_SOC_CAPABLE 0x10000UL 688 u8 roce_fw_maj_8b; 689 u8 roce_fw_min_8b; 690 u8 roce_fw_bld_8b; 691 u8 roce_fw_rsvd_8b; 692 char hwrm_fw_name[16]; 693 char mgmt_fw_name[16]; 694 char netctrl_fw_name[16]; 695 char active_pkg_name[16]; 696 char roce_fw_name[16]; 697 __le16 chip_num; 698 u8 chip_rev; 699 u8 chip_metal; 700 u8 chip_bond_id; 701 u8 chip_platform_type; 702 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 703 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 704 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 705 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 706 __le16 max_req_win_len; 707 __le16 max_resp_len; 708 __le16 def_req_timeout; 709 u8 flags; 710 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 711 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 712 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 713 u8 unused_0[2]; 714 u8 always_1; 715 __le16 hwrm_intf_major; 716 __le16 hwrm_intf_minor; 717 __le16 hwrm_intf_build; 718 __le16 hwrm_intf_patch; 719 __le16 hwrm_fw_major; 720 __le16 hwrm_fw_minor; 721 __le16 hwrm_fw_build; 722 __le16 hwrm_fw_patch; 723 __le16 mgmt_fw_major; 724 __le16 mgmt_fw_minor; 725 __le16 mgmt_fw_build; 726 __le16 mgmt_fw_patch; 727 __le16 netctrl_fw_major; 728 __le16 netctrl_fw_minor; 729 __le16 netctrl_fw_build; 730 __le16 netctrl_fw_patch; 731 __le16 roce_fw_major; 732 __le16 roce_fw_minor; 733 __le16 roce_fw_build; 734 __le16 roce_fw_patch; 735 __le16 max_ext_req_len; 736 __le16 max_req_timeout; 737 u8 unused_1[3]; 738 u8 valid; 739 }; 740 741 /* eject_cmpl (size:128b/16B) */ 742 struct eject_cmpl { 743 __le16 type; 744 #define EJECT_CMPL_TYPE_MASK 0x3fUL 745 #define EJECT_CMPL_TYPE_SFT 0 746 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 747 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 748 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 749 #define EJECT_CMPL_FLAGS_SFT 6 750 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 751 __le16 len; 752 __le32 opaque; 753 __le16 v; 754 #define EJECT_CMPL_V 0x1UL 755 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 756 #define EJECT_CMPL_ERRORS_SFT 1 757 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 758 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 759 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 760 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 761 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 762 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 763 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 764 __le16 reserved16; 765 __le32 unused_2; 766 }; 767 768 /* hwrm_cmpl (size:128b/16B) */ 769 struct hwrm_cmpl { 770 __le16 type; 771 #define CMPL_TYPE_MASK 0x3fUL 772 #define CMPL_TYPE_SFT 0 773 #define CMPL_TYPE_HWRM_DONE 0x20UL 774 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 775 __le16 sequence_id; 776 __le32 unused_1; 777 __le32 v; 778 #define CMPL_V 0x1UL 779 __le32 unused_3; 780 }; 781 782 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 783 struct hwrm_fwd_req_cmpl { 784 __le16 req_len_type; 785 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 786 #define FWD_REQ_CMPL_TYPE_SFT 0 787 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 788 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 789 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 790 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 791 __le16 source_id; 792 __le32 unused0; 793 __le32 req_buf_addr_v[2]; 794 #define FWD_REQ_CMPL_V 0x1UL 795 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 796 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 797 }; 798 799 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 800 struct hwrm_fwd_resp_cmpl { 801 __le16 type; 802 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 803 #define FWD_RESP_CMPL_TYPE_SFT 0 804 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 805 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 806 __le16 source_id; 807 __le16 resp_len; 808 __le16 unused_1; 809 __le32 resp_buf_addr_v[2]; 810 #define FWD_RESP_CMPL_V 0x1UL 811 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 812 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 813 }; 814 815 /* hwrm_async_event_cmpl (size:128b/16B) */ 816 struct hwrm_async_event_cmpl { 817 __le16 type; 818 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 819 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 820 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 821 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 822 __le16 event_id; 823 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 824 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 825 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 826 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 827 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 828 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 829 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 830 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 831 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 832 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 833 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 834 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 835 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 836 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 837 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 838 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 839 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 840 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 841 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 842 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 843 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 844 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 845 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 846 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 847 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 848 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 849 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 850 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 851 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 852 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 853 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 854 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 855 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 856 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 857 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 858 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL 859 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 860 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 861 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL 862 #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL 863 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL 864 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL 865 #define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR 0x4aUL 866 #define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE 0x4bUL 867 #define ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL 868 #define ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE 0x4dUL 869 #define ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE 0x4eUL 870 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE 0x4fUL 871 #define ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP 0x50UL 872 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x51UL 873 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 874 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 875 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 876 __le32 event_data2; 877 u8 opaque_v; 878 #define ASYNC_EVENT_CMPL_V 0x1UL 879 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 880 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 881 u8 timestamp_lo; 882 __le16 timestamp_hi; 883 __le32 event_data1; 884 }; 885 886 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 887 struct hwrm_async_event_cmpl_link_status_change { 888 __le16 type; 889 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 890 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 891 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 892 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 893 __le16 event_id; 894 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 895 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 896 __le32 event_data2; 897 u8 opaque_v; 898 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 899 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 900 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 901 u8 timestamp_lo; 902 __le16 timestamp_hi; 903 __le32 event_data1; 904 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 905 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 906 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 907 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 908 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 909 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 910 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 911 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 912 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 913 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 914 }; 915 916 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 917 struct hwrm_async_event_cmpl_port_conn_not_allowed { 918 __le16 type; 919 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 920 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 921 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 922 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 923 __le16 event_id; 924 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 925 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 926 __le32 event_data2; 927 u8 opaque_v; 928 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 929 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 930 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 931 u8 timestamp_lo; 932 __le16 timestamp_hi; 933 __le32 event_data1; 934 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 935 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 936 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 937 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 938 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 939 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 940 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 941 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 942 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 943 }; 944 945 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 946 struct hwrm_async_event_cmpl_link_speed_cfg_change { 947 __le16 type; 948 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 949 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 950 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 951 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 952 __le16 event_id; 953 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 954 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 955 __le32 event_data2; 956 u8 opaque_v; 957 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 958 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 959 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 960 u8 timestamp_lo; 961 __le16 timestamp_hi; 962 __le32 event_data1; 963 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 964 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 965 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 966 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 967 }; 968 969 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 970 struct hwrm_async_event_cmpl_reset_notify { 971 __le16 type; 972 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 973 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 974 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 975 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 976 __le16 event_id; 977 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 978 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 979 __le32 event_data2; 980 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 981 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 982 u8 opaque_v; 983 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 984 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 985 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 986 u8 timestamp_lo; 987 __le16 timestamp_hi; 988 __le32 event_data1; 989 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 990 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 991 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 992 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 993 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 994 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 995 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 996 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 997 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 998 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 999 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 1000 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 1001 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 1002 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 1003 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 1004 }; 1005 1006 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 1007 struct hwrm_async_event_cmpl_error_recovery { 1008 __le16 type; 1009 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 1010 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 1011 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1012 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 1013 __le16 event_id; 1014 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 1015 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 1016 __le32 event_data2; 1017 u8 opaque_v; 1018 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 1019 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 1020 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 1021 u8 timestamp_lo; 1022 __le16 timestamp_hi; 1023 __le32 event_data1; 1024 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 1025 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 1026 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 1027 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 1028 }; 1029 1030 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 1031 struct hwrm_async_event_cmpl_ring_monitor_msg { 1032 __le16 type; 1033 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 1034 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 1035 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1036 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 1037 __le16 event_id; 1038 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 1039 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 1040 __le32 event_data2; 1041 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 1042 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 1043 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 1044 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 1045 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 1046 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 1047 u8 opaque_v; 1048 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 1049 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 1050 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 1051 u8 timestamp_lo; 1052 __le16 timestamp_hi; 1053 __le32 event_data1; 1054 }; 1055 1056 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 1057 struct hwrm_async_event_cmpl_vf_cfg_change { 1058 __le16 type; 1059 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 1060 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 1061 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1062 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 1063 __le16 event_id; 1064 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 1065 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 1066 __le32 event_data2; 1067 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 1068 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 1069 u8 opaque_v; 1070 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 1071 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 1072 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 1073 u8 timestamp_lo; 1074 __le16 timestamp_hi; 1075 __le32 event_data1; 1076 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 1077 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 1078 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 1079 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 1080 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 1081 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE 0x20UL 1082 }; 1083 1084 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 1085 struct hwrm_async_event_cmpl_default_vnic_change { 1086 __le16 type; 1087 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 1088 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 1089 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1090 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 1091 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 1092 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 1093 __le16 event_id; 1094 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 1095 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 1096 __le32 event_data2; 1097 u8 opaque_v; 1098 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 1099 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 1100 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 1101 u8 timestamp_lo; 1102 __le16 timestamp_hi; 1103 __le32 event_data1; 1104 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 1105 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 1106 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 1107 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 1108 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 1109 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 1110 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 1111 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 1112 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1113 }; 1114 1115 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1116 struct hwrm_async_event_cmpl_hw_flow_aged { 1117 __le16 type; 1118 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1119 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1120 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1121 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1122 __le16 event_id; 1123 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1124 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1125 __le32 event_data2; 1126 u8 opaque_v; 1127 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1128 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1129 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1130 u8 timestamp_lo; 1131 __le16 timestamp_hi; 1132 __le32 event_data1; 1133 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1134 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1135 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1136 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1137 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1138 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1139 }; 1140 1141 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1142 struct hwrm_async_event_cmpl_eem_cache_flush_req { 1143 __le16 type; 1144 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1145 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1146 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1147 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1148 __le16 event_id; 1149 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1150 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1151 __le32 event_data2; 1152 u8 opaque_v; 1153 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1154 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1155 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1156 u8 timestamp_lo; 1157 __le16 timestamp_hi; 1158 __le32 event_data1; 1159 }; 1160 1161 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1162 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1163 __le16 type; 1164 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1165 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1166 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1167 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1168 __le16 event_id; 1169 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1170 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1171 __le32 event_data2; 1172 u8 opaque_v; 1173 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1174 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1175 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1176 u8 timestamp_lo; 1177 __le16 timestamp_hi; 1178 __le32 event_data1; 1179 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1180 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1181 }; 1182 1183 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1184 struct hwrm_async_event_cmpl_deferred_response { 1185 __le16 type; 1186 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1187 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1188 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1189 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1190 __le16 event_id; 1191 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1192 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1193 __le32 event_data2; 1194 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1195 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1196 u8 opaque_v; 1197 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1198 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1199 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1200 u8 timestamp_lo; 1201 __le16 timestamp_hi; 1202 __le32 event_data1; 1203 }; 1204 1205 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1206 struct hwrm_async_event_cmpl_echo_request { 1207 __le16 type; 1208 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1209 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1210 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1211 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1212 __le16 event_id; 1213 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1214 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1215 __le32 event_data2; 1216 u8 opaque_v; 1217 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1218 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1219 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1220 u8 timestamp_lo; 1221 __le16 timestamp_hi; 1222 __le32 event_data1; 1223 }; 1224 1225 /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ 1226 struct hwrm_async_event_cmpl_phc_update { 1227 __le16 type; 1228 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL 1229 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 1230 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1231 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 1232 __le16 event_id; 1233 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL 1234 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 1235 __le32 event_data2; 1236 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1237 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1238 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1239 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16 1240 u8 opaque_v; 1241 #define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL 1242 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL 1243 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 1244 u8 timestamp_lo; 1245 __le16 timestamp_hi; 1246 __le32 event_data1; 1247 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL 1248 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0 1249 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1250 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1251 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1252 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL 1253 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 1254 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL 1255 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4 1256 }; 1257 1258 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1259 struct hwrm_async_event_cmpl_pps_timestamp { 1260 __le16 type; 1261 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1262 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1263 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1264 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1265 __le16 event_id; 1266 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1267 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1268 __le32 event_data2; 1269 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1270 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1271 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1272 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1273 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1274 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1275 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1276 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1277 u8 opaque_v; 1278 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1279 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1280 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1281 u8 timestamp_lo; 1282 __le16 timestamp_hi; 1283 __le32 event_data1; 1284 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1285 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1286 }; 1287 1288 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1289 struct hwrm_async_event_cmpl_error_report { 1290 __le16 type; 1291 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1292 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1293 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1294 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1295 __le16 event_id; 1296 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1297 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1298 __le32 event_data2; 1299 u8 opaque_v; 1300 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1301 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1302 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1303 u8 timestamp_lo; 1304 __le16 timestamp_hi; 1305 __le32 event_data1; 1306 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1307 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1308 }; 1309 1310 /* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */ 1311 struct hwrm_async_event_cmpl_dbg_buf_producer { 1312 __le16 type; 1313 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK 0x3fUL 1314 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT 0 1315 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1316 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT 1317 __le16 event_id; 1318 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL 1319 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER 1320 __le32 event_data2; 1321 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_MASK 0xffffffffUL 1322 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_SFT 0 1323 u8 opaque_v; 1324 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V 0x1UL 1325 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK 0xfeUL 1326 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_SFT 1 1327 u8 timestamp_lo; 1328 __le16 timestamp_hi; 1329 __le32 event_data1; 1330 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK 0xffffUL 1331 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT 0 1332 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE 0x0UL 1333 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE 0x1UL 1334 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE 0x2UL 1335 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE 0x3UL 1336 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE 0x4UL 1337 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE 0x5UL 1338 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE 0x6UL 1339 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE 0x7UL 1340 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE 0x8UL 1341 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE 0x9UL 1342 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE 0xaUL 1343 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE 0xbUL 1344 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE 1345 }; 1346 1347 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1348 struct hwrm_async_event_cmpl_hwrm_error { 1349 __le16 type; 1350 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1351 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1352 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1353 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1354 __le16 event_id; 1355 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1356 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1357 __le32 event_data2; 1358 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1359 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1360 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1361 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1362 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1363 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1364 u8 opaque_v; 1365 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1366 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1367 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1368 u8 timestamp_lo; 1369 __le16 timestamp_hi; 1370 __le32 event_data1; 1371 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1372 }; 1373 1374 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1375 struct hwrm_async_event_cmpl_error_report_base { 1376 __le16 type; 1377 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1378 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1379 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1380 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1381 __le16 event_id; 1382 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1383 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1384 __le32 event_data2; 1385 u8 opaque_v; 1386 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1387 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1388 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1389 u8 timestamp_lo; 1390 __le16 timestamp_hi; 1391 __le32 event_data1; 1392 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1393 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1394 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1395 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1396 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1397 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1398 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1399 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1400 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1401 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1402 }; 1403 1404 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1405 struct hwrm_async_event_cmpl_error_report_pause_storm { 1406 __le16 type; 1407 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1408 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1409 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1410 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1411 __le16 event_id; 1412 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1413 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1414 __le32 event_data2; 1415 u8 opaque_v; 1416 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1417 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1418 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1419 u8 timestamp_lo; 1420 __le16 timestamp_hi; 1421 __le32 event_data1; 1422 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1423 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1424 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1425 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1426 }; 1427 1428 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1429 struct hwrm_async_event_cmpl_error_report_invalid_signal { 1430 __le16 type; 1431 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1432 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1433 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1434 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1435 __le16 event_id; 1436 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1437 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1438 __le32 event_data2; 1439 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1440 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1441 u8 opaque_v; 1442 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1443 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1444 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1445 u8 timestamp_lo; 1446 __le16 timestamp_hi; 1447 __le32 event_data1; 1448 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1449 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1450 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1451 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1452 }; 1453 1454 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1455 struct hwrm_async_event_cmpl_error_report_nvm { 1456 __le16 type; 1457 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1458 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1459 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1460 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1461 __le16 event_id; 1462 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1463 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1464 __le32 event_data2; 1465 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1466 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1467 u8 opaque_v; 1468 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1469 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1470 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1471 u8 timestamp_lo; 1472 __le16 timestamp_hi; 1473 __le32 event_data1; 1474 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1475 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1476 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1477 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1478 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1479 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1480 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1481 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1482 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1483 }; 1484 1485 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ 1486 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { 1487 __le16 type; 1488 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL 1489 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0 1490 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1491 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 1492 __le16 event_id; 1493 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL 1494 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 1495 __le32 event_data2; 1496 u8 opaque_v; 1497 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL 1498 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL 1499 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1 1500 u8 timestamp_lo; 1501 __le16 timestamp_hi; 1502 __le32 event_data1; 1503 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1504 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0 1505 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1506 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1507 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL 1508 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8 1509 }; 1510 1511 /* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ 1512 struct hwrm_async_event_cmpl_error_report_thermal { 1513 __le16 type; 1514 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK 0x3fUL 1515 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT 0 1516 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1517 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 1518 __le16 event_id; 1519 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 0x45UL 1520 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 1521 __le32 event_data2; 1522 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK 0xffUL 1523 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0 1524 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK 0xff00UL 1525 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT 8 1526 u8 opaque_v; 1527 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V 0x1UL 1528 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK 0xfeUL 1529 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1 1530 u8 timestamp_lo; 1531 __le16 timestamp_hi; 1532 __le32 event_data1; 1533 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1534 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1535 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 0x5UL 1536 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 1537 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK 0x700UL 1538 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT 8 1539 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN (0x0UL << 8) 1540 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL (0x1UL << 8) 1541 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL (0x2UL << 8) 1542 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN (0x3UL << 8) 1543 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN 1544 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR 0x800UL 1545 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (0x0UL << 11) 1546 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (0x1UL << 11) 1547 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING 1548 }; 1549 1550 /* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */ 1551 struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { 1552 __le16 type; 1553 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK 0x3fUL 1554 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT 0 1555 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1556 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 1557 __le16 event_id; 1558 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 0x45UL 1559 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 1560 __le32 event_data2; 1561 u8 opaque_v; 1562 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V 0x1UL 1563 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK 0xfeUL 1564 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT 1 1565 u8 timestamp_lo; 1566 __le16 timestamp_hi; 1567 __le32 event_data1; 1568 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1569 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT 0 1570 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1571 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1572 }; 1573 1574 /* hwrm_func_reset_input (size:192b/24B) */ 1575 struct hwrm_func_reset_input { 1576 __le16 req_type; 1577 __le16 cmpl_ring; 1578 __le16 seq_id; 1579 __le16 target_id; 1580 __le64 resp_addr; 1581 __le32 enables; 1582 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1583 __le16 vf_id; 1584 u8 func_reset_level; 1585 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1586 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1587 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1588 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1589 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1590 u8 unused_0; 1591 }; 1592 1593 /* hwrm_func_reset_output (size:128b/16B) */ 1594 struct hwrm_func_reset_output { 1595 __le16 error_code; 1596 __le16 req_type; 1597 __le16 seq_id; 1598 __le16 resp_len; 1599 u8 unused_0[7]; 1600 u8 valid; 1601 }; 1602 1603 /* hwrm_func_getfid_input (size:192b/24B) */ 1604 struct hwrm_func_getfid_input { 1605 __le16 req_type; 1606 __le16 cmpl_ring; 1607 __le16 seq_id; 1608 __le16 target_id; 1609 __le64 resp_addr; 1610 __le32 enables; 1611 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1612 __le16 pci_id; 1613 u8 unused_0[2]; 1614 }; 1615 1616 /* hwrm_func_getfid_output (size:128b/16B) */ 1617 struct hwrm_func_getfid_output { 1618 __le16 error_code; 1619 __le16 req_type; 1620 __le16 seq_id; 1621 __le16 resp_len; 1622 __le16 fid; 1623 u8 unused_0[5]; 1624 u8 valid; 1625 }; 1626 1627 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1628 struct hwrm_func_vf_alloc_input { 1629 __le16 req_type; 1630 __le16 cmpl_ring; 1631 __le16 seq_id; 1632 __le16 target_id; 1633 __le64 resp_addr; 1634 __le32 enables; 1635 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1636 __le16 first_vf_id; 1637 __le16 num_vfs; 1638 }; 1639 1640 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1641 struct hwrm_func_vf_alloc_output { 1642 __le16 error_code; 1643 __le16 req_type; 1644 __le16 seq_id; 1645 __le16 resp_len; 1646 __le16 first_vf_id; 1647 u8 unused_0[5]; 1648 u8 valid; 1649 }; 1650 1651 /* hwrm_func_vf_free_input (size:192b/24B) */ 1652 struct hwrm_func_vf_free_input { 1653 __le16 req_type; 1654 __le16 cmpl_ring; 1655 __le16 seq_id; 1656 __le16 target_id; 1657 __le64 resp_addr; 1658 __le32 enables; 1659 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1660 __le16 first_vf_id; 1661 __le16 num_vfs; 1662 }; 1663 1664 /* hwrm_func_vf_free_output (size:128b/16B) */ 1665 struct hwrm_func_vf_free_output { 1666 __le16 error_code; 1667 __le16 req_type; 1668 __le16 seq_id; 1669 __le16 resp_len; 1670 u8 unused_0[7]; 1671 u8 valid; 1672 }; 1673 1674 /* hwrm_func_vf_cfg_input (size:576b/72B) */ 1675 struct hwrm_func_vf_cfg_input { 1676 __le16 req_type; 1677 __le16 cmpl_ring; 1678 __le16 seq_id; 1679 __le16 target_id; 1680 __le64 resp_addr; 1681 __le32 enables; 1682 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1683 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1684 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1685 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1686 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1687 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1688 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1689 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1690 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1691 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1692 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1693 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1694 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_TX_KEY_CTXS 0x1000UL 1695 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_RX_KEY_CTXS 0x2000UL 1696 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_TX_KEY_CTXS 0x4000UL 1697 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_RX_KEY_CTXS 0x8000UL 1698 __le16 mtu; 1699 __le16 guest_vlan; 1700 __le16 async_event_cr; 1701 u8 dflt_mac_addr[6]; 1702 __le32 flags; 1703 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1704 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1705 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1706 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1707 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1708 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1709 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1710 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1711 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1712 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1713 __le16 num_rsscos_ctxs; 1714 __le16 num_cmpl_rings; 1715 __le16 num_tx_rings; 1716 __le16 num_rx_rings; 1717 __le16 num_l2_ctxs; 1718 __le16 num_vnics; 1719 __le16 num_stat_ctxs; 1720 __le16 num_hw_ring_grps; 1721 __le32 num_ktls_tx_key_ctxs; 1722 __le32 num_ktls_rx_key_ctxs; 1723 __le16 num_msix; 1724 u8 unused[2]; 1725 __le32 num_quic_tx_key_ctxs; 1726 __le32 num_quic_rx_key_ctxs; 1727 }; 1728 1729 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1730 struct hwrm_func_vf_cfg_output { 1731 __le16 error_code; 1732 __le16 req_type; 1733 __le16 seq_id; 1734 __le16 resp_len; 1735 u8 unused_0[7]; 1736 u8 valid; 1737 }; 1738 1739 /* hwrm_func_qcaps_input (size:192b/24B) */ 1740 struct hwrm_func_qcaps_input { 1741 __le16 req_type; 1742 __le16 cmpl_ring; 1743 __le16 seq_id; 1744 __le16 target_id; 1745 __le64 resp_addr; 1746 __le16 fid; 1747 u8 unused_0[6]; 1748 }; 1749 1750 /* hwrm_func_qcaps_output (size:1152b/144B) */ 1751 struct hwrm_func_qcaps_output { 1752 __le16 error_code; 1753 __le16 req_type; 1754 __le16 seq_id; 1755 __le16 resp_len; 1756 __le16 fid; 1757 __le16 port_id; 1758 __le32 flags; 1759 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1760 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1761 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1762 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1763 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1764 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1765 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1766 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1767 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1768 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1769 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1770 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1771 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1772 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1773 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1774 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1775 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1776 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1777 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1778 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1779 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1780 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1781 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1782 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1783 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1784 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1785 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1786 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1787 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1788 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1789 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1790 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1791 u8 mac_address[6]; 1792 __le16 max_rsscos_ctx; 1793 __le16 max_cmpl_rings; 1794 __le16 max_tx_rings; 1795 __le16 max_rx_rings; 1796 __le16 max_l2_ctxs; 1797 __le16 max_vnics; 1798 __le16 first_vf_id; 1799 __le16 max_vfs; 1800 __le16 max_stat_ctx; 1801 __le32 max_encap_records; 1802 __le32 max_decap_records; 1803 __le32 max_tx_em_flows; 1804 __le32 max_tx_wm_flows; 1805 __le32 max_rx_em_flows; 1806 __le32 max_rx_wm_flows; 1807 __le32 max_mcast_filters; 1808 __le32 max_flow_id; 1809 __le32 max_hw_ring_grps; 1810 __le16 max_sp_tx_rings; 1811 __le16 max_msix_vfs; 1812 __le32 flags_ext; 1813 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1814 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1815 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1816 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1817 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1818 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1819 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1820 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1821 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1822 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1823 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1824 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1825 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1826 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1827 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1828 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1829 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1830 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1831 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1832 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1833 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1834 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1835 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1836 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1837 #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 1838 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 1839 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL 1840 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL 1841 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL 1842 #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL 1843 #define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL 1844 #define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL 1845 u8 max_schqs; 1846 u8 mpc_chnls_cap; 1847 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1848 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1849 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1850 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1851 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1852 __le16 max_key_ctxs_alloc; 1853 __le32 flags_ext2; 1854 #define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL 1855 #define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL 1856 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL 1857 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL 1858 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL 1859 #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL 1860 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL 1861 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL 1862 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL 1863 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL 1864 #define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED 0x400UL 1865 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED 0x800UL 1866 #define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED 0x1000UL 1867 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED 0x2000UL 1868 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED 0x4000UL 1869 #define FUNC_QCAPS_RESP_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED 0x8000UL 1870 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED 0x10000UL 1871 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED 0x20000UL 1872 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED 0x40000UL 1873 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED 0x80000UL 1874 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED 0x100000UL 1875 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDCC_SUPPORTED 0x200000UL 1876 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED 0x400000UL 1877 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED 0x800000UL 1878 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED 0x1000000UL 1879 #define FUNC_QCAPS_RESP_FLAGS_EXT2_LPBK_STATS_SUPPORTED 0x2000000UL 1880 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED 0x4000000UL 1881 #define FUNC_QCAPS_RESP_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED 0x8000000UL 1882 #define FUNC_QCAPS_RESP_FLAGS_EXT2_PEER_MMAP_SUPPORTED 0x10000000UL 1883 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_PACING_SUPPORTED 0x20000000UL 1884 #define FUNC_QCAPS_RESP_FLAGS_EXT2_VF_STAT_EJECTION_SUPPORTED 0x40000000UL 1885 #define FUNC_QCAPS_RESP_FLAGS_EXT2_HOST_COREDUMP_SUPPORTED 0x80000000UL 1886 __le16 tunnel_disable_flag; 1887 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1888 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL 1889 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL 1890 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL 1891 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL 1892 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL 1893 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL 1894 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL 1895 __le16 xid_partition_cap; 1896 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_TX_CK 0x1UL 1897 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_RX_CK 0x2UL 1898 u8 device_serial_number[8]; 1899 __le16 ctxs_per_partition; 1900 __le16 max_tso_segs; 1901 __le32 roce_vf_max_av; 1902 __le32 roce_vf_max_cq; 1903 __le32 roce_vf_max_mrw; 1904 __le32 roce_vf_max_qp; 1905 __le32 roce_vf_max_srq; 1906 __le32 roce_vf_max_gid; 1907 __le32 flags_ext3; 1908 #define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL 1909 #define FUNC_QCAPS_RESP_FLAGS_EXT3_REQUIRE_L2_FILTER 0x2UL 1910 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED 0x4UL 1911 __le16 max_roce_vfs; 1912 u8 unused_3[5]; 1913 u8 valid; 1914 }; 1915 1916 /* hwrm_func_qcfg_input (size:192b/24B) */ 1917 struct hwrm_func_qcfg_input { 1918 __le16 req_type; 1919 __le16 cmpl_ring; 1920 __le16 seq_id; 1921 __le16 target_id; 1922 __le64 resp_addr; 1923 __le16 fid; 1924 u8 unused_0[6]; 1925 }; 1926 1927 /* hwrm_func_qcfg_output (size:1280b/160B) */ 1928 struct hwrm_func_qcfg_output { 1929 __le16 error_code; 1930 __le16 req_type; 1931 __le16 seq_id; 1932 __le16 resp_len; 1933 __le16 fid; 1934 __le16 port_id; 1935 __le16 vlan; 1936 __le16 flags; 1937 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1938 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1939 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1940 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1941 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1942 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1943 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1944 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1945 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1946 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1947 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1948 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1949 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1950 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1951 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1952 #define FUNC_QCFG_RESP_FLAGS_ROCE_VNIC_ID_VALID 0x8000UL 1953 u8 mac_address[6]; 1954 __le16 pci_id; 1955 __le16 alloc_rsscos_ctx; 1956 __le16 alloc_cmpl_rings; 1957 __le16 alloc_tx_rings; 1958 __le16 alloc_rx_rings; 1959 __le16 alloc_l2_ctx; 1960 __le16 alloc_vnics; 1961 __le16 admin_mtu; 1962 __le16 mru; 1963 __le16 stat_ctx_id; 1964 u8 port_partition_type; 1965 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1966 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1967 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1968 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1969 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1970 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1971 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1972 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1973 u8 port_pf_cnt; 1974 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1975 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1976 __le16 dflt_vnic_id; 1977 __le16 max_mtu_configured; 1978 __le32 min_bw; 1979 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1980 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1981 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1982 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1983 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1984 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1985 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1986 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1987 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1988 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1989 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1990 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1991 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1992 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1993 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1994 __le32 max_bw; 1995 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1996 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1997 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1998 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1999 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 2000 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 2001 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2002 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 2003 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2004 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2005 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2006 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2007 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2008 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2009 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 2010 u8 evb_mode; 2011 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 2012 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 2013 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 2014 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 2015 u8 options; 2016 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 2017 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 2018 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 2019 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 2020 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 2021 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 2022 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 2023 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 2024 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 2025 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 2026 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 2027 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 2028 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 2029 __le16 alloc_vfs; 2030 __le32 alloc_mcast_filters; 2031 __le32 alloc_hw_ring_grps; 2032 __le16 alloc_sp_tx_rings; 2033 __le16 alloc_stat_ctx; 2034 __le16 alloc_msix; 2035 __le16 registered_vfs; 2036 __le16 l2_doorbell_bar_size_kb; 2037 u8 active_endpoints; 2038 u8 always_1; 2039 __le32 reset_addr_poll; 2040 __le16 legacy_l2_db_size_kb; 2041 __le16 svif_info; 2042 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 2043 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 2044 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 2045 u8 mpc_chnls; 2046 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 2047 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 2048 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 2049 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 2050 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 2051 u8 db_page_size; 2052 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL 2053 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL 2054 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL 2055 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL 2056 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL 2057 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL 2058 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL 2059 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL 2060 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL 2061 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL 2062 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL 2063 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 2064 __le16 roce_vnic_id; 2065 __le32 partition_min_bw; 2066 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2067 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 2068 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 2069 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2070 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2071 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 2072 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2073 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2074 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2075 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2076 __le32 partition_max_bw; 2077 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2078 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 2079 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 2080 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2081 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2082 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 2083 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2084 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2085 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2086 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2087 __le16 host_mtu; 2088 __le16 flags2; 2089 #define FUNC_QCFG_RESP_FLAGS2_SRIOV_DSCP_INSERT_ENABLED 0x1UL 2090 u8 unused_4[2]; 2091 u8 port_kdnet_mode; 2092 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL 2093 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL 2094 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 2095 u8 kdnet_pcie_function; 2096 __le16 port_kdnet_fid; 2097 u8 unused_5[2]; 2098 __le32 num_ktls_tx_key_ctxs; 2099 __le32 num_ktls_rx_key_ctxs; 2100 u8 lag_id; 2101 u8 parif; 2102 u8 fw_lag_id; 2103 u8 unused_6; 2104 __le32 num_quic_tx_key_ctxs; 2105 __le32 num_quic_rx_key_ctxs; 2106 __le32 roce_max_av_per_vf; 2107 __le32 roce_max_cq_per_vf; 2108 __le32 roce_max_mrw_per_vf; 2109 __le32 roce_max_qp_per_vf; 2110 __le32 roce_max_srq_per_vf; 2111 __le32 roce_max_gid_per_vf; 2112 __le16 xid_partition_cfg; 2113 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK 0x1UL 2114 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK 0x2UL 2115 u8 unused_7; 2116 u8 valid; 2117 }; 2118 2119 /* hwrm_func_cfg_input (size:1280b/160B) */ 2120 struct hwrm_func_cfg_input { 2121 __le16 req_type; 2122 __le16 cmpl_ring; 2123 __le16 seq_id; 2124 __le16 target_id; 2125 __le64 resp_addr; 2126 __le16 fid; 2127 __le16 num_msix; 2128 __le32 flags; 2129 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 2130 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 2131 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 2132 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 2133 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 2134 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 2135 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 2136 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 2137 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 2138 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 2139 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 2140 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 2141 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 2142 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 2143 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 2144 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 2145 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 2146 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 2147 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 2148 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 2149 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 2150 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 2151 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 2152 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 2153 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 2154 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 2155 __le32 enables; 2156 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 2157 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 2158 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 2159 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 2160 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 2161 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 2162 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 2163 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 2164 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 2165 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 2166 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 2167 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 2168 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 2169 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 2170 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 2171 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 2172 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 2173 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 2174 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 2175 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 2176 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 2177 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 2178 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 2179 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 2180 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 2181 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 2182 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 2183 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 2184 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 2185 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 2186 #define FUNC_CFG_REQ_ENABLES_KTLS_TX_KEY_CTXS 0x40000000UL 2187 #define FUNC_CFG_REQ_ENABLES_KTLS_RX_KEY_CTXS 0x80000000UL 2188 __le16 admin_mtu; 2189 __le16 mru; 2190 __le16 num_rsscos_ctxs; 2191 __le16 num_cmpl_rings; 2192 __le16 num_tx_rings; 2193 __le16 num_rx_rings; 2194 __le16 num_l2_ctxs; 2195 __le16 num_vnics; 2196 __le16 num_stat_ctxs; 2197 __le16 num_hw_ring_grps; 2198 u8 dflt_mac_addr[6]; 2199 __le16 dflt_vlan; 2200 __be32 dflt_ip_addr[4]; 2201 __le32 min_bw; 2202 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2203 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 2204 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 2205 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 2206 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 2207 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 2208 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2209 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 2210 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2211 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2212 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2213 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2214 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2215 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2216 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 2217 __le32 max_bw; 2218 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2219 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 2220 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 2221 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 2222 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 2223 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 2224 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2225 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 2226 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2227 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2228 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2229 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2230 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2231 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2232 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 2233 __le16 async_event_cr; 2234 u8 vlan_antispoof_mode; 2235 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 2236 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 2237 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 2238 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 2239 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 2240 u8 allowed_vlan_pris; 2241 u8 evb_mode; 2242 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 2243 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 2244 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 2245 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 2246 u8 options; 2247 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 2248 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 2249 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 2250 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 2251 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 2252 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 2253 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 2254 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 2255 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 2256 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 2257 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 2258 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 2259 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 2260 __le16 num_mcast_filters; 2261 __le16 schq_id; 2262 __le16 mpc_chnls; 2263 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 2264 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 2265 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 2266 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 2267 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 2268 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 2269 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 2270 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 2271 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 2272 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 2273 __le32 partition_min_bw; 2274 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2275 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 2276 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 2277 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2278 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2279 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 2280 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2281 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2282 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2283 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2284 __le32 partition_max_bw; 2285 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2286 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 2287 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 2288 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2289 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2290 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 2291 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2292 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2293 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2294 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2295 __be16 tpid; 2296 __le16 host_mtu; 2297 __le32 flags2; 2298 #define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST 0x1UL 2299 #define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST 0x2UL 2300 __le32 enables2; 2301 #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL 2302 #define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL 2303 #define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL 2304 #define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL 2305 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL 2306 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL 2307 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL 2308 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL 2309 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL 2310 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL 2311 #define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL 2312 #define FUNC_CFG_REQ_ENABLES2_PHYSICAL_SLOT_NUMBER 0x800UL 2313 u8 port_kdnet_mode; 2314 #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL 2315 #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL 2316 #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 2317 u8 db_page_size; 2318 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL 2319 #define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL 2320 #define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL 2321 #define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL 2322 #define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL 2323 #define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL 2324 #define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL 2325 #define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL 2326 #define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL 2327 #define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL 2328 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL 2329 #define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 2330 __le16 physical_slot_number; 2331 __le32 num_ktls_tx_key_ctxs; 2332 __le32 num_ktls_rx_key_ctxs; 2333 __le32 num_quic_tx_key_ctxs; 2334 __le32 num_quic_rx_key_ctxs; 2335 __le32 roce_max_av_per_vf; 2336 __le32 roce_max_cq_per_vf; 2337 __le32 roce_max_mrw_per_vf; 2338 __le32 roce_max_qp_per_vf; 2339 __le32 roce_max_srq_per_vf; 2340 __le32 roce_max_gid_per_vf; 2341 __le16 xid_partition_cfg; 2342 #define FUNC_CFG_REQ_XID_PARTITION_CFG_TX_CK 0x1UL 2343 #define FUNC_CFG_REQ_XID_PARTITION_CFG_RX_CK 0x2UL 2344 __le16 unused_2; 2345 }; 2346 2347 /* hwrm_func_cfg_output (size:128b/16B) */ 2348 struct hwrm_func_cfg_output { 2349 __le16 error_code; 2350 __le16 req_type; 2351 __le16 seq_id; 2352 __le16 resp_len; 2353 u8 unused_0[7]; 2354 u8 valid; 2355 }; 2356 2357 /* hwrm_func_cfg_cmd_err (size:64b/8B) */ 2358 struct hwrm_func_cfg_cmd_err { 2359 u8 code; 2360 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2361 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL 2362 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL 2363 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL 2364 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL 2365 #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 2366 u8 unused_0[7]; 2367 }; 2368 2369 /* hwrm_func_qstats_input (size:192b/24B) */ 2370 struct hwrm_func_qstats_input { 2371 __le16 req_type; 2372 __le16 cmpl_ring; 2373 __le16 seq_id; 2374 __le16 target_id; 2375 __le64 resp_addr; 2376 __le16 fid; 2377 u8 flags; 2378 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2379 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 2380 #define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL 2381 u8 unused_0[5]; 2382 }; 2383 2384 /* hwrm_func_qstats_output (size:1408b/176B) */ 2385 struct hwrm_func_qstats_output { 2386 __le16 error_code; 2387 __le16 req_type; 2388 __le16 seq_id; 2389 __le16 resp_len; 2390 __le64 tx_ucast_pkts; 2391 __le64 tx_mcast_pkts; 2392 __le64 tx_bcast_pkts; 2393 __le64 tx_discard_pkts; 2394 __le64 tx_drop_pkts; 2395 __le64 tx_ucast_bytes; 2396 __le64 tx_mcast_bytes; 2397 __le64 tx_bcast_bytes; 2398 __le64 rx_ucast_pkts; 2399 __le64 rx_mcast_pkts; 2400 __le64 rx_bcast_pkts; 2401 __le64 rx_discard_pkts; 2402 __le64 rx_drop_pkts; 2403 __le64 rx_ucast_bytes; 2404 __le64 rx_mcast_bytes; 2405 __le64 rx_bcast_bytes; 2406 __le64 rx_agg_pkts; 2407 __le64 rx_agg_bytes; 2408 __le64 rx_agg_events; 2409 __le64 rx_agg_aborts; 2410 u8 clear_seq; 2411 u8 unused_0[6]; 2412 u8 valid; 2413 }; 2414 2415 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2416 struct hwrm_func_qstats_ext_input { 2417 __le16 req_type; 2418 __le16 cmpl_ring; 2419 __le16 seq_id; 2420 __le16 target_id; 2421 __le64 resp_addr; 2422 __le16 fid; 2423 u8 flags; 2424 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2425 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2426 u8 unused_0[1]; 2427 __le32 enables; 2428 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2429 __le16 schq_id; 2430 __le16 traffic_class; 2431 u8 unused_1[4]; 2432 }; 2433 2434 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2435 struct hwrm_func_qstats_ext_output { 2436 __le16 error_code; 2437 __le16 req_type; 2438 __le16 seq_id; 2439 __le16 resp_len; 2440 __le64 rx_ucast_pkts; 2441 __le64 rx_mcast_pkts; 2442 __le64 rx_bcast_pkts; 2443 __le64 rx_discard_pkts; 2444 __le64 rx_error_pkts; 2445 __le64 rx_ucast_bytes; 2446 __le64 rx_mcast_bytes; 2447 __le64 rx_bcast_bytes; 2448 __le64 tx_ucast_pkts; 2449 __le64 tx_mcast_pkts; 2450 __le64 tx_bcast_pkts; 2451 __le64 tx_error_pkts; 2452 __le64 tx_discard_pkts; 2453 __le64 tx_ucast_bytes; 2454 __le64 tx_mcast_bytes; 2455 __le64 tx_bcast_bytes; 2456 __le64 rx_tpa_eligible_pkt; 2457 __le64 rx_tpa_eligible_bytes; 2458 __le64 rx_tpa_pkt; 2459 __le64 rx_tpa_bytes; 2460 __le64 rx_tpa_errors; 2461 __le64 rx_tpa_events; 2462 u8 unused_0[7]; 2463 u8 valid; 2464 }; 2465 2466 /* hwrm_func_clr_stats_input (size:192b/24B) */ 2467 struct hwrm_func_clr_stats_input { 2468 __le16 req_type; 2469 __le16 cmpl_ring; 2470 __le16 seq_id; 2471 __le16 target_id; 2472 __le64 resp_addr; 2473 __le16 fid; 2474 u8 unused_0[6]; 2475 }; 2476 2477 /* hwrm_func_clr_stats_output (size:128b/16B) */ 2478 struct hwrm_func_clr_stats_output { 2479 __le16 error_code; 2480 __le16 req_type; 2481 __le16 seq_id; 2482 __le16 resp_len; 2483 u8 unused_0[7]; 2484 u8 valid; 2485 }; 2486 2487 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2488 struct hwrm_func_vf_resc_free_input { 2489 __le16 req_type; 2490 __le16 cmpl_ring; 2491 __le16 seq_id; 2492 __le16 target_id; 2493 __le64 resp_addr; 2494 __le16 vf_id; 2495 u8 unused_0[6]; 2496 }; 2497 2498 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2499 struct hwrm_func_vf_resc_free_output { 2500 __le16 error_code; 2501 __le16 req_type; 2502 __le16 seq_id; 2503 __le16 resp_len; 2504 u8 unused_0[7]; 2505 u8 valid; 2506 }; 2507 2508 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2509 struct hwrm_func_drv_rgtr_input { 2510 __le16 req_type; 2511 __le16 cmpl_ring; 2512 __le16 seq_id; 2513 __le16 target_id; 2514 __le64 resp_addr; 2515 __le32 flags; 2516 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2517 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2518 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2519 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2520 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2521 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2522 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2523 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2524 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2525 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2526 #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL 2527 #define FUNC_DRV_RGTR_REQ_FLAGS_TF_INGRESS_NIC_FLOW_MODE 0x800UL 2528 #define FUNC_DRV_RGTR_REQ_FLAGS_TF_EGRESS_NIC_FLOW_MODE 0x1000UL 2529 __le32 enables; 2530 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2531 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2532 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2533 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2534 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2535 __le16 os_type; 2536 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2537 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2538 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2539 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2540 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2541 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2542 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2543 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2544 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2545 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2546 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2547 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2548 u8 ver_maj_8b; 2549 u8 ver_min_8b; 2550 u8 ver_upd_8b; 2551 u8 unused_0[3]; 2552 __le32 timestamp; 2553 u8 unused_1[4]; 2554 __le32 vf_req_fwd[8]; 2555 __le32 async_event_fwd[8]; 2556 __le16 ver_maj; 2557 __le16 ver_min; 2558 __le16 ver_upd; 2559 __le16 ver_patch; 2560 }; 2561 2562 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2563 struct hwrm_func_drv_rgtr_output { 2564 __le16 error_code; 2565 __le16 req_type; 2566 __le16 seq_id; 2567 __le16 resp_len; 2568 __le32 flags; 2569 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2570 u8 unused_0[3]; 2571 u8 valid; 2572 }; 2573 2574 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2575 struct hwrm_func_drv_unrgtr_input { 2576 __le16 req_type; 2577 __le16 cmpl_ring; 2578 __le16 seq_id; 2579 __le16 target_id; 2580 __le64 resp_addr; 2581 __le32 flags; 2582 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2583 u8 unused_0[4]; 2584 }; 2585 2586 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2587 struct hwrm_func_drv_unrgtr_output { 2588 __le16 error_code; 2589 __le16 req_type; 2590 __le16 seq_id; 2591 __le16 resp_len; 2592 u8 unused_0[7]; 2593 u8 valid; 2594 }; 2595 2596 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2597 struct hwrm_func_buf_rgtr_input { 2598 __le16 req_type; 2599 __le16 cmpl_ring; 2600 __le16 seq_id; 2601 __le16 target_id; 2602 __le64 resp_addr; 2603 __le32 enables; 2604 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2605 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2606 __le16 vf_id; 2607 __le16 req_buf_num_pages; 2608 __le16 req_buf_page_size; 2609 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2610 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2611 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2612 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2613 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2614 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2615 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2616 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2617 __le16 req_buf_len; 2618 __le16 resp_buf_len; 2619 u8 unused_0[2]; 2620 __le64 req_buf_page_addr0; 2621 __le64 req_buf_page_addr1; 2622 __le64 req_buf_page_addr2; 2623 __le64 req_buf_page_addr3; 2624 __le64 req_buf_page_addr4; 2625 __le64 req_buf_page_addr5; 2626 __le64 req_buf_page_addr6; 2627 __le64 req_buf_page_addr7; 2628 __le64 req_buf_page_addr8; 2629 __le64 req_buf_page_addr9; 2630 __le64 error_buf_addr; 2631 __le64 resp_buf_addr; 2632 }; 2633 2634 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2635 struct hwrm_func_buf_rgtr_output { 2636 __le16 error_code; 2637 __le16 req_type; 2638 __le16 seq_id; 2639 __le16 resp_len; 2640 u8 unused_0[7]; 2641 u8 valid; 2642 }; 2643 2644 /* hwrm_func_drv_qver_input (size:192b/24B) */ 2645 struct hwrm_func_drv_qver_input { 2646 __le16 req_type; 2647 __le16 cmpl_ring; 2648 __le16 seq_id; 2649 __le16 target_id; 2650 __le64 resp_addr; 2651 __le32 reserved; 2652 __le16 fid; 2653 u8 driver_type; 2654 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_L2 0x0UL 2655 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 0x1UL 2656 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_LAST FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 2657 u8 unused_0; 2658 }; 2659 2660 /* hwrm_func_drv_qver_output (size:256b/32B) */ 2661 struct hwrm_func_drv_qver_output { 2662 __le16 error_code; 2663 __le16 req_type; 2664 __le16 seq_id; 2665 __le16 resp_len; 2666 __le16 os_type; 2667 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2668 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2669 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2670 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2671 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2672 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2673 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2674 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2675 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2676 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2677 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2678 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2679 u8 ver_maj_8b; 2680 u8 ver_min_8b; 2681 u8 ver_upd_8b; 2682 u8 unused_0[3]; 2683 __le16 ver_maj; 2684 __le16 ver_min; 2685 __le16 ver_upd; 2686 __le16 ver_patch; 2687 u8 unused_1[7]; 2688 u8 valid; 2689 }; 2690 2691 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2692 struct hwrm_func_resource_qcaps_input { 2693 __le16 req_type; 2694 __le16 cmpl_ring; 2695 __le16 seq_id; 2696 __le16 target_id; 2697 __le64 resp_addr; 2698 __le16 fid; 2699 u8 unused_0[6]; 2700 }; 2701 2702 /* hwrm_func_resource_qcaps_output (size:704b/88B) */ 2703 struct hwrm_func_resource_qcaps_output { 2704 __le16 error_code; 2705 __le16 req_type; 2706 __le16 seq_id; 2707 __le16 resp_len; 2708 __le16 max_vfs; 2709 __le16 max_msix; 2710 __le16 vf_reservation_strategy; 2711 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2712 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2713 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2714 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2715 __le16 min_rsscos_ctx; 2716 __le16 max_rsscos_ctx; 2717 __le16 min_cmpl_rings; 2718 __le16 max_cmpl_rings; 2719 __le16 min_tx_rings; 2720 __le16 max_tx_rings; 2721 __le16 min_rx_rings; 2722 __le16 max_rx_rings; 2723 __le16 min_l2_ctxs; 2724 __le16 max_l2_ctxs; 2725 __le16 min_vnics; 2726 __le16 max_vnics; 2727 __le16 min_stat_ctx; 2728 __le16 max_stat_ctx; 2729 __le16 min_hw_ring_grps; 2730 __le16 max_hw_ring_grps; 2731 __le16 max_tx_scheduler_inputs; 2732 __le16 flags; 2733 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2734 __le16 min_msix; 2735 __le32 min_ktls_tx_key_ctxs; 2736 __le32 max_ktls_tx_key_ctxs; 2737 __le32 min_ktls_rx_key_ctxs; 2738 __le32 max_ktls_rx_key_ctxs; 2739 __le32 min_quic_tx_key_ctxs; 2740 __le32 max_quic_tx_key_ctxs; 2741 __le32 min_quic_rx_key_ctxs; 2742 __le32 max_quic_rx_key_ctxs; 2743 u8 unused_0[3]; 2744 u8 valid; 2745 }; 2746 2747 /* hwrm_func_vf_resource_cfg_input (size:704b/88B) */ 2748 struct hwrm_func_vf_resource_cfg_input { 2749 __le16 req_type; 2750 __le16 cmpl_ring; 2751 __le16 seq_id; 2752 __le16 target_id; 2753 __le64 resp_addr; 2754 __le16 vf_id; 2755 __le16 max_msix; 2756 __le16 min_rsscos_ctx; 2757 __le16 max_rsscos_ctx; 2758 __le16 min_cmpl_rings; 2759 __le16 max_cmpl_rings; 2760 __le16 min_tx_rings; 2761 __le16 max_tx_rings; 2762 __le16 min_rx_rings; 2763 __le16 max_rx_rings; 2764 __le16 min_l2_ctxs; 2765 __le16 max_l2_ctxs; 2766 __le16 min_vnics; 2767 __le16 max_vnics; 2768 __le16 min_stat_ctx; 2769 __le16 max_stat_ctx; 2770 __le16 min_hw_ring_grps; 2771 __le16 max_hw_ring_grps; 2772 __le16 flags; 2773 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2774 __le16 min_msix; 2775 __le32 min_ktls_tx_key_ctxs; 2776 __le32 max_ktls_tx_key_ctxs; 2777 __le32 min_ktls_rx_key_ctxs; 2778 __le32 max_ktls_rx_key_ctxs; 2779 __le32 min_quic_tx_key_ctxs; 2780 __le32 max_quic_tx_key_ctxs; 2781 __le32 min_quic_rx_key_ctxs; 2782 __le32 max_quic_rx_key_ctxs; 2783 }; 2784 2785 /* hwrm_func_vf_resource_cfg_output (size:384b/48B) */ 2786 struct hwrm_func_vf_resource_cfg_output { 2787 __le16 error_code; 2788 __le16 req_type; 2789 __le16 seq_id; 2790 __le16 resp_len; 2791 __le16 reserved_rsscos_ctx; 2792 __le16 reserved_cmpl_rings; 2793 __le16 reserved_tx_rings; 2794 __le16 reserved_rx_rings; 2795 __le16 reserved_l2_ctxs; 2796 __le16 reserved_vnics; 2797 __le16 reserved_stat_ctx; 2798 __le16 reserved_hw_ring_grps; 2799 __le32 reserved_ktls_tx_key_ctxs; 2800 __le32 reserved_ktls_rx_key_ctxs; 2801 __le32 reserved_quic_tx_key_ctxs; 2802 __le32 reserved_quic_rx_key_ctxs; 2803 u8 unused_0[7]; 2804 u8 valid; 2805 }; 2806 2807 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2808 struct hwrm_func_backing_store_qcaps_input { 2809 __le16 req_type; 2810 __le16 cmpl_ring; 2811 __le16 seq_id; 2812 __le16 target_id; 2813 __le64 resp_addr; 2814 }; 2815 2816 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2817 struct hwrm_func_backing_store_qcaps_output { 2818 __le16 error_code; 2819 __le16 req_type; 2820 __le16 seq_id; 2821 __le16 resp_len; 2822 __le32 qp_max_entries; 2823 __le16 qp_min_qp1_entries; 2824 __le16 qp_max_l2_entries; 2825 __le16 qp_entry_size; 2826 __le16 srq_max_l2_entries; 2827 __le32 srq_max_entries; 2828 __le16 srq_entry_size; 2829 __le16 cq_max_l2_entries; 2830 __le32 cq_max_entries; 2831 __le16 cq_entry_size; 2832 __le16 vnic_max_vnic_entries; 2833 __le16 vnic_max_ring_table_entries; 2834 __le16 vnic_entry_size; 2835 __le32 stat_max_entries; 2836 __le16 stat_entry_size; 2837 __le16 tqm_entry_size; 2838 __le32 tqm_min_entries_per_ring; 2839 __le32 tqm_max_entries_per_ring; 2840 __le32 mrav_max_entries; 2841 __le16 mrav_entry_size; 2842 __le16 tim_entry_size; 2843 __le32 tim_max_entries; 2844 __le16 mrav_num_entries_units; 2845 u8 tqm_entries_multiple; 2846 u8 ctx_kind_initializer; 2847 __le16 ctx_init_mask; 2848 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2849 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2850 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2851 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2852 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2853 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2854 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2855 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2856 u8 qp_init_offset; 2857 u8 srq_init_offset; 2858 u8 cq_init_offset; 2859 u8 vnic_init_offset; 2860 u8 tqm_fp_rings_count; 2861 u8 stat_init_offset; 2862 u8 mrav_init_offset; 2863 u8 tqm_fp_rings_count_ext; 2864 u8 tkc_init_offset; 2865 u8 rkc_init_offset; 2866 __le16 tkc_entry_size; 2867 __le16 rkc_entry_size; 2868 __le32 tkc_max_entries; 2869 __le32 rkc_max_entries; 2870 __le16 fast_qpmd_qp_num_entries; 2871 u8 rsvd1[5]; 2872 u8 valid; 2873 }; 2874 2875 /* tqm_fp_ring_cfg (size:128b/16B) */ 2876 struct tqm_fp_ring_cfg { 2877 u8 tqm_ring_pg_size_tqm_ring_lvl; 2878 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2879 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2880 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2881 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2882 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2883 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2884 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2885 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2886 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2887 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2888 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2889 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2890 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2891 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2892 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2893 u8 unused[3]; 2894 __le32 tqm_ring_num_entries; 2895 __le64 tqm_ring_page_dir; 2896 }; 2897 2898 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 2899 struct hwrm_func_backing_store_cfg_input { 2900 __le16 req_type; 2901 __le16 cmpl_ring; 2902 __le16 seq_id; 2903 __le16 target_id; 2904 __le64 resp_addr; 2905 __le32 flags; 2906 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2907 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2908 __le32 enables; 2909 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2910 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2911 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2912 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2913 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2914 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2915 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2916 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2917 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2918 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2919 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2920 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2921 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2922 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2923 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2924 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2925 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2926 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2927 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2928 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 2929 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 2930 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD 0x200000UL 2931 u8 qpc_pg_size_qpc_lvl; 2932 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2933 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2934 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2935 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2936 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2937 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2938 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2939 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2940 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2941 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2942 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2943 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2944 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2945 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2946 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2947 u8 srq_pg_size_srq_lvl; 2948 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2949 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2950 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2951 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2952 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2953 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2954 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2955 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2956 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2957 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2958 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2959 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2960 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2961 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2962 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2963 u8 cq_pg_size_cq_lvl; 2964 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2965 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2966 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2967 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2968 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2969 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2970 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2971 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2972 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2973 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2974 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2975 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2976 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2977 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2978 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2979 u8 vnic_pg_size_vnic_lvl; 2980 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2981 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2982 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2983 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2984 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2985 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2986 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2987 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2988 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2989 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2990 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2991 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2992 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2993 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2994 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2995 u8 stat_pg_size_stat_lvl; 2996 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2997 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2998 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2999 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 3000 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 3001 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 3002 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 3003 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 3004 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 3005 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 3006 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 3007 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 3008 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 3009 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 3010 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 3011 u8 tqm_sp_pg_size_tqm_sp_lvl; 3012 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 3013 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 3014 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 3015 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 3016 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 3017 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 3018 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 3019 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 3020 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 3021 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 3022 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 3023 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 3024 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 3025 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 3026 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 3027 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 3028 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 3029 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 3030 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 3031 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 3032 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 3033 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 3034 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 3035 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 3036 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 3037 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 3038 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 3039 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 3040 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 3041 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 3042 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 3043 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 3044 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 3045 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 3046 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 3047 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 3048 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 3049 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 3050 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 3051 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 3052 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 3053 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 3054 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 3055 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 3056 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 3057 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 3058 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 3059 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 3060 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 3061 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 3062 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 3063 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 3064 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 3065 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 3066 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 3067 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 3068 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 3069 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 3070 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 3071 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 3072 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 3073 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 3074 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 3075 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 3076 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 3077 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 3078 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 3079 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 3080 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 3081 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 3082 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 3083 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 3084 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 3085 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 3086 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 3087 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 3088 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 3089 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 3090 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 3091 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 3092 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 3093 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 3094 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 3095 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 3096 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 3097 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 3098 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 3099 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 3100 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 3101 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 3102 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 3103 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 3104 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 3105 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 3106 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 3107 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 3108 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 3109 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 3110 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 3111 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 3112 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 3113 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 3114 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 3115 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 3116 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 3117 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 3118 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 3119 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 3120 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 3121 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 3122 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 3123 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 3124 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 3125 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 3126 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 3127 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 3128 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 3129 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 3130 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 3131 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 3132 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 3133 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 3134 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 3135 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 3136 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 3137 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 3138 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 3139 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 3140 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 3141 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 3142 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 3143 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 3144 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 3145 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 3146 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 3147 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 3148 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 3149 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 3150 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 3151 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 3152 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 3153 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 3154 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 3155 u8 mrav_pg_size_mrav_lvl; 3156 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 3157 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 3158 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 3159 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 3160 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 3161 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 3162 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 3163 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 3164 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 3165 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 3166 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 3167 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 3168 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 3169 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 3170 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 3171 u8 tim_pg_size_tim_lvl; 3172 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 3173 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 3174 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 3175 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 3176 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 3177 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 3178 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 3179 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 3180 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 3181 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 3182 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 3183 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 3184 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 3185 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 3186 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 3187 __le64 qpc_page_dir; 3188 __le64 srq_page_dir; 3189 __le64 cq_page_dir; 3190 __le64 vnic_page_dir; 3191 __le64 stat_page_dir; 3192 __le64 tqm_sp_page_dir; 3193 __le64 tqm_ring0_page_dir; 3194 __le64 tqm_ring1_page_dir; 3195 __le64 tqm_ring2_page_dir; 3196 __le64 tqm_ring3_page_dir; 3197 __le64 tqm_ring4_page_dir; 3198 __le64 tqm_ring5_page_dir; 3199 __le64 tqm_ring6_page_dir; 3200 __le64 tqm_ring7_page_dir; 3201 __le64 mrav_page_dir; 3202 __le64 tim_page_dir; 3203 __le32 qp_num_entries; 3204 __le32 srq_num_entries; 3205 __le32 cq_num_entries; 3206 __le32 stat_num_entries; 3207 __le32 tqm_sp_num_entries; 3208 __le32 tqm_ring0_num_entries; 3209 __le32 tqm_ring1_num_entries; 3210 __le32 tqm_ring2_num_entries; 3211 __le32 tqm_ring3_num_entries; 3212 __le32 tqm_ring4_num_entries; 3213 __le32 tqm_ring5_num_entries; 3214 __le32 tqm_ring6_num_entries; 3215 __le32 tqm_ring7_num_entries; 3216 __le32 mrav_num_entries; 3217 __le32 tim_num_entries; 3218 __le16 qp_num_qp1_entries; 3219 __le16 qp_num_l2_entries; 3220 __le16 qp_entry_size; 3221 __le16 srq_num_l2_entries; 3222 __le16 srq_entry_size; 3223 __le16 cq_num_l2_entries; 3224 __le16 cq_entry_size; 3225 __le16 vnic_num_vnic_entries; 3226 __le16 vnic_num_ring_table_entries; 3227 __le16 vnic_entry_size; 3228 __le16 stat_entry_size; 3229 __le16 tqm_entry_size; 3230 __le16 mrav_entry_size; 3231 __le16 tim_entry_size; 3232 u8 tqm_ring8_pg_size_tqm_ring_lvl; 3233 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 3234 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 3235 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 3236 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 3237 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 3238 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 3239 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 3240 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 3241 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3242 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3243 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3244 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3245 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3246 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3247 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 3248 u8 ring8_unused[3]; 3249 __le32 tqm_ring8_num_entries; 3250 __le64 tqm_ring8_page_dir; 3251 u8 tqm_ring9_pg_size_tqm_ring_lvl; 3252 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 3253 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 3254 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 3255 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 3256 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 3257 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 3258 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 3259 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 3260 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3261 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3262 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3263 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3264 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3265 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3266 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 3267 u8 ring9_unused[3]; 3268 __le32 tqm_ring9_num_entries; 3269 __le64 tqm_ring9_page_dir; 3270 u8 tqm_ring10_pg_size_tqm_ring_lvl; 3271 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 3272 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 3273 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 3274 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 3275 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 3276 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 3277 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 3278 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 3279 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3280 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3281 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3282 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3283 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3284 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3285 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 3286 u8 ring10_unused[3]; 3287 __le32 tqm_ring10_num_entries; 3288 __le64 tqm_ring10_page_dir; 3289 __le32 tkc_num_entries; 3290 __le32 rkc_num_entries; 3291 __le64 tkc_page_dir; 3292 __le64 rkc_page_dir; 3293 __le16 tkc_entry_size; 3294 __le16 rkc_entry_size; 3295 u8 tkc_pg_size_tkc_lvl; 3296 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 3297 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 3298 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 3299 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 3300 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 3301 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 3302 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 3303 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 3304 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 3305 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 3306 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 3307 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 3308 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 3309 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 3310 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 3311 u8 rkc_pg_size_rkc_lvl; 3312 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 3313 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 3314 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 3315 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 3316 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 3317 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 3318 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 3319 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 3320 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 3321 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 3322 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 3323 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 3324 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 3325 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 3326 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 3327 __le16 qp_num_fast_qpmd_entries; 3328 }; 3329 3330 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 3331 struct hwrm_func_backing_store_cfg_output { 3332 __le16 error_code; 3333 __le16 req_type; 3334 __le16 seq_id; 3335 __le16 resp_len; 3336 u8 unused_0[7]; 3337 u8 valid; 3338 }; 3339 3340 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 3341 struct hwrm_error_recovery_qcfg_input { 3342 __le16 req_type; 3343 __le16 cmpl_ring; 3344 __le16 seq_id; 3345 __le16 target_id; 3346 __le64 resp_addr; 3347 u8 unused_0[8]; 3348 }; 3349 3350 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 3351 struct hwrm_error_recovery_qcfg_output { 3352 __le16 error_code; 3353 __le16 req_type; 3354 __le16 seq_id; 3355 __le16 resp_len; 3356 __le32 flags; 3357 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 3358 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 3359 __le32 driver_polling_freq; 3360 __le32 master_func_wait_period; 3361 __le32 normal_func_wait_period; 3362 __le32 master_func_wait_period_after_reset; 3363 __le32 max_bailout_time_after_reset; 3364 __le32 fw_health_status_reg; 3365 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 3366 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 3367 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3368 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 3369 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 3370 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 3371 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 3372 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 3373 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 3374 __le32 fw_heartbeat_reg; 3375 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 3376 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 3377 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3378 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 3379 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 3380 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 3381 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 3382 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 3383 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 3384 __le32 fw_reset_cnt_reg; 3385 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 3386 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 3387 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3388 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 3389 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3390 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3391 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 3392 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 3393 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 3394 __le32 reset_inprogress_reg; 3395 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 3396 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 3397 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3398 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 3399 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 3400 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 3401 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 3402 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 3403 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 3404 __le32 reset_inprogress_reg_mask; 3405 u8 unused_0[3]; 3406 u8 reg_array_cnt; 3407 __le32 reset_reg[16]; 3408 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 3409 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 3410 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3411 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 3412 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 3413 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 3414 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 3415 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 3416 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 3417 __le32 reset_reg_val[16]; 3418 u8 delay_after_reset[16]; 3419 __le32 err_recovery_cnt_reg; 3420 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3421 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3422 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3423 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3424 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3425 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3426 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3427 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3428 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3429 u8 unused_1[3]; 3430 u8 valid; 3431 }; 3432 3433 /* hwrm_func_echo_response_input (size:192b/24B) */ 3434 struct hwrm_func_echo_response_input { 3435 __le16 req_type; 3436 __le16 cmpl_ring; 3437 __le16 seq_id; 3438 __le16 target_id; 3439 __le64 resp_addr; 3440 __le32 event_data1; 3441 __le32 event_data2; 3442 }; 3443 3444 /* hwrm_func_echo_response_output (size:128b/16B) */ 3445 struct hwrm_func_echo_response_output { 3446 __le16 error_code; 3447 __le16 req_type; 3448 __le16 seq_id; 3449 __le16 resp_len; 3450 u8 unused_0[7]; 3451 u8 valid; 3452 }; 3453 3454 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3455 struct hwrm_func_ptp_pin_qcfg_input { 3456 __le16 req_type; 3457 __le16 cmpl_ring; 3458 __le16 seq_id; 3459 __le16 target_id; 3460 __le64 resp_addr; 3461 u8 unused_0[8]; 3462 }; 3463 3464 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3465 struct hwrm_func_ptp_pin_qcfg_output { 3466 __le16 error_code; 3467 __le16 req_type; 3468 __le16 seq_id; 3469 __le16 resp_len; 3470 u8 num_pins; 3471 u8 state; 3472 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3473 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3474 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3475 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3476 u8 pin0_usage; 3477 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3478 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3479 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3480 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3481 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3482 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3483 u8 pin1_usage; 3484 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3485 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3486 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3487 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3488 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3489 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3490 u8 pin2_usage; 3491 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3492 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3493 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3494 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3495 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3496 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3497 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3498 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3499 u8 pin3_usage; 3500 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3501 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3502 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3503 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3504 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3505 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3506 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3507 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3508 u8 unused_0; 3509 u8 valid; 3510 }; 3511 3512 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3513 struct hwrm_func_ptp_pin_cfg_input { 3514 __le16 req_type; 3515 __le16 cmpl_ring; 3516 __le16 seq_id; 3517 __le16 target_id; 3518 __le64 resp_addr; 3519 __le32 enables; 3520 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3521 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3522 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3523 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3524 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3525 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3526 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3527 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3528 u8 pin0_state; 3529 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3530 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3531 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3532 u8 pin0_usage; 3533 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3534 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3535 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3536 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3537 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3538 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3539 u8 pin1_state; 3540 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3541 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3542 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3543 u8 pin1_usage; 3544 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3545 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3546 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3547 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3548 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3549 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3550 u8 pin2_state; 3551 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3552 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3553 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3554 u8 pin2_usage; 3555 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3556 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3557 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3558 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3559 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3560 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3561 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3562 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3563 u8 pin3_state; 3564 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3565 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3566 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3567 u8 pin3_usage; 3568 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3569 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3570 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3571 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3572 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3573 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3574 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3575 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3576 u8 unused_0[4]; 3577 }; 3578 3579 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3580 struct hwrm_func_ptp_pin_cfg_output { 3581 __le16 error_code; 3582 __le16 req_type; 3583 __le16 seq_id; 3584 __le16 resp_len; 3585 u8 unused_0[7]; 3586 u8 valid; 3587 }; 3588 3589 /* hwrm_func_ptp_cfg_input (size:384b/48B) */ 3590 struct hwrm_func_ptp_cfg_input { 3591 __le16 req_type; 3592 __le16 cmpl_ring; 3593 __le16 seq_id; 3594 __le16 target_id; 3595 __le64 resp_addr; 3596 __le16 enables; 3597 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3598 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3599 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3600 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3601 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3602 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3603 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL 3604 u8 ptp_pps_event; 3605 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3606 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3607 u8 ptp_freq_adj_dll_source; 3608 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3609 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3610 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3611 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3612 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3613 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3614 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3615 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3616 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3617 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3618 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3619 u8 ptp_freq_adj_dll_phase; 3620 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3621 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3622 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3623 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3624 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 0x4UL 3625 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 3626 u8 unused_0[3]; 3627 __le32 ptp_freq_adj_ext_period; 3628 __le32 ptp_freq_adj_ext_up; 3629 __le32 ptp_freq_adj_ext_phase_lower; 3630 __le32 ptp_freq_adj_ext_phase_upper; 3631 __le64 ptp_set_time; 3632 }; 3633 3634 /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3635 struct hwrm_func_ptp_cfg_output { 3636 __le16 error_code; 3637 __le16 req_type; 3638 __le16 seq_id; 3639 __le16 resp_len; 3640 u8 unused_0[7]; 3641 u8 valid; 3642 }; 3643 3644 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3645 struct hwrm_func_ptp_ts_query_input { 3646 __le16 req_type; 3647 __le16 cmpl_ring; 3648 __le16 seq_id; 3649 __le16 target_id; 3650 __le64 resp_addr; 3651 __le32 flags; 3652 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3653 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3654 u8 unused_0[4]; 3655 }; 3656 3657 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3658 struct hwrm_func_ptp_ts_query_output { 3659 __le16 error_code; 3660 __le16 req_type; 3661 __le16 seq_id; 3662 __le16 resp_len; 3663 __le64 pps_event_ts; 3664 __le64 ptm_local_ts; 3665 __le64 ptm_system_ts; 3666 __le32 ptm_link_delay; 3667 u8 unused_0[3]; 3668 u8 valid; 3669 }; 3670 3671 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ 3672 struct hwrm_func_ptp_ext_cfg_input { 3673 __le16 req_type; 3674 __le16 cmpl_ring; 3675 __le16 seq_id; 3676 __le16 target_id; 3677 __le64 resp_addr; 3678 __le16 enables; 3679 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL 3680 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL 3681 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL 3682 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL 3683 __le16 phc_master_fid; 3684 __le16 phc_sec_fid; 3685 u8 phc_sec_mode; 3686 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL 3687 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL 3688 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL 3689 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 3690 u8 unused_0; 3691 __le32 failover_timer; 3692 u8 unused_1[4]; 3693 }; 3694 3695 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ 3696 struct hwrm_func_ptp_ext_cfg_output { 3697 __le16 error_code; 3698 __le16 req_type; 3699 __le16 seq_id; 3700 __le16 resp_len; 3701 u8 unused_0[7]; 3702 u8 valid; 3703 }; 3704 3705 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ 3706 struct hwrm_func_ptp_ext_qcfg_input { 3707 __le16 req_type; 3708 __le16 cmpl_ring; 3709 __le16 seq_id; 3710 __le16 target_id; 3711 __le64 resp_addr; 3712 u8 unused_0[8]; 3713 }; 3714 3715 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ 3716 struct hwrm_func_ptp_ext_qcfg_output { 3717 __le16 error_code; 3718 __le16 req_type; 3719 __le16 seq_id; 3720 __le16 resp_len; 3721 __le16 phc_master_fid; 3722 __le16 phc_sec_fid; 3723 __le16 phc_active_fid0; 3724 __le16 phc_active_fid1; 3725 __le32 last_failover_event; 3726 __le16 from_fid; 3727 __le16 to_fid; 3728 u8 unused_0[7]; 3729 u8 valid; 3730 }; 3731 3732 /* hwrm_func_backing_store_cfg_v2_input (size:512b/64B) */ 3733 struct hwrm_func_backing_store_cfg_v2_input { 3734 __le16 req_type; 3735 __le16 cmpl_ring; 3736 __le16 seq_id; 3737 __le16 target_id; 3738 __le64 resp_addr; 3739 __le16 type; 3740 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 3741 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 3742 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 3743 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 3744 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 3745 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3746 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3747 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3748 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3749 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TX_CK 0x13UL 3750 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RX_CK 0x14UL 3751 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3752 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3753 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3754 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3755 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3756 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3757 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3758 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3759 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3760 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3761 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3762 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3763 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3764 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3765 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 3766 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA0_TRACE 0x26UL 3767 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA1_TRACE 0x27UL 3768 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA2_TRACE 0x28UL 3769 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3770 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 3771 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3772 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3773 __le16 instance; 3774 __le32 flags; 3775 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 3776 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL 3777 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL 3778 __le64 page_dir; 3779 __le32 num_entries; 3780 __le16 entry_size; 3781 u8 page_size_pbl_level; 3782 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL 3783 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0 3784 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL 3785 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL 3786 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL 3787 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 3788 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL 3789 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4 3790 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4) 3791 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4) 3792 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4) 3793 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4) 3794 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4) 3795 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4) 3796 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G 3797 u8 subtype_valid_cnt; 3798 __le32 split_entry_0; 3799 __le32 split_entry_1; 3800 __le32 split_entry_2; 3801 __le32 split_entry_3; 3802 __le32 enables; 3803 #define FUNC_BACKING_STORE_CFG_V2_REQ_ENABLES_NEXT_BS_OFFSET 0x1UL 3804 __le32 next_bs_offset; 3805 }; 3806 3807 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ 3808 struct hwrm_func_backing_store_cfg_v2_output { 3809 __le16 error_code; 3810 __le16 req_type; 3811 __le16 seq_id; 3812 __le16 resp_len; 3813 u8 rsvd0[7]; 3814 u8 valid; 3815 }; 3816 3817 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ 3818 struct hwrm_func_backing_store_qcfg_v2_input { 3819 __le16 req_type; 3820 __le16 cmpl_ring; 3821 __le16 seq_id; 3822 __le16 target_id; 3823 __le64 resp_addr; 3824 __le16 type; 3825 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL 3826 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL 3827 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL 3828 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL 3829 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL 3830 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3831 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3832 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL 3833 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL 3834 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TX_CK 0x13UL 3835 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RX_CK 0x14UL 3836 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3837 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3838 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3839 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3840 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3841 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3842 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION_TABLE 0x1dUL 3843 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3844 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3845 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3846 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3847 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3848 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3849 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3850 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 3851 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA0_TRACE 0x26UL 3852 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA1_TRACE 0x27UL 3853 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA2_TRACE 0x28UL 3854 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3855 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 3856 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3857 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3858 __le16 instance; 3859 u8 rsvd[4]; 3860 }; 3861 3862 /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ 3863 struct hwrm_func_backing_store_qcfg_v2_output { 3864 __le16 error_code; 3865 __le16 req_type; 3866 __le16 seq_id; 3867 __le16 resp_len; 3868 __le16 type; 3869 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 3870 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 3871 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 3872 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 3873 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 3874 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3875 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3876 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3877 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3878 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TX_CK 0x13UL 3879 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RX_CK 0x14UL 3880 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3881 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3882 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3883 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3884 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3885 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT_TRACE 0x20UL 3886 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3887 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3888 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3889 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3890 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL 3891 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA0_TRACE 0x26UL 3892 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA1_TRACE 0x27UL 3893 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA2_TRACE 0x28UL 3894 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP1_TRACE 0x29UL 3895 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3896 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 3897 __le16 instance; 3898 __le32 flags; 3899 __le64 page_dir; 3900 __le32 num_entries; 3901 u8 page_size_pbl_level; 3902 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL 3903 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0 3904 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL 3905 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL 3906 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL 3907 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 3908 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL 3909 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4 3910 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4) 3911 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4) 3912 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4) 3913 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4) 3914 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4) 3915 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4) 3916 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G 3917 u8 subtype_valid_cnt; 3918 u8 rsvd[2]; 3919 __le32 split_entry_0; 3920 __le32 split_entry_1; 3921 __le32 split_entry_2; 3922 __le32 split_entry_3; 3923 u8 rsvd2[7]; 3924 u8 valid; 3925 }; 3926 3927 /* qpc_split_entries (size:128b/16B) */ 3928 struct qpc_split_entries { 3929 __le32 qp_num_l2_entries; 3930 __le32 qp_num_qp1_entries; 3931 __le32 qp_num_fast_qpmd_entries; 3932 __le32 rsvd; 3933 }; 3934 3935 /* srq_split_entries (size:128b/16B) */ 3936 struct srq_split_entries { 3937 __le32 srq_num_l2_entries; 3938 __le32 rsvd; 3939 __le32 rsvd2[2]; 3940 }; 3941 3942 /* cq_split_entries (size:128b/16B) */ 3943 struct cq_split_entries { 3944 __le32 cq_num_l2_entries; 3945 __le32 rsvd; 3946 __le32 rsvd2[2]; 3947 }; 3948 3949 /* vnic_split_entries (size:128b/16B) */ 3950 struct vnic_split_entries { 3951 __le32 vnic_num_vnic_entries; 3952 __le32 rsvd; 3953 __le32 rsvd2[2]; 3954 }; 3955 3956 /* mrav_split_entries (size:128b/16B) */ 3957 struct mrav_split_entries { 3958 __le32 mrav_num_av_entries; 3959 __le32 rsvd; 3960 __le32 rsvd2[2]; 3961 }; 3962 3963 /* ts_split_entries (size:128b/16B) */ 3964 struct ts_split_entries { 3965 __le32 region_num_entries; 3966 u8 tsid; 3967 u8 lkup_static_bkt_cnt_exp[2]; 3968 u8 rsvd; 3969 __le32 rsvd2[2]; 3970 }; 3971 3972 /* ck_split_entries (size:128b/16B) */ 3973 struct ck_split_entries { 3974 __le32 num_quic_entries; 3975 __le32 rsvd; 3976 __le32 rsvd2[2]; 3977 }; 3978 3979 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ 3980 struct hwrm_func_backing_store_qcaps_v2_input { 3981 __le16 req_type; 3982 __le16 cmpl_ring; 3983 __le16 seq_id; 3984 __le16 target_id; 3985 __le64 resp_addr; 3986 __le16 type; 3987 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 3988 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 3989 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 3990 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 3991 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 3992 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3993 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3994 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 3995 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 3996 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK 0x13UL 3997 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK 0x14UL 3998 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3999 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 4000 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 4001 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 4002 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 4003 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 4004 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL 4005 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE 0x1eUL 4006 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 4007 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE 0x20UL 4008 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE 0x21UL 4009 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 4010 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 4011 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 4012 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 4013 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA0_TRACE 0x26UL 4014 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE 0x27UL 4015 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE 0x28UL 4016 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 4017 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 4018 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 4019 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 4020 u8 rsvd[6]; 4021 }; 4022 4023 /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ 4024 struct hwrm_func_backing_store_qcaps_v2_output { 4025 __le16 error_code; 4026 __le16 req_type; 4027 __le16 seq_id; 4028 __le16 resp_len; 4029 __le16 type; 4030 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 4031 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 4032 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 4033 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 4034 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 4035 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 4036 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 4037 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 4038 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 4039 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TX_CK 0x13UL 4040 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RX_CK 0x14UL 4041 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 4042 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 4043 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 4044 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 4045 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 4046 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 4047 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL 4048 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT_TRACE 0x1eUL 4049 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 4050 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT_TRACE 0x20UL 4051 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT2_TRACE 0x21UL 4052 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 4053 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 4054 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 4055 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL 4056 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA0_TRACE 0x26UL 4057 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA1_TRACE 0x27UL 4058 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA2_TRACE 0x28UL 4059 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP1_TRACE 0x29UL 4060 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 4061 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 4062 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 4063 __le16 entry_size; 4064 __le32 flags; 4065 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL 4066 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL 4067 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL 4068 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL 4069 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE 0x10UL 4070 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_BIN_DBG_TRACE 0x20UL 4071 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_NEXT_BS_OFFSET 0x40UL 4072 __le32 instance_bit_map; 4073 u8 ctx_init_value; 4074 u8 ctx_init_offset; 4075 u8 entry_multiple; 4076 u8 rsvd; 4077 __le32 max_num_entries; 4078 __le32 min_num_entries; 4079 __le16 next_valid_type; 4080 u8 subtype_valid_cnt; 4081 u8 exact_cnt_bit_map; 4082 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT 0x1UL 4083 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT 0x2UL 4084 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT 0x4UL 4085 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT 0x8UL 4086 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_MASK 0xf0UL 4087 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_SFT 4 4088 __le32 split_entry_0; 4089 __le32 split_entry_1; 4090 __le32 split_entry_2; 4091 __le32 split_entry_3; 4092 __le16 max_instance_count; 4093 u8 rsvd3; 4094 u8 valid; 4095 }; 4096 4097 /* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */ 4098 struct hwrm_func_dbr_pacing_qcfg_input { 4099 __le16 req_type; 4100 __le16 cmpl_ring; 4101 __le16 seq_id; 4102 __le16 target_id; 4103 __le64 resp_addr; 4104 }; 4105 4106 /* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */ 4107 struct hwrm_func_dbr_pacing_qcfg_output { 4108 __le16 error_code; 4109 __le16 req_type; 4110 __le16 seq_id; 4111 __le16 resp_len; 4112 u8 flags; 4113 #define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED 0x1UL 4114 u8 unused_0[7]; 4115 __le32 dbr_stat_db_fifo_reg; 4116 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK 0x3UL 4117 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT 0 4118 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG 0x0UL 4119 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC 0x1UL 4120 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 0x2UL 4121 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 0x3UL 4122 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 4123 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK 0xfffffffcUL 4124 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT 2 4125 __le32 dbr_stat_db_fifo_reg_watermark_mask; 4126 u8 dbr_stat_db_fifo_reg_watermark_shift; 4127 u8 unused_1[3]; 4128 __le32 dbr_stat_db_fifo_reg_fifo_room_mask; 4129 u8 dbr_stat_db_fifo_reg_fifo_room_shift; 4130 u8 unused_2[3]; 4131 __le32 dbr_throttling_aeq_arm_reg; 4132 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK 0x3UL 4133 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT 0 4134 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG 0x0UL 4135 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC 0x1UL 4136 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 0x2UL 4137 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 0x3UL 4138 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 4139 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK 0xfffffffcUL 4140 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT 2 4141 u8 dbr_throttling_aeq_arm_reg_val; 4142 u8 unused_3[3]; 4143 __le32 dbr_stat_db_max_fifo_depth; 4144 __le32 primary_nq_id; 4145 __le32 pacing_threshold; 4146 u8 unused_4[7]; 4147 u8 valid; 4148 }; 4149 4150 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 4151 struct hwrm_func_drv_if_change_input { 4152 __le16 req_type; 4153 __le16 cmpl_ring; 4154 __le16 seq_id; 4155 __le16 target_id; 4156 __le64 resp_addr; 4157 __le32 flags; 4158 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 4159 __le32 unused; 4160 }; 4161 4162 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 4163 struct hwrm_func_drv_if_change_output { 4164 __le16 error_code; 4165 __le16 req_type; 4166 __le16 seq_id; 4167 __le16 resp_len; 4168 __le32 flags; 4169 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 4170 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 4171 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_CAPS_CHANGE 0x4UL 4172 u8 unused_0[3]; 4173 u8 valid; 4174 }; 4175 4176 /* hwrm_port_phy_cfg_input (size:512b/64B) */ 4177 struct hwrm_port_phy_cfg_input { 4178 __le16 req_type; 4179 __le16 cmpl_ring; 4180 __le16 seq_id; 4181 __le16 target_id; 4182 __le64 resp_addr; 4183 __le32 flags; 4184 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 4185 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 4186 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 4187 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 4188 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 4189 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 4190 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 4191 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 4192 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 4193 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 4194 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 4195 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 4196 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 4197 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 4198 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 4199 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 4200 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 4201 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 4202 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 4203 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 4204 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 4205 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 4206 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 4207 __le32 enables; 4208 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 4209 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 4210 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 4211 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 4212 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 4213 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 4214 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 4215 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 4216 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 4217 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 4218 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 4219 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 4220 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 4221 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2 0x2000UL 4222 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK 0x4000UL 4223 __le16 port_id; 4224 __le16 force_link_speed; 4225 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 4226 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 4227 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 4228 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 4229 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 4230 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 4231 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 4232 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 4233 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 4234 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 4235 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 4236 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 4237 u8 auto_mode; 4238 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 4239 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 4240 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 4241 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 4242 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 4243 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 4244 u8 auto_duplex; 4245 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 4246 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 4247 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 4248 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 4249 u8 auto_pause; 4250 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 4251 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 4252 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4253 u8 mgmt_flag; 4254 #define PORT_PHY_CFG_REQ_MGMT_FLAG_LINK_RELEASE 0x1UL 4255 #define PORT_PHY_CFG_REQ_MGMT_FLAG_MGMT_VALID 0x80UL 4256 __le16 auto_link_speed; 4257 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 4258 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 4259 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 4260 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 4261 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 4262 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 4263 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 4264 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 4265 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 4266 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 4267 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 4268 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 4269 __le16 auto_link_speed_mask; 4270 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4271 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4272 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4273 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4274 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4275 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4276 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4277 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4278 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4279 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4280 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4281 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4282 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4283 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4284 u8 wirespeed; 4285 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 4286 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 4287 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 4288 u8 lpbk; 4289 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 4290 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 4291 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 4292 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 4293 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 4294 u8 force_pause; 4295 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 4296 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 4297 u8 unused_1; 4298 __le32 preemphasis; 4299 __le16 eee_link_speed_mask; 4300 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4301 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 4302 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4303 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 4304 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4305 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4306 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 4307 __le16 force_pam4_link_speed; 4308 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4309 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4310 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4311 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 4312 __le32 tx_lpi_timer; 4313 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 4314 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 4315 __le16 auto_link_pam4_speed_mask; 4316 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 4317 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 4318 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 4319 __le16 force_link_speeds2; 4320 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB 0xaUL 4321 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB 0x64UL 4322 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4323 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB 0x190UL 4324 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4325 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4326 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4327 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4328 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4329 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4330 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4331 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4332 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4333 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4334 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4335 __le16 auto_link_speeds2_mask; 4336 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL 4337 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL 4338 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB 0x4UL 4339 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB 0x8UL 4340 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB 0x10UL 4341 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB 0x20UL 4342 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 0x40UL 4343 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 0x80UL 4344 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 0x100UL 4345 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 0x200UL 4346 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 0x400UL 4347 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL 4348 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL 4349 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 0x2000UL 4350 u8 unused_2[6]; 4351 }; 4352 4353 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 4354 struct hwrm_port_phy_cfg_output { 4355 __le16 error_code; 4356 __le16 req_type; 4357 __le16 seq_id; 4358 __le16 resp_len; 4359 u8 unused_0[7]; 4360 u8 valid; 4361 }; 4362 4363 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 4364 struct hwrm_port_phy_cfg_cmd_err { 4365 u8 code; 4366 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 4367 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 4368 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 4369 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 4370 u8 unused_0[7]; 4371 }; 4372 4373 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 4374 struct hwrm_port_phy_qcfg_input { 4375 __le16 req_type; 4376 __le16 cmpl_ring; 4377 __le16 seq_id; 4378 __le16 target_id; 4379 __le64 resp_addr; 4380 __le16 port_id; 4381 u8 unused_0[6]; 4382 }; 4383 4384 /* hwrm_port_phy_qcfg_output (size:832b/104B) */ 4385 struct hwrm_port_phy_qcfg_output { 4386 __le16 error_code; 4387 __le16 req_type; 4388 __le16 seq_id; 4389 __le16 resp_len; 4390 u8 link; 4391 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 4392 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 4393 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 4394 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 4395 u8 active_fec_signal_mode; 4396 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 4397 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 4398 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 4399 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 4400 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL 4401 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 4402 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 4403 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 4404 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 4405 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 4406 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 4407 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 4408 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 4409 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 4410 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 4411 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 4412 __le16 link_speed; 4413 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 4414 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 4415 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 4416 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 4417 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 4418 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 4419 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 4420 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 4421 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 4422 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 4423 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 4424 #define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL 4425 #define PORT_PHY_QCFG_RESP_LINK_SPEED_800GB 0x1f40UL 4426 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 4427 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 4428 u8 duplex_cfg; 4429 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 4430 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 4431 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 4432 u8 pause; 4433 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 4434 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 4435 __le16 support_speeds; 4436 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 4437 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 4438 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 4439 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 4440 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 4441 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 4442 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 4443 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 4444 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 4445 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 4446 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 4447 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 4448 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 4449 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 4450 __le16 force_link_speed; 4451 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 4452 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 4453 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 4454 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 4455 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 4456 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 4457 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 4458 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 4459 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 4460 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 4461 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 4462 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 4463 u8 auto_mode; 4464 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 4465 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 4466 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 4467 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 4468 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 4469 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 4470 u8 auto_pause; 4471 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 4472 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 4473 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4474 __le16 auto_link_speed; 4475 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 4476 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 4477 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 4478 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 4479 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 4480 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 4481 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 4482 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 4483 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 4484 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 4485 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 4486 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 4487 __le16 auto_link_speed_mask; 4488 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4489 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4490 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4491 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4492 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4493 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4494 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4495 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4496 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4497 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4498 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4499 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4500 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4501 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4502 u8 wirespeed; 4503 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 4504 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 4505 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 4506 u8 lpbk; 4507 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 4508 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 4509 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 4510 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 4511 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 4512 u8 force_pause; 4513 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 4514 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 4515 u8 module_status; 4516 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 4517 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 4518 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 4519 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 4520 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 4521 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 4522 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_OVERHEATED 0x6UL 4523 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 4524 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 4525 __le32 preemphasis; 4526 u8 phy_maj; 4527 u8 phy_min; 4528 u8 phy_bld; 4529 u8 phy_type; 4530 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 4531 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 4532 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 4533 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 4534 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 4535 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 4536 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 4537 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 4538 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 4539 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 4540 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 4541 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 4542 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 4543 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 4544 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 4545 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 4546 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 4547 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 4548 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 4549 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 4550 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 4551 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 4552 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 4553 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 4554 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 4555 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 4556 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 4557 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 4558 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 4559 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 4560 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 4561 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 4562 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 4563 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 4564 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 4565 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 4566 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 4567 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 4568 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 4569 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 4570 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR 0x28UL 4571 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR 0x29UL 4572 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR 0x2aUL 4573 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER 0x2bUL 4574 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2 0x2cUL 4575 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2 0x2dUL 4576 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2 0x2eUL 4577 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2 0x2fUL 4578 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8 0x30UL 4579 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8 0x31UL 4580 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8 0x32UL 4581 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8 0x33UL 4582 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4 0x34UL 4583 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4 0x35UL 4584 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4 0x36UL 4585 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 0x37UL 4586 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASECR8 0x38UL 4587 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASESR8 0x39UL 4588 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASELR8 0x3aUL 4589 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEER8 0x3bUL 4590 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEFR8 0x3cUL 4591 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 0x3dUL 4592 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 4593 u8 media_type; 4594 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 4595 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 4596 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 4597 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 4598 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE 0x4UL 4599 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE 4600 u8 xcvr_pkg_type; 4601 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 4602 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 4603 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 4604 u8 eee_config_phy_addr; 4605 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 4606 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 4607 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 4608 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 4609 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 4610 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 4611 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 4612 u8 parallel_detect; 4613 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 4614 __le16 link_partner_adv_speeds; 4615 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 4616 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 4617 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 4618 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 4619 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 4620 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 4621 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 4622 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 4623 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 4624 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 4625 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 4626 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 4627 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 4628 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 4629 u8 link_partner_adv_auto_mode; 4630 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 4631 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 4632 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 4633 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 4634 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 4635 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 4636 u8 link_partner_adv_pause; 4637 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 4638 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 4639 __le16 adv_eee_link_speed_mask; 4640 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4641 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4642 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4643 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4644 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4645 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4646 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4647 __le16 link_partner_adv_eee_link_speed_mask; 4648 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4649 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4650 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4651 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4652 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4653 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4654 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4655 __le32 xcvr_identifier_type_tx_lpi_timer; 4656 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 4657 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 4658 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 4659 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 4660 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 4661 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 4662 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 4663 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 4664 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 4665 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPDD (0x18UL << 24) 4666 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP112 (0x1eUL << 24) 4667 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFPDD (0x1fUL << 24) 4668 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP (0x20UL << 24) 4669 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP 4670 __le16 fec_cfg; 4671 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 4672 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 4673 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 4674 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 4675 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 4676 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 4677 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 4678 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 4679 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 4680 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 4681 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 4682 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 4683 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 4684 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 4685 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 4686 u8 duplex_state; 4687 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 4688 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 4689 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 4690 u8 option_flags; 4691 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 4692 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 4693 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED 0x4UL 4694 char phy_vendor_name[16]; 4695 char phy_vendor_partnumber[16]; 4696 __le16 support_pam4_speeds; 4697 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 4698 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 4699 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 4700 __le16 force_pam4_link_speed; 4701 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4702 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4703 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4704 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 4705 __le16 auto_pam4_link_speed_mask; 4706 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 4707 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 4708 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 4709 u8 link_partner_pam4_adv_speeds; 4710 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 4711 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 4712 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 4713 u8 link_down_reason; 4714 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL 4715 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION 0x2UL 4716 __le16 support_speeds2; 4717 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL 4718 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL 4719 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB 0x4UL 4720 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB 0x8UL 4721 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB 0x10UL 4722 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB 0x20UL 4723 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56 0x40UL 4724 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56 0x80UL 4725 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56 0x100UL 4726 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56 0x200UL 4727 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112 0x400UL 4728 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112 0x800UL 4729 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112 0x1000UL 4730 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112 0x2000UL 4731 __le16 force_link_speeds2; 4732 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB 0xaUL 4733 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB 0x64UL 4734 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4735 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB 0x190UL 4736 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4737 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4738 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4739 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4740 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4741 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4742 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4743 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4744 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4745 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4746 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4747 __le16 auto_link_speeds2; 4748 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL 4749 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL 4750 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB 0x4UL 4751 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB 0x8UL 4752 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB 0x10UL 4753 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB 0x20UL 4754 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56 0x40UL 4755 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56 0x80UL 4756 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56 0x100UL 4757 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56 0x200UL 4758 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112 0x400UL 4759 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112 0x800UL 4760 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL 4761 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL 4762 u8 active_lanes; 4763 u8 valid; 4764 }; 4765 4766 /* hwrm_port_mac_cfg_input (size:448b/56B) */ 4767 struct hwrm_port_mac_cfg_input { 4768 __le16 req_type; 4769 __le16 cmpl_ring; 4770 __le16 seq_id; 4771 __le16 target_id; 4772 __le64 resp_addr; 4773 __le32 flags; 4774 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 4775 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 4776 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 4777 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 4778 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 4779 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 4780 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 4781 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 4782 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 4783 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 4784 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 4785 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 4786 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 4787 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 4788 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL 4789 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL 4790 __le32 enables; 4791 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 4792 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 4793 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 4794 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 4795 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 4796 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 4797 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 4798 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 4799 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 4800 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 4801 #define PORT_MAC_CFG_REQ_ENABLES_PTP_LOAD_CONTROL 0x800UL 4802 __le16 port_id; 4803 u8 ipg; 4804 u8 lpbk; 4805 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 4806 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 4807 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 4808 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 4809 u8 vlan_pri2cos_map_pri; 4810 u8 reserved1; 4811 u8 tunnel_pri2cos_map_pri; 4812 u8 dscp2pri_map_pri; 4813 __le16 rx_ts_capture_ptp_msg_type; 4814 __le16 tx_ts_capture_ptp_msg_type; 4815 u8 cos_field_cfg; 4816 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 4817 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 4818 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 4819 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 4820 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 4821 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 4822 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 4823 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 4824 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 4825 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 4826 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 4827 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 4828 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 4829 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 4830 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 4831 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 4832 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 4833 u8 unused_0[3]; 4834 __le32 ptp_freq_adj_ppb; 4835 u8 unused_1[3]; 4836 u8 ptp_load_control; 4837 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_NONE 0x0UL 4838 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_IMMEDIATE 0x1UL 4839 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 0x2UL 4840 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_LAST PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 4841 __le64 ptp_adj_phase; 4842 }; 4843 4844 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 4845 struct hwrm_port_mac_cfg_output { 4846 __le16 error_code; 4847 __le16 req_type; 4848 __le16 seq_id; 4849 __le16 resp_len; 4850 __le16 mru; 4851 __le16 mtu; 4852 u8 ipg; 4853 u8 lpbk; 4854 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 4855 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 4856 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 4857 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 4858 u8 unused_0; 4859 u8 valid; 4860 }; 4861 4862 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 4863 struct hwrm_port_mac_ptp_qcfg_input { 4864 __le16 req_type; 4865 __le16 cmpl_ring; 4866 __le16 seq_id; 4867 __le16 target_id; 4868 __le64 resp_addr; 4869 __le16 port_id; 4870 u8 unused_0[6]; 4871 }; 4872 4873 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 4874 struct hwrm_port_mac_ptp_qcfg_output { 4875 __le16 error_code; 4876 __le16 req_type; 4877 __le16 seq_id; 4878 __le16 resp_len; 4879 u8 flags; 4880 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 4881 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 4882 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 4883 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 4884 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL 4885 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_64B_PHC_TIME 0x40UL 4886 u8 unused_0[3]; 4887 __le32 rx_ts_reg_off_lower; 4888 __le32 rx_ts_reg_off_upper; 4889 __le32 rx_ts_reg_off_seq_id; 4890 __le32 rx_ts_reg_off_src_id_0; 4891 __le32 rx_ts_reg_off_src_id_1; 4892 __le32 rx_ts_reg_off_src_id_2; 4893 __le32 rx_ts_reg_off_domain_id; 4894 __le32 rx_ts_reg_off_fifo; 4895 __le32 rx_ts_reg_off_fifo_adv; 4896 __le32 rx_ts_reg_off_granularity; 4897 __le32 tx_ts_reg_off_lower; 4898 __le32 tx_ts_reg_off_upper; 4899 __le32 tx_ts_reg_off_seq_id; 4900 __le32 tx_ts_reg_off_fifo; 4901 __le32 tx_ts_reg_off_granularity; 4902 __le32 ts_ref_clock_reg_lower; 4903 __le32 ts_ref_clock_reg_upper; 4904 u8 unused_1[7]; 4905 u8 valid; 4906 }; 4907 4908 /* tx_port_stats (size:3264b/408B) */ 4909 struct tx_port_stats { 4910 __le64 tx_64b_frames; 4911 __le64 tx_65b_127b_frames; 4912 __le64 tx_128b_255b_frames; 4913 __le64 tx_256b_511b_frames; 4914 __le64 tx_512b_1023b_frames; 4915 __le64 tx_1024b_1518b_frames; 4916 __le64 tx_good_vlan_frames; 4917 __le64 tx_1519b_2047b_frames; 4918 __le64 tx_2048b_4095b_frames; 4919 __le64 tx_4096b_9216b_frames; 4920 __le64 tx_9217b_16383b_frames; 4921 __le64 tx_good_frames; 4922 __le64 tx_total_frames; 4923 __le64 tx_ucast_frames; 4924 __le64 tx_mcast_frames; 4925 __le64 tx_bcast_frames; 4926 __le64 tx_pause_frames; 4927 __le64 tx_pfc_frames; 4928 __le64 tx_jabber_frames; 4929 __le64 tx_fcs_err_frames; 4930 __le64 tx_control_frames; 4931 __le64 tx_oversz_frames; 4932 __le64 tx_single_dfrl_frames; 4933 __le64 tx_multi_dfrl_frames; 4934 __le64 tx_single_coll_frames; 4935 __le64 tx_multi_coll_frames; 4936 __le64 tx_late_coll_frames; 4937 __le64 tx_excessive_coll_frames; 4938 __le64 tx_frag_frames; 4939 __le64 tx_err; 4940 __le64 tx_tagged_frames; 4941 __le64 tx_dbl_tagged_frames; 4942 __le64 tx_runt_frames; 4943 __le64 tx_fifo_underruns; 4944 __le64 tx_pfc_ena_frames_pri0; 4945 __le64 tx_pfc_ena_frames_pri1; 4946 __le64 tx_pfc_ena_frames_pri2; 4947 __le64 tx_pfc_ena_frames_pri3; 4948 __le64 tx_pfc_ena_frames_pri4; 4949 __le64 tx_pfc_ena_frames_pri5; 4950 __le64 tx_pfc_ena_frames_pri6; 4951 __le64 tx_pfc_ena_frames_pri7; 4952 __le64 tx_eee_lpi_events; 4953 __le64 tx_eee_lpi_duration; 4954 __le64 tx_llfc_logical_msgs; 4955 __le64 tx_hcfc_msgs; 4956 __le64 tx_total_collisions; 4957 __le64 tx_bytes; 4958 __le64 tx_xthol_frames; 4959 __le64 tx_stat_discard; 4960 __le64 tx_stat_error; 4961 }; 4962 4963 /* rx_port_stats (size:4224b/528B) */ 4964 struct rx_port_stats { 4965 __le64 rx_64b_frames; 4966 __le64 rx_65b_127b_frames; 4967 __le64 rx_128b_255b_frames; 4968 __le64 rx_256b_511b_frames; 4969 __le64 rx_512b_1023b_frames; 4970 __le64 rx_1024b_1518b_frames; 4971 __le64 rx_good_vlan_frames; 4972 __le64 rx_1519b_2047b_frames; 4973 __le64 rx_2048b_4095b_frames; 4974 __le64 rx_4096b_9216b_frames; 4975 __le64 rx_9217b_16383b_frames; 4976 __le64 rx_total_frames; 4977 __le64 rx_ucast_frames; 4978 __le64 rx_mcast_frames; 4979 __le64 rx_bcast_frames; 4980 __le64 rx_fcs_err_frames; 4981 __le64 rx_ctrl_frames; 4982 __le64 rx_pause_frames; 4983 __le64 rx_pfc_frames; 4984 __le64 rx_unsupported_opcode_frames; 4985 __le64 rx_unsupported_da_pausepfc_frames; 4986 __le64 rx_wrong_sa_frames; 4987 __le64 rx_align_err_frames; 4988 __le64 rx_oor_len_frames; 4989 __le64 rx_code_err_frames; 4990 __le64 rx_false_carrier_frames; 4991 __le64 rx_ovrsz_frames; 4992 __le64 rx_jbr_frames; 4993 __le64 rx_mtu_err_frames; 4994 __le64 rx_match_crc_frames; 4995 __le64 rx_promiscuous_frames; 4996 __le64 rx_tagged_frames; 4997 __le64 rx_double_tagged_frames; 4998 __le64 rx_trunc_frames; 4999 __le64 rx_good_frames; 5000 __le64 rx_pfc_xon2xoff_frames_pri0; 5001 __le64 rx_pfc_xon2xoff_frames_pri1; 5002 __le64 rx_pfc_xon2xoff_frames_pri2; 5003 __le64 rx_pfc_xon2xoff_frames_pri3; 5004 __le64 rx_pfc_xon2xoff_frames_pri4; 5005 __le64 rx_pfc_xon2xoff_frames_pri5; 5006 __le64 rx_pfc_xon2xoff_frames_pri6; 5007 __le64 rx_pfc_xon2xoff_frames_pri7; 5008 __le64 rx_pfc_ena_frames_pri0; 5009 __le64 rx_pfc_ena_frames_pri1; 5010 __le64 rx_pfc_ena_frames_pri2; 5011 __le64 rx_pfc_ena_frames_pri3; 5012 __le64 rx_pfc_ena_frames_pri4; 5013 __le64 rx_pfc_ena_frames_pri5; 5014 __le64 rx_pfc_ena_frames_pri6; 5015 __le64 rx_pfc_ena_frames_pri7; 5016 __le64 rx_sch_crc_err_frames; 5017 __le64 rx_undrsz_frames; 5018 __le64 rx_frag_frames; 5019 __le64 rx_eee_lpi_events; 5020 __le64 rx_eee_lpi_duration; 5021 __le64 rx_llfc_physical_msgs; 5022 __le64 rx_llfc_logical_msgs; 5023 __le64 rx_llfc_msgs_with_crc_err; 5024 __le64 rx_hcfc_msgs; 5025 __le64 rx_hcfc_msgs_with_crc_err; 5026 __le64 rx_bytes; 5027 __le64 rx_runt_bytes; 5028 __le64 rx_runt_frames; 5029 __le64 rx_stat_discard; 5030 __le64 rx_stat_err; 5031 }; 5032 5033 /* hwrm_port_qstats_input (size:320b/40B) */ 5034 struct hwrm_port_qstats_input { 5035 __le16 req_type; 5036 __le16 cmpl_ring; 5037 __le16 seq_id; 5038 __le16 target_id; 5039 __le64 resp_addr; 5040 __le16 port_id; 5041 u8 flags; 5042 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5043 u8 unused_0[5]; 5044 __le64 tx_stat_host_addr; 5045 __le64 rx_stat_host_addr; 5046 }; 5047 5048 /* hwrm_port_qstats_output (size:128b/16B) */ 5049 struct hwrm_port_qstats_output { 5050 __le16 error_code; 5051 __le16 req_type; 5052 __le16 seq_id; 5053 __le16 resp_len; 5054 __le16 tx_stat_size; 5055 __le16 rx_stat_size; 5056 u8 flags; 5057 #define PORT_QSTATS_RESP_FLAGS_CLEARED 0x1UL 5058 u8 unused_0[2]; 5059 u8 valid; 5060 }; 5061 5062 /* tx_port_stats_ext (size:2048b/256B) */ 5063 struct tx_port_stats_ext { 5064 __le64 tx_bytes_cos0; 5065 __le64 tx_bytes_cos1; 5066 __le64 tx_bytes_cos2; 5067 __le64 tx_bytes_cos3; 5068 __le64 tx_bytes_cos4; 5069 __le64 tx_bytes_cos5; 5070 __le64 tx_bytes_cos6; 5071 __le64 tx_bytes_cos7; 5072 __le64 tx_packets_cos0; 5073 __le64 tx_packets_cos1; 5074 __le64 tx_packets_cos2; 5075 __le64 tx_packets_cos3; 5076 __le64 tx_packets_cos4; 5077 __le64 tx_packets_cos5; 5078 __le64 tx_packets_cos6; 5079 __le64 tx_packets_cos7; 5080 __le64 pfc_pri0_tx_duration_us; 5081 __le64 pfc_pri0_tx_transitions; 5082 __le64 pfc_pri1_tx_duration_us; 5083 __le64 pfc_pri1_tx_transitions; 5084 __le64 pfc_pri2_tx_duration_us; 5085 __le64 pfc_pri2_tx_transitions; 5086 __le64 pfc_pri3_tx_duration_us; 5087 __le64 pfc_pri3_tx_transitions; 5088 __le64 pfc_pri4_tx_duration_us; 5089 __le64 pfc_pri4_tx_transitions; 5090 __le64 pfc_pri5_tx_duration_us; 5091 __le64 pfc_pri5_tx_transitions; 5092 __le64 pfc_pri6_tx_duration_us; 5093 __le64 pfc_pri6_tx_transitions; 5094 __le64 pfc_pri7_tx_duration_us; 5095 __le64 pfc_pri7_tx_transitions; 5096 }; 5097 5098 /* rx_port_stats_ext (size:3904b/488B) */ 5099 struct rx_port_stats_ext { 5100 __le64 link_down_events; 5101 __le64 continuous_pause_events; 5102 __le64 resume_pause_events; 5103 __le64 continuous_roce_pause_events; 5104 __le64 resume_roce_pause_events; 5105 __le64 rx_bytes_cos0; 5106 __le64 rx_bytes_cos1; 5107 __le64 rx_bytes_cos2; 5108 __le64 rx_bytes_cos3; 5109 __le64 rx_bytes_cos4; 5110 __le64 rx_bytes_cos5; 5111 __le64 rx_bytes_cos6; 5112 __le64 rx_bytes_cos7; 5113 __le64 rx_packets_cos0; 5114 __le64 rx_packets_cos1; 5115 __le64 rx_packets_cos2; 5116 __le64 rx_packets_cos3; 5117 __le64 rx_packets_cos4; 5118 __le64 rx_packets_cos5; 5119 __le64 rx_packets_cos6; 5120 __le64 rx_packets_cos7; 5121 __le64 pfc_pri0_rx_duration_us; 5122 __le64 pfc_pri0_rx_transitions; 5123 __le64 pfc_pri1_rx_duration_us; 5124 __le64 pfc_pri1_rx_transitions; 5125 __le64 pfc_pri2_rx_duration_us; 5126 __le64 pfc_pri2_rx_transitions; 5127 __le64 pfc_pri3_rx_duration_us; 5128 __le64 pfc_pri3_rx_transitions; 5129 __le64 pfc_pri4_rx_duration_us; 5130 __le64 pfc_pri4_rx_transitions; 5131 __le64 pfc_pri5_rx_duration_us; 5132 __le64 pfc_pri5_rx_transitions; 5133 __le64 pfc_pri6_rx_duration_us; 5134 __le64 pfc_pri6_rx_transitions; 5135 __le64 pfc_pri7_rx_duration_us; 5136 __le64 pfc_pri7_rx_transitions; 5137 __le64 rx_bits; 5138 __le64 rx_buffer_passed_threshold; 5139 __le64 rx_pcs_symbol_err; 5140 __le64 rx_corrected_bits; 5141 __le64 rx_discard_bytes_cos0; 5142 __le64 rx_discard_bytes_cos1; 5143 __le64 rx_discard_bytes_cos2; 5144 __le64 rx_discard_bytes_cos3; 5145 __le64 rx_discard_bytes_cos4; 5146 __le64 rx_discard_bytes_cos5; 5147 __le64 rx_discard_bytes_cos6; 5148 __le64 rx_discard_bytes_cos7; 5149 __le64 rx_discard_packets_cos0; 5150 __le64 rx_discard_packets_cos1; 5151 __le64 rx_discard_packets_cos2; 5152 __le64 rx_discard_packets_cos3; 5153 __le64 rx_discard_packets_cos4; 5154 __le64 rx_discard_packets_cos5; 5155 __le64 rx_discard_packets_cos6; 5156 __le64 rx_discard_packets_cos7; 5157 __le64 rx_fec_corrected_blocks; 5158 __le64 rx_fec_uncorrectable_blocks; 5159 __le64 rx_filter_miss; 5160 __le64 rx_fec_symbol_err; 5161 }; 5162 5163 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 5164 struct hwrm_port_qstats_ext_input { 5165 __le16 req_type; 5166 __le16 cmpl_ring; 5167 __le16 seq_id; 5168 __le16 target_id; 5169 __le64 resp_addr; 5170 __le16 port_id; 5171 __le16 tx_stat_size; 5172 __le16 rx_stat_size; 5173 u8 flags; 5174 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 5175 u8 unused_0; 5176 __le64 tx_stat_host_addr; 5177 __le64 rx_stat_host_addr; 5178 }; 5179 5180 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 5181 struct hwrm_port_qstats_ext_output { 5182 __le16 error_code; 5183 __le16 req_type; 5184 __le16 seq_id; 5185 __le16 resp_len; 5186 __le16 tx_stat_size; 5187 __le16 rx_stat_size; 5188 __le16 total_active_cos_queues; 5189 u8 flags; 5190 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 5191 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEARED 0x2UL 5192 u8 valid; 5193 }; 5194 5195 /* hwrm_port_lpbk_qstats_input (size:256b/32B) */ 5196 struct hwrm_port_lpbk_qstats_input { 5197 __le16 req_type; 5198 __le16 cmpl_ring; 5199 __le16 seq_id; 5200 __le16 target_id; 5201 __le64 resp_addr; 5202 __le16 lpbk_stat_size; 5203 u8 flags; 5204 #define PORT_LPBK_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5205 u8 unused_0[5]; 5206 __le64 lpbk_stat_host_addr; 5207 }; 5208 5209 /* hwrm_port_lpbk_qstats_output (size:128b/16B) */ 5210 struct hwrm_port_lpbk_qstats_output { 5211 __le16 error_code; 5212 __le16 req_type; 5213 __le16 seq_id; 5214 __le16 resp_len; 5215 __le16 lpbk_stat_size; 5216 u8 unused_0[5]; 5217 u8 valid; 5218 }; 5219 5220 /* port_lpbk_stats (size:640b/80B) */ 5221 struct port_lpbk_stats { 5222 __le64 lpbk_ucast_frames; 5223 __le64 lpbk_mcast_frames; 5224 __le64 lpbk_bcast_frames; 5225 __le64 lpbk_ucast_bytes; 5226 __le64 lpbk_mcast_bytes; 5227 __le64 lpbk_bcast_bytes; 5228 __le64 lpbk_tx_discards; 5229 __le64 lpbk_tx_errors; 5230 __le64 lpbk_rx_discards; 5231 __le64 lpbk_rx_errors; 5232 }; 5233 5234 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 5235 struct hwrm_port_ecn_qstats_input { 5236 __le16 req_type; 5237 __le16 cmpl_ring; 5238 __le16 seq_id; 5239 __le16 target_id; 5240 __le64 resp_addr; 5241 __le16 port_id; 5242 __le16 ecn_stat_buf_size; 5243 u8 flags; 5244 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5245 u8 unused_0[3]; 5246 __le64 ecn_stat_host_addr; 5247 }; 5248 5249 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 5250 struct hwrm_port_ecn_qstats_output { 5251 __le16 error_code; 5252 __le16 req_type; 5253 __le16 seq_id; 5254 __le16 resp_len; 5255 __le16 ecn_stat_buf_size; 5256 u8 mark_en; 5257 u8 unused_0[4]; 5258 u8 valid; 5259 }; 5260 5261 /* port_stats_ecn (size:512b/64B) */ 5262 struct port_stats_ecn { 5263 __le64 mark_cnt_cos0; 5264 __le64 mark_cnt_cos1; 5265 __le64 mark_cnt_cos2; 5266 __le64 mark_cnt_cos3; 5267 __le64 mark_cnt_cos4; 5268 __le64 mark_cnt_cos5; 5269 __le64 mark_cnt_cos6; 5270 __le64 mark_cnt_cos7; 5271 }; 5272 5273 /* hwrm_port_clr_stats_input (size:192b/24B) */ 5274 struct hwrm_port_clr_stats_input { 5275 __le16 req_type; 5276 __le16 cmpl_ring; 5277 __le16 seq_id; 5278 __le16 target_id; 5279 __le64 resp_addr; 5280 __le16 port_id; 5281 u8 flags; 5282 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 5283 u8 unused_0[5]; 5284 }; 5285 5286 /* hwrm_port_clr_stats_output (size:128b/16B) */ 5287 struct hwrm_port_clr_stats_output { 5288 __le16 error_code; 5289 __le16 req_type; 5290 __le16 seq_id; 5291 __le16 resp_len; 5292 u8 unused_0[7]; 5293 u8 valid; 5294 }; 5295 5296 /* hwrm_port_lpbk_clr_stats_input (size:192b/24B) */ 5297 struct hwrm_port_lpbk_clr_stats_input { 5298 __le16 req_type; 5299 __le16 cmpl_ring; 5300 __le16 seq_id; 5301 __le16 target_id; 5302 __le64 resp_addr; 5303 __le16 port_id; 5304 u8 unused_0[6]; 5305 }; 5306 5307 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 5308 struct hwrm_port_lpbk_clr_stats_output { 5309 __le16 error_code; 5310 __le16 req_type; 5311 __le16 seq_id; 5312 __le16 resp_len; 5313 u8 unused_0[7]; 5314 u8 valid; 5315 }; 5316 5317 /* hwrm_port_ts_query_input (size:320b/40B) */ 5318 struct hwrm_port_ts_query_input { 5319 __le16 req_type; 5320 __le16 cmpl_ring; 5321 __le16 seq_id; 5322 __le16 target_id; 5323 __le64 resp_addr; 5324 __le32 flags; 5325 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 5326 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 5327 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 5328 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 5329 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 5330 __le16 port_id; 5331 u8 unused_0[2]; 5332 __le16 enables; 5333 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 5334 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 5335 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 5336 __le16 ts_req_timeout; 5337 __le32 ptp_seq_id; 5338 __le16 ptp_hdr_offset; 5339 u8 unused_1[6]; 5340 }; 5341 5342 /* hwrm_port_ts_query_output (size:192b/24B) */ 5343 struct hwrm_port_ts_query_output { 5344 __le16 error_code; 5345 __le16 req_type; 5346 __le16 seq_id; 5347 __le16 resp_len; 5348 __le64 ptp_msg_ts; 5349 __le16 ptp_msg_seqid; 5350 u8 unused_0[5]; 5351 u8 valid; 5352 }; 5353 5354 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 5355 struct hwrm_port_phy_qcaps_input { 5356 __le16 req_type; 5357 __le16 cmpl_ring; 5358 __le16 seq_id; 5359 __le16 target_id; 5360 __le64 resp_addr; 5361 __le16 port_id; 5362 u8 unused_0[6]; 5363 }; 5364 5365 /* hwrm_port_phy_qcaps_output (size:320b/40B) */ 5366 struct hwrm_port_phy_qcaps_output { 5367 __le16 error_code; 5368 __le16 req_type; 5369 __le16 seq_id; 5370 __le16 resp_len; 5371 u8 flags; 5372 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 5373 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 5374 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 5375 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 5376 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 5377 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 5378 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 5379 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 5380 u8 port_cnt; 5381 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 5382 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 5383 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 5384 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 5385 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 5386 #define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL 5387 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12 5388 __le16 supported_speeds_force_mode; 5389 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 5390 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 5391 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 5392 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 5393 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 5394 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 5395 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 5396 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 5397 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 5398 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 5399 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 5400 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 5401 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 5402 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 5403 __le16 supported_speeds_auto_mode; 5404 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 5405 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 5406 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 5407 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 5408 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 5409 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 5410 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 5411 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 5412 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 5413 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 5414 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 5415 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 5416 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 5417 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 5418 __le16 supported_speeds_eee_mode; 5419 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 5420 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 5421 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 5422 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 5423 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 5424 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 5425 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 5426 __le32 tx_lpi_timer_low; 5427 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 5428 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 5429 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 5430 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 5431 __le32 valid_tx_lpi_timer_high; 5432 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 5433 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 5434 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 5435 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 5436 __le16 supported_pam4_speeds_auto_mode; 5437 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 5438 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 5439 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 5440 __le16 supported_pam4_speeds_force_mode; 5441 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 5442 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 5443 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 5444 __le16 flags2; 5445 #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 5446 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 5447 #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL 5448 #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL 5449 #define PORT_PHY_QCAPS_RESP_FLAGS2_REMOTE_LPBK_UNSUPPORTED 0x10UL 5450 u8 internal_port_cnt; 5451 u8 unused_0; 5452 __le16 supported_speeds2_force_mode; 5453 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB 0x1UL 5454 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB 0x2UL 5455 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB 0x4UL 5456 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB 0x8UL 5457 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB 0x10UL 5458 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB 0x20UL 5459 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 0x40UL 5460 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 0x80UL 5461 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 0x100UL 5462 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 0x200UL 5463 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 0x400UL 5464 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 0x800UL 5465 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 0x1000UL 5466 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 0x2000UL 5467 __le16 supported_speeds2_auto_mode; 5468 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB 0x1UL 5469 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB 0x2UL 5470 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB 0x4UL 5471 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB 0x8UL 5472 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB 0x10UL 5473 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB 0x20UL 5474 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 0x40UL 5475 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 0x80UL 5476 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 0x100UL 5477 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 0x200UL 5478 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 0x400UL 5479 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL 5480 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL 5481 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL 5482 u8 unused_1[3]; 5483 u8 valid; 5484 }; 5485 5486 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 5487 struct hwrm_port_phy_i2c_read_input { 5488 __le16 req_type; 5489 __le16 cmpl_ring; 5490 __le16 seq_id; 5491 __le16 target_id; 5492 __le64 resp_addr; 5493 __le32 flags; 5494 __le32 enables; 5495 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 5496 #define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL 5497 __le16 port_id; 5498 u8 i2c_slave_addr; 5499 u8 bank_number; 5500 __le16 page_number; 5501 __le16 page_offset; 5502 u8 data_length; 5503 u8 unused_1[7]; 5504 }; 5505 5506 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 5507 struct hwrm_port_phy_i2c_read_output { 5508 __le16 error_code; 5509 __le16 req_type; 5510 __le16 seq_id; 5511 __le16 resp_len; 5512 __le32 data[16]; 5513 u8 unused_0[7]; 5514 u8 valid; 5515 }; 5516 5517 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 5518 struct hwrm_port_phy_mdio_write_input { 5519 __le16 req_type; 5520 __le16 cmpl_ring; 5521 __le16 seq_id; 5522 __le16 target_id; 5523 __le64 resp_addr; 5524 __le32 unused_0[2]; 5525 __le16 port_id; 5526 u8 phy_addr; 5527 u8 dev_addr; 5528 __le16 reg_addr; 5529 __le16 reg_data; 5530 u8 cl45_mdio; 5531 u8 unused_1[7]; 5532 }; 5533 5534 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 5535 struct hwrm_port_phy_mdio_write_output { 5536 __le16 error_code; 5537 __le16 req_type; 5538 __le16 seq_id; 5539 __le16 resp_len; 5540 u8 unused_0[7]; 5541 u8 valid; 5542 }; 5543 5544 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 5545 struct hwrm_port_phy_mdio_read_input { 5546 __le16 req_type; 5547 __le16 cmpl_ring; 5548 __le16 seq_id; 5549 __le16 target_id; 5550 __le64 resp_addr; 5551 __le32 unused_0[2]; 5552 __le16 port_id; 5553 u8 phy_addr; 5554 u8 dev_addr; 5555 __le16 reg_addr; 5556 u8 cl45_mdio; 5557 u8 unused_1; 5558 }; 5559 5560 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 5561 struct hwrm_port_phy_mdio_read_output { 5562 __le16 error_code; 5563 __le16 req_type; 5564 __le16 seq_id; 5565 __le16 resp_len; 5566 __le16 reg_data; 5567 u8 unused_0[5]; 5568 u8 valid; 5569 }; 5570 5571 /* hwrm_port_led_cfg_input (size:512b/64B) */ 5572 struct hwrm_port_led_cfg_input { 5573 __le16 req_type; 5574 __le16 cmpl_ring; 5575 __le16 seq_id; 5576 __le16 target_id; 5577 __le64 resp_addr; 5578 __le32 enables; 5579 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 5580 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 5581 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 5582 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 5583 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 5584 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 5585 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 5586 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 5587 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 5588 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 5589 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 5590 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 5591 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 5592 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 5593 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 5594 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 5595 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 5596 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 5597 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 5598 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 5599 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 5600 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 5601 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 5602 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 5603 __le16 port_id; 5604 u8 num_leds; 5605 u8 rsvd; 5606 u8 led0_id; 5607 u8 led0_state; 5608 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 5609 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 5610 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 5611 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 5612 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 5613 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 5614 u8 led0_color; 5615 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 5616 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 5617 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 5618 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 5619 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 5620 u8 unused_0; 5621 __le16 led0_blink_on; 5622 __le16 led0_blink_off; 5623 u8 led0_group_id; 5624 u8 rsvd0; 5625 u8 led1_id; 5626 u8 led1_state; 5627 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 5628 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 5629 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 5630 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 5631 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 5632 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 5633 u8 led1_color; 5634 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 5635 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 5636 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 5637 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 5638 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 5639 u8 unused_1; 5640 __le16 led1_blink_on; 5641 __le16 led1_blink_off; 5642 u8 led1_group_id; 5643 u8 rsvd1; 5644 u8 led2_id; 5645 u8 led2_state; 5646 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 5647 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 5648 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 5649 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 5650 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 5651 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 5652 u8 led2_color; 5653 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 5654 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 5655 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 5656 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 5657 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 5658 u8 unused_2; 5659 __le16 led2_blink_on; 5660 __le16 led2_blink_off; 5661 u8 led2_group_id; 5662 u8 rsvd2; 5663 u8 led3_id; 5664 u8 led3_state; 5665 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 5666 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 5667 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 5668 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 5669 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 5670 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 5671 u8 led3_color; 5672 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 5673 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 5674 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 5675 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 5676 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 5677 u8 unused_3; 5678 __le16 led3_blink_on; 5679 __le16 led3_blink_off; 5680 u8 led3_group_id; 5681 u8 rsvd3; 5682 }; 5683 5684 /* hwrm_port_led_cfg_output (size:128b/16B) */ 5685 struct hwrm_port_led_cfg_output { 5686 __le16 error_code; 5687 __le16 req_type; 5688 __le16 seq_id; 5689 __le16 resp_len; 5690 u8 unused_0[7]; 5691 u8 valid; 5692 }; 5693 5694 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 5695 struct hwrm_port_led_qcfg_input { 5696 __le16 req_type; 5697 __le16 cmpl_ring; 5698 __le16 seq_id; 5699 __le16 target_id; 5700 __le64 resp_addr; 5701 __le16 port_id; 5702 u8 unused_0[6]; 5703 }; 5704 5705 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 5706 struct hwrm_port_led_qcfg_output { 5707 __le16 error_code; 5708 __le16 req_type; 5709 __le16 seq_id; 5710 __le16 resp_len; 5711 u8 num_leds; 5712 u8 led0_id; 5713 u8 led0_type; 5714 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 5715 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 5716 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 5717 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 5718 u8 led0_state; 5719 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 5720 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 5721 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 5722 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 5723 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 5724 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 5725 u8 led0_color; 5726 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 5727 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 5728 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 5729 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 5730 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 5731 u8 unused_0; 5732 __le16 led0_blink_on; 5733 __le16 led0_blink_off; 5734 u8 led0_group_id; 5735 u8 led1_id; 5736 u8 led1_type; 5737 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 5738 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 5739 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 5740 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 5741 u8 led1_state; 5742 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 5743 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 5744 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 5745 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 5746 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 5747 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 5748 u8 led1_color; 5749 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 5750 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 5751 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 5752 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 5753 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 5754 u8 unused_1; 5755 __le16 led1_blink_on; 5756 __le16 led1_blink_off; 5757 u8 led1_group_id; 5758 u8 led2_id; 5759 u8 led2_type; 5760 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 5761 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 5762 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 5763 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 5764 u8 led2_state; 5765 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 5766 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 5767 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 5768 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 5769 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 5770 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 5771 u8 led2_color; 5772 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 5773 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 5774 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 5775 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 5776 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 5777 u8 unused_2; 5778 __le16 led2_blink_on; 5779 __le16 led2_blink_off; 5780 u8 led2_group_id; 5781 u8 led3_id; 5782 u8 led3_type; 5783 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 5784 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 5785 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 5786 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 5787 u8 led3_state; 5788 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 5789 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 5790 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 5791 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 5792 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 5793 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 5794 u8 led3_color; 5795 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 5796 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 5797 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 5798 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 5799 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 5800 u8 unused_3; 5801 __le16 led3_blink_on; 5802 __le16 led3_blink_off; 5803 u8 led3_group_id; 5804 u8 unused_4[6]; 5805 u8 valid; 5806 }; 5807 5808 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 5809 struct hwrm_port_led_qcaps_input { 5810 __le16 req_type; 5811 __le16 cmpl_ring; 5812 __le16 seq_id; 5813 __le16 target_id; 5814 __le64 resp_addr; 5815 __le16 port_id; 5816 u8 unused_0[6]; 5817 }; 5818 5819 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 5820 struct hwrm_port_led_qcaps_output { 5821 __le16 error_code; 5822 __le16 req_type; 5823 __le16 seq_id; 5824 __le16 resp_len; 5825 u8 num_leds; 5826 u8 unused[3]; 5827 u8 led0_id; 5828 u8 led0_type; 5829 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 5830 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 5831 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 5832 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 5833 u8 led0_group_id; 5834 u8 unused_0; 5835 __le16 led0_state_caps; 5836 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 5837 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 5838 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 5839 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5840 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5841 __le16 led0_color_caps; 5842 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 5843 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5844 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5845 u8 led1_id; 5846 u8 led1_type; 5847 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 5848 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 5849 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 5850 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 5851 u8 led1_group_id; 5852 u8 unused_1; 5853 __le16 led1_state_caps; 5854 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 5855 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 5856 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 5857 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5858 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5859 __le16 led1_color_caps; 5860 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 5861 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5862 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5863 u8 led2_id; 5864 u8 led2_type; 5865 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 5866 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 5867 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 5868 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 5869 u8 led2_group_id; 5870 u8 unused_2; 5871 __le16 led2_state_caps; 5872 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 5873 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 5874 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 5875 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5876 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5877 __le16 led2_color_caps; 5878 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 5879 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5880 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5881 u8 led3_id; 5882 u8 led3_type; 5883 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 5884 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 5885 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 5886 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 5887 u8 led3_group_id; 5888 u8 unused_3; 5889 __le16 led3_state_caps; 5890 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 5891 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 5892 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 5893 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5894 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5895 __le16 led3_color_caps; 5896 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 5897 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5898 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5899 u8 unused_4[3]; 5900 u8 valid; 5901 }; 5902 5903 /* hwrm_port_mac_qcaps_input (size:192b/24B) */ 5904 struct hwrm_port_mac_qcaps_input { 5905 __le16 req_type; 5906 __le16 cmpl_ring; 5907 __le16 seq_id; 5908 __le16 target_id; 5909 __le64 resp_addr; 5910 __le16 port_id; 5911 u8 unused_0[6]; 5912 }; 5913 5914 /* hwrm_port_mac_qcaps_output (size:128b/16B) */ 5915 struct hwrm_port_mac_qcaps_output { 5916 __le16 error_code; 5917 __le16 req_type; 5918 __le16 seq_id; 5919 __le16 resp_len; 5920 u8 flags; 5921 #define PORT_MAC_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x1UL 5922 #define PORT_MAC_QCAPS_RESP_FLAGS_REMOTE_LPBK_SUPPORTED 0x2UL 5923 u8 unused_0[6]; 5924 u8 valid; 5925 }; 5926 5927 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 5928 struct hwrm_queue_qportcfg_input { 5929 __le16 req_type; 5930 __le16 cmpl_ring; 5931 __le16 seq_id; 5932 __le16 target_id; 5933 __le64 resp_addr; 5934 __le32 flags; 5935 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 5936 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 5937 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 5938 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 5939 __le16 port_id; 5940 u8 drv_qmap_cap; 5941 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 5942 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 5943 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 5944 u8 unused_0; 5945 }; 5946 5947 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 5948 struct hwrm_queue_qportcfg_output { 5949 __le16 error_code; 5950 __le16 req_type; 5951 __le16 seq_id; 5952 __le16 resp_len; 5953 u8 max_configurable_queues; 5954 u8 max_configurable_lossless_queues; 5955 u8 queue_cfg_allowed; 5956 u8 queue_cfg_info; 5957 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5958 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 5959 u8 queue_pfcenable_cfg_allowed; 5960 u8 queue_pri2cos_cfg_allowed; 5961 u8 queue_cos2bw_cfg_allowed; 5962 u8 queue_id0; 5963 u8 queue_id0_service_profile; 5964 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 5965 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 5966 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5967 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5968 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5969 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 5970 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 5971 u8 queue_id1; 5972 u8 queue_id1_service_profile; 5973 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 5974 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 5975 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5976 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5977 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5978 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 5979 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 5980 u8 queue_id2; 5981 u8 queue_id2_service_profile; 5982 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 5983 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 5984 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5985 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5986 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5987 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 5988 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 5989 u8 queue_id3; 5990 u8 queue_id3_service_profile; 5991 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 5992 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 5993 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5994 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5995 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5996 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 5997 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 5998 u8 queue_id4; 5999 u8 queue_id4_service_profile; 6000 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 6001 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 6002 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6003 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6004 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6005 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 6006 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 6007 u8 queue_id5; 6008 u8 queue_id5_service_profile; 6009 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 6010 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 6011 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6012 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6013 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6014 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 6015 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 6016 u8 queue_id6; 6017 u8 queue_id6_service_profile; 6018 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 6019 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 6020 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6021 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6022 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6023 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 6024 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 6025 u8 queue_id7; 6026 u8 queue_id7_service_profile; 6027 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 6028 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 6029 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6030 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6031 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6032 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 6033 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 6034 u8 queue_id0_service_profile_type; 6035 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6036 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 6037 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 6038 char qid0_name[16]; 6039 char qid1_name[16]; 6040 char qid2_name[16]; 6041 char qid3_name[16]; 6042 char qid4_name[16]; 6043 char qid5_name[16]; 6044 char qid6_name[16]; 6045 char qid7_name[16]; 6046 u8 queue_id1_service_profile_type; 6047 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6048 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 6049 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 6050 u8 queue_id2_service_profile_type; 6051 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6052 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 6053 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 6054 u8 queue_id3_service_profile_type; 6055 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6056 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 6057 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 6058 u8 queue_id4_service_profile_type; 6059 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6060 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 6061 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 6062 u8 queue_id5_service_profile_type; 6063 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6064 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 6065 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 6066 u8 queue_id6_service_profile_type; 6067 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6068 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 6069 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 6070 u8 queue_id7_service_profile_type; 6071 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6072 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 6073 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 6074 u8 valid; 6075 }; 6076 6077 /* hwrm_queue_qcfg_input (size:192b/24B) */ 6078 struct hwrm_queue_qcfg_input { 6079 __le16 req_type; 6080 __le16 cmpl_ring; 6081 __le16 seq_id; 6082 __le16 target_id; 6083 __le64 resp_addr; 6084 __le32 flags; 6085 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 6086 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 6087 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 6088 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 6089 __le32 queue_id; 6090 }; 6091 6092 /* hwrm_queue_qcfg_output (size:128b/16B) */ 6093 struct hwrm_queue_qcfg_output { 6094 __le16 error_code; 6095 __le16 req_type; 6096 __le16 seq_id; 6097 __le16 resp_len; 6098 __le32 queue_len; 6099 u8 service_profile; 6100 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 6101 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 6102 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 6103 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 6104 u8 queue_cfg_info; 6105 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6106 u8 unused_0; 6107 u8 valid; 6108 }; 6109 6110 /* hwrm_queue_cfg_input (size:320b/40B) */ 6111 struct hwrm_queue_cfg_input { 6112 __le16 req_type; 6113 __le16 cmpl_ring; 6114 __le16 seq_id; 6115 __le16 target_id; 6116 __le64 resp_addr; 6117 __le32 flags; 6118 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 6119 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 6120 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 6121 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 6122 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 6123 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 6124 __le32 enables; 6125 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 6126 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 6127 __le32 queue_id; 6128 __le32 dflt_len; 6129 u8 service_profile; 6130 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 6131 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 6132 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 6133 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 6134 u8 unused_0[7]; 6135 }; 6136 6137 /* hwrm_queue_cfg_output (size:128b/16B) */ 6138 struct hwrm_queue_cfg_output { 6139 __le16 error_code; 6140 __le16 req_type; 6141 __le16 seq_id; 6142 __le16 resp_len; 6143 u8 unused_0[7]; 6144 u8 valid; 6145 }; 6146 6147 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 6148 struct hwrm_queue_pfcenable_qcfg_input { 6149 __le16 req_type; 6150 __le16 cmpl_ring; 6151 __le16 seq_id; 6152 __le16 target_id; 6153 __le64 resp_addr; 6154 __le16 port_id; 6155 u8 unused_0[6]; 6156 }; 6157 6158 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 6159 struct hwrm_queue_pfcenable_qcfg_output { 6160 __le16 error_code; 6161 __le16 req_type; 6162 __le16 seq_id; 6163 __le16 resp_len; 6164 __le32 flags; 6165 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 6166 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 6167 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 6168 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 6169 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 6170 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 6171 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 6172 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 6173 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 6174 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 6175 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 6176 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 6177 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 6178 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 6179 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 6180 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 6181 u8 unused_0[3]; 6182 u8 valid; 6183 }; 6184 6185 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 6186 struct hwrm_queue_pfcenable_cfg_input { 6187 __le16 req_type; 6188 __le16 cmpl_ring; 6189 __le16 seq_id; 6190 __le16 target_id; 6191 __le64 resp_addr; 6192 __le32 flags; 6193 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 6194 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 6195 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 6196 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 6197 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 6198 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 6199 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 6200 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 6201 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 6202 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 6203 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 6204 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 6205 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 6206 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 6207 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 6208 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 6209 __le16 port_id; 6210 u8 unused_0[2]; 6211 }; 6212 6213 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 6214 struct hwrm_queue_pfcenable_cfg_output { 6215 __le16 error_code; 6216 __le16 req_type; 6217 __le16 seq_id; 6218 __le16 resp_len; 6219 u8 unused_0[7]; 6220 u8 valid; 6221 }; 6222 6223 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 6224 struct hwrm_queue_pri2cos_qcfg_input { 6225 __le16 req_type; 6226 __le16 cmpl_ring; 6227 __le16 seq_id; 6228 __le16 target_id; 6229 __le64 resp_addr; 6230 __le32 flags; 6231 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 6232 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 6233 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 6234 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 6235 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 6236 u8 port_id; 6237 u8 unused_0[3]; 6238 }; 6239 6240 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 6241 struct hwrm_queue_pri2cos_qcfg_output { 6242 __le16 error_code; 6243 __le16 req_type; 6244 __le16 seq_id; 6245 __le16 resp_len; 6246 u8 pri0_cos_queue_id; 6247 u8 pri1_cos_queue_id; 6248 u8 pri2_cos_queue_id; 6249 u8 pri3_cos_queue_id; 6250 u8 pri4_cos_queue_id; 6251 u8 pri5_cos_queue_id; 6252 u8 pri6_cos_queue_id; 6253 u8 pri7_cos_queue_id; 6254 u8 queue_cfg_info; 6255 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6256 u8 unused_0[6]; 6257 u8 valid; 6258 }; 6259 6260 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 6261 struct hwrm_queue_pri2cos_cfg_input { 6262 __le16 req_type; 6263 __le16 cmpl_ring; 6264 __le16 seq_id; 6265 __le16 target_id; 6266 __le64 resp_addr; 6267 __le32 flags; 6268 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 6269 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 6270 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 6271 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 6272 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 6273 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 6274 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 6275 __le32 enables; 6276 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 6277 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 6278 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 6279 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 6280 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 6281 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 6282 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 6283 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 6284 u8 port_id; 6285 u8 pri0_cos_queue_id; 6286 u8 pri1_cos_queue_id; 6287 u8 pri2_cos_queue_id; 6288 u8 pri3_cos_queue_id; 6289 u8 pri4_cos_queue_id; 6290 u8 pri5_cos_queue_id; 6291 u8 pri6_cos_queue_id; 6292 u8 pri7_cos_queue_id; 6293 u8 unused_0[7]; 6294 }; 6295 6296 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 6297 struct hwrm_queue_pri2cos_cfg_output { 6298 __le16 error_code; 6299 __le16 req_type; 6300 __le16 seq_id; 6301 __le16 resp_len; 6302 u8 unused_0[7]; 6303 u8 valid; 6304 }; 6305 6306 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 6307 struct hwrm_queue_cos2bw_qcfg_input { 6308 __le16 req_type; 6309 __le16 cmpl_ring; 6310 __le16 seq_id; 6311 __le16 target_id; 6312 __le64 resp_addr; 6313 __le16 port_id; 6314 u8 unused_0[6]; 6315 }; 6316 6317 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 6318 struct hwrm_queue_cos2bw_qcfg_output { 6319 __le16 error_code; 6320 __le16 req_type; 6321 __le16 seq_id; 6322 __le16 resp_len; 6323 u8 queue_id0; 6324 u8 unused_0; 6325 __le16 unused_1; 6326 __le32 queue_id0_min_bw; 6327 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6328 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6329 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6330 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6331 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6332 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 6333 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6334 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6335 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6336 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6337 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6338 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6339 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6340 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6341 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6342 __le32 queue_id0_max_bw; 6343 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6344 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6345 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6346 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6347 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6348 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 6349 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6350 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6351 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6352 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6353 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6354 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6355 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6356 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6357 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6358 u8 queue_id0_tsa_assign; 6359 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6360 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6361 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6362 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6363 u8 queue_id0_pri_lvl; 6364 u8 queue_id0_bw_weight; 6365 struct { 6366 u8 queue_id; 6367 __le32 queue_id_min_bw; 6368 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6369 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6370 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6371 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6372 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6373 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES 6374 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6375 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6376 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6377 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6378 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6379 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6380 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6381 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6382 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6383 __le32 queue_id_max_bw; 6384 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6385 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6386 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6387 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6388 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6389 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES 6390 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6391 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6392 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6393 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6394 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6395 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6396 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6397 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6398 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6399 u8 queue_id_tsa_assign; 6400 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6401 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6402 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6403 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6404 u8 queue_id_pri_lvl; 6405 u8 queue_id_bw_weight; 6406 } __packed cfg[7]; 6407 u8 unused_2[4]; 6408 u8 valid; 6409 }; 6410 6411 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 6412 struct hwrm_queue_cos2bw_cfg_input { 6413 __le16 req_type; 6414 __le16 cmpl_ring; 6415 __le16 seq_id; 6416 __le16 target_id; 6417 __le64 resp_addr; 6418 __le32 flags; 6419 __le32 enables; 6420 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 6421 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 6422 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 6423 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 6424 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 6425 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 6426 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 6427 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 6428 __le16 port_id; 6429 u8 queue_id0; 6430 u8 unused_0; 6431 __le32 queue_id0_min_bw; 6432 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6433 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6434 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6435 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6436 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6437 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 6438 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6439 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6440 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6441 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6442 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6443 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6444 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6445 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6446 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6447 __le32 queue_id0_max_bw; 6448 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6449 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6450 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6451 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6453 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 6454 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6455 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6456 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6457 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6458 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6459 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6460 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6461 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6462 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6463 u8 queue_id0_tsa_assign; 6464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6465 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6467 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6468 u8 queue_id0_pri_lvl; 6469 u8 queue_id0_bw_weight; 6470 struct { 6471 u8 queue_id; 6472 __le32 queue_id_min_bw; 6473 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6477 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6478 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES 6479 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6483 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6484 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6485 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6486 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6487 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6488 __le32 queue_id_max_bw; 6489 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6490 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6491 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6492 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6493 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6494 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES 6495 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6496 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6497 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6498 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6499 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6500 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6501 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6502 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6503 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6504 u8 queue_id_tsa_assign; 6505 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6506 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6507 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6508 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6509 u8 queue_id_pri_lvl; 6510 u8 queue_id_bw_weight; 6511 } __packed cfg[7]; 6512 u8 unused_1[5]; 6513 }; 6514 6515 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 6516 struct hwrm_queue_cos2bw_cfg_output { 6517 __le16 error_code; 6518 __le16 req_type; 6519 __le16 seq_id; 6520 __le16 resp_len; 6521 u8 unused_0[7]; 6522 u8 valid; 6523 }; 6524 6525 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 6526 struct hwrm_queue_dscp_qcaps_input { 6527 __le16 req_type; 6528 __le16 cmpl_ring; 6529 __le16 seq_id; 6530 __le16 target_id; 6531 __le64 resp_addr; 6532 u8 port_id; 6533 u8 unused_0[7]; 6534 }; 6535 6536 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 6537 struct hwrm_queue_dscp_qcaps_output { 6538 __le16 error_code; 6539 __le16 req_type; 6540 __le16 seq_id; 6541 __le16 resp_len; 6542 u8 num_dscp_bits; 6543 u8 unused_0; 6544 __le16 max_entries; 6545 u8 unused_1[3]; 6546 u8 valid; 6547 }; 6548 6549 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 6550 struct hwrm_queue_dscp2pri_qcfg_input { 6551 __le16 req_type; 6552 __le16 cmpl_ring; 6553 __le16 seq_id; 6554 __le16 target_id; 6555 __le64 resp_addr; 6556 __le64 dest_data_addr; 6557 u8 port_id; 6558 u8 unused_0; 6559 __le16 dest_data_buffer_size; 6560 u8 unused_1[4]; 6561 }; 6562 6563 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 6564 struct hwrm_queue_dscp2pri_qcfg_output { 6565 __le16 error_code; 6566 __le16 req_type; 6567 __le16 seq_id; 6568 __le16 resp_len; 6569 __le16 entry_cnt; 6570 u8 default_pri; 6571 u8 unused_0[4]; 6572 u8 valid; 6573 }; 6574 6575 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 6576 struct hwrm_queue_dscp2pri_cfg_input { 6577 __le16 req_type; 6578 __le16 cmpl_ring; 6579 __le16 seq_id; 6580 __le16 target_id; 6581 __le64 resp_addr; 6582 __le64 src_data_addr; 6583 __le32 flags; 6584 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 6585 __le32 enables; 6586 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 6587 u8 port_id; 6588 u8 default_pri; 6589 __le16 entry_cnt; 6590 u8 unused_0[4]; 6591 }; 6592 6593 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 6594 struct hwrm_queue_dscp2pri_cfg_output { 6595 __le16 error_code; 6596 __le16 req_type; 6597 __le16 seq_id; 6598 __le16 resp_len; 6599 u8 unused_0[7]; 6600 u8 valid; 6601 }; 6602 6603 /* hwrm_vnic_alloc_input (size:192b/24B) */ 6604 struct hwrm_vnic_alloc_input { 6605 __le16 req_type; 6606 __le16 cmpl_ring; 6607 __le16 seq_id; 6608 __le16 target_id; 6609 __le64 resp_addr; 6610 __le32 flags; 6611 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 6612 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 6613 __le16 virtio_net_fid; 6614 u8 unused_0[2]; 6615 }; 6616 6617 /* hwrm_vnic_alloc_output (size:128b/16B) */ 6618 struct hwrm_vnic_alloc_output { 6619 __le16 error_code; 6620 __le16 req_type; 6621 __le16 seq_id; 6622 __le16 resp_len; 6623 __le32 vnic_id; 6624 u8 unused_0[3]; 6625 u8 valid; 6626 }; 6627 6628 /* hwrm_vnic_update_input (size:256b/32B) */ 6629 struct hwrm_vnic_update_input { 6630 __le16 req_type; 6631 __le16 cmpl_ring; 6632 __le16 seq_id; 6633 __le16 target_id; 6634 __le64 resp_addr; 6635 __le32 vnic_id; 6636 __le32 enables; 6637 #define VNIC_UPDATE_REQ_ENABLES_VNIC_STATE_VALID 0x1UL 6638 #define VNIC_UPDATE_REQ_ENABLES_MRU_VALID 0x2UL 6639 #define VNIC_UPDATE_REQ_ENABLES_METADATA_FORMAT_TYPE_VALID 0x4UL 6640 u8 vnic_state; 6641 #define VNIC_UPDATE_REQ_VNIC_STATE_NORMAL 0x0UL 6642 #define VNIC_UPDATE_REQ_VNIC_STATE_DROP 0x1UL 6643 #define VNIC_UPDATE_REQ_VNIC_STATE_LAST VNIC_UPDATE_REQ_VNIC_STATE_DROP 6644 u8 metadata_format_type; 6645 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_0 0x0UL 6646 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_1 0x1UL 6647 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_2 0x2UL 6648 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_3 0x3UL 6649 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4 0x4UL 6650 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_LAST VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4 6651 __le16 mru; 6652 u8 unused_1[4]; 6653 }; 6654 6655 /* hwrm_vnic_update_output (size:128b/16B) */ 6656 struct hwrm_vnic_update_output { 6657 __le16 error_code; 6658 __le16 req_type; 6659 __le16 seq_id; 6660 __le16 resp_len; 6661 u8 unused_0[7]; 6662 u8 valid; 6663 }; 6664 6665 /* hwrm_vnic_free_input (size:192b/24B) */ 6666 struct hwrm_vnic_free_input { 6667 __le16 req_type; 6668 __le16 cmpl_ring; 6669 __le16 seq_id; 6670 __le16 target_id; 6671 __le64 resp_addr; 6672 __le32 vnic_id; 6673 u8 unused_0[4]; 6674 }; 6675 6676 /* hwrm_vnic_free_output (size:128b/16B) */ 6677 struct hwrm_vnic_free_output { 6678 __le16 error_code; 6679 __le16 req_type; 6680 __le16 seq_id; 6681 __le16 resp_len; 6682 u8 unused_0[7]; 6683 u8 valid; 6684 }; 6685 6686 /* hwrm_vnic_cfg_input (size:384b/48B) */ 6687 struct hwrm_vnic_cfg_input { 6688 __le16 req_type; 6689 __le16 cmpl_ring; 6690 __le16 seq_id; 6691 __le16 target_id; 6692 __le64 resp_addr; 6693 __le32 flags; 6694 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6695 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6696 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 6697 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 6698 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6699 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 6700 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6701 #define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE 0x80UL 6702 __le32 enables; 6703 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6704 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6705 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6706 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6707 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 6708 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 6709 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 6710 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6711 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6712 #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL 6713 __le16 vnic_id; 6714 __le16 dflt_ring_grp; 6715 __le16 rss_rule; 6716 __le16 cos_rule; 6717 __le16 lb_rule; 6718 __le16 mru; 6719 __le16 default_rx_ring_id; 6720 __le16 default_cmpl_ring_id; 6721 __le16 queue_id; 6722 u8 rx_csum_v2_mode; 6723 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6724 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6725 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6726 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6727 u8 l2_cqe_mode; 6728 #define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL 6729 #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL 6730 #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL 6731 #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED 6732 u8 unused0[4]; 6733 }; 6734 6735 /* hwrm_vnic_cfg_output (size:128b/16B) */ 6736 struct hwrm_vnic_cfg_output { 6737 __le16 error_code; 6738 __le16 req_type; 6739 __le16 seq_id; 6740 __le16 resp_len; 6741 u8 unused_0[7]; 6742 u8 valid; 6743 }; 6744 6745 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 6746 struct hwrm_vnic_qcaps_input { 6747 __le16 req_type; 6748 __le16 cmpl_ring; 6749 __le16 seq_id; 6750 __le16 target_id; 6751 __le64 resp_addr; 6752 __le32 enables; 6753 u8 unused_0[4]; 6754 }; 6755 6756 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 6757 struct hwrm_vnic_qcaps_output { 6758 __le16 error_code; 6759 __le16 req_type; 6760 __le16 seq_id; 6761 __le16 resp_len; 6762 __le16 mru; 6763 u8 unused_0[2]; 6764 __le32 flags; 6765 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 6766 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 6767 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 6768 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 6769 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 6770 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6771 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 6772 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 6773 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6774 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 6775 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 6776 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 6777 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 6778 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6779 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 6780 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL 6781 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL 6782 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL 6783 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 6784 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL 6785 #define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL 6786 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL 6787 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL 6788 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL 6789 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL 6790 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL 6791 #define VNIC_QCAPS_RESP_FLAGS_PORTCOS_MAPPING_MODE 0x4000000UL 6792 #define VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED 0x8000000UL 6793 #define VNIC_QCAPS_RESP_FLAGS_VNIC_RSS_HASH_MODE_CAP 0x10000000UL 6794 #define VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP 0x20000000UL 6795 #define VNIC_QCAPS_RESP_FLAGS_RE_FLUSH_CAP 0x40000000UL 6796 __le16 max_aggs_supported; 6797 u8 unused_1[5]; 6798 u8 valid; 6799 }; 6800 6801 /* hwrm_vnic_tpa_cfg_input (size:384b/48B) */ 6802 struct hwrm_vnic_tpa_cfg_input { 6803 __le16 req_type; 6804 __le16 cmpl_ring; 6805 __le16 seq_id; 6806 __le16 target_id; 6807 __le64 resp_addr; 6808 __le32 flags; 6809 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6810 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6811 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6812 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6813 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6814 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6815 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6816 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 6817 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6818 __le32 enables; 6819 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6820 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6821 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6822 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6823 #define VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN 0x10UL 6824 __le16 vnic_id; 6825 __le16 max_agg_segs; 6826 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6827 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6828 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6829 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6830 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6831 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6832 __le16 max_aggs; 6833 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6834 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6835 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6836 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6837 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6838 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6839 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6840 u8 unused_0[2]; 6841 __le32 max_agg_timer; 6842 __le32 min_agg_len; 6843 __le32 tnl_tpa_en_bitmap; 6844 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 6845 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 6846 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 6847 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE 0x8UL 6848 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4 0x10UL 6849 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6 0x20UL 6850 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 6851 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 6852 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 6853 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 6854 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 6855 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 6856 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 6857 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 6858 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 6859 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 6860 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 6861 u8 unused_1[4]; 6862 }; 6863 6864 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6865 struct hwrm_vnic_tpa_cfg_output { 6866 __le16 error_code; 6867 __le16 req_type; 6868 __le16 seq_id; 6869 __le16 resp_len; 6870 u8 unused_0[7]; 6871 u8 valid; 6872 }; 6873 6874 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6875 struct hwrm_vnic_tpa_qcfg_input { 6876 __le16 req_type; 6877 __le16 cmpl_ring; 6878 __le16 seq_id; 6879 __le16 target_id; 6880 __le64 resp_addr; 6881 __le16 vnic_id; 6882 u8 unused_0[6]; 6883 }; 6884 6885 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6886 struct hwrm_vnic_tpa_qcfg_output { 6887 __le16 error_code; 6888 __le16 req_type; 6889 __le16 seq_id; 6890 __le16 resp_len; 6891 __le32 flags; 6892 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6893 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6894 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6895 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6896 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6897 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6898 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6899 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6900 __le16 max_agg_segs; 6901 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6902 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6903 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6904 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6905 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6906 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6907 __le16 max_aggs; 6908 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6909 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6910 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6911 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6912 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6913 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6914 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6915 __le32 max_agg_timer; 6916 __le32 min_agg_len; 6917 __le32 tnl_tpa_en_bitmap; 6918 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 6919 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 6920 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 6921 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE 0x8UL 6922 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV4 0x10UL 6923 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV6 0x20UL 6924 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 6925 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 6926 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 6927 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 6928 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 6929 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 6930 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 6931 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 6932 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 6933 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 6934 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 6935 u8 unused_0[3]; 6936 u8 valid; 6937 }; 6938 6939 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6940 struct hwrm_vnic_rss_cfg_input { 6941 __le16 req_type; 6942 __le16 cmpl_ring; 6943 __le16 seq_id; 6944 __le16 target_id; 6945 __le64 resp_addr; 6946 __le32 hash_type; 6947 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6948 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6949 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6950 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6951 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6952 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 6953 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 6954 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL 6955 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL 6956 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL 6957 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL 6958 __le16 vnic_id; 6959 u8 ring_table_pair_index; 6960 u8 hash_mode_flags; 6961 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 6962 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6963 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6964 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6965 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6966 __le64 ring_grp_tbl_addr; 6967 __le64 hash_key_tbl_addr; 6968 __le16 rss_ctx_idx; 6969 u8 flags; 6970 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 6971 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 6972 #define VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT 0x4UL 6973 u8 ring_select_mode; 6974 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL 6975 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL 6976 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 6977 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 6978 u8 unused_1[4]; 6979 }; 6980 6981 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6982 struct hwrm_vnic_rss_cfg_output { 6983 __le16 error_code; 6984 __le16 req_type; 6985 __le16 seq_id; 6986 __le16 resp_len; 6987 u8 unused_0[7]; 6988 u8 valid; 6989 }; 6990 6991 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 6992 struct hwrm_vnic_rss_cfg_cmd_err { 6993 u8 code; 6994 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 6995 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 6996 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 6997 u8 unused_0[7]; 6998 }; 6999 7000 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ 7001 struct hwrm_vnic_rss_qcfg_input { 7002 __le16 req_type; 7003 __le16 cmpl_ring; 7004 __le16 seq_id; 7005 __le16 target_id; 7006 __le64 resp_addr; 7007 __le16 rss_ctx_idx; 7008 __le16 vnic_id; 7009 u8 unused_0[4]; 7010 }; 7011 7012 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ 7013 struct hwrm_vnic_rss_qcfg_output { 7014 __le16 error_code; 7015 __le16 req_type; 7016 __le16 seq_id; 7017 __le16 resp_len; 7018 __le32 hash_type; 7019 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL 7020 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL 7021 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL 7022 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL 7023 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL 7024 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL 7025 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 7026 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL 7027 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL 7028 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL 7029 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL 7030 u8 unused_0[4]; 7031 __le32 hash_key[10]; 7032 u8 hash_mode_flags; 7033 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL 7034 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 7035 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 7036 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 7037 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 7038 u8 ring_select_mode; 7039 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL 7040 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL 7041 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 7042 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 7043 u8 unused_1[5]; 7044 u8 valid; 7045 }; 7046 7047 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 7048 struct hwrm_vnic_plcmodes_cfg_input { 7049 __le16 req_type; 7050 __le16 cmpl_ring; 7051 __le16 seq_id; 7052 __le16 target_id; 7053 __le64 resp_addr; 7054 __le32 flags; 7055 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 7056 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 7057 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 7058 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 7059 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 7060 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 7061 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 7062 __le32 enables; 7063 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 7064 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 7065 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 7066 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 7067 __le32 vnic_id; 7068 __le16 jumbo_thresh; 7069 __le16 hds_offset; 7070 __le16 hds_threshold; 7071 __le16 max_bds; 7072 u8 unused_0[4]; 7073 }; 7074 7075 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 7076 struct hwrm_vnic_plcmodes_cfg_output { 7077 __le16 error_code; 7078 __le16 req_type; 7079 __le16 seq_id; 7080 __le16 resp_len; 7081 u8 unused_0[7]; 7082 u8 valid; 7083 }; 7084 7085 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 7086 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 7087 __le16 req_type; 7088 __le16 cmpl_ring; 7089 __le16 seq_id; 7090 __le16 target_id; 7091 __le64 resp_addr; 7092 }; 7093 7094 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 7095 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 7096 __le16 error_code; 7097 __le16 req_type; 7098 __le16 seq_id; 7099 __le16 resp_len; 7100 __le16 rss_cos_lb_ctx_id; 7101 u8 unused_0[5]; 7102 u8 valid; 7103 }; 7104 7105 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 7106 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 7107 __le16 req_type; 7108 __le16 cmpl_ring; 7109 __le16 seq_id; 7110 __le16 target_id; 7111 __le64 resp_addr; 7112 __le16 rss_cos_lb_ctx_id; 7113 u8 unused_0[6]; 7114 }; 7115 7116 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 7117 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 7118 __le16 error_code; 7119 __le16 req_type; 7120 __le16 seq_id; 7121 __le16 resp_len; 7122 u8 unused_0[7]; 7123 u8 valid; 7124 }; 7125 7126 /* hwrm_ring_alloc_input (size:704b/88B) */ 7127 struct hwrm_ring_alloc_input { 7128 __le16 req_type; 7129 __le16 cmpl_ring; 7130 __le16 seq_id; 7131 __le16 target_id; 7132 __le64 resp_addr; 7133 __le32 enables; 7134 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 7135 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 7136 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 7137 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 7138 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 7139 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 7140 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 7141 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 7142 #define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL 7143 u8 ring_type; 7144 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 7145 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 7146 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 7147 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7148 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 7149 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 7150 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 7151 u8 cmpl_coal_cnt; 7152 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 7153 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 7154 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 7155 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 7156 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 7157 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 7158 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 7159 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 7160 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 7161 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 7162 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 7163 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 7164 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 7165 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 7166 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 7167 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 7168 #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 7169 __le16 flags; 7170 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 7171 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 7172 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 7173 #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL 7174 __le64 page_tbl_addr; 7175 __le32 fbo; 7176 u8 page_size; 7177 u8 page_tbl_depth; 7178 __le16 schq_id; 7179 __le32 length; 7180 __le16 logical_id; 7181 __le16 cmpl_ring_id; 7182 __le16 queue_id; 7183 __le16 rx_buf_size; 7184 __le16 rx_ring_id; 7185 __le16 nq_ring_id; 7186 __le16 ring_arb_cfg; 7187 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 7188 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 7189 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 7190 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 7191 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 7192 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 7193 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 7194 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 7195 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 7196 __le16 steering_tag; 7197 __le32 reserved3; 7198 __le32 stat_ctx_id; 7199 __le32 reserved4; 7200 __le32 max_bw; 7201 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 7202 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 7203 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 7204 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 7205 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 7206 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 7207 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 7208 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 7209 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 7210 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 7211 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 7212 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 7213 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 7214 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 7215 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 7216 u8 int_mode; 7217 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 7218 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 7219 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 7220 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 7221 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 7222 u8 mpc_chnls_type; 7223 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 7224 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 7225 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 7226 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 7227 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 7228 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 7229 u8 unused_4[2]; 7230 __le64 cq_handle; 7231 }; 7232 7233 /* hwrm_ring_alloc_output (size:128b/16B) */ 7234 struct hwrm_ring_alloc_output { 7235 __le16 error_code; 7236 __le16 req_type; 7237 __le16 seq_id; 7238 __le16 resp_len; 7239 __le16 ring_id; 7240 __le16 logical_ring_id; 7241 u8 push_buffer_index; 7242 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7243 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7244 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7245 u8 unused_0[2]; 7246 u8 valid; 7247 }; 7248 7249 /* hwrm_ring_free_input (size:256b/32B) */ 7250 struct hwrm_ring_free_input { 7251 __le16 req_type; 7252 __le16 cmpl_ring; 7253 __le16 seq_id; 7254 __le16 target_id; 7255 __le64 resp_addr; 7256 u8 ring_type; 7257 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 7258 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 7259 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 7260 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7261 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 7262 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 7263 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 7264 u8 flags; 7265 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 7266 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 7267 __le16 ring_id; 7268 __le32 prod_idx; 7269 __le32 opaque; 7270 __le32 unused_1; 7271 }; 7272 7273 /* hwrm_ring_free_output (size:128b/16B) */ 7274 struct hwrm_ring_free_output { 7275 __le16 error_code; 7276 __le16 req_type; 7277 __le16 seq_id; 7278 __le16 resp_len; 7279 u8 unused_0[7]; 7280 u8 valid; 7281 }; 7282 7283 /* hwrm_ring_reset_input (size:192b/24B) */ 7284 struct hwrm_ring_reset_input { 7285 __le16 req_type; 7286 __le16 cmpl_ring; 7287 __le16 seq_id; 7288 __le16 target_id; 7289 __le64 resp_addr; 7290 u8 ring_type; 7291 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 7292 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 7293 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 7294 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7295 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 7296 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 7297 u8 unused_0; 7298 __le16 ring_id; 7299 u8 unused_1[4]; 7300 }; 7301 7302 /* hwrm_ring_reset_output (size:128b/16B) */ 7303 struct hwrm_ring_reset_output { 7304 __le16 error_code; 7305 __le16 req_type; 7306 __le16 seq_id; 7307 __le16 resp_len; 7308 u8 push_buffer_index; 7309 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7310 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7311 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7312 u8 unused_0[3]; 7313 u8 consumer_idx[3]; 7314 u8 valid; 7315 }; 7316 7317 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 7318 struct hwrm_ring_aggint_qcaps_input { 7319 __le16 req_type; 7320 __le16 cmpl_ring; 7321 __le16 seq_id; 7322 __le16 target_id; 7323 __le64 resp_addr; 7324 }; 7325 7326 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 7327 struct hwrm_ring_aggint_qcaps_output { 7328 __le16 error_code; 7329 __le16 req_type; 7330 __le16 seq_id; 7331 __le16 resp_len; 7332 __le32 cmpl_params; 7333 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 7334 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 7335 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 7336 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 7337 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 7338 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 7339 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 7340 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 7341 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 7342 __le32 nq_params; 7343 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 7344 __le16 num_cmpl_dma_aggr_min; 7345 __le16 num_cmpl_dma_aggr_max; 7346 __le16 num_cmpl_dma_aggr_during_int_min; 7347 __le16 num_cmpl_dma_aggr_during_int_max; 7348 __le16 cmpl_aggr_dma_tmr_min; 7349 __le16 cmpl_aggr_dma_tmr_max; 7350 __le16 cmpl_aggr_dma_tmr_during_int_min; 7351 __le16 cmpl_aggr_dma_tmr_during_int_max; 7352 __le16 int_lat_tmr_min_min; 7353 __le16 int_lat_tmr_min_max; 7354 __le16 int_lat_tmr_max_min; 7355 __le16 int_lat_tmr_max_max; 7356 __le16 num_cmpl_aggr_int_min; 7357 __le16 num_cmpl_aggr_int_max; 7358 __le16 timer_units; 7359 u8 unused_0[1]; 7360 u8 valid; 7361 }; 7362 7363 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 7364 struct hwrm_ring_cmpl_ring_qaggint_params_input { 7365 __le16 req_type; 7366 __le16 cmpl_ring; 7367 __le16 seq_id; 7368 __le16 target_id; 7369 __le64 resp_addr; 7370 __le16 ring_id; 7371 __le16 flags; 7372 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 7373 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 7374 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7375 u8 unused_0[4]; 7376 }; 7377 7378 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 7379 struct hwrm_ring_cmpl_ring_qaggint_params_output { 7380 __le16 error_code; 7381 __le16 req_type; 7382 __le16 seq_id; 7383 __le16 resp_len; 7384 __le16 flags; 7385 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 7386 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 7387 __le16 num_cmpl_dma_aggr; 7388 __le16 num_cmpl_dma_aggr_during_int; 7389 __le16 cmpl_aggr_dma_tmr; 7390 __le16 cmpl_aggr_dma_tmr_during_int; 7391 __le16 int_lat_tmr_min; 7392 __le16 int_lat_tmr_max; 7393 __le16 num_cmpl_aggr_int; 7394 u8 unused_0[7]; 7395 u8 valid; 7396 }; 7397 7398 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 7399 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 7400 __le16 req_type; 7401 __le16 cmpl_ring; 7402 __le16 seq_id; 7403 __le16 target_id; 7404 __le64 resp_addr; 7405 __le16 ring_id; 7406 __le16 flags; 7407 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 7408 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 7409 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7410 __le16 num_cmpl_dma_aggr; 7411 __le16 num_cmpl_dma_aggr_during_int; 7412 __le16 cmpl_aggr_dma_tmr; 7413 __le16 cmpl_aggr_dma_tmr_during_int; 7414 __le16 int_lat_tmr_min; 7415 __le16 int_lat_tmr_max; 7416 __le16 num_cmpl_aggr_int; 7417 __le16 enables; 7418 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 7419 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 7420 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 7421 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 7422 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 7423 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 7424 u8 unused_0[4]; 7425 }; 7426 7427 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 7428 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 7429 __le16 error_code; 7430 __le16 req_type; 7431 __le16 seq_id; 7432 __le16 resp_len; 7433 u8 unused_0[7]; 7434 u8 valid; 7435 }; 7436 7437 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 7438 struct hwrm_ring_grp_alloc_input { 7439 __le16 req_type; 7440 __le16 cmpl_ring; 7441 __le16 seq_id; 7442 __le16 target_id; 7443 __le64 resp_addr; 7444 __le16 cr; 7445 __le16 rr; 7446 __le16 ar; 7447 __le16 sc; 7448 }; 7449 7450 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 7451 struct hwrm_ring_grp_alloc_output { 7452 __le16 error_code; 7453 __le16 req_type; 7454 __le16 seq_id; 7455 __le16 resp_len; 7456 __le32 ring_group_id; 7457 u8 unused_0[3]; 7458 u8 valid; 7459 }; 7460 7461 /* hwrm_ring_grp_free_input (size:192b/24B) */ 7462 struct hwrm_ring_grp_free_input { 7463 __le16 req_type; 7464 __le16 cmpl_ring; 7465 __le16 seq_id; 7466 __le16 target_id; 7467 __le64 resp_addr; 7468 __le32 ring_group_id; 7469 u8 unused_0[4]; 7470 }; 7471 7472 /* hwrm_ring_grp_free_output (size:128b/16B) */ 7473 struct hwrm_ring_grp_free_output { 7474 __le16 error_code; 7475 __le16 req_type; 7476 __le16 seq_id; 7477 __le16 resp_len; 7478 u8 unused_0[7]; 7479 u8 valid; 7480 }; 7481 7482 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 7483 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 7484 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 7485 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 7486 7487 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 7488 struct hwrm_cfa_l2_filter_alloc_input { 7489 __le16 req_type; 7490 __le16 cmpl_ring; 7491 __le16 seq_id; 7492 __le16 target_id; 7493 __le64 resp_addr; 7494 __le32 flags; 7495 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 7496 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 7497 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 7498 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 7499 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 7500 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 7501 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 7502 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 7503 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 7504 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 7505 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 7506 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 7507 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 7508 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 7509 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 7510 __le32 enables; 7511 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 7512 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 7513 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 7514 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 7515 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 7516 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 7517 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 7518 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 7519 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 7520 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 7521 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 7522 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 7523 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 7524 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 7525 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 7526 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7527 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7528 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 7529 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 7530 u8 l2_addr[6]; 7531 u8 num_vlans; 7532 u8 t_num_vlans; 7533 u8 l2_addr_mask[6]; 7534 __le16 l2_ovlan; 7535 __le16 l2_ovlan_mask; 7536 __le16 l2_ivlan; 7537 __le16 l2_ivlan_mask; 7538 u8 unused_1[2]; 7539 u8 t_l2_addr[6]; 7540 u8 unused_2[2]; 7541 u8 t_l2_addr_mask[6]; 7542 __le16 t_l2_ovlan; 7543 __le16 t_l2_ovlan_mask; 7544 __le16 t_l2_ivlan; 7545 __le16 t_l2_ivlan_mask; 7546 u8 src_type; 7547 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 7548 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 7549 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 7550 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 7551 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 7552 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 7553 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 7554 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 7555 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 7556 u8 unused_3; 7557 __le32 src_id; 7558 u8 tunnel_type; 7559 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7560 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7561 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7562 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7563 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7564 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7565 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7566 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7567 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7568 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7569 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7570 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7571 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7572 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7573 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7574 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7575 u8 unused_4; 7576 __le16 dst_id; 7577 __le16 mirror_vnic_id; 7578 u8 pri_hint; 7579 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7580 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 7581 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 7582 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 7583 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 7584 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 7585 u8 unused_5; 7586 __le32 unused_6; 7587 __le64 l2_filter_id_hint; 7588 }; 7589 7590 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 7591 struct hwrm_cfa_l2_filter_alloc_output { 7592 __le16 error_code; 7593 __le16 req_type; 7594 __le16 seq_id; 7595 __le16 resp_len; 7596 __le64 l2_filter_id; 7597 __le32 flow_id; 7598 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7599 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7600 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7601 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7602 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7603 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7604 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7605 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7606 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7607 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7608 u8 unused_0[3]; 7609 u8 valid; 7610 }; 7611 7612 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 7613 struct hwrm_cfa_l2_filter_free_input { 7614 __le16 req_type; 7615 __le16 cmpl_ring; 7616 __le16 seq_id; 7617 __le16 target_id; 7618 __le64 resp_addr; 7619 __le64 l2_filter_id; 7620 }; 7621 7622 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 7623 struct hwrm_cfa_l2_filter_free_output { 7624 __le16 error_code; 7625 __le16 req_type; 7626 __le16 seq_id; 7627 __le16 resp_len; 7628 u8 unused_0[7]; 7629 u8 valid; 7630 }; 7631 7632 /* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */ 7633 struct hwrm_cfa_l2_filter_cfg_input { 7634 __le16 req_type; 7635 __le16 cmpl_ring; 7636 __le16 seq_id; 7637 __le16 target_id; 7638 __le64 resp_addr; 7639 __le32 flags; 7640 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7641 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7642 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 7643 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7644 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 7645 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 7646 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 7647 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 7648 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7649 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7650 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7651 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_MASK 0x30UL 7652 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_SFT 4 7653 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_NO_UPDATE (0x0UL << 4) 7654 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_BYPASS_LKUP (0x1UL << 4) 7655 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP (0x2UL << 4) 7656 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP (0x3UL << 4) 7657 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP 7658 __le32 enables; 7659 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 7660 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7661 #define CFA_L2_FILTER_CFG_REQ_ENABLES_PROF_FUNC 0x4UL 7662 #define CFA_L2_FILTER_CFG_REQ_ENABLES_L2_CONTEXT_ID 0x8UL 7663 __le64 l2_filter_id; 7664 __le32 dst_id; 7665 __le32 new_mirror_vnic_id; 7666 __le32 prof_func; 7667 __le32 l2_context_id; 7668 }; 7669 7670 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 7671 struct hwrm_cfa_l2_filter_cfg_output { 7672 __le16 error_code; 7673 __le16 req_type; 7674 __le16 seq_id; 7675 __le16 resp_len; 7676 u8 unused_0[7]; 7677 u8 valid; 7678 }; 7679 7680 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 7681 struct hwrm_cfa_l2_set_rx_mask_input { 7682 __le16 req_type; 7683 __le16 cmpl_ring; 7684 __le16 seq_id; 7685 __le16 target_id; 7686 __le64 resp_addr; 7687 __le32 vnic_id; 7688 __le32 mask; 7689 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 7690 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 7691 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 7692 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 7693 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 7694 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 7695 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 7696 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 7697 __le64 mc_tbl_addr; 7698 __le32 num_mc_entries; 7699 u8 unused_0[4]; 7700 __le64 vlan_tag_tbl_addr; 7701 __le32 num_vlan_tags; 7702 u8 unused_1[4]; 7703 }; 7704 7705 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 7706 struct hwrm_cfa_l2_set_rx_mask_output { 7707 __le16 error_code; 7708 __le16 req_type; 7709 __le16 seq_id; 7710 __le16 resp_len; 7711 u8 unused_0[7]; 7712 u8 valid; 7713 }; 7714 7715 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 7716 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 7717 u8 code; 7718 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 7719 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 7720 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 7721 u8 unused_0[7]; 7722 }; 7723 7724 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 7725 struct hwrm_cfa_tunnel_filter_alloc_input { 7726 __le16 req_type; 7727 __le16 cmpl_ring; 7728 __le16 seq_id; 7729 __le16 target_id; 7730 __le64 resp_addr; 7731 __le32 flags; 7732 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7733 __le32 enables; 7734 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7735 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 7736 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 7737 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 7738 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 7739 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 7740 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 7741 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 7742 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 7743 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 7744 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 7745 __le64 l2_filter_id; 7746 u8 l2_addr[6]; 7747 __le16 l2_ivlan; 7748 __le32 l3_addr[4]; 7749 __le32 t_l3_addr[4]; 7750 u8 l3_addr_type; 7751 u8 t_l3_addr_type; 7752 u8 tunnel_type; 7753 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7754 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7755 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7756 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7757 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7758 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7759 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7760 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7761 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7762 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7763 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7764 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7765 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7766 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7767 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7768 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7769 u8 tunnel_flags; 7770 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 7771 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 7772 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 7773 __le32 vni; 7774 __le32 dst_vnic_id; 7775 __le32 mirror_vnic_id; 7776 }; 7777 7778 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 7779 struct hwrm_cfa_tunnel_filter_alloc_output { 7780 __le16 error_code; 7781 __le16 req_type; 7782 __le16 seq_id; 7783 __le16 resp_len; 7784 __le64 tunnel_filter_id; 7785 __le32 flow_id; 7786 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7787 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7788 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7789 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7790 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7791 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7792 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7793 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7794 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7795 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7796 u8 unused_0[3]; 7797 u8 valid; 7798 }; 7799 7800 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 7801 struct hwrm_cfa_tunnel_filter_free_input { 7802 __le16 req_type; 7803 __le16 cmpl_ring; 7804 __le16 seq_id; 7805 __le16 target_id; 7806 __le64 resp_addr; 7807 __le64 tunnel_filter_id; 7808 }; 7809 7810 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 7811 struct hwrm_cfa_tunnel_filter_free_output { 7812 __le16 error_code; 7813 __le16 req_type; 7814 __le16 seq_id; 7815 __le16 resp_len; 7816 u8 unused_0[7]; 7817 u8 valid; 7818 }; 7819 7820 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 7821 struct hwrm_vxlan_ipv4_hdr { 7822 u8 ver_hlen; 7823 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 7824 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 7825 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 7826 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 7827 u8 tos; 7828 __be16 ip_id; 7829 __be16 flags_frag_offset; 7830 u8 ttl; 7831 u8 protocol; 7832 __be32 src_ip_addr; 7833 __be32 dest_ip_addr; 7834 }; 7835 7836 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 7837 struct hwrm_vxlan_ipv6_hdr { 7838 __be32 ver_tc_flow_label; 7839 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 7840 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 7841 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 7842 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 7843 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 7844 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 7845 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 7846 __be16 payload_len; 7847 u8 next_hdr; 7848 u8 ttl; 7849 __be32 src_ip_addr[4]; 7850 __be32 dest_ip_addr[4]; 7851 }; 7852 7853 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 7854 struct hwrm_cfa_encap_data_vxlan { 7855 u8 src_mac_addr[6]; 7856 __le16 unused_0; 7857 u8 dst_mac_addr[6]; 7858 u8 num_vlan_tags; 7859 u8 unused_1; 7860 __be16 ovlan_tpid; 7861 __be16 ovlan_tci; 7862 __be16 ivlan_tpid; 7863 __be16 ivlan_tci; 7864 __le32 l3[10]; 7865 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 7866 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 7867 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 7868 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 7869 __be16 src_port; 7870 __be16 dst_port; 7871 __be32 vni; 7872 u8 hdr_rsvd0[3]; 7873 u8 hdr_rsvd1; 7874 u8 hdr_flags; 7875 u8 unused[3]; 7876 }; 7877 7878 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7879 struct hwrm_cfa_encap_record_alloc_input { 7880 __le16 req_type; 7881 __le16 cmpl_ring; 7882 __le16 seq_id; 7883 __le16 target_id; 7884 __le64 resp_addr; 7885 __le32 flags; 7886 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7887 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7888 u8 encap_type; 7889 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7890 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7891 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7892 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7893 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7894 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7895 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7896 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 7897 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 7898 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 7899 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 7900 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 7901 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 0x10UL 7902 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 7903 u8 unused_0[3]; 7904 __le32 encap_data[20]; 7905 }; 7906 7907 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7908 struct hwrm_cfa_encap_record_alloc_output { 7909 __le16 error_code; 7910 __le16 req_type; 7911 __le16 seq_id; 7912 __le16 resp_len; 7913 __le32 encap_record_id; 7914 u8 unused_0[3]; 7915 u8 valid; 7916 }; 7917 7918 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7919 struct hwrm_cfa_encap_record_free_input { 7920 __le16 req_type; 7921 __le16 cmpl_ring; 7922 __le16 seq_id; 7923 __le16 target_id; 7924 __le64 resp_addr; 7925 __le32 encap_record_id; 7926 u8 unused_0[4]; 7927 }; 7928 7929 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7930 struct hwrm_cfa_encap_record_free_output { 7931 __le16 error_code; 7932 __le16 req_type; 7933 __le16 seq_id; 7934 __le16 resp_len; 7935 u8 unused_0[7]; 7936 u8 valid; 7937 }; 7938 7939 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7940 struct hwrm_cfa_ntuple_filter_alloc_input { 7941 __le16 req_type; 7942 __le16 cmpl_ring; 7943 __le16 seq_id; 7944 __le16 target_id; 7945 __le64 resp_addr; 7946 __le32 flags; 7947 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7948 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7949 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 7950 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 7951 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 7952 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 7953 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 7954 __le32 enables; 7955 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7956 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7957 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7958 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7959 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7960 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7961 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7962 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7963 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7964 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7965 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7966 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7967 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7968 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7969 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7970 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7971 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7972 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7973 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 7974 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7975 __le64 l2_filter_id; 7976 u8 src_macaddr[6]; 7977 __be16 ethertype; 7978 u8 ip_addr_type; 7979 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7980 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7981 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7982 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7983 u8 ip_protocol; 7984 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7985 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7986 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7987 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP 0x1UL 7988 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6 0x3aUL 7989 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 0xffUL 7990 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 7991 __le16 dst_id; 7992 __le16 rfs_ring_tbl_idx; 7993 u8 tunnel_type; 7994 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7995 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7996 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7997 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7998 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7999 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8000 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8001 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8002 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8003 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8004 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8005 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8006 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8007 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8008 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8009 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8010 u8 pri_hint; 8011 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 8012 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 8013 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 8014 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 8015 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 8016 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 8017 __be32 src_ipaddr[4]; 8018 __be32 src_ipaddr_mask[4]; 8019 __be32 dst_ipaddr[4]; 8020 __be32 dst_ipaddr_mask[4]; 8021 __be16 src_port; 8022 __be16 src_port_mask; 8023 __be16 dst_port; 8024 __be16 dst_port_mask; 8025 __le64 ntuple_filter_id_hint; 8026 }; 8027 8028 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 8029 struct hwrm_cfa_ntuple_filter_alloc_output { 8030 __le16 error_code; 8031 __le16 req_type; 8032 __le16 seq_id; 8033 __le16 resp_len; 8034 __le64 ntuple_filter_id; 8035 __le32 flow_id; 8036 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8037 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8038 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8039 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8040 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8041 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 8042 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8043 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8044 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8045 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 8046 u8 unused_0[3]; 8047 u8 valid; 8048 }; 8049 8050 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 8051 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 8052 u8 code; 8053 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8054 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 8055 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 8056 u8 unused_0[7]; 8057 }; 8058 8059 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 8060 struct hwrm_cfa_ntuple_filter_free_input { 8061 __le16 req_type; 8062 __le16 cmpl_ring; 8063 __le16 seq_id; 8064 __le16 target_id; 8065 __le64 resp_addr; 8066 __le64 ntuple_filter_id; 8067 }; 8068 8069 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 8070 struct hwrm_cfa_ntuple_filter_free_output { 8071 __le16 error_code; 8072 __le16 req_type; 8073 __le16 seq_id; 8074 __le16 resp_len; 8075 u8 unused_0[7]; 8076 u8 valid; 8077 }; 8078 8079 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 8080 struct hwrm_cfa_ntuple_filter_cfg_input { 8081 __le16 req_type; 8082 __le16 cmpl_ring; 8083 __le16 seq_id; 8084 __le16 target_id; 8085 __le64 resp_addr; 8086 __le32 enables; 8087 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 8088 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 8089 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 8090 __le32 flags; 8091 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 8092 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 8093 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 8094 __le64 ntuple_filter_id; 8095 __le32 new_dst_id; 8096 __le32 new_mirror_vnic_id; 8097 __le16 new_meter_instance_id; 8098 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 8099 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 8100 u8 unused_1[6]; 8101 }; 8102 8103 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 8104 struct hwrm_cfa_ntuple_filter_cfg_output { 8105 __le16 error_code; 8106 __le16 req_type; 8107 __le16 seq_id; 8108 __le16 resp_len; 8109 u8 unused_0[7]; 8110 u8 valid; 8111 }; 8112 8113 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 8114 struct hwrm_cfa_decap_filter_alloc_input { 8115 __le16 req_type; 8116 __le16 cmpl_ring; 8117 __le16 seq_id; 8118 __le16 target_id; 8119 __le64 resp_addr; 8120 __le32 flags; 8121 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 8122 __le32 enables; 8123 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 8124 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 8125 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 8126 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 8127 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 8128 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 8129 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 8130 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 8131 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 8132 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 8133 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 8134 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 8135 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 8136 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 8137 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 8138 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 8139 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 8140 __be32 tunnel_id; 8141 u8 tunnel_type; 8142 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8143 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8144 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8145 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8146 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8147 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8148 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8149 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8150 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8151 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8152 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8153 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8154 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8155 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8156 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8157 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8158 u8 unused_0; 8159 __le16 unused_1; 8160 u8 src_macaddr[6]; 8161 u8 unused_2[2]; 8162 u8 dst_macaddr[6]; 8163 __be16 ovlan_vid; 8164 __be16 ivlan_vid; 8165 __be16 t_ovlan_vid; 8166 __be16 t_ivlan_vid; 8167 __be16 ethertype; 8168 u8 ip_addr_type; 8169 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 8170 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 8171 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 8172 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 8173 u8 ip_protocol; 8174 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 8175 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 8176 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 8177 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 8178 __le16 unused_3; 8179 __le32 unused_4; 8180 __be32 src_ipaddr[4]; 8181 __be32 dst_ipaddr[4]; 8182 __be16 src_port; 8183 __be16 dst_port; 8184 __le16 dst_id; 8185 __le16 l2_ctxt_ref_id; 8186 }; 8187 8188 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 8189 struct hwrm_cfa_decap_filter_alloc_output { 8190 __le16 error_code; 8191 __le16 req_type; 8192 __le16 seq_id; 8193 __le16 resp_len; 8194 __le32 decap_filter_id; 8195 u8 unused_0[3]; 8196 u8 valid; 8197 }; 8198 8199 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 8200 struct hwrm_cfa_decap_filter_free_input { 8201 __le16 req_type; 8202 __le16 cmpl_ring; 8203 __le16 seq_id; 8204 __le16 target_id; 8205 __le64 resp_addr; 8206 __le32 decap_filter_id; 8207 u8 unused_0[4]; 8208 }; 8209 8210 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 8211 struct hwrm_cfa_decap_filter_free_output { 8212 __le16 error_code; 8213 __le16 req_type; 8214 __le16 seq_id; 8215 __le16 resp_len; 8216 u8 unused_0[7]; 8217 u8 valid; 8218 }; 8219 8220 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 8221 struct hwrm_cfa_flow_alloc_input { 8222 __le16 req_type; 8223 __le16 cmpl_ring; 8224 __le16 seq_id; 8225 __le16 target_id; 8226 __le64 resp_addr; 8227 __le16 flags; 8228 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 8229 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 8230 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 8231 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 8232 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 8233 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 8234 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 8235 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 8236 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 8237 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 8238 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 8239 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 8240 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 8241 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 8242 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 8243 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 8244 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 8245 __le16 src_fid; 8246 __le32 tunnel_handle; 8247 __le16 action_flags; 8248 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 8249 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 8250 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 8251 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 8252 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 8253 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 8254 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 8255 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 8256 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 8257 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 8258 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 8259 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 8260 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 8261 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 8262 __le16 dst_fid; 8263 __be16 l2_rewrite_vlan_tpid; 8264 __be16 l2_rewrite_vlan_tci; 8265 __le16 act_meter_id; 8266 __le16 ref_flow_handle; 8267 __be16 ethertype; 8268 __be16 outer_vlan_tci; 8269 __be16 dmac[3]; 8270 __be16 inner_vlan_tci; 8271 __be16 smac[3]; 8272 u8 ip_dst_mask_len; 8273 u8 ip_src_mask_len; 8274 __be32 ip_dst[4]; 8275 __be32 ip_src[4]; 8276 __be16 l4_src_port; 8277 __be16 l4_src_port_mask; 8278 __be16 l4_dst_port; 8279 __be16 l4_dst_port_mask; 8280 __be32 nat_ip_address[4]; 8281 __be16 l2_rewrite_dmac[3]; 8282 __be16 nat_port; 8283 __be16 l2_rewrite_smac[3]; 8284 u8 ip_proto; 8285 u8 tunnel_type; 8286 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8287 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8288 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8289 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8290 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8291 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8292 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8293 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8294 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8295 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8296 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8297 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8298 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8299 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8300 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8301 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8302 }; 8303 8304 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 8305 struct hwrm_cfa_flow_alloc_output { 8306 __le16 error_code; 8307 __le16 req_type; 8308 __le16 seq_id; 8309 __le16 resp_len; 8310 __le16 flow_handle; 8311 u8 unused_0[2]; 8312 __le32 flow_id; 8313 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8314 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8315 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8316 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8317 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8318 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 8319 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8320 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8321 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8322 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 8323 __le64 ext_flow_handle; 8324 __le32 flow_counter_id; 8325 u8 unused_1[3]; 8326 u8 valid; 8327 }; 8328 8329 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 8330 struct hwrm_cfa_flow_alloc_cmd_err { 8331 u8 code; 8332 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8333 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 8334 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 8335 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 8336 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 8337 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 8338 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 8339 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 8340 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 8341 u8 unused_0[7]; 8342 }; 8343 8344 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 8345 struct hwrm_cfa_flow_free_input { 8346 __le16 req_type; 8347 __le16 cmpl_ring; 8348 __le16 seq_id; 8349 __le16 target_id; 8350 __le64 resp_addr; 8351 __le16 flow_handle; 8352 __le16 unused_0; 8353 __le32 flow_counter_id; 8354 __le64 ext_flow_handle; 8355 }; 8356 8357 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 8358 struct hwrm_cfa_flow_free_output { 8359 __le16 error_code; 8360 __le16 req_type; 8361 __le16 seq_id; 8362 __le16 resp_len; 8363 __le64 packet; 8364 __le64 byte; 8365 u8 unused_0[7]; 8366 u8 valid; 8367 }; 8368 8369 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 8370 struct hwrm_cfa_flow_info_input { 8371 __le16 req_type; 8372 __le16 cmpl_ring; 8373 __le16 seq_id; 8374 __le16 target_id; 8375 __le64 resp_addr; 8376 __le16 flow_handle; 8377 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 8378 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 8379 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 8380 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX 0x3000UL 8381 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 8382 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 8383 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX 0x9000UL 8384 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL 8385 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX 0xb000UL 8386 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL 8387 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 8388 u8 unused_0[6]; 8389 __le64 ext_flow_handle; 8390 }; 8391 8392 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 8393 struct hwrm_cfa_flow_info_output { 8394 __le16 error_code; 8395 __le16 req_type; 8396 __le16 seq_id; 8397 __le16 resp_len; 8398 u8 flags; 8399 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 8400 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 8401 u8 profile; 8402 __le16 src_fid; 8403 __le16 dst_fid; 8404 __le16 l2_ctxt_id; 8405 __le64 em_info; 8406 __le64 tcam_info; 8407 __le64 vfp_tcam_info; 8408 __le16 ar_id; 8409 __le16 flow_handle; 8410 __le32 tunnel_handle; 8411 __le16 flow_timer; 8412 u8 unused_0[6]; 8413 __le32 flow_key_data[130]; 8414 __le32 flow_action_info[30]; 8415 u8 unused_1[7]; 8416 u8 valid; 8417 }; 8418 8419 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 8420 struct hwrm_cfa_flow_stats_input { 8421 __le16 req_type; 8422 __le16 cmpl_ring; 8423 __le16 seq_id; 8424 __le16 target_id; 8425 __le64 resp_addr; 8426 __le16 num_flows; 8427 __le16 flow_handle_0; 8428 __le16 flow_handle_1; 8429 __le16 flow_handle_2; 8430 __le16 flow_handle_3; 8431 __le16 flow_handle_4; 8432 __le16 flow_handle_5; 8433 __le16 flow_handle_6; 8434 __le16 flow_handle_7; 8435 __le16 flow_handle_8; 8436 __le16 flow_handle_9; 8437 u8 unused_0[2]; 8438 __le32 flow_id_0; 8439 __le32 flow_id_1; 8440 __le32 flow_id_2; 8441 __le32 flow_id_3; 8442 __le32 flow_id_4; 8443 __le32 flow_id_5; 8444 __le32 flow_id_6; 8445 __le32 flow_id_7; 8446 __le32 flow_id_8; 8447 __le32 flow_id_9; 8448 }; 8449 8450 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 8451 struct hwrm_cfa_flow_stats_output { 8452 __le16 error_code; 8453 __le16 req_type; 8454 __le16 seq_id; 8455 __le16 resp_len; 8456 __le64 packet_0; 8457 __le64 packet_1; 8458 __le64 packet_2; 8459 __le64 packet_3; 8460 __le64 packet_4; 8461 __le64 packet_5; 8462 __le64 packet_6; 8463 __le64 packet_7; 8464 __le64 packet_8; 8465 __le64 packet_9; 8466 __le64 byte_0; 8467 __le64 byte_1; 8468 __le64 byte_2; 8469 __le64 byte_3; 8470 __le64 byte_4; 8471 __le64 byte_5; 8472 __le64 byte_6; 8473 __le64 byte_7; 8474 __le64 byte_8; 8475 __le64 byte_9; 8476 __le16 flow_hits; 8477 u8 unused_0[5]; 8478 u8 valid; 8479 }; 8480 8481 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 8482 struct hwrm_cfa_vfr_alloc_input { 8483 __le16 req_type; 8484 __le16 cmpl_ring; 8485 __le16 seq_id; 8486 __le16 target_id; 8487 __le64 resp_addr; 8488 __le16 vf_id; 8489 __le16 reserved; 8490 u8 unused_0[4]; 8491 char vfr_name[32]; 8492 }; 8493 8494 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 8495 struct hwrm_cfa_vfr_alloc_output { 8496 __le16 error_code; 8497 __le16 req_type; 8498 __le16 seq_id; 8499 __le16 resp_len; 8500 __le16 rx_cfa_code; 8501 __le16 tx_cfa_action; 8502 u8 unused_0[3]; 8503 u8 valid; 8504 }; 8505 8506 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 8507 struct hwrm_cfa_vfr_free_input { 8508 __le16 req_type; 8509 __le16 cmpl_ring; 8510 __le16 seq_id; 8511 __le16 target_id; 8512 __le64 resp_addr; 8513 char vfr_name[32]; 8514 __le16 vf_id; 8515 __le16 reserved; 8516 u8 unused_0[4]; 8517 }; 8518 8519 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 8520 struct hwrm_cfa_vfr_free_output { 8521 __le16 error_code; 8522 __le16 req_type; 8523 __le16 seq_id; 8524 __le16 resp_len; 8525 u8 unused_0[7]; 8526 u8 valid; 8527 }; 8528 8529 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 8530 struct hwrm_cfa_eem_qcaps_input { 8531 __le16 req_type; 8532 __le16 cmpl_ring; 8533 __le16 seq_id; 8534 __le16 target_id; 8535 __le64 resp_addr; 8536 __le32 flags; 8537 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 8538 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 8539 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8540 __le32 unused_0; 8541 }; 8542 8543 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 8544 struct hwrm_cfa_eem_qcaps_output { 8545 __le16 error_code; 8546 __le16 req_type; 8547 __le16 seq_id; 8548 __le16 resp_len; 8549 __le32 flags; 8550 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 8551 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 8552 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 8553 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 8554 __le32 unused_0; 8555 __le32 supported; 8556 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 8557 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 8558 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 8559 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 8560 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 8561 __le32 max_entries_supported; 8562 __le16 key_entry_size; 8563 __le16 record_entry_size; 8564 __le16 efc_entry_size; 8565 __le16 fid_entry_size; 8566 u8 unused_1[7]; 8567 u8 valid; 8568 }; 8569 8570 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 8571 struct hwrm_cfa_eem_cfg_input { 8572 __le16 req_type; 8573 __le16 cmpl_ring; 8574 __le16 seq_id; 8575 __le16 target_id; 8576 __le64 resp_addr; 8577 __le32 flags; 8578 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 8579 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 8580 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8581 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 8582 __le16 group_id; 8583 __le16 unused_0; 8584 __le32 num_entries; 8585 __le32 unused_1; 8586 __le16 key0_ctx_id; 8587 __le16 key1_ctx_id; 8588 __le16 record_ctx_id; 8589 __le16 efc_ctx_id; 8590 __le16 fid_ctx_id; 8591 __le16 unused_2; 8592 __le32 unused_3; 8593 }; 8594 8595 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 8596 struct hwrm_cfa_eem_cfg_output { 8597 __le16 error_code; 8598 __le16 req_type; 8599 __le16 seq_id; 8600 __le16 resp_len; 8601 u8 unused_0[7]; 8602 u8 valid; 8603 }; 8604 8605 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 8606 struct hwrm_cfa_eem_qcfg_input { 8607 __le16 req_type; 8608 __le16 cmpl_ring; 8609 __le16 seq_id; 8610 __le16 target_id; 8611 __le64 resp_addr; 8612 __le32 flags; 8613 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 8614 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 8615 __le32 unused_0; 8616 }; 8617 8618 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 8619 struct hwrm_cfa_eem_qcfg_output { 8620 __le16 error_code; 8621 __le16 req_type; 8622 __le16 seq_id; 8623 __le16 resp_len; 8624 __le32 flags; 8625 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 8626 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 8627 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 8628 __le32 num_entries; 8629 __le16 key0_ctx_id; 8630 __le16 key1_ctx_id; 8631 __le16 record_ctx_id; 8632 __le16 efc_ctx_id; 8633 __le16 fid_ctx_id; 8634 u8 unused_2[5]; 8635 u8 valid; 8636 }; 8637 8638 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 8639 struct hwrm_cfa_eem_op_input { 8640 __le16 req_type; 8641 __le16 cmpl_ring; 8642 __le16 seq_id; 8643 __le16 target_id; 8644 __le64 resp_addr; 8645 __le32 flags; 8646 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 8647 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 8648 __le16 unused_0; 8649 __le16 op; 8650 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 8651 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 8652 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 8653 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 8654 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 8655 }; 8656 8657 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 8658 struct hwrm_cfa_eem_op_output { 8659 __le16 error_code; 8660 __le16 req_type; 8661 __le16 seq_id; 8662 __le16 resp_len; 8663 u8 unused_0[7]; 8664 u8 valid; 8665 }; 8666 8667 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 8668 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 8669 __le16 req_type; 8670 __le16 cmpl_ring; 8671 __le16 seq_id; 8672 __le16 target_id; 8673 __le64 resp_addr; 8674 __le32 unused_0[4]; 8675 }; 8676 8677 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 8678 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 8679 __le16 error_code; 8680 __le16 req_type; 8681 __le16 seq_id; 8682 __le16 resp_len; 8683 __le32 flags; 8684 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 8685 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 8686 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 8687 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 8688 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 8689 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 8690 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 8691 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 8692 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 8693 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 8694 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 8695 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 8696 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 8697 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 8698 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 8699 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 8700 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 8701 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 8702 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 8703 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL 8704 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED 0x100000UL 8705 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED 0x200000UL 8706 u8 unused_0[3]; 8707 u8 valid; 8708 }; 8709 8710 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 8711 struct hwrm_tunnel_dst_port_query_input { 8712 __le16 req_type; 8713 __le16 cmpl_ring; 8714 __le16 seq_id; 8715 __le16 target_id; 8716 __le64 resp_addr; 8717 u8 tunnel_type; 8718 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8719 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8720 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8721 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8722 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8723 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8724 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8725 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8726 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_SRV6 0xfUL 8727 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8728 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE 0x11UL 8729 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8730 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8731 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8732 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8733 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8734 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8735 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8736 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8737 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8738 u8 tunnel_next_proto; 8739 u8 unused_0[6]; 8740 }; 8741 8742 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 8743 struct hwrm_tunnel_dst_port_query_output { 8744 __le16 error_code; 8745 __le16 req_type; 8746 __le16 seq_id; 8747 __le16 resp_len; 8748 __le16 tunnel_dst_port_id; 8749 __be16 tunnel_dst_port_val; 8750 u8 upar_in_use; 8751 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0 0x1UL 8752 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1 0x2UL 8753 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2 0x4UL 8754 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3 0x8UL 8755 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4 0x10UL 8756 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5 0x20UL 8757 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6 0x40UL 8758 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7 0x80UL 8759 u8 status; 8760 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_CHIP_LEVEL 0x1UL 8761 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_FUNC_LEVEL 0x2UL 8762 u8 unused_0; 8763 u8 valid; 8764 }; 8765 8766 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 8767 struct hwrm_tunnel_dst_port_alloc_input { 8768 __le16 req_type; 8769 __le16 cmpl_ring; 8770 __le16 seq_id; 8771 __le16 target_id; 8772 __le64 resp_addr; 8773 u8 tunnel_type; 8774 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8775 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8776 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8777 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8778 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8779 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8780 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8781 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8782 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6 0xfUL 8783 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8784 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE 0x11UL 8785 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8786 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8787 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8788 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8789 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8790 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8791 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8792 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8793 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8794 u8 tunnel_next_proto; 8795 __be16 tunnel_dst_port_val; 8796 u8 unused_0[4]; 8797 }; 8798 8799 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 8800 struct hwrm_tunnel_dst_port_alloc_output { 8801 __le16 error_code; 8802 __le16 req_type; 8803 __le16 seq_id; 8804 __le16 resp_len; 8805 __le16 tunnel_dst_port_id; 8806 u8 error_info; 8807 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL 8808 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL 8809 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL 8810 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 0x3UL 8811 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 8812 u8 upar_in_use; 8813 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL 8814 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL 8815 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL 8816 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL 8817 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL 8818 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL 8819 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL 8820 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL 8821 u8 unused_0[3]; 8822 u8 valid; 8823 }; 8824 8825 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 8826 struct hwrm_tunnel_dst_port_free_input { 8827 __le16 req_type; 8828 __le16 cmpl_ring; 8829 __le16 seq_id; 8830 __le16 target_id; 8831 __le64 resp_addr; 8832 u8 tunnel_type; 8833 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8834 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8835 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8836 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8837 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8838 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8839 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8840 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8841 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6 0xfUL 8842 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8843 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE 0x11UL 8844 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8845 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8846 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8847 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8848 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8849 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8850 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8851 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8852 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8853 u8 tunnel_next_proto; 8854 __le16 tunnel_dst_port_id; 8855 u8 unused_0[4]; 8856 }; 8857 8858 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 8859 struct hwrm_tunnel_dst_port_free_output { 8860 __le16 error_code; 8861 __le16 req_type; 8862 __le16 seq_id; 8863 __le16 resp_len; 8864 u8 error_info; 8865 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL 8866 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL 8867 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL 8868 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 8869 u8 unused_1[6]; 8870 u8 valid; 8871 }; 8872 8873 /* ctx_hw_stats (size:1280b/160B) */ 8874 struct ctx_hw_stats { 8875 __le64 rx_ucast_pkts; 8876 __le64 rx_mcast_pkts; 8877 __le64 rx_bcast_pkts; 8878 __le64 rx_discard_pkts; 8879 __le64 rx_error_pkts; 8880 __le64 rx_ucast_bytes; 8881 __le64 rx_mcast_bytes; 8882 __le64 rx_bcast_bytes; 8883 __le64 tx_ucast_pkts; 8884 __le64 tx_mcast_pkts; 8885 __le64 tx_bcast_pkts; 8886 __le64 tx_error_pkts; 8887 __le64 tx_discard_pkts; 8888 __le64 tx_ucast_bytes; 8889 __le64 tx_mcast_bytes; 8890 __le64 tx_bcast_bytes; 8891 __le64 tpa_pkts; 8892 __le64 tpa_bytes; 8893 __le64 tpa_events; 8894 __le64 tpa_aborts; 8895 }; 8896 8897 /* ctx_hw_stats_ext (size:1408b/176B) */ 8898 struct ctx_hw_stats_ext { 8899 __le64 rx_ucast_pkts; 8900 __le64 rx_mcast_pkts; 8901 __le64 rx_bcast_pkts; 8902 __le64 rx_discard_pkts; 8903 __le64 rx_error_pkts; 8904 __le64 rx_ucast_bytes; 8905 __le64 rx_mcast_bytes; 8906 __le64 rx_bcast_bytes; 8907 __le64 tx_ucast_pkts; 8908 __le64 tx_mcast_pkts; 8909 __le64 tx_bcast_pkts; 8910 __le64 tx_error_pkts; 8911 __le64 tx_discard_pkts; 8912 __le64 tx_ucast_bytes; 8913 __le64 tx_mcast_bytes; 8914 __le64 tx_bcast_bytes; 8915 __le64 rx_tpa_eligible_pkt; 8916 __le64 rx_tpa_eligible_bytes; 8917 __le64 rx_tpa_pkt; 8918 __le64 rx_tpa_bytes; 8919 __le64 rx_tpa_errors; 8920 __le64 rx_tpa_events; 8921 }; 8922 8923 /* hwrm_stat_ctx_alloc_input (size:384b/48B) */ 8924 struct hwrm_stat_ctx_alloc_input { 8925 __le16 req_type; 8926 __le16 cmpl_ring; 8927 __le16 seq_id; 8928 __le16 target_id; 8929 __le64 resp_addr; 8930 __le64 stats_dma_addr; 8931 __le32 update_period_ms; 8932 u8 stat_ctx_flags; 8933 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 8934 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_DUP_HOST_BUF 0x2UL 8935 u8 unused_0; 8936 __le16 stats_dma_length; 8937 __le16 flags; 8938 #define STAT_CTX_ALLOC_REQ_FLAGS_STEERING_TAG_VALID 0x1UL 8939 __le16 steering_tag; 8940 __le32 stat_ctx_id; 8941 __le16 alloc_seq_id; 8942 u8 unused_1[6]; 8943 }; 8944 8945 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 8946 struct hwrm_stat_ctx_alloc_output { 8947 __le16 error_code; 8948 __le16 req_type; 8949 __le16 seq_id; 8950 __le16 resp_len; 8951 __le32 stat_ctx_id; 8952 u8 unused_0[3]; 8953 u8 valid; 8954 }; 8955 8956 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 8957 struct hwrm_stat_ctx_free_input { 8958 __le16 req_type; 8959 __le16 cmpl_ring; 8960 __le16 seq_id; 8961 __le16 target_id; 8962 __le64 resp_addr; 8963 __le32 stat_ctx_id; 8964 u8 unused_0[4]; 8965 }; 8966 8967 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 8968 struct hwrm_stat_ctx_free_output { 8969 __le16 error_code; 8970 __le16 req_type; 8971 __le16 seq_id; 8972 __le16 resp_len; 8973 __le32 stat_ctx_id; 8974 u8 unused_0[3]; 8975 u8 valid; 8976 }; 8977 8978 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8979 struct hwrm_stat_ctx_query_input { 8980 __le16 req_type; 8981 __le16 cmpl_ring; 8982 __le16 seq_id; 8983 __le16 target_id; 8984 __le64 resp_addr; 8985 __le32 stat_ctx_id; 8986 u8 flags; 8987 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8988 u8 unused_0[3]; 8989 }; 8990 8991 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8992 struct hwrm_stat_ctx_query_output { 8993 __le16 error_code; 8994 __le16 req_type; 8995 __le16 seq_id; 8996 __le16 resp_len; 8997 __le64 tx_ucast_pkts; 8998 __le64 tx_mcast_pkts; 8999 __le64 tx_bcast_pkts; 9000 __le64 tx_discard_pkts; 9001 __le64 tx_error_pkts; 9002 __le64 tx_ucast_bytes; 9003 __le64 tx_mcast_bytes; 9004 __le64 tx_bcast_bytes; 9005 __le64 rx_ucast_pkts; 9006 __le64 rx_mcast_pkts; 9007 __le64 rx_bcast_pkts; 9008 __le64 rx_discard_pkts; 9009 __le64 rx_error_pkts; 9010 __le64 rx_ucast_bytes; 9011 __le64 rx_mcast_bytes; 9012 __le64 rx_bcast_bytes; 9013 __le64 rx_agg_pkts; 9014 __le64 rx_agg_bytes; 9015 __le64 rx_agg_events; 9016 __le64 rx_agg_aborts; 9017 u8 unused_0[7]; 9018 u8 valid; 9019 }; 9020 9021 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 9022 struct hwrm_stat_ext_ctx_query_input { 9023 __le16 req_type; 9024 __le16 cmpl_ring; 9025 __le16 seq_id; 9026 __le16 target_id; 9027 __le64 resp_addr; 9028 __le32 stat_ctx_id; 9029 u8 flags; 9030 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 9031 u8 unused_0[3]; 9032 }; 9033 9034 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 9035 struct hwrm_stat_ext_ctx_query_output { 9036 __le16 error_code; 9037 __le16 req_type; 9038 __le16 seq_id; 9039 __le16 resp_len; 9040 __le64 rx_ucast_pkts; 9041 __le64 rx_mcast_pkts; 9042 __le64 rx_bcast_pkts; 9043 __le64 rx_discard_pkts; 9044 __le64 rx_error_pkts; 9045 __le64 rx_ucast_bytes; 9046 __le64 rx_mcast_bytes; 9047 __le64 rx_bcast_bytes; 9048 __le64 tx_ucast_pkts; 9049 __le64 tx_mcast_pkts; 9050 __le64 tx_bcast_pkts; 9051 __le64 tx_error_pkts; 9052 __le64 tx_discard_pkts; 9053 __le64 tx_ucast_bytes; 9054 __le64 tx_mcast_bytes; 9055 __le64 tx_bcast_bytes; 9056 __le64 rx_tpa_eligible_pkt; 9057 __le64 rx_tpa_eligible_bytes; 9058 __le64 rx_tpa_pkt; 9059 __le64 rx_tpa_bytes; 9060 __le64 rx_tpa_errors; 9061 __le64 rx_tpa_events; 9062 u8 unused_0[7]; 9063 u8 valid; 9064 }; 9065 9066 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 9067 struct hwrm_stat_ctx_clr_stats_input { 9068 __le16 req_type; 9069 __le16 cmpl_ring; 9070 __le16 seq_id; 9071 __le16 target_id; 9072 __le64 resp_addr; 9073 __le32 stat_ctx_id; 9074 u8 unused_0[4]; 9075 }; 9076 9077 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 9078 struct hwrm_stat_ctx_clr_stats_output { 9079 __le16 error_code; 9080 __le16 req_type; 9081 __le16 seq_id; 9082 __le16 resp_len; 9083 u8 unused_0[7]; 9084 u8 valid; 9085 }; 9086 9087 /* hwrm_pcie_qstats_input (size:256b/32B) */ 9088 struct hwrm_pcie_qstats_input { 9089 __le16 req_type; 9090 __le16 cmpl_ring; 9091 __le16 seq_id; 9092 __le16 target_id; 9093 __le64 resp_addr; 9094 __le16 pcie_stat_size; 9095 u8 unused_0[6]; 9096 __le64 pcie_stat_host_addr; 9097 }; 9098 9099 /* hwrm_pcie_qstats_output (size:128b/16B) */ 9100 struct hwrm_pcie_qstats_output { 9101 __le16 error_code; 9102 __le16 req_type; 9103 __le16 seq_id; 9104 __le16 resp_len; 9105 __le16 pcie_stat_size; 9106 u8 unused_0[5]; 9107 u8 valid; 9108 }; 9109 9110 /* pcie_ctx_hw_stats (size:768b/96B) */ 9111 struct pcie_ctx_hw_stats { 9112 __le64 pcie_pl_signal_integrity; 9113 __le64 pcie_dl_signal_integrity; 9114 __le64 pcie_tl_signal_integrity; 9115 __le64 pcie_link_integrity; 9116 __le64 pcie_tx_traffic_rate; 9117 __le64 pcie_rx_traffic_rate; 9118 __le64 pcie_tx_dllp_statistics; 9119 __le64 pcie_rx_dllp_statistics; 9120 __le64 pcie_equalization_time; 9121 __le32 pcie_ltssm_histogram[4]; 9122 __le64 pcie_recovery_histogram; 9123 }; 9124 9125 /* hwrm_stat_generic_qstats_input (size:256b/32B) */ 9126 struct hwrm_stat_generic_qstats_input { 9127 __le16 req_type; 9128 __le16 cmpl_ring; 9129 __le16 seq_id; 9130 __le16 target_id; 9131 __le64 resp_addr; 9132 __le16 generic_stat_size; 9133 u8 flags; 9134 #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 9135 u8 unused_0[5]; 9136 __le64 generic_stat_host_addr; 9137 }; 9138 9139 /* hwrm_stat_generic_qstats_output (size:128b/16B) */ 9140 struct hwrm_stat_generic_qstats_output { 9141 __le16 error_code; 9142 __le16 req_type; 9143 __le16 seq_id; 9144 __le16 resp_len; 9145 __le16 generic_stat_size; 9146 u8 unused_0[5]; 9147 u8 valid; 9148 }; 9149 9150 /* generic_sw_hw_stats (size:1472b/184B) */ 9151 struct generic_sw_hw_stats { 9152 __le64 pcie_statistics_tx_tlp; 9153 __le64 pcie_statistics_rx_tlp; 9154 __le64 pcie_credit_fc_hdr_posted; 9155 __le64 pcie_credit_fc_hdr_nonposted; 9156 __le64 pcie_credit_fc_hdr_cmpl; 9157 __le64 pcie_credit_fc_data_posted; 9158 __le64 pcie_credit_fc_data_nonposted; 9159 __le64 pcie_credit_fc_data_cmpl; 9160 __le64 pcie_credit_fc_tgt_nonposted; 9161 __le64 pcie_credit_fc_tgt_data_posted; 9162 __le64 pcie_credit_fc_tgt_hdr_posted; 9163 __le64 pcie_credit_fc_cmpl_hdr_posted; 9164 __le64 pcie_credit_fc_cmpl_data_posted; 9165 __le64 pcie_cmpl_longest; 9166 __le64 pcie_cmpl_shortest; 9167 __le64 cache_miss_count_cfcq; 9168 __le64 cache_miss_count_cfcs; 9169 __le64 cache_miss_count_cfcc; 9170 __le64 cache_miss_count_cfcm; 9171 __le64 hw_db_recov_dbs_dropped; 9172 __le64 hw_db_recov_drops_serviced; 9173 __le64 hw_db_recov_dbs_recovered; 9174 __le64 hw_db_recov_oo_drop_count; 9175 }; 9176 9177 /* hwrm_fw_reset_input (size:192b/24B) */ 9178 struct hwrm_fw_reset_input { 9179 __le16 req_type; 9180 __le16 cmpl_ring; 9181 __le16 seq_id; 9182 __le16 target_id; 9183 __le64 resp_addr; 9184 u8 embedded_proc_type; 9185 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 9186 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 9187 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 9188 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 9189 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 9190 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 9191 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 9192 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 9193 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 9194 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 9195 u8 selfrst_status; 9196 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 9197 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 9198 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9199 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 9200 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 9201 u8 host_idx; 9202 u8 flags; 9203 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 9204 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 9205 u8 unused_0[4]; 9206 }; 9207 9208 /* hwrm_fw_reset_output (size:128b/16B) */ 9209 struct hwrm_fw_reset_output { 9210 __le16 error_code; 9211 __le16 req_type; 9212 __le16 seq_id; 9213 __le16 resp_len; 9214 u8 selfrst_status; 9215 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 9216 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 9217 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9218 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 9219 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 9220 u8 unused_0[6]; 9221 u8 valid; 9222 }; 9223 9224 /* hwrm_fw_qstatus_input (size:192b/24B) */ 9225 struct hwrm_fw_qstatus_input { 9226 __le16 req_type; 9227 __le16 cmpl_ring; 9228 __le16 seq_id; 9229 __le16 target_id; 9230 __le64 resp_addr; 9231 u8 embedded_proc_type; 9232 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 9233 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 9234 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 9235 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 9236 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 9237 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 9238 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 9239 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 9240 u8 unused_0[7]; 9241 }; 9242 9243 /* hwrm_fw_qstatus_output (size:128b/16B) */ 9244 struct hwrm_fw_qstatus_output { 9245 __le16 error_code; 9246 __le16 req_type; 9247 __le16 seq_id; 9248 __le16 resp_len; 9249 u8 selfrst_status; 9250 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 9251 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 9252 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9253 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 9254 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 9255 u8 nvm_option_action_status; 9256 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 9257 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 9258 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 9259 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 9260 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 9261 u8 unused_0[5]; 9262 u8 valid; 9263 }; 9264 9265 /* hwrm_fw_set_time_input (size:256b/32B) */ 9266 struct hwrm_fw_set_time_input { 9267 __le16 req_type; 9268 __le16 cmpl_ring; 9269 __le16 seq_id; 9270 __le16 target_id; 9271 __le64 resp_addr; 9272 __le16 year; 9273 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 9274 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 9275 u8 month; 9276 u8 day; 9277 u8 hour; 9278 u8 minute; 9279 u8 second; 9280 u8 unused_0; 9281 __le16 millisecond; 9282 __le16 zone; 9283 #define FW_SET_TIME_REQ_ZONE_UTC 0 9284 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 9285 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 9286 u8 unused_1[4]; 9287 }; 9288 9289 /* hwrm_fw_set_time_output (size:128b/16B) */ 9290 struct hwrm_fw_set_time_output { 9291 __le16 error_code; 9292 __le16 req_type; 9293 __le16 seq_id; 9294 __le16 resp_len; 9295 u8 unused_0[7]; 9296 u8 valid; 9297 }; 9298 9299 /* hwrm_struct_hdr (size:128b/16B) */ 9300 struct hwrm_struct_hdr { 9301 __le16 struct_id; 9302 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 9303 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 9304 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 9305 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 9306 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 9307 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 9308 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 9309 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 9310 #define STRUCT_HDR_STRUCT_ID_PEER_MMAP 0x429UL 9311 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 9312 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 9313 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 9314 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 9315 #define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_COUNT 0x12cUL 9316 #define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND 0x12dUL 9317 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND 9318 __le16 len; 9319 u8 version; 9320 u8 count; 9321 __le16 subtype; 9322 __le16 next_offset; 9323 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 9324 u8 unused_0[6]; 9325 }; 9326 9327 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 9328 struct hwrm_struct_data_dcbx_app { 9329 __be16 protocol_id; 9330 u8 protocol_selector; 9331 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 9332 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 9333 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 9334 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 9335 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 9336 u8 priority; 9337 u8 valid; 9338 u8 unused_0[3]; 9339 }; 9340 9341 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 9342 struct hwrm_fw_set_structured_data_input { 9343 __le16 req_type; 9344 __le16 cmpl_ring; 9345 __le16 seq_id; 9346 __le16 target_id; 9347 __le64 resp_addr; 9348 __le64 src_data_addr; 9349 __le16 data_len; 9350 u8 hdr_cnt; 9351 u8 unused_0[5]; 9352 }; 9353 9354 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 9355 struct hwrm_fw_set_structured_data_output { 9356 __le16 error_code; 9357 __le16 req_type; 9358 __le16 seq_id; 9359 __le16 resp_len; 9360 u8 unused_0[7]; 9361 u8 valid; 9362 }; 9363 9364 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 9365 struct hwrm_fw_set_structured_data_cmd_err { 9366 u8 code; 9367 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9368 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 9369 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 9370 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9371 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9372 u8 unused_0[7]; 9373 }; 9374 9375 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 9376 struct hwrm_fw_get_structured_data_input { 9377 __le16 req_type; 9378 __le16 cmpl_ring; 9379 __le16 seq_id; 9380 __le16 target_id; 9381 __le64 resp_addr; 9382 __le64 dest_data_addr; 9383 __le16 data_len; 9384 __le16 structure_id; 9385 __le16 subtype; 9386 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 9387 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 9388 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 9389 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 9390 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 9391 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 9392 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 9393 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 9394 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 9395 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 9396 u8 count; 9397 u8 unused_0; 9398 }; 9399 9400 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 9401 struct hwrm_fw_get_structured_data_output { 9402 __le16 error_code; 9403 __le16 req_type; 9404 __le16 seq_id; 9405 __le16 resp_len; 9406 u8 hdr_cnt; 9407 u8 unused_0[6]; 9408 u8 valid; 9409 }; 9410 9411 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 9412 struct hwrm_fw_get_structured_data_cmd_err { 9413 u8 code; 9414 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9415 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9416 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9417 u8 unused_0[7]; 9418 }; 9419 9420 /* hwrm_fw_livepatch_query_input (size:192b/24B) */ 9421 struct hwrm_fw_livepatch_query_input { 9422 __le16 req_type; 9423 __le16 cmpl_ring; 9424 __le16 seq_id; 9425 __le16 target_id; 9426 __le64 resp_addr; 9427 u8 fw_target; 9428 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 9429 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 9430 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 9431 u8 unused_0[7]; 9432 }; 9433 9434 /* hwrm_fw_livepatch_query_output (size:640b/80B) */ 9435 struct hwrm_fw_livepatch_query_output { 9436 __le16 error_code; 9437 __le16 req_type; 9438 __le16 seq_id; 9439 __le16 resp_len; 9440 char install_ver[32]; 9441 char active_ver[32]; 9442 __le16 status_flags; 9443 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 9444 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 9445 u8 unused_0[5]; 9446 u8 valid; 9447 }; 9448 9449 /* hwrm_fw_livepatch_input (size:256b/32B) */ 9450 struct hwrm_fw_livepatch_input { 9451 __le16 req_type; 9452 __le16 cmpl_ring; 9453 __le16 seq_id; 9454 __le16 target_id; 9455 __le64 resp_addr; 9456 u8 opcode; 9457 #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 9458 #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 9459 #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 9460 u8 fw_target; 9461 #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 9462 #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 9463 #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 9464 u8 loadtype; 9465 #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 9466 #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 9467 #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 9468 u8 flags; 9469 __le32 patch_len; 9470 __le64 host_addr; 9471 }; 9472 9473 /* hwrm_fw_livepatch_output (size:128b/16B) */ 9474 struct hwrm_fw_livepatch_output { 9475 __le16 error_code; 9476 __le16 req_type; 9477 __le16 seq_id; 9478 __le16 resp_len; 9479 u8 unused_0[7]; 9480 u8 valid; 9481 }; 9482 9483 /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 9484 struct hwrm_fw_livepatch_cmd_err { 9485 u8 code; 9486 #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 9487 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 9488 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 9489 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 9490 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 9491 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 9492 #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 9493 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 9494 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 9495 #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 9496 #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 9497 u8 unused_0[7]; 9498 }; 9499 9500 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 9501 struct hwrm_exec_fwd_resp_input { 9502 __le16 req_type; 9503 __le16 cmpl_ring; 9504 __le16 seq_id; 9505 __le16 target_id; 9506 __le64 resp_addr; 9507 __le32 encap_request[26]; 9508 __le16 encap_resp_target_id; 9509 u8 unused_0[6]; 9510 }; 9511 9512 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 9513 struct hwrm_exec_fwd_resp_output { 9514 __le16 error_code; 9515 __le16 req_type; 9516 __le16 seq_id; 9517 __le16 resp_len; 9518 u8 unused_0[7]; 9519 u8 valid; 9520 }; 9521 9522 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 9523 struct hwrm_reject_fwd_resp_input { 9524 __le16 req_type; 9525 __le16 cmpl_ring; 9526 __le16 seq_id; 9527 __le16 target_id; 9528 __le64 resp_addr; 9529 __le32 encap_request[26]; 9530 __le16 encap_resp_target_id; 9531 u8 unused_0[6]; 9532 }; 9533 9534 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 9535 struct hwrm_reject_fwd_resp_output { 9536 __le16 error_code; 9537 __le16 req_type; 9538 __le16 seq_id; 9539 __le16 resp_len; 9540 u8 unused_0[7]; 9541 u8 valid; 9542 }; 9543 9544 /* hwrm_fwd_resp_input (size:1024b/128B) */ 9545 struct hwrm_fwd_resp_input { 9546 __le16 req_type; 9547 __le16 cmpl_ring; 9548 __le16 seq_id; 9549 __le16 target_id; 9550 __le64 resp_addr; 9551 __le16 encap_resp_target_id; 9552 __le16 encap_resp_cmpl_ring; 9553 __le16 encap_resp_len; 9554 u8 unused_0; 9555 u8 unused_1; 9556 __le64 encap_resp_addr; 9557 __le32 encap_resp[24]; 9558 }; 9559 9560 /* hwrm_fwd_resp_output (size:128b/16B) */ 9561 struct hwrm_fwd_resp_output { 9562 __le16 error_code; 9563 __le16 req_type; 9564 __le16 seq_id; 9565 __le16 resp_len; 9566 u8 unused_0[7]; 9567 u8 valid; 9568 }; 9569 9570 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 9571 struct hwrm_fwd_async_event_cmpl_input { 9572 __le16 req_type; 9573 __le16 cmpl_ring; 9574 __le16 seq_id; 9575 __le16 target_id; 9576 __le64 resp_addr; 9577 __le16 encap_async_event_target_id; 9578 u8 unused_0[6]; 9579 __le32 encap_async_event_cmpl[4]; 9580 }; 9581 9582 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 9583 struct hwrm_fwd_async_event_cmpl_output { 9584 __le16 error_code; 9585 __le16 req_type; 9586 __le16 seq_id; 9587 __le16 resp_len; 9588 u8 unused_0[7]; 9589 u8 valid; 9590 }; 9591 9592 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 9593 struct hwrm_temp_monitor_query_input { 9594 __le16 req_type; 9595 __le16 cmpl_ring; 9596 __le16 seq_id; 9597 __le16 target_id; 9598 __le64 resp_addr; 9599 }; 9600 9601 /* hwrm_temp_monitor_query_output (size:192b/24B) */ 9602 struct hwrm_temp_monitor_query_output { 9603 __le16 error_code; 9604 __le16 req_type; 9605 __le16 seq_id; 9606 __le16 resp_len; 9607 u8 temp; 9608 u8 phy_temp; 9609 u8 om_temp; 9610 u8 flags; 9611 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 9612 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 9613 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 9614 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 9615 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 9616 #define TEMP_MONITOR_QUERY_RESP_FLAGS_THRESHOLD_VALUES_AVAILABLE 0x20UL 9617 u8 temp2; 9618 u8 phy_temp2; 9619 u8 om_temp2; 9620 u8 warn_threshold; 9621 u8 critical_threshold; 9622 u8 fatal_threshold; 9623 u8 shutdown_threshold; 9624 u8 unused_0[4]; 9625 u8 valid; 9626 }; 9627 9628 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 9629 struct hwrm_wol_filter_alloc_input { 9630 __le16 req_type; 9631 __le16 cmpl_ring; 9632 __le16 seq_id; 9633 __le16 target_id; 9634 __le64 resp_addr; 9635 __le32 flags; 9636 __le32 enables; 9637 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 9638 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 9639 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 9640 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 9641 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 9642 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 9643 __le16 port_id; 9644 u8 wol_type; 9645 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 9646 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 9647 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 9648 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 9649 u8 unused_0[5]; 9650 u8 mac_address[6]; 9651 __le16 pattern_offset; 9652 __le16 pattern_buf_size; 9653 __le16 pattern_mask_size; 9654 u8 unused_1[4]; 9655 __le64 pattern_buf_addr; 9656 __le64 pattern_mask_addr; 9657 }; 9658 9659 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 9660 struct hwrm_wol_filter_alloc_output { 9661 __le16 error_code; 9662 __le16 req_type; 9663 __le16 seq_id; 9664 __le16 resp_len; 9665 u8 wol_filter_id; 9666 u8 unused_0[6]; 9667 u8 valid; 9668 }; 9669 9670 /* hwrm_wol_filter_free_input (size:256b/32B) */ 9671 struct hwrm_wol_filter_free_input { 9672 __le16 req_type; 9673 __le16 cmpl_ring; 9674 __le16 seq_id; 9675 __le16 target_id; 9676 __le64 resp_addr; 9677 __le32 flags; 9678 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 9679 __le32 enables; 9680 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 9681 __le16 port_id; 9682 u8 wol_filter_id; 9683 u8 unused_0[5]; 9684 }; 9685 9686 /* hwrm_wol_filter_free_output (size:128b/16B) */ 9687 struct hwrm_wol_filter_free_output { 9688 __le16 error_code; 9689 __le16 req_type; 9690 __le16 seq_id; 9691 __le16 resp_len; 9692 u8 unused_0[7]; 9693 u8 valid; 9694 }; 9695 9696 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 9697 struct hwrm_wol_filter_qcfg_input { 9698 __le16 req_type; 9699 __le16 cmpl_ring; 9700 __le16 seq_id; 9701 __le16 target_id; 9702 __le64 resp_addr; 9703 __le16 port_id; 9704 __le16 handle; 9705 u8 unused_0[4]; 9706 __le64 pattern_buf_addr; 9707 __le16 pattern_buf_size; 9708 u8 unused_1[6]; 9709 __le64 pattern_mask_addr; 9710 __le16 pattern_mask_size; 9711 u8 unused_2[6]; 9712 }; 9713 9714 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 9715 struct hwrm_wol_filter_qcfg_output { 9716 __le16 error_code; 9717 __le16 req_type; 9718 __le16 seq_id; 9719 __le16 resp_len; 9720 __le16 next_handle; 9721 u8 wol_filter_id; 9722 u8 wol_type; 9723 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 9724 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 9725 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 9726 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 9727 __le32 unused_0; 9728 u8 mac_address[6]; 9729 __le16 pattern_offset; 9730 __le16 pattern_size; 9731 __le16 pattern_mask_size; 9732 u8 unused_1[3]; 9733 u8 valid; 9734 }; 9735 9736 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 9737 struct hwrm_wol_reason_qcfg_input { 9738 __le16 req_type; 9739 __le16 cmpl_ring; 9740 __le16 seq_id; 9741 __le16 target_id; 9742 __le64 resp_addr; 9743 __le16 port_id; 9744 u8 unused_0[6]; 9745 __le64 wol_pkt_buf_addr; 9746 __le16 wol_pkt_buf_size; 9747 u8 unused_1[6]; 9748 }; 9749 9750 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 9751 struct hwrm_wol_reason_qcfg_output { 9752 __le16 error_code; 9753 __le16 req_type; 9754 __le16 seq_id; 9755 __le16 resp_len; 9756 u8 wol_filter_id; 9757 u8 wol_reason; 9758 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 9759 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 9760 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 9761 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 9762 u8 wol_pkt_len; 9763 u8 unused_0[4]; 9764 u8 valid; 9765 }; 9766 9767 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 9768 struct hwrm_dbg_read_direct_input { 9769 __le16 req_type; 9770 __le16 cmpl_ring; 9771 __le16 seq_id; 9772 __le16 target_id; 9773 __le64 resp_addr; 9774 __le64 host_dest_addr; 9775 __le32 read_addr; 9776 __le32 read_len32; 9777 }; 9778 9779 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 9780 struct hwrm_dbg_read_direct_output { 9781 __le16 error_code; 9782 __le16 req_type; 9783 __le16 seq_id; 9784 __le16 resp_len; 9785 __le32 crc32; 9786 u8 unused_0[3]; 9787 u8 valid; 9788 }; 9789 9790 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 9791 struct hwrm_dbg_qcaps_input { 9792 __le16 req_type; 9793 __le16 cmpl_ring; 9794 __le16 seq_id; 9795 __le16 target_id; 9796 __le64 resp_addr; 9797 __le16 fid; 9798 u8 unused_0[6]; 9799 }; 9800 9801 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 9802 struct hwrm_dbg_qcaps_output { 9803 __le16 error_code; 9804 __le16 req_type; 9805 __le16 seq_id; 9806 __le16 resp_len; 9807 __le16 fid; 9808 u8 unused_0[2]; 9809 __le32 coredump_component_disable_caps; 9810 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 9811 __le32 flags; 9812 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 9813 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 9814 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 9815 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 9816 #define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_DDR 0x10UL 9817 #define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_CAPTURE 0x20UL 9818 #define DBG_QCAPS_RESP_FLAGS_PTRACE 0x40UL 9819 #define DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED 0x80UL 9820 u8 unused_1[3]; 9821 u8 valid; 9822 }; 9823 9824 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 9825 struct hwrm_dbg_qcfg_input { 9826 __le16 req_type; 9827 __le16 cmpl_ring; 9828 __le16 seq_id; 9829 __le16 target_id; 9830 __le64 resp_addr; 9831 __le16 fid; 9832 __le16 flags; 9833 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 9834 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 9835 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 9836 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 9837 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 9838 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 9839 __le32 coredump_component_disable_flags; 9840 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 9841 }; 9842 9843 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 9844 struct hwrm_dbg_qcfg_output { 9845 __le16 error_code; 9846 __le16 req_type; 9847 __le16 seq_id; 9848 __le16 resp_len; 9849 __le16 fid; 9850 u8 unused_0[2]; 9851 __le32 coredump_size; 9852 __le32 flags; 9853 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 9854 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 9855 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 9856 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 9857 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 9858 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 9859 __le16 async_cmpl_ring; 9860 u8 unused_2[2]; 9861 __le32 crashdump_size; 9862 u8 unused_3[3]; 9863 u8 valid; 9864 }; 9865 9866 /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ 9867 struct hwrm_dbg_crashdump_medium_cfg_input { 9868 __le16 req_type; 9869 __le16 cmpl_ring; 9870 __le16 seq_id; 9871 __le16 target_id; 9872 __le64 resp_addr; 9873 __le16 output_dest_flags; 9874 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL 9875 __le16 pg_size_lvl; 9876 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL 9877 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0 9878 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL 9879 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL 9880 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL 9881 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 9882 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL 9883 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2 9884 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2) 9885 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2) 9886 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2) 9887 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2) 9888 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2) 9889 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2) 9890 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G 9891 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL 9892 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5 9893 __le32 size; 9894 __le32 coredump_component_disable_flags; 9895 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL 9896 __le32 unused_0; 9897 __le64 pbl; 9898 }; 9899 9900 /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ 9901 struct hwrm_dbg_crashdump_medium_cfg_output { 9902 __le16 error_code; 9903 __le16 req_type; 9904 __le16 seq_id; 9905 __le16 resp_len; 9906 u8 unused_1[7]; 9907 u8 valid; 9908 }; 9909 9910 /* coredump_segment_record (size:128b/16B) */ 9911 struct coredump_segment_record { 9912 __le16 component_id; 9913 __le16 segment_id; 9914 __le16 max_instances; 9915 u8 version_hi; 9916 u8 version_low; 9917 u8 seg_flags; 9918 u8 compress_flags; 9919 #define SFLAG_COMPRESSED_ZLIB 0x1UL 9920 u8 unused_0[2]; 9921 __le32 segment_len; 9922 }; 9923 9924 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 9925 struct hwrm_dbg_coredump_list_input { 9926 __le16 req_type; 9927 __le16 cmpl_ring; 9928 __le16 seq_id; 9929 __le16 target_id; 9930 __le64 resp_addr; 9931 __le64 host_dest_addr; 9932 __le32 host_buf_len; 9933 __le16 seq_no; 9934 u8 flags; 9935 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 9936 u8 unused_0[1]; 9937 }; 9938 9939 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 9940 struct hwrm_dbg_coredump_list_output { 9941 __le16 error_code; 9942 __le16 req_type; 9943 __le16 seq_id; 9944 __le16 resp_len; 9945 u8 flags; 9946 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 9947 u8 unused_0; 9948 __le16 total_segments; 9949 __le16 data_len; 9950 u8 unused_1; 9951 u8 valid; 9952 }; 9953 9954 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 9955 struct hwrm_dbg_coredump_initiate_input { 9956 __le16 req_type; 9957 __le16 cmpl_ring; 9958 __le16 seq_id; 9959 __le16 target_id; 9960 __le64 resp_addr; 9961 __le16 component_id; 9962 __le16 segment_id; 9963 __le16 instance; 9964 __le16 unused_0; 9965 u8 seg_flags; 9966 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_LIVE_DATA 0x1UL 9967 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_CRASH_DATA 0x2UL 9968 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_COLLECT_CTX_L1_CACHE 0x4UL 9969 u8 unused_1[7]; 9970 }; 9971 9972 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 9973 struct hwrm_dbg_coredump_initiate_output { 9974 __le16 error_code; 9975 __le16 req_type; 9976 __le16 seq_id; 9977 __le16 resp_len; 9978 u8 unused_0[7]; 9979 u8 valid; 9980 }; 9981 9982 /* coredump_data_hdr (size:128b/16B) */ 9983 struct coredump_data_hdr { 9984 __le32 address; 9985 __le32 flags_length; 9986 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 9987 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 9988 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 9989 __le32 instance; 9990 __le32 next_offset; 9991 }; 9992 9993 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 9994 struct hwrm_dbg_coredump_retrieve_input { 9995 __le16 req_type; 9996 __le16 cmpl_ring; 9997 __le16 seq_id; 9998 __le16 target_id; 9999 __le64 resp_addr; 10000 __le64 host_dest_addr; 10001 __le32 host_buf_len; 10002 __le32 unused_0; 10003 __le16 component_id; 10004 __le16 segment_id; 10005 __le16 instance; 10006 __le16 unused_1; 10007 u8 seg_flags; 10008 u8 unused_2; 10009 __le16 unused_3; 10010 __le32 unused_4; 10011 __le32 seq_no; 10012 __le32 unused_5; 10013 }; 10014 10015 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 10016 struct hwrm_dbg_coredump_retrieve_output { 10017 __le16 error_code; 10018 __le16 req_type; 10019 __le16 seq_id; 10020 __le16 resp_len; 10021 u8 flags; 10022 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 10023 u8 unused_0; 10024 __le16 data_len; 10025 u8 unused_1[3]; 10026 u8 valid; 10027 }; 10028 10029 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 10030 struct hwrm_dbg_ring_info_get_input { 10031 __le16 req_type; 10032 __le16 cmpl_ring; 10033 __le16 seq_id; 10034 __le16 target_id; 10035 __le64 resp_addr; 10036 u8 ring_type; 10037 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 10038 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 10039 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 10040 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 10041 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 10042 u8 unused_0[3]; 10043 __le32 fw_ring_id; 10044 }; 10045 10046 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 10047 struct hwrm_dbg_ring_info_get_output { 10048 __le16 error_code; 10049 __le16 req_type; 10050 __le16 seq_id; 10051 __le16 resp_len; 10052 __le32 producer_index; 10053 __le32 consumer_index; 10054 __le32 cag_vector_ctrl; 10055 __le16 st_tag; 10056 u8 unused_0; 10057 u8 valid; 10058 }; 10059 10060 /* hwrm_dbg_log_buffer_flush_input (size:192b/24B) */ 10061 struct hwrm_dbg_log_buffer_flush_input { 10062 __le16 req_type; 10063 __le16 cmpl_ring; 10064 __le16 seq_id; 10065 __le16 target_id; 10066 __le64 resp_addr; 10067 __le16 type; 10068 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_SRT_TRACE 0x0UL 10069 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_SRT2_TRACE 0x1UL 10070 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CRT_TRACE 0x2UL 10071 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CRT2_TRACE 0x3UL 10072 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP0_TRACE 0x4UL 10073 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_L2_HWRM_TRACE 0x5UL 10074 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ROCE_HWRM_TRACE 0x6UL 10075 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA0_TRACE 0x7UL 10076 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA1_TRACE 0x8UL 10077 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA2_TRACE 0x9UL 10078 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP1_TRACE 0xaUL 10079 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE 0xbUL 10080 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_LAST DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE 10081 u8 unused_1[2]; 10082 __le32 flags; 10083 #define DBG_LOG_BUFFER_FLUSH_REQ_FLAGS_FLUSH_ALL_BUFFERS 0x1UL 10084 }; 10085 10086 /* hwrm_dbg_log_buffer_flush_output (size:128b/16B) */ 10087 struct hwrm_dbg_log_buffer_flush_output { 10088 __le16 error_code; 10089 __le16 req_type; 10090 __le16 seq_id; 10091 __le16 resp_len; 10092 __le32 current_buffer_offset; 10093 u8 unused_1[3]; 10094 u8 valid; 10095 }; 10096 10097 /* hwrm_nvm_read_input (size:320b/40B) */ 10098 struct hwrm_nvm_read_input { 10099 __le16 req_type; 10100 __le16 cmpl_ring; 10101 __le16 seq_id; 10102 __le16 target_id; 10103 __le64 resp_addr; 10104 __le64 host_dest_addr; 10105 __le16 dir_idx; 10106 u8 unused_0[2]; 10107 __le32 offset; 10108 __le32 len; 10109 u8 unused_1[4]; 10110 }; 10111 10112 /* hwrm_nvm_read_output (size:128b/16B) */ 10113 struct hwrm_nvm_read_output { 10114 __le16 error_code; 10115 __le16 req_type; 10116 __le16 seq_id; 10117 __le16 resp_len; 10118 u8 unused_0[7]; 10119 u8 valid; 10120 }; 10121 10122 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 10123 struct hwrm_nvm_get_dir_entries_input { 10124 __le16 req_type; 10125 __le16 cmpl_ring; 10126 __le16 seq_id; 10127 __le16 target_id; 10128 __le64 resp_addr; 10129 __le64 host_dest_addr; 10130 }; 10131 10132 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 10133 struct hwrm_nvm_get_dir_entries_output { 10134 __le16 error_code; 10135 __le16 req_type; 10136 __le16 seq_id; 10137 __le16 resp_len; 10138 u8 unused_0[7]; 10139 u8 valid; 10140 }; 10141 10142 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 10143 struct hwrm_nvm_get_dir_info_input { 10144 __le16 req_type; 10145 __le16 cmpl_ring; 10146 __le16 seq_id; 10147 __le16 target_id; 10148 __le64 resp_addr; 10149 }; 10150 10151 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 10152 struct hwrm_nvm_get_dir_info_output { 10153 __le16 error_code; 10154 __le16 req_type; 10155 __le16 seq_id; 10156 __le16 resp_len; 10157 __le32 entries; 10158 __le32 entry_length; 10159 u8 unused_0[7]; 10160 u8 valid; 10161 }; 10162 10163 /* hwrm_nvm_write_input (size:448b/56B) */ 10164 struct hwrm_nvm_write_input { 10165 __le16 req_type; 10166 __le16 cmpl_ring; 10167 __le16 seq_id; 10168 __le16 target_id; 10169 __le64 resp_addr; 10170 __le64 host_src_addr; 10171 __le16 dir_type; 10172 __le16 dir_ordinal; 10173 __le16 dir_ext; 10174 __le16 dir_attr; 10175 __le32 dir_data_length; 10176 __le16 option; 10177 __le16 flags; 10178 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 10179 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 10180 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 10181 #define NVM_WRITE_REQ_FLAGS_SKIP_CRID_CHECK 0x8UL 10182 __le32 dir_item_length; 10183 __le32 offset; 10184 __le32 len; 10185 __le32 unused_0; 10186 }; 10187 10188 /* hwrm_nvm_write_output (size:128b/16B) */ 10189 struct hwrm_nvm_write_output { 10190 __le16 error_code; 10191 __le16 req_type; 10192 __le16 seq_id; 10193 __le16 resp_len; 10194 __le32 dir_item_length; 10195 __le16 dir_idx; 10196 u8 unused_0; 10197 u8 valid; 10198 }; 10199 10200 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 10201 struct hwrm_nvm_write_cmd_err { 10202 u8 code; 10203 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 10204 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10205 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 10206 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 10207 u8 unused_0[7]; 10208 }; 10209 10210 /* hwrm_nvm_modify_input (size:320b/40B) */ 10211 struct hwrm_nvm_modify_input { 10212 __le16 req_type; 10213 __le16 cmpl_ring; 10214 __le16 seq_id; 10215 __le16 target_id; 10216 __le64 resp_addr; 10217 __le64 host_src_addr; 10218 __le16 dir_idx; 10219 __le16 flags; 10220 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 10221 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 10222 __le32 offset; 10223 __le32 len; 10224 u8 unused_1[4]; 10225 }; 10226 10227 /* hwrm_nvm_modify_output (size:128b/16B) */ 10228 struct hwrm_nvm_modify_output { 10229 __le16 error_code; 10230 __le16 req_type; 10231 __le16 seq_id; 10232 __le16 resp_len; 10233 u8 unused_0[7]; 10234 u8 valid; 10235 }; 10236 10237 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 10238 struct hwrm_nvm_find_dir_entry_input { 10239 __le16 req_type; 10240 __le16 cmpl_ring; 10241 __le16 seq_id; 10242 __le16 target_id; 10243 __le64 resp_addr; 10244 __le32 enables; 10245 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 10246 __le16 dir_idx; 10247 __le16 dir_type; 10248 __le16 dir_ordinal; 10249 __le16 dir_ext; 10250 u8 opt_ordinal; 10251 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 10252 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 10253 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 10254 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 10255 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 10256 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 10257 u8 unused_0[3]; 10258 }; 10259 10260 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 10261 struct hwrm_nvm_find_dir_entry_output { 10262 __le16 error_code; 10263 __le16 req_type; 10264 __le16 seq_id; 10265 __le16 resp_len; 10266 __le32 dir_item_length; 10267 __le32 dir_data_length; 10268 __le32 fw_ver; 10269 __le16 dir_ordinal; 10270 __le16 dir_idx; 10271 u8 unused_0[7]; 10272 u8 valid; 10273 }; 10274 10275 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 10276 struct hwrm_nvm_erase_dir_entry_input { 10277 __le16 req_type; 10278 __le16 cmpl_ring; 10279 __le16 seq_id; 10280 __le16 target_id; 10281 __le64 resp_addr; 10282 __le16 dir_idx; 10283 u8 unused_0[6]; 10284 }; 10285 10286 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 10287 struct hwrm_nvm_erase_dir_entry_output { 10288 __le16 error_code; 10289 __le16 req_type; 10290 __le16 seq_id; 10291 __le16 resp_len; 10292 u8 unused_0[7]; 10293 u8 valid; 10294 }; 10295 10296 /* hwrm_nvm_get_dev_info_input (size:192b/24B) */ 10297 struct hwrm_nvm_get_dev_info_input { 10298 __le16 req_type; 10299 __le16 cmpl_ring; 10300 __le16 seq_id; 10301 __le16 target_id; 10302 __le64 resp_addr; 10303 u8 flags; 10304 #define NVM_GET_DEV_INFO_REQ_FLAGS_SECURITY_SOC_NVM 0x1UL 10305 u8 unused_0[7]; 10306 }; 10307 10308 /* hwrm_nvm_get_dev_info_output (size:768b/96B) */ 10309 struct hwrm_nvm_get_dev_info_output { 10310 __le16 error_code; 10311 __le16 req_type; 10312 __le16 seq_id; 10313 __le16 resp_len; 10314 __le16 manufacturer_id; 10315 __le16 device_id; 10316 __le32 sector_size; 10317 __le32 nvram_size; 10318 __le32 reserved_size; 10319 __le32 available_size; 10320 u8 nvm_cfg_ver_maj; 10321 u8 nvm_cfg_ver_min; 10322 u8 nvm_cfg_ver_upd; 10323 u8 flags; 10324 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 10325 char pkg_name[16]; 10326 __le16 hwrm_fw_major; 10327 __le16 hwrm_fw_minor; 10328 __le16 hwrm_fw_build; 10329 __le16 hwrm_fw_patch; 10330 __le16 mgmt_fw_major; 10331 __le16 mgmt_fw_minor; 10332 __le16 mgmt_fw_build; 10333 __le16 mgmt_fw_patch; 10334 __le16 roce_fw_major; 10335 __le16 roce_fw_minor; 10336 __le16 roce_fw_build; 10337 __le16 roce_fw_patch; 10338 __le16 netctrl_fw_major; 10339 __le16 netctrl_fw_minor; 10340 __le16 netctrl_fw_build; 10341 __le16 netctrl_fw_patch; 10342 __le16 srt2_fw_major; 10343 __le16 srt2_fw_minor; 10344 __le16 srt2_fw_build; 10345 __le16 srt2_fw_patch; 10346 u8 unused_0[7]; 10347 u8 valid; 10348 }; 10349 10350 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 10351 struct hwrm_nvm_mod_dir_entry_input { 10352 __le16 req_type; 10353 __le16 cmpl_ring; 10354 __le16 seq_id; 10355 __le16 target_id; 10356 __le64 resp_addr; 10357 __le32 enables; 10358 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 10359 __le16 dir_idx; 10360 __le16 dir_ordinal; 10361 __le16 dir_ext; 10362 __le16 dir_attr; 10363 __le32 checksum; 10364 }; 10365 10366 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 10367 struct hwrm_nvm_mod_dir_entry_output { 10368 __le16 error_code; 10369 __le16 req_type; 10370 __le16 seq_id; 10371 __le16 resp_len; 10372 u8 unused_0[7]; 10373 u8 valid; 10374 }; 10375 10376 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 10377 struct hwrm_nvm_verify_update_input { 10378 __le16 req_type; 10379 __le16 cmpl_ring; 10380 __le16 seq_id; 10381 __le16 target_id; 10382 __le64 resp_addr; 10383 __le16 dir_type; 10384 __le16 dir_ordinal; 10385 __le16 dir_ext; 10386 u8 unused_0[2]; 10387 }; 10388 10389 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 10390 struct hwrm_nvm_verify_update_output { 10391 __le16 error_code; 10392 __le16 req_type; 10393 __le16 seq_id; 10394 __le16 resp_len; 10395 u8 unused_0[7]; 10396 u8 valid; 10397 }; 10398 10399 /* hwrm_nvm_install_update_input (size:192b/24B) */ 10400 struct hwrm_nvm_install_update_input { 10401 __le16 req_type; 10402 __le16 cmpl_ring; 10403 __le16 seq_id; 10404 __le16 target_id; 10405 __le64 resp_addr; 10406 __le32 install_type; 10407 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 10408 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 10409 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 10410 __le16 flags; 10411 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 10412 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 10413 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 10414 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 10415 u8 unused_0[2]; 10416 }; 10417 10418 /* hwrm_nvm_install_update_output (size:192b/24B) */ 10419 struct hwrm_nvm_install_update_output { 10420 __le16 error_code; 10421 __le16 req_type; 10422 __le16 seq_id; 10423 __le16 resp_len; 10424 __le64 installed_items; 10425 u8 result; 10426 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 10427 #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL 10428 #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL 10429 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL 10430 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL 10431 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL 10432 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL 10433 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL 10434 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL 10435 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL 10436 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL 10437 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL 10438 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL 10439 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL 10440 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL 10441 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL 10442 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL 10443 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL 10444 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL 10445 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL 10446 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL 10447 #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL 10448 #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL 10449 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL 10450 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL 10451 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL 10452 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL 10453 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL 10454 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 10455 u8 problem_item; 10456 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 10457 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 10458 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 10459 u8 reset_required; 10460 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 10461 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 10462 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 10463 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 10464 u8 unused_0[4]; 10465 u8 valid; 10466 }; 10467 10468 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 10469 struct hwrm_nvm_install_update_cmd_err { 10470 u8 code; 10471 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 10472 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10473 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 10474 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 10475 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL 10476 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 10477 u8 unused_0[7]; 10478 }; 10479 10480 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 10481 struct hwrm_nvm_get_variable_input { 10482 __le16 req_type; 10483 __le16 cmpl_ring; 10484 __le16 seq_id; 10485 __le16 target_id; 10486 __le64 resp_addr; 10487 __le64 dest_data_addr; 10488 __le16 data_len; 10489 __le16 option_num; 10490 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10491 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10492 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10493 __le16 dimensions; 10494 __le16 index_0; 10495 __le16 index_1; 10496 __le16 index_2; 10497 __le16 index_3; 10498 u8 flags; 10499 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 10500 u8 unused_0; 10501 }; 10502 10503 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 10504 struct hwrm_nvm_get_variable_output { 10505 __le16 error_code; 10506 __le16 req_type; 10507 __le16 seq_id; 10508 __le16 resp_len; 10509 __le16 data_len; 10510 __le16 option_num; 10511 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 10512 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 10513 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 10514 u8 unused_0[3]; 10515 u8 valid; 10516 }; 10517 10518 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 10519 struct hwrm_nvm_get_variable_cmd_err { 10520 u8 code; 10521 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10522 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10523 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10524 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10525 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 10526 u8 unused_0[7]; 10527 }; 10528 10529 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 10530 struct hwrm_nvm_set_variable_input { 10531 __le16 req_type; 10532 __le16 cmpl_ring; 10533 __le16 seq_id; 10534 __le16 target_id; 10535 __le64 resp_addr; 10536 __le64 src_data_addr; 10537 __le16 data_len; 10538 __le16 option_num; 10539 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10540 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10541 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10542 __le16 dimensions; 10543 __le16 index_0; 10544 __le16 index_1; 10545 __le16 index_2; 10546 __le16 index_3; 10547 u8 flags; 10548 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 10549 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 10550 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 10551 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 10552 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 10553 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 10554 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 10555 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 10556 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 10557 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 10558 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 10559 u8 unused_0; 10560 }; 10561 10562 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 10563 struct hwrm_nvm_set_variable_output { 10564 __le16 error_code; 10565 __le16 req_type; 10566 __le16 seq_id; 10567 __le16 resp_len; 10568 u8 unused_0[7]; 10569 u8 valid; 10570 }; 10571 10572 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 10573 struct hwrm_nvm_set_variable_cmd_err { 10574 u8 code; 10575 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10576 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10577 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10578 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 10579 u8 unused_0[7]; 10580 }; 10581 10582 /* hwrm_selftest_qlist_input (size:128b/16B) */ 10583 struct hwrm_selftest_qlist_input { 10584 __le16 req_type; 10585 __le16 cmpl_ring; 10586 __le16 seq_id; 10587 __le16 target_id; 10588 __le64 resp_addr; 10589 }; 10590 10591 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 10592 struct hwrm_selftest_qlist_output { 10593 __le16 error_code; 10594 __le16 req_type; 10595 __le16 seq_id; 10596 __le16 resp_len; 10597 u8 num_tests; 10598 u8 available_tests; 10599 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 10600 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 10601 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 10602 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 10603 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 10604 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10605 u8 offline_tests; 10606 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 10607 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 10608 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 10609 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 10610 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 10611 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10612 u8 unused_0; 10613 __le16 test_timeout; 10614 u8 unused_1[2]; 10615 char test_name[8][32]; 10616 u8 eyescope_target_BER_support; 10617 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 10618 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 10619 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 10620 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 10621 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 10622 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 10623 u8 unused_2[6]; 10624 u8 valid; 10625 }; 10626 10627 /* hwrm_selftest_exec_input (size:192b/24B) */ 10628 struct hwrm_selftest_exec_input { 10629 __le16 req_type; 10630 __le16 cmpl_ring; 10631 __le16 seq_id; 10632 __le16 target_id; 10633 __le64 resp_addr; 10634 u8 flags; 10635 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 10636 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 10637 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 10638 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 10639 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 10640 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 10641 u8 unused_0[7]; 10642 }; 10643 10644 /* hwrm_selftest_exec_output (size:128b/16B) */ 10645 struct hwrm_selftest_exec_output { 10646 __le16 error_code; 10647 __le16 req_type; 10648 __le16 seq_id; 10649 __le16 resp_len; 10650 u8 requested_tests; 10651 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 10652 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 10653 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 10654 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 10655 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 10656 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 10657 u8 test_success; 10658 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 10659 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 10660 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 10661 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 10662 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 10663 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 10664 u8 unused_0[5]; 10665 u8 valid; 10666 }; 10667 10668 /* hwrm_selftest_irq_input (size:128b/16B) */ 10669 struct hwrm_selftest_irq_input { 10670 __le16 req_type; 10671 __le16 cmpl_ring; 10672 __le16 seq_id; 10673 __le16 target_id; 10674 __le64 resp_addr; 10675 }; 10676 10677 /* hwrm_selftest_irq_output (size:128b/16B) */ 10678 struct hwrm_selftest_irq_output { 10679 __le16 error_code; 10680 __le16 req_type; 10681 __le16 seq_id; 10682 __le16 resp_len; 10683 u8 unused_0[7]; 10684 u8 valid; 10685 }; 10686 10687 /* dbc_dbc (size:64b/8B) */ 10688 struct dbc_dbc { 10689 __le32 index; 10690 #define DBC_DBC_INDEX_MASK 0xffffffUL 10691 #define DBC_DBC_INDEX_SFT 0 10692 #define DBC_DBC_EPOCH 0x1000000UL 10693 #define DBC_DBC_TOGGLE_MASK 0x6000000UL 10694 #define DBC_DBC_TOGGLE_SFT 25 10695 __le32 type_path_xid; 10696 #define DBC_DBC_XID_MASK 0xfffffUL 10697 #define DBC_DBC_XID_SFT 0 10698 #define DBC_DBC_PATH_MASK 0x3000000UL 10699 #define DBC_DBC_PATH_SFT 24 10700 #define DBC_DBC_PATH_ROCE (0x0UL << 24) 10701 #define DBC_DBC_PATH_L2 (0x1UL << 24) 10702 #define DBC_DBC_PATH_ENGINE (0x2UL << 24) 10703 #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE 10704 #define DBC_DBC_VALID 0x4000000UL 10705 #define DBC_DBC_DEBUG_TRACE 0x8000000UL 10706 #define DBC_DBC_TYPE_MASK 0xf0000000UL 10707 #define DBC_DBC_TYPE_SFT 28 10708 #define DBC_DBC_TYPE_SQ (0x0UL << 28) 10709 #define DBC_DBC_TYPE_RQ (0x1UL << 28) 10710 #define DBC_DBC_TYPE_SRQ (0x2UL << 28) 10711 #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28) 10712 #define DBC_DBC_TYPE_CQ (0x4UL << 28) 10713 #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28) 10714 #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28) 10715 #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28) 10716 #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28) 10717 #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28) 10718 #define DBC_DBC_TYPE_NQ (0xaUL << 28) 10719 #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28) 10720 #define DBC_DBC_TYPE_NQ_MASK (0xeUL << 28) 10721 #define DBC_DBC_TYPE_NULL (0xfUL << 28) 10722 #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL 10723 }; 10724 10725 /* db_push_start (size:64b/8B) */ 10726 struct db_push_start { 10727 u64 db; 10728 #define DB_PUSH_START_DB_INDEX_MASK 0xffffffUL 10729 #define DB_PUSH_START_DB_INDEX_SFT 0 10730 #define DB_PUSH_START_DB_PI_LO_MASK 0xff000000UL 10731 #define DB_PUSH_START_DB_PI_LO_SFT 24 10732 #define DB_PUSH_START_DB_XID_MASK 0xfffff00000000ULL 10733 #define DB_PUSH_START_DB_XID_SFT 32 10734 #define DB_PUSH_START_DB_PI_HI_MASK 0xf0000000000000ULL 10735 #define DB_PUSH_START_DB_PI_HI_SFT 52 10736 #define DB_PUSH_START_DB_TYPE_MASK 0xf000000000000000ULL 10737 #define DB_PUSH_START_DB_TYPE_SFT 60 10738 #define DB_PUSH_START_DB_TYPE_PUSH_START (0xcULL << 60) 10739 #define DB_PUSH_START_DB_TYPE_PUSH_END (0xdULL << 60) 10740 #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END 10741 }; 10742 10743 /* db_push_end (size:64b/8B) */ 10744 struct db_push_end { 10745 u64 db; 10746 #define DB_PUSH_END_DB_INDEX_MASK 0xffffffUL 10747 #define DB_PUSH_END_DB_INDEX_SFT 0 10748 #define DB_PUSH_END_DB_PI_LO_MASK 0xff000000UL 10749 #define DB_PUSH_END_DB_PI_LO_SFT 24 10750 #define DB_PUSH_END_DB_XID_MASK 0xfffff00000000ULL 10751 #define DB_PUSH_END_DB_XID_SFT 32 10752 #define DB_PUSH_END_DB_PI_HI_MASK 0xf0000000000000ULL 10753 #define DB_PUSH_END_DB_PI_HI_SFT 52 10754 #define DB_PUSH_END_DB_PATH_MASK 0x300000000000000ULL 10755 #define DB_PUSH_END_DB_PATH_SFT 56 10756 #define DB_PUSH_END_DB_PATH_ROCE (0x0ULL << 56) 10757 #define DB_PUSH_END_DB_PATH_L2 (0x1ULL << 56) 10758 #define DB_PUSH_END_DB_PATH_ENGINE (0x2ULL << 56) 10759 #define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE 10760 #define DB_PUSH_END_DB_DEBUG_TRACE 0x800000000000000ULL 10761 #define DB_PUSH_END_DB_TYPE_MASK 0xf000000000000000ULL 10762 #define DB_PUSH_END_DB_TYPE_SFT 60 10763 #define DB_PUSH_END_DB_TYPE_PUSH_START (0xcULL << 60) 10764 #define DB_PUSH_END_DB_TYPE_PUSH_END (0xdULL << 60) 10765 #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END 10766 }; 10767 10768 /* db_push_info (size:64b/8B) */ 10769 struct db_push_info { 10770 u32 push_size_push_index; 10771 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 10772 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 10773 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 10774 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 10775 u32 reserved32; 10776 }; 10777 10778 /* fw_status_reg (size:32b/4B) */ 10779 struct fw_status_reg { 10780 u32 fw_status; 10781 #define FW_STATUS_REG_CODE_MASK 0xffffUL 10782 #define FW_STATUS_REG_CODE_SFT 0 10783 #define FW_STATUS_REG_CODE_READY 0x8000UL 10784 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 10785 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 10786 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 10787 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 10788 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 10789 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 10790 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 10791 #define FW_STATUS_REG_RECOVERING 0x400000UL 10792 #define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL 10793 }; 10794 10795 /* hcomm_status (size:64b/8B) */ 10796 struct hcomm_status { 10797 u32 sig_ver; 10798 #define HCOMM_STATUS_VER_MASK 0xffUL 10799 #define HCOMM_STATUS_VER_SFT 0 10800 #define HCOMM_STATUS_VER_LATEST 0x1UL 10801 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 10802 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 10803 #define HCOMM_STATUS_SIGNATURE_SFT 8 10804 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 10805 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 10806 u32 fw_status_loc; 10807 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 10808 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 10809 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 10810 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 10811 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 10812 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 10813 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 10814 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 10815 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 10816 }; 10817 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 10818 10819 #endif /* _BNXT_HSI_H_ */ 10820