1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 4 * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> 5 * Author: Markus Gothe <markus.gothe@genexis.eu> 6 */ 7 8 #include "airoha-common.h" 9 10 /* MUX */ 11 #define REG_SW_TOD_1PPS_MODE 0x0214 12 #define GPIO_LAN3_LED1_MODE_MASK BIT(10) 13 #define GPIO_LAN3_LED0_MODE_MASK BIT(9) 14 #define GPIO_LAN2_LED1_MODE_MASK BIT(8) 15 #define GPIO_LAN2_LED0_MODE_MASK BIT(7) 16 #define GPIO_LAN1_LED1_MODE_MASK BIT(6) 17 #define GPIO_LAN1_LED0_MODE_MASK BIT(5) 18 #define GPIO_LAN0_LED1_MODE_MASK BIT(4) 19 #define GPIO_LAN0_LED0_MODE_MASK BIT(3) 20 #define PON_TOD_1PPS_MODE_MASK BIT(2) 21 #define GSW_TOD_1PPS_MODE_MASK BIT(1) 22 23 #define REG_GPIO_SPI_CS1_MODE 0x0218 24 #define GPIO_MDC_IO_MASTER_MODE_MASK BIT(22) 25 #define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) 26 #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) 27 #define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) 28 #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) 29 #define GPIO_PCM_SPI_MODE_MASK BIT(16) 30 #define GPIO_PCM2_MODE_MASK BIT(13) 31 #define GPIO_PCM1_MODE_MASK BIT(12) 32 #define GPIO_PCM_INT_MODE_MASK BIT(9) 33 #define GPIO_PCM_RESET_MODE_MASK BIT(8) 34 #define GPIO_SPI_QUAD_MODE_MASK BIT(4) 35 #define GPIO_SPI_CS4_MODE_MASK BIT(3) 36 #define GPIO_SPI_CS3_MODE_MASK BIT(2) 37 #define GPIO_SPI_CS2_MODE_MASK BIT(1) 38 #define GPIO_SPI_CS1_MODE_MASK BIT(0) 39 40 #define REG_GPIO_PON_MODE 0x021c 41 #define GPIO_PON_ALT_MODE_MASK BIT(27) 42 #define MDIO_0_GPIO_MODE_MASK BIT(26) 43 #define MDC_0_GPIO_MODE_MASK BIT(25) 44 #define UART_RXD_GPIO_MODE_MASK BIT(24) 45 #define UART_TXD_GPIO_MODE_MASK BIT(23) 46 #define SPI_MISO_GPIO_MODE_MASK BIT(22) 47 #define SPI_MOSI_GPIO_MODE_MASK BIT(21) 48 #define SPI_CS_GPIO_MODE_MASK BIT(20) 49 #define SPI_CLK_GPIO_MODE_MASK BIT(19) 50 #define I2C1_SDA_GPIO_MODE_MASK BIT(18) 51 #define I2C1_SCL_GPIO_MODE_MASK BIT(17) 52 #define I2C0_SDA_GPIO_MODE_MASK BIT(16) 53 #define I2C0_SCL_GPIO_MODE_MASK BIT(15) 54 #define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) 55 #define GPIO_SGMII_MDIO_MODE_MASK BIT(13) 56 #define GPIO_OLT_MODE_MASK BIT(12) 57 #define SIPO_RCLK_MODE_MASK BIT(11) 58 #define GPIO_PCIE_RESET1_MASK BIT(10) 59 #define GPIO_PCIE_RESET0_MASK BIT(9) 60 #define GPIO_UART5_MODE_MASK BIT(8) 61 #define GPIO_UART4_MODE_MASK BIT(7) 62 #define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) 63 #define GPIO_HSUART_MODE_MASK BIT(5) 64 #define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) 65 #define GPIO_UART2_MODE_MASK BIT(3) 66 #define GPIO_SIPO_MODE_MASK BIT(2) 67 #define GPIO_EMMC_MODE_MASK BIT(1) 68 #define GPIO_PON_MODE_MASK BIT(0) 69 70 #define REG_NPU_UART_EN 0x0224 71 #define JTAG_UDI_EN_MASK BIT(4) 72 #define JTAG_DFD_EN_MASK BIT(3) 73 #define NPU_UART_EN_MASK BIT(2) 74 75 #define REG_FORCE_GPIO_EN 0x0228 76 #define FORCE_GPIO_EN(n) BIT(n) 77 78 /* LED MAP */ 79 #define REG_LAN_LED0_MAPPING 0x027c 80 #define REG_LAN_LED1_MAPPING 0x0280 81 82 #define LAN4_LED_MAPPING_MASK GENMASK(18, 16) 83 #define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) 84 85 #define LAN3_LED_MAPPING_MASK GENMASK(14, 12) 86 #define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) 87 88 #define LAN2_LED_MAPPING_MASK GENMASK(10, 8) 89 #define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) 90 91 #define LAN1_LED_MAPPING_MASK GENMASK(6, 4) 92 #define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) 93 94 #define LAN0_LED_MAPPING_MASK GENMASK(2, 0) 95 #define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) 96 97 /* CONF */ 98 #define REG_I2C_SDA_E2 0x001c 99 #define I2C1_SCL_E2_MASK BIT(16) 100 #define I2C1_SDA_E2_MASK BIT(15) 101 #define SPI_MISO_E2_MASK BIT(14) 102 #define SPI_MOSI_E2_MASK BIT(13) 103 #define SPI_CLK_E2_MASK BIT(12) 104 #define SPI_CS0_E2_MASK BIT(11) 105 #define PCIE1_RESET_E2_MASK BIT(9) 106 #define PCIE0_RESET_E2_MASK BIT(8) 107 #define MDIO_0_E2_MASK BIT(5) 108 #define MDC_0_E2_MASK BIT(4) 109 #define UART1_RXD_E2_MASK BIT(3) 110 #define UART1_TXD_E2_MASK BIT(2) 111 #define I2C_SCL_E2_MASK BIT(1) 112 #define I2C_SDA_E2_MASK BIT(0) 113 114 #define REG_I2C_SDA_E4 0x0020 115 #define I2C1_SCL_E4_MASK BIT(16) 116 #define I2C1_SDA_E4_MASK BIT(15) 117 #define SPI_MISO_E4_MASK BIT(14) 118 #define SPI_MOSI_E4_MASK BIT(13) 119 #define SPI_CLK_E4_MASK BIT(12) 120 #define SPI_CS0_E4_MASK BIT(11) 121 #define PCIE1_RESET_E4_MASK BIT(9) 122 #define PCIE0_RESET_E4_MASK BIT(8) 123 #define MDIO_0_E4_MASK BIT(5) 124 #define MDC_0_E4_MASK BIT(4) 125 #define UART1_RXD_E4_MASK BIT(3) 126 #define UART1_TXD_E4_MASK BIT(2) 127 #define I2C_SCL_E4_MASK BIT(1) 128 #define I2C_SDA_E4_MASK BIT(0) 129 130 #define REG_GPIO_L_E2 0x0024 131 #define REG_GPIO_L_E4 0x0028 132 #define REG_GPIO_H_E2 0x002c 133 #define REG_GPIO_H_E4 0x0030 134 135 #define REG_I2C_SDA_PU 0x0044 136 #define I2C1_SCL_PU_MASK BIT(16) 137 #define I2C1_SDA_PU_MASK BIT(15) 138 #define SPI_MISO_PU_MASK BIT(14) 139 #define SPI_MOSI_PU_MASK BIT(13) 140 #define SPI_CLK_PU_MASK BIT(12) 141 #define SPI_CS0_PU_MASK BIT(11) 142 #define PCIE1_RESET_PU_MASK BIT(9) 143 #define PCIE0_RESET_PU_MASK BIT(8) 144 #define MDIO_0_PU_MASK BIT(5) 145 #define MDC_0_PU_MASK BIT(4) 146 #define UART1_RXD_PU_MASK BIT(3) 147 #define UART1_TXD_PU_MASK BIT(2) 148 #define I2C_SCL_PU_MASK BIT(1) 149 #define I2C_SDA_PU_MASK BIT(0) 150 151 #define REG_I2C_SDA_PD 0x0048 152 #define I2C1_SCL_PD_MASK BIT(16) 153 #define I2C1_SDA_PD_MASK BIT(15) 154 #define SPI_MISO_PD_MASK BIT(14) 155 #define SPI_MOSI_PD_MASK BIT(13) 156 #define SPI_CLK_PD_MASK BIT(12) 157 #define SPI_CS0_PD_MASK BIT(11) 158 #define PCIE1_RESET_PD_MASK BIT(9) 159 #define PCIE0_RESET_PD_MASK BIT(8) 160 #define MDIO_0_PD_MASK BIT(5) 161 #define MDC_0_PD_MASK BIT(4) 162 #define UART1_RXD_PD_MASK BIT(3) 163 #define UART1_TXD_PD_MASK BIT(2) 164 #define I2C_SCL_PD_MASK BIT(1) 165 #define I2C_SDA_PD_MASK BIT(0) 166 167 #define REG_GPIO_L_PU 0x004c 168 #define REG_GPIO_L_PD 0x0050 169 #define REG_GPIO_H_PU 0x0054 170 #define REG_GPIO_H_PD 0x0058 171 172 #define REG_PCIE_RESET_OD 0x018c 173 #define PCIE1_RESET_OD_MASK BIT(1) 174 #define PCIE0_RESET_OD_MASK BIT(0) 175 176 /* PWM MODE CONF */ 177 #define REG_GPIO_FLASH_MODE_CFG 0x0034 178 #define GPIO15_FLASH_MODE_CFG BIT(15) 179 #define GPIO14_FLASH_MODE_CFG BIT(14) 180 #define GPIO13_FLASH_MODE_CFG BIT(13) 181 #define GPIO12_FLASH_MODE_CFG BIT(12) 182 #define GPIO11_FLASH_MODE_CFG BIT(11) 183 #define GPIO10_FLASH_MODE_CFG BIT(10) 184 #define GPIO9_FLASH_MODE_CFG BIT(9) 185 #define GPIO8_FLASH_MODE_CFG BIT(8) 186 #define GPIO7_FLASH_MODE_CFG BIT(7) 187 #define GPIO6_FLASH_MODE_CFG BIT(6) 188 #define GPIO5_FLASH_MODE_CFG BIT(5) 189 #define GPIO4_FLASH_MODE_CFG BIT(4) 190 #define GPIO3_FLASH_MODE_CFG BIT(3) 191 #define GPIO2_FLASH_MODE_CFG BIT(2) 192 #define GPIO1_FLASH_MODE_CFG BIT(1) 193 #define GPIO0_FLASH_MODE_CFG BIT(0) 194 195 /* PWM MODE CONF EXT */ 196 #define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 197 #define GPIO51_FLASH_MODE_CFG BIT(31) 198 #define GPIO50_FLASH_MODE_CFG BIT(30) 199 #define GPIO49_FLASH_MODE_CFG BIT(29) 200 #define GPIO48_FLASH_MODE_CFG BIT(28) 201 #define GPIO47_FLASH_MODE_CFG BIT(27) 202 #define GPIO46_FLASH_MODE_CFG BIT(26) 203 #define GPIO45_FLASH_MODE_CFG BIT(25) 204 #define GPIO44_FLASH_MODE_CFG BIT(24) 205 #define GPIO43_FLASH_MODE_CFG BIT(23) 206 #define GPIO42_FLASH_MODE_CFG BIT(22) 207 #define GPIO41_FLASH_MODE_CFG BIT(21) 208 #define GPIO40_FLASH_MODE_CFG BIT(20) 209 #define GPIO39_FLASH_MODE_CFG BIT(19) 210 #define GPIO38_FLASH_MODE_CFG BIT(18) 211 #define GPIO37_FLASH_MODE_CFG BIT(17) 212 #define GPIO36_FLASH_MODE_CFG BIT(16) 213 #define GPIO31_FLASH_MODE_CFG BIT(15) 214 #define GPIO30_FLASH_MODE_CFG BIT(14) 215 #define GPIO29_FLASH_MODE_CFG BIT(13) 216 #define GPIO28_FLASH_MODE_CFG BIT(12) 217 #define GPIO27_FLASH_MODE_CFG BIT(11) 218 #define GPIO26_FLASH_MODE_CFG BIT(10) 219 #define GPIO25_FLASH_MODE_CFG BIT(9) 220 #define GPIO24_FLASH_MODE_CFG BIT(8) 221 #define GPIO23_FLASH_MODE_CFG BIT(7) 222 #define GPIO22_FLASH_MODE_CFG BIT(6) 223 #define GPIO21_FLASH_MODE_CFG BIT(5) 224 #define GPIO20_FLASH_MODE_CFG BIT(4) 225 #define GPIO19_FLASH_MODE_CFG BIT(3) 226 #define GPIO18_FLASH_MODE_CFG BIT(2) 227 #define GPIO17_FLASH_MODE_CFG BIT(1) 228 #define GPIO16_FLASH_MODE_CFG BIT(0) 229 230 #define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ 231 { \ 232 .name = (gpio), \ 233 .regmap[0] = { \ 234 AIROHA_FUNC_MUX, \ 235 REG_GPIO_PON_MODE, \ 236 (mux_val), \ 237 (mux_val) \ 238 }, \ 239 .regmap_size = 1, \ 240 } 241 242 #define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ 243 { \ 244 .name = (gpio), \ 245 .regmap[0] = { \ 246 AIROHA_FUNC_PWM_EXT_MUX, \ 247 REG_GPIO_FLASH_MODE_CFG_EXT, \ 248 (mux_val), \ 249 0 \ 250 }, \ 251 .regmap[1] = { \ 252 AIROHA_FUNC_MUX, \ 253 REG_GPIO_PON_MODE, \ 254 (smux_val), \ 255 (smux_val) \ 256 }, \ 257 .regmap_size = 2, \ 258 } 259 260 /* PWM */ 261 #define AIROHA_PINCTRL_PWM(gpio, mux_val) \ 262 { \ 263 .name = (gpio), \ 264 .regmap[0] = { \ 265 AIROHA_FUNC_PWM_MUX, \ 266 REG_GPIO_FLASH_MODE_CFG, \ 267 (mux_val), \ 268 (mux_val) \ 269 }, \ 270 .regmap_size = 1, \ 271 } 272 273 #define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ 274 { \ 275 .name = (gpio), \ 276 .regmap[0] = { \ 277 AIROHA_FUNC_PWM_EXT_MUX, \ 278 REG_GPIO_FLASH_MODE_CFG_EXT, \ 279 (mux_val), \ 280 (mux_val) \ 281 }, \ 282 .regmap_size = 1, \ 283 } 284 285 #define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ 286 { \ 287 .name = (gpio), \ 288 .regmap[0] = { \ 289 AIROHA_FUNC_PWM_EXT_MUX, \ 290 REG_GPIO_FLASH_MODE_CFG_EXT, \ 291 (mux_val), \ 292 (mux_val) \ 293 }, \ 294 .regmap[1] = { \ 295 AIROHA_FUNC_MUX, \ 296 REG_GPIO_PON_MODE, \ 297 (smux_val), \ 298 (smux_val) \ 299 }, \ 300 .regmap_size = 2, \ 301 } 302 303 #define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ 304 { \ 305 .name = (gpio), \ 306 .regmap[0] = { \ 307 AIROHA_FUNC_MUX, \ 308 REG_SW_TOD_1PPS_MODE, \ 309 (mux_val), \ 310 (mux_val), \ 311 }, \ 312 .regmap[1] = { \ 313 AIROHA_FUNC_MUX, \ 314 REG_LAN_LED0_MAPPING, \ 315 (map_mask), \ 316 (map_val), \ 317 }, \ 318 .regmap_size = 2, \ 319 } 320 321 #define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ 322 { \ 323 .name = (gpio), \ 324 .regmap[0] = { \ 325 AIROHA_FUNC_MUX, \ 326 REG_SW_TOD_1PPS_MODE, \ 327 (mux_val), \ 328 (mux_val), \ 329 }, \ 330 .regmap[1] = { \ 331 AIROHA_FUNC_MUX, \ 332 REG_LAN_LED1_MAPPING, \ 333 (map_mask), \ 334 (map_val), \ 335 }, \ 336 .regmap_size = 2, \ 337 } 338 339 static struct pinctrl_pin_desc pinctrl_pins[] = { 340 PINCTRL_PIN(2, "gpio0"), 341 PINCTRL_PIN(3, "gpio1"), 342 PINCTRL_PIN(4, "gpio2"), 343 PINCTRL_PIN(5, "gpio3"), 344 PINCTRL_PIN(6, "gpio4"), 345 PINCTRL_PIN(7, "gpio5"), 346 PINCTRL_PIN(8, "gpio6"), 347 PINCTRL_PIN(9, "gpio7"), 348 PINCTRL_PIN(10, "gpio8"), 349 PINCTRL_PIN(11, "gpio9"), 350 PINCTRL_PIN(12, "gpio10"), 351 PINCTRL_PIN(13, "gpio11"), 352 PINCTRL_PIN(14, "gpio12"), 353 PINCTRL_PIN(15, "gpio13"), 354 PINCTRL_PIN(16, "gpio14"), 355 PINCTRL_PIN(17, "gpio15"), 356 PINCTRL_PIN(18, "gpio16"), 357 PINCTRL_PIN(19, "gpio17"), 358 PINCTRL_PIN(20, "gpio18"), 359 PINCTRL_PIN(21, "gpio19"), 360 PINCTRL_PIN(22, "gpio20"), 361 PINCTRL_PIN(23, "gpio21"), 362 PINCTRL_PIN(24, "gpio22"), 363 PINCTRL_PIN(25, "gpio23"), 364 PINCTRL_PIN(26, "gpio24"), 365 PINCTRL_PIN(27, "gpio25"), 366 PINCTRL_PIN(28, "gpio26"), 367 PINCTRL_PIN(29, "gpio27"), 368 PINCTRL_PIN(30, "gpio28"), 369 PINCTRL_PIN(31, "gpio29"), 370 PINCTRL_PIN(32, "gpio30"), 371 PINCTRL_PIN(33, "gpio31"), 372 PINCTRL_PIN(34, "gpio32"), 373 PINCTRL_PIN(35, "gpio33"), 374 PINCTRL_PIN(36, "gpio34"), 375 PINCTRL_PIN(37, "gpio35"), 376 PINCTRL_PIN(38, "gpio36"), 377 PINCTRL_PIN(39, "gpio37"), 378 PINCTRL_PIN(40, "gpio38"), 379 PINCTRL_PIN(41, "i2c0_scl"), 380 PINCTRL_PIN(42, "i2c0_sda"), 381 PINCTRL_PIN(43, "i2c1_scl"), 382 PINCTRL_PIN(44, "i2c1_sda"), 383 PINCTRL_PIN(45, "spi_clk"), 384 PINCTRL_PIN(46, "spi_cs"), 385 PINCTRL_PIN(47, "spi_mosi"), 386 PINCTRL_PIN(48, "spi_miso"), 387 PINCTRL_PIN(49, "uart_txd"), 388 PINCTRL_PIN(50, "uart_rxd"), 389 PINCTRL_PIN(51, "pcie_reset0"), 390 PINCTRL_PIN(52, "pcie_reset1"), 391 PINCTRL_PIN(53, "mdc_0"), 392 PINCTRL_PIN(54, "mdio_0"), 393 }; 394 395 static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 }; 396 static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 }; 397 static const int olt_pins[] = { 36, 37, 38, 39, 40 }; 398 static const int pon_tod_1pps_pins[] = { 32 }; 399 static const int gsw_tod_1pps_pins[] = { 32 }; 400 static const int sipo_pins[] = { 34, 35 }; 401 static const int sipo_rclk_pins[] = { 34, 35, 33 }; 402 static const int mdio_pins[] = { 53, 54 }; 403 static const int mdio1_pins[] = { 43, 44 }; 404 static const int uart2_pins[] = { 34, 35 }; 405 static const int uart2_cts_rts_pins[] = { 32, 33 }; 406 static const int hsuart_pins[] = { 30, 31 }; 407 static const int hsuart_cts_rts_pins[] = { 28, 29 }; 408 static const int npu_uart_pins[] = { 7, 8 }; 409 static const int uart4_pins[] = { 7, 8 }; 410 static const int uart5_pins[] = { 23, 24 }; 411 static const int i2c0_pins[] = { 41, 42 }; 412 static const int i2c1_pins[] = { 43, 44 }; 413 static const int jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; 414 static const int jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; 415 static const int pcm1_pins[] = { 10, 11, 12, 13, 14 }; 416 static const int pcm2_pins[] = { 28, 29, 30, 31, 24 }; 417 static const int spi_pins[] = { 45, 46, 47, 48 }; 418 static const int spi_quad_pins[] = { 25, 26 }; 419 static const int spi_cs1_pins[] = { 27 }; 420 static const int pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; 421 static const int pcm_spi_rst_pins[] = { 14 }; 422 static const int pcm_spi_cs1_pins[] = { 24 }; 423 static const int emmc_pins[] = { 424 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 425 }; 426 static const int pnand_pins[] = { 427 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 428 }; 429 static const int gpio0_pins[] = { 2 }; 430 static const int gpio1_pins[] = { 3 }; 431 static const int gpio2_pins[] = { 4 }; 432 static const int gpio3_pins[] = { 5 }; 433 static const int gpio4_pins[] = { 6 }; 434 static const int gpio5_pins[] = { 7 }; 435 static const int gpio6_pins[] = { 8 }; 436 static const int gpio7_pins[] = { 9 }; 437 static const int gpio8_pins[] = { 10 }; 438 static const int gpio9_pins[] = { 11 }; 439 static const int gpio10_pins[] = { 12 }; 440 static const int gpio11_pins[] = { 13 }; 441 static const int gpio12_pins[] = { 14 }; 442 static const int gpio13_pins[] = { 15 }; 443 static const int gpio14_pins[] = { 16 }; 444 static const int gpio15_pins[] = { 17 }; 445 static const int gpio16_pins[] = { 18 }; 446 static const int gpio17_pins[] = { 19 }; 447 static const int gpio18_pins[] = { 20 }; 448 static const int gpio19_pins[] = { 21 }; 449 static const int gpio20_pins[] = { 22 }; 450 static const int gpio21_pins[] = { 23 }; 451 static const int gpio22_pins[] = { 24 }; 452 static const int gpio23_pins[] = { 25 }; 453 static const int gpio24_pins[] = { 26 }; 454 static const int gpio25_pins[] = { 27 }; 455 static const int gpio26_pins[] = { 28 }; 456 static const int gpio27_pins[] = { 29 }; 457 static const int gpio28_pins[] = { 30 }; 458 static const int gpio29_pins[] = { 31 }; 459 static const int gpio30_pins[] = { 32 }; 460 static const int gpio31_pins[] = { 33 }; 461 static const int gpio32_pins[] = { 34 }; 462 static const int gpio33_pins[] = { 35 }; 463 static const int gpio34_pins[] = { 36 }; 464 static const int gpio35_pins[] = { 37 }; 465 static const int gpio36_pins[] = { 38 }; 466 static const int gpio37_pins[] = { 39 }; 467 static const int gpio38_pins[] = { 40 }; 468 static const int gpio39_pins[] = { 41 }; 469 static const int gpio40_pins[] = { 42 }; 470 static const int gpio41_pins[] = { 43 }; 471 static const int gpio42_pins[] = { 44 }; 472 static const int gpio43_pins[] = { 45 }; 473 static const int gpio44_pins[] = { 46 }; 474 static const int gpio45_pins[] = { 47 }; 475 static const int gpio46_pins[] = { 48 }; 476 static const int gpio47_pins[] = { 49 }; 477 static const int gpio48_pins[] = { 50 }; 478 static const int gpio49_pins[] = { 51 }; 479 static const int gpio50_pins[] = { 52 }; 480 static const int gpio51_pins[] = { 53 }; 481 static const int gpio52_pins[] = { 54 }; 482 static const int pcie_reset0_pins[] = { 51 }; 483 static const int pcie_reset1_pins[] = { 52 }; 484 485 static const struct pingroup pinctrl_groups[] = { 486 PINCTRL_PIN_GROUP("pon", pon), 487 PINCTRL_PIN_GROUP("pon_alt", pon_alt), 488 PINCTRL_PIN_GROUP("olt", olt), 489 PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), 490 PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), 491 PINCTRL_PIN_GROUP("sipo", sipo), 492 PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), 493 PINCTRL_PIN_GROUP("mdio", mdio), 494 PINCTRL_PIN_GROUP("mdio1", mdio1), 495 PINCTRL_PIN_GROUP("uart2", uart2), 496 PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), 497 PINCTRL_PIN_GROUP("hsuart", hsuart), 498 PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), 499 PINCTRL_PIN_GROUP("npu_uart", npu_uart), 500 PINCTRL_PIN_GROUP("uart4", uart4), 501 PINCTRL_PIN_GROUP("uart5", uart5), 502 PINCTRL_PIN_GROUP("i2c0", i2c0), 503 PINCTRL_PIN_GROUP("i2c1", i2c1), 504 PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), 505 PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), 506 PINCTRL_PIN_GROUP("pcm1", pcm1), 507 PINCTRL_PIN_GROUP("pcm2", pcm2), 508 PINCTRL_PIN_GROUP("spi", spi), 509 PINCTRL_PIN_GROUP("spi_quad", spi_quad), 510 PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), 511 PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), 512 PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), 513 PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), 514 PINCTRL_PIN_GROUP("emmc", emmc), 515 PINCTRL_PIN_GROUP("pnand", pnand), 516 PINCTRL_PIN_GROUP("gpio0", gpio0), 517 PINCTRL_PIN_GROUP("gpio1", gpio1), 518 PINCTRL_PIN_GROUP("gpio2", gpio2), 519 PINCTRL_PIN_GROUP("gpio3", gpio3), 520 PINCTRL_PIN_GROUP("gpio4", gpio4), 521 PINCTRL_PIN_GROUP("gpio5", gpio5), 522 PINCTRL_PIN_GROUP("gpio6", gpio6), 523 PINCTRL_PIN_GROUP("gpio7", gpio7), 524 PINCTRL_PIN_GROUP("gpio8", gpio8), 525 PINCTRL_PIN_GROUP("gpio9", gpio9), 526 PINCTRL_PIN_GROUP("gpio10", gpio10), 527 PINCTRL_PIN_GROUP("gpio11", gpio11), 528 PINCTRL_PIN_GROUP("gpio12", gpio12), 529 PINCTRL_PIN_GROUP("gpio13", gpio13), 530 PINCTRL_PIN_GROUP("gpio14", gpio14), 531 PINCTRL_PIN_GROUP("gpio15", gpio15), 532 PINCTRL_PIN_GROUP("gpio16", gpio16), 533 PINCTRL_PIN_GROUP("gpio17", gpio17), 534 PINCTRL_PIN_GROUP("gpio18", gpio18), 535 PINCTRL_PIN_GROUP("gpio19", gpio19), 536 PINCTRL_PIN_GROUP("gpio20", gpio20), 537 PINCTRL_PIN_GROUP("gpio21", gpio21), 538 PINCTRL_PIN_GROUP("gpio22", gpio22), 539 PINCTRL_PIN_GROUP("gpio23", gpio23), 540 PINCTRL_PIN_GROUP("gpio24", gpio24), 541 PINCTRL_PIN_GROUP("gpio25", gpio25), 542 PINCTRL_PIN_GROUP("gpio26", gpio26), 543 PINCTRL_PIN_GROUP("gpio27", gpio27), 544 PINCTRL_PIN_GROUP("gpio28", gpio28), 545 PINCTRL_PIN_GROUP("gpio29", gpio29), 546 PINCTRL_PIN_GROUP("gpio30", gpio30), 547 PINCTRL_PIN_GROUP("gpio31", gpio31), 548 PINCTRL_PIN_GROUP("gpio32", gpio32), 549 PINCTRL_PIN_GROUP("gpio33", gpio33), 550 PINCTRL_PIN_GROUP("gpio34", gpio34), 551 PINCTRL_PIN_GROUP("gpio35", gpio35), 552 PINCTRL_PIN_GROUP("gpio36", gpio36), 553 PINCTRL_PIN_GROUP("gpio37", gpio37), 554 PINCTRL_PIN_GROUP("gpio38", gpio38), 555 PINCTRL_PIN_GROUP("gpio39", gpio39), 556 PINCTRL_PIN_GROUP("gpio40", gpio40), 557 PINCTRL_PIN_GROUP("gpio41", gpio41), 558 PINCTRL_PIN_GROUP("gpio42", gpio42), 559 PINCTRL_PIN_GROUP("gpio43", gpio43), 560 PINCTRL_PIN_GROUP("gpio44", gpio44), 561 PINCTRL_PIN_GROUP("gpio45", gpio45), 562 PINCTRL_PIN_GROUP("gpio46", gpio46), 563 PINCTRL_PIN_GROUP("gpio47", gpio47), 564 PINCTRL_PIN_GROUP("gpio48", gpio48), 565 PINCTRL_PIN_GROUP("gpio49", gpio49), 566 PINCTRL_PIN_GROUP("gpio50", gpio50), 567 PINCTRL_PIN_GROUP("gpio51", gpio51), 568 PINCTRL_PIN_GROUP("gpio52", gpio52), 569 PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), 570 PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), 571 }; 572 573 static const char *const pon_groups[] = { "pon", "pon_alt" }; 574 static const char *const olt_groups[] = { "olt" }; 575 static const char *const tod_1pps_groups[] = { 576 "pon_tod_1pps", "gsw_tod_1pps" 577 }; 578 static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; 579 static const char *const mdio_groups[] = { "mdio" }; 580 static const char *const uart_groups[] = { 581 "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", 582 "uart4", "uart5", "npu_uart" 583 }; 584 static const char *const i2c_groups[] = { "i2c0", "i2c1" }; 585 static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; 586 static const char *const pcm_groups[] = { "pcm1", "pcm2" }; 587 static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; 588 static const char *const pcm_spi_groups[] = { 589 "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1" 590 }; 591 static const char *const emmc_groups[] = { "emmc" }; 592 static const char *const pnand_groups[] = { "pnand" }; 593 static const char *const gpio_groups[] = { 594 "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", 595 "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", 596 "gpio49", "gpio50", "gpio51", "gpio52" 597 }; 598 static const char *const pcie_reset_groups[] = { 599 "pcie_reset0", "pcie_reset1" 600 }; 601 static const char *const pwm_groups[] = { 602 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 603 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 604 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", 605 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", 606 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 607 "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39", 608 "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", 609 "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51" 610 }; 611 static const char *const phy1_led0_groups[] = { 612 "gpio1", "gpio2", "gpio3", "gpio4" 613 }; 614 static const char *const phy2_led0_groups[] = { 615 "gpio1", "gpio2", "gpio3", "gpio4" 616 }; 617 static const char *const phy3_led0_groups[] = { 618 "gpio1", "gpio2", "gpio3", "gpio4" 619 }; 620 static const char *const phy4_led0_groups[] = { 621 "gpio1", "gpio2", "gpio3", "gpio4" 622 }; 623 static const char *const phy1_led1_groups[] = { 624 "gpio8", "gpio9", "gpio10", "gpio11" 625 }; 626 static const char *const phy2_led1_groups[] = { 627 "gpio8", "gpio9", "gpio10", "gpio11" 628 }; 629 static const char *const phy3_led1_groups[] = { 630 "gpio8", "gpio9", "gpio10", "gpio11" 631 }; 632 static const char *const phy4_led1_groups[] = { 633 "gpio8", "gpio9", "gpio10", "gpio11" 634 }; 635 636 static const struct airoha_pinctrl_func_group pon_func_group[] = { 637 { 638 .name = "pon", 639 .regmap[0] = { 640 AIROHA_FUNC_MUX, 641 REG_GPIO_PON_MODE, 642 GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK, 643 GPIO_PON_MODE_MASK 644 }, 645 .regmap_size = 1, 646 }, { 647 .name = "pon_alt", 648 .regmap[0] = { 649 AIROHA_FUNC_MUX, 650 REG_GPIO_PON_MODE, 651 GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK, 652 GPIO_PON_ALT_MODE_MASK 653 }, 654 .regmap_size = 1, 655 }, 656 }; 657 658 static const struct airoha_pinctrl_func_group olt_func_group[] = { 659 { 660 .name = "olt", 661 .regmap[0] = { 662 AIROHA_FUNC_MUX, 663 REG_GPIO_PON_MODE, 664 GPIO_OLT_MODE_MASK, 665 GPIO_OLT_MODE_MASK 666 }, 667 .regmap_size = 1, 668 }, 669 }; 670 671 static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { 672 { 673 .name = "pon_tod_1pps", 674 .regmap[0] = { 675 AIROHA_FUNC_MUX, 676 REG_SW_TOD_1PPS_MODE, 677 PON_TOD_1PPS_MODE_MASK, 678 PON_TOD_1PPS_MODE_MASK 679 }, 680 .regmap_size = 1, 681 }, { 682 .name = "gsw_tod_1pps", 683 .regmap[0] = { 684 AIROHA_FUNC_MUX, 685 REG_SW_TOD_1PPS_MODE, 686 GSW_TOD_1PPS_MODE_MASK, 687 GSW_TOD_1PPS_MODE_MASK 688 }, 689 .regmap_size = 1, 690 }, 691 }; 692 693 static const struct airoha_pinctrl_func_group sipo_func_group[] = { 694 { 695 .name = "sipo", 696 .regmap[0] = { 697 AIROHA_FUNC_MUX, 698 REG_GPIO_PON_MODE, 699 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, 700 GPIO_SIPO_MODE_MASK 701 }, 702 .regmap_size = 1, 703 }, { 704 .name = "sipo_rclk", 705 .regmap[0] = { 706 AIROHA_FUNC_MUX, 707 REG_GPIO_PON_MODE, 708 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, 709 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK 710 }, 711 .regmap_size = 1, 712 }, 713 }; 714 715 static const struct airoha_pinctrl_func_group mdio_func_group[] = { 716 { 717 .name = "mdio", 718 .regmap[0] = { 719 AIROHA_FUNC_MUX, 720 REG_GPIO_PON_MODE, 721 MDC_0_GPIO_MODE_MASK | MDIO_0_GPIO_MODE_MASK, 722 0 723 }, 724 .regmap_size = 1, 725 }, 726 }; 727 728 static const struct airoha_pinctrl_func_group uart_func_group[] = { 729 { 730 .name = "uart2", 731 .regmap[0] = { 732 AIROHA_FUNC_MUX, 733 REG_GPIO_PON_MODE, 734 GPIO_UART2_MODE_MASK, 735 GPIO_UART2_MODE_MASK 736 }, 737 .regmap_size = 1, 738 }, { 739 .name = "uart2_cts_rts", 740 .regmap[0] = { 741 AIROHA_FUNC_MUX, 742 REG_GPIO_PON_MODE, 743 GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, 744 GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK 745 }, 746 .regmap_size = 1, 747 }, { 748 .name = "hsuart", 749 .regmap[0] = { 750 AIROHA_FUNC_MUX, 751 REG_GPIO_PON_MODE, 752 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, 753 GPIO_HSUART_MODE_MASK 754 }, 755 .regmap_size = 1, 756 }, 757 { 758 .name = "hsuart_cts_rts", 759 .regmap[0] = { 760 AIROHA_FUNC_MUX, 761 REG_GPIO_PON_MODE, 762 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, 763 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK 764 }, 765 .regmap_size = 1, 766 }, { 767 .name = "uart4", 768 .regmap[0] = { 769 AIROHA_FUNC_MUX, 770 REG_GPIO_PON_MODE, 771 GPIO_UART4_MODE_MASK, 772 GPIO_UART4_MODE_MASK 773 }, 774 .regmap_size = 1, 775 }, { 776 .name = "uart5", 777 .regmap[0] = { 778 AIROHA_FUNC_MUX, 779 REG_GPIO_PON_MODE, 780 GPIO_UART5_MODE_MASK, 781 GPIO_UART5_MODE_MASK 782 }, 783 .regmap_size = 1, 784 }, { 785 .name = "npu_uart", 786 .regmap[0] = { 787 AIROHA_FUNC_MUX, 788 REG_NPU_UART_EN, 789 NPU_UART_EN_MASK, 790 NPU_UART_EN_MASK 791 }, 792 .regmap_size = 1, 793 }, 794 }; 795 796 static const struct airoha_pinctrl_func_group i2c_func_group[] = { 797 { 798 .name = "i2c0", 799 .regmap[0] = { 800 AIROHA_FUNC_MUX, 801 REG_GPIO_PON_MODE, 802 I2C0_SCL_GPIO_MODE_MASK | I2C0_SDA_GPIO_MODE_MASK, 803 0 804 }, 805 .regmap_size = 1, 806 }, { 807 .name = "i2c1", 808 .regmap[0] = { 809 AIROHA_FUNC_MUX, 810 REG_GPIO_PON_MODE, 811 I2C1_SCL_GPIO_MODE_MASK | I2C1_SDA_GPIO_MODE_MASK, 812 0 813 }, 814 .regmap_size = 1, 815 }, 816 }; 817 818 static const struct airoha_pinctrl_func_group jtag_func_group[] = { 819 { 820 .name = "jtag_udi", 821 .regmap[0] = { 822 AIROHA_FUNC_MUX, 823 REG_NPU_UART_EN, 824 JTAG_UDI_EN_MASK, 825 JTAG_UDI_EN_MASK 826 }, 827 .regmap_size = 1, 828 }, { 829 .name = "jtag_dfd", 830 .regmap[0] = { 831 AIROHA_FUNC_MUX, 832 REG_NPU_UART_EN, 833 JTAG_DFD_EN_MASK, 834 JTAG_DFD_EN_MASK 835 }, 836 .regmap_size = 1, 837 }, 838 }; 839 840 static const struct airoha_pinctrl_func_group pcm_func_group[] = { 841 { 842 .name = "pcm1", 843 .regmap[0] = { 844 AIROHA_FUNC_MUX, 845 REG_GPIO_SPI_CS1_MODE, 846 GPIO_PCM1_MODE_MASK, 847 GPIO_PCM1_MODE_MASK 848 }, 849 .regmap_size = 1, 850 }, { 851 .name = "pcm2", 852 .regmap[0] = { 853 AIROHA_FUNC_MUX, 854 REG_GPIO_SPI_CS1_MODE, 855 GPIO_PCM2_MODE_MASK, 856 GPIO_PCM2_MODE_MASK 857 }, 858 .regmap_size = 1, 859 }, 860 }; 861 862 static const struct airoha_pinctrl_func_group spi_func_group[] = { 863 { 864 .name = "spi_quad", 865 .regmap[0] = { 866 AIROHA_FUNC_MUX, 867 REG_GPIO_SPI_CS1_MODE, 868 GPIO_SPI_QUAD_MODE_MASK, 869 GPIO_SPI_QUAD_MODE_MASK 870 }, 871 .regmap_size = 1, 872 }, { 873 .name = "spi_cs1", 874 .regmap[0] = { 875 AIROHA_FUNC_MUX, 876 REG_GPIO_SPI_CS1_MODE, 877 GPIO_SPI_CS1_MODE_MASK, 878 GPIO_SPI_CS1_MODE_MASK 879 }, 880 .regmap_size = 1, 881 }, { 882 .name = "spi_cs2", 883 .regmap[0] = { 884 AIROHA_FUNC_MUX, 885 REG_GPIO_SPI_CS1_MODE, 886 GPIO_SPI_CS2_MODE_MASK, 887 GPIO_SPI_CS2_MODE_MASK 888 }, 889 .regmap_size = 1, 890 }, { 891 .name = "spi_cs3", 892 .regmap[0] = { 893 AIROHA_FUNC_MUX, 894 REG_GPIO_SPI_CS1_MODE, 895 GPIO_SPI_CS3_MODE_MASK, 896 GPIO_SPI_CS3_MODE_MASK 897 }, 898 .regmap_size = 1, 899 }, { 900 .name = "spi_cs4", 901 .regmap[0] = { 902 AIROHA_FUNC_MUX, 903 REG_GPIO_SPI_CS1_MODE, 904 GPIO_SPI_CS4_MODE_MASK, 905 GPIO_SPI_CS4_MODE_MASK 906 }, 907 .regmap_size = 1, 908 }, 909 }; 910 911 static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { 912 { 913 .name = "pcm_spi", 914 .regmap[0] = { 915 AIROHA_FUNC_MUX, 916 REG_GPIO_SPI_CS1_MODE, 917 GPIO_PCM_SPI_MODE_MASK, 918 GPIO_PCM_SPI_MODE_MASK 919 }, 920 .regmap_size = 1, 921 }, { 922 .name = "pcm_spi_int", 923 .regmap[0] = { 924 AIROHA_FUNC_MUX, 925 REG_GPIO_SPI_CS1_MODE, 926 GPIO_PCM_INT_MODE_MASK, 927 GPIO_PCM_INT_MODE_MASK 928 }, 929 .regmap_size = 1, 930 }, { 931 .name = "pcm_spi_rst", 932 .regmap[0] = { 933 AIROHA_FUNC_MUX, 934 REG_GPIO_SPI_CS1_MODE, 935 GPIO_PCM_RESET_MODE_MASK, 936 GPIO_PCM_RESET_MODE_MASK 937 }, 938 .regmap_size = 1, 939 }, { 940 .name = "pcm_spi_cs1", 941 .regmap[0] = { 942 AIROHA_FUNC_MUX, 943 REG_GPIO_SPI_CS1_MODE, 944 GPIO_PCM_SPI_CS1_MODE_MASK, 945 GPIO_PCM_SPI_CS1_MODE_MASK 946 }, 947 .regmap_size = 1, 948 }, { 949 .name = "pcm_spi_cs2", 950 .regmap[0] = { 951 AIROHA_FUNC_MUX, 952 REG_GPIO_SPI_CS1_MODE, 953 GPIO_PCM_SPI_CS2_MODE_MASK, 954 GPIO_PCM_SPI_CS2_MODE_MASK 955 }, 956 .regmap_size = 1, 957 }, { 958 .name = "pcm_spi_cs3", 959 .regmap[0] = { 960 AIROHA_FUNC_MUX, 961 REG_GPIO_SPI_CS1_MODE, 962 GPIO_PCM_SPI_CS3_MODE_MASK, 963 GPIO_PCM_SPI_CS3_MODE_MASK 964 }, 965 .regmap_size = 1, 966 }, { 967 .name = "pcm_spi_cs4", 968 .regmap[0] = { 969 AIROHA_FUNC_MUX, 970 REG_GPIO_SPI_CS1_MODE, 971 GPIO_PCM_SPI_CS4_MODE_MASK, 972 GPIO_PCM_SPI_CS4_MODE_MASK 973 }, 974 .regmap_size = 1, 975 }, 976 }; 977 978 static const struct airoha_pinctrl_func_group emmc_func_group[] = { 979 { 980 .name = "emmc", 981 .regmap[0] = { 982 AIROHA_FUNC_MUX, 983 REG_GPIO_PON_MODE, 984 GPIO_EMMC_MODE_MASK, 985 GPIO_EMMC_MODE_MASK 986 }, 987 .regmap_size = 1, 988 }, 989 }; 990 991 static const struct airoha_pinctrl_func_group pnand_func_group[] = { 992 { 993 .name = "pnand", 994 .regmap[0] = { 995 AIROHA_FUNC_MUX, 996 REG_GPIO_PON_MODE, 997 GPIO_PARALLEL_NAND_MODE_MASK, 998 GPIO_PARALLEL_NAND_MODE_MASK 999 }, 1000 .regmap_size = 1, 1001 }, 1002 }; 1003 1004 static const struct airoha_pinctrl_func_group gpio_func_group[] = { 1005 AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG, 1006 I2C0_SCL_GPIO_MODE_MASK), 1007 AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG, 1008 I2C0_SDA_GPIO_MODE_MASK), 1009 AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG, 1010 I2C1_SCL_GPIO_MODE_MASK), 1011 AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG, 1012 I2C1_SDA_GPIO_MODE_MASK), 1013 AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG, 1014 SPI_CLK_GPIO_MODE_MASK), 1015 AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG, 1016 SPI_CS_GPIO_MODE_MASK), 1017 AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG, 1018 SPI_MOSI_GPIO_MODE_MASK), 1019 AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG, 1020 SPI_MISO_GPIO_MODE_MASK), 1021 AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, 1022 UART_TXD_GPIO_MODE_MASK), 1023 AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, 1024 UART_RXD_GPIO_MODE_MASK), 1025 AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, 1026 GPIO_PCIE_RESET0_MASK), 1027 AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG, 1028 GPIO_PCIE_RESET1_MASK), 1029 AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG, 1030 MDC_0_GPIO_MODE_MASK), 1031 AIROHA_PINCTRL_GPIO("gpio52", MDIO_0_GPIO_MODE_MASK), 1032 }; 1033 1034 static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { 1035 { 1036 .name = "pcie_reset0", 1037 .regmap[0] = { 1038 AIROHA_FUNC_MUX, 1039 REG_GPIO_PON_MODE, 1040 GPIO_PCIE_RESET0_MASK, 1041 0 1042 }, 1043 .regmap_size = 1, 1044 }, { 1045 .name = "pcie_reset1", 1046 .regmap[0] = { 1047 AIROHA_FUNC_MUX, 1048 REG_GPIO_PON_MODE, 1049 GPIO_PCIE_RESET1_MASK, 1050 0 1051 }, 1052 .regmap_size = 1, 1053 }, 1054 }; 1055 1056 static const struct airoha_pinctrl_func_group pwm_func_group[] = { 1057 AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), 1058 AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), 1059 AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), 1060 AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), 1061 AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), 1062 AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), 1063 AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), 1064 AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), 1065 AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), 1066 AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), 1067 AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), 1068 AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), 1069 AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), 1070 AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), 1071 AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), 1072 AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), 1073 AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), 1074 AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), 1075 AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), 1076 AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), 1077 AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), 1078 AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), 1079 AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), 1080 AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), 1081 AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), 1082 AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), 1083 AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), 1084 AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), 1085 AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), 1086 AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), 1087 AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), 1088 AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), 1089 AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), 1090 AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), 1091 AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), 1092 AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG, 1093 I2C0_SCL_GPIO_MODE_MASK), 1094 AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG, 1095 I2C0_SDA_GPIO_MODE_MASK), 1096 AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG, 1097 I2C1_SCL_GPIO_MODE_MASK), 1098 AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG, 1099 I2C1_SDA_GPIO_MODE_MASK), 1100 AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG, 1101 SPI_CLK_GPIO_MODE_MASK), 1102 AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG, 1103 SPI_CS_GPIO_MODE_MASK), 1104 AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG, 1105 SPI_MOSI_GPIO_MODE_MASK), 1106 AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG, 1107 SPI_MISO_GPIO_MODE_MASK), 1108 AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, 1109 UART_TXD_GPIO_MODE_MASK), 1110 AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, 1111 UART_RXD_GPIO_MODE_MASK), 1112 AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, 1113 GPIO_PCIE_RESET0_MASK), 1114 AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG, 1115 GPIO_PCIE_RESET1_MASK), 1116 AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG, 1117 MDC_0_GPIO_MODE_MASK), 1118 }; 1119 1120 static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { 1121 AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, 1122 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 1123 AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, 1124 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 1125 AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, 1126 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 1127 AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, 1128 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 1129 }; 1130 1131 static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { 1132 AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, 1133 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 1134 AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, 1135 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 1136 AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, 1137 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 1138 AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, 1139 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 1140 }; 1141 1142 static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { 1143 AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, 1144 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 1145 AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, 1146 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 1147 AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, 1148 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 1149 AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, 1150 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 1151 }; 1152 1153 static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { 1154 AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, 1155 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), 1156 AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, 1157 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), 1158 AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, 1159 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), 1160 AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, 1161 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), 1162 }; 1163 1164 static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { 1165 AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, 1166 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 1167 AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, 1168 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 1169 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, 1170 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 1171 AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, 1172 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 1173 }; 1174 1175 static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { 1176 AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, 1177 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 1178 AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, 1179 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 1180 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, 1181 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 1182 AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, 1183 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 1184 }; 1185 1186 static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { 1187 AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, 1188 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 1189 AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, 1190 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 1191 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, 1192 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 1193 AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, 1194 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 1195 }; 1196 1197 static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { 1198 AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, 1199 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), 1200 AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, 1201 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), 1202 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, 1203 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), 1204 AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, 1205 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), 1206 }; 1207 1208 static const struct airoha_pinctrl_func pinctrl_funcs[] = { 1209 PINCTRL_FUNC_DESC("pon", pon), 1210 PINCTRL_FUNC_DESC("olt", olt), 1211 PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), 1212 PINCTRL_FUNC_DESC("sipo", sipo), 1213 PINCTRL_FUNC_DESC("mdio", mdio), 1214 PINCTRL_FUNC_DESC("uart", uart), 1215 PINCTRL_FUNC_DESC("i2c", i2c), 1216 PINCTRL_FUNC_DESC("jtag", jtag), 1217 PINCTRL_FUNC_DESC("pcm", pcm), 1218 PINCTRL_FUNC_DESC("spi", spi), 1219 PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), 1220 PINCTRL_FUNC_DESC("emmc", emmc), 1221 PINCTRL_FUNC_DESC("pnand", pnand), 1222 PINCTRL_FUNC_DESC("gpio", gpio), 1223 PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), 1224 PINCTRL_FUNC_DESC("pwm", pwm), 1225 PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), 1226 PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), 1227 PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), 1228 PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), 1229 PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), 1230 PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), 1231 PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), 1232 PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), 1233 }; 1234 1235 static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { 1236 PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), 1237 PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), 1238 PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), 1239 PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), 1240 PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), 1241 PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), 1242 PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), 1243 PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), 1244 PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), 1245 PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), 1246 PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), 1247 PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), 1248 PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), 1249 PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), 1250 PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), 1251 PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), 1252 PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), 1253 PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), 1254 PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), 1255 PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)), 1256 PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), 1257 PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), 1258 PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), 1259 PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), 1260 PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), 1261 PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), 1262 PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), 1263 PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), 1264 PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), 1265 PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), 1266 PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), 1267 PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), 1268 PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), 1269 PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), 1270 PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), 1271 PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), 1272 PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), 1273 PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), 1274 PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), 1275 PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), 1276 PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), 1277 PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, I2C1_SCL_PU_MASK), 1278 PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, I2C1_SDA_PU_MASK), 1279 PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), 1280 PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), 1281 PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), 1282 PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), 1283 PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), 1284 PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), 1285 PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), 1286 PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), 1287 PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, MDC_0_PU_MASK), 1288 PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, MDIO_0_PU_MASK), 1289 }; 1290 1291 static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { 1292 PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), 1293 PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), 1294 PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), 1295 PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), 1296 PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), 1297 PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), 1298 PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), 1299 PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), 1300 PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), 1301 PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), 1302 PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), 1303 PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), 1304 PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), 1305 PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), 1306 PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), 1307 PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), 1308 PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), 1309 PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), 1310 PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), 1311 PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)), 1312 PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), 1313 PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), 1314 PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), 1315 PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), 1316 PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), 1317 PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), 1318 PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), 1319 PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), 1320 PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), 1321 PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), 1322 PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), 1323 PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), 1324 PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), 1325 PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), 1326 PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), 1327 PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), 1328 PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), 1329 PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), 1330 PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), 1331 PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), 1332 PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), 1333 PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, I2C1_SCL_PD_MASK), 1334 PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, I2C1_SDA_PD_MASK), 1335 PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), 1336 PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), 1337 PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), 1338 PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), 1339 PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), 1340 PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), 1341 PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), 1342 PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), 1343 PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, MDC_0_PD_MASK), 1344 PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, MDIO_0_PD_MASK), 1345 }; 1346 1347 static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { 1348 PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), 1349 PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), 1350 PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), 1351 PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), 1352 PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), 1353 PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), 1354 PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), 1355 PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), 1356 PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), 1357 PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), 1358 PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), 1359 PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), 1360 PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), 1361 PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), 1362 PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), 1363 PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), 1364 PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), 1365 PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), 1366 PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), 1367 PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)), 1368 PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), 1369 PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), 1370 PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), 1371 PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), 1372 PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), 1373 PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), 1374 PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), 1375 PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), 1376 PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), 1377 PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), 1378 PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), 1379 PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), 1380 PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), 1381 PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), 1382 PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), 1383 PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), 1384 PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), 1385 PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), 1386 PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), 1387 PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), 1388 PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), 1389 PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, I2C1_SCL_E2_MASK), 1390 PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, I2C1_SDA_E2_MASK), 1391 PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), 1392 PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), 1393 PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), 1394 PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), 1395 PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), 1396 PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), 1397 PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), 1398 PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), 1399 PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, MDC_0_E2_MASK), 1400 PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, MDIO_0_E2_MASK), 1401 }; 1402 1403 static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { 1404 PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), 1405 PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), 1406 PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), 1407 PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), 1408 PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), 1409 PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), 1410 PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), 1411 PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), 1412 PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), 1413 PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), 1414 PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), 1415 PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), 1416 PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), 1417 PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), 1418 PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), 1419 PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), 1420 PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), 1421 PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), 1422 PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), 1423 PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)), 1424 PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), 1425 PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), 1426 PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), 1427 PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), 1428 PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), 1429 PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), 1430 PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), 1431 PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), 1432 PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), 1433 PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), 1434 PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), 1435 PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), 1436 PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), 1437 PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), 1438 PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), 1439 PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), 1440 PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), 1441 PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), 1442 PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), 1443 PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), 1444 PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), 1445 PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, I2C1_SCL_E4_MASK), 1446 PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, I2C1_SDA_E4_MASK), 1447 PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), 1448 PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), 1449 PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), 1450 PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), 1451 PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), 1452 PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), 1453 PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), 1454 PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), 1455 PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, MDC_0_E4_MASK), 1456 PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, MDIO_0_E4_MASK), 1457 }; 1458 1459 static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { 1460 PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), 1461 PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), 1462 }; 1463 1464 static const struct airoha_pinctrl_match_data pinctrl_match_data = { 1465 .chip_scu_compatible = "airoha,en7581-chip-scu", 1466 .pinctrl_name = KBUILD_MODNAME, 1467 .pinctrl_owner = THIS_MODULE, 1468 .pins = pinctrl_pins, 1469 .num_pins = ARRAY_SIZE(pinctrl_pins), 1470 .grps = pinctrl_groups, 1471 .num_grps = ARRAY_SIZE(pinctrl_groups), 1472 .funcs = pinctrl_funcs, 1473 .num_funcs = ARRAY_SIZE(pinctrl_funcs), 1474 .confs_info = { 1475 [AIROHA_PINCTRL_CONFS_PULLUP] = { 1476 .confs = pinctrl_pullup_conf, 1477 .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), 1478 }, 1479 [AIROHA_PINCTRL_CONFS_PULLDOWN] = { 1480 .confs = pinctrl_pulldown_conf, 1481 .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), 1482 }, 1483 [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { 1484 .confs = pinctrl_drive_e2_conf, 1485 .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), 1486 }, 1487 [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { 1488 .confs = pinctrl_drive_e4_conf, 1489 .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), 1490 }, 1491 [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { 1492 .confs = pinctrl_pcie_rst_od_conf, 1493 .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), 1494 }, 1495 }, 1496 }; 1497 1498 static const struct of_device_id airoha_pinctrl_of_match[] = { 1499 { .compatible = "airoha,an7583-pinctrl", .data = &pinctrl_match_data }, 1500 { /* sentinel */ } 1501 }; 1502 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); 1503 1504 static struct platform_driver airoha_pinctrl_driver = { 1505 .probe = airoha_pinctrl_probe, 1506 .driver = { 1507 .name = "pinctrl-airoha-an7583", 1508 .of_match_table = airoha_pinctrl_of_match, 1509 }, 1510 }; 1511 module_platform_driver(airoha_pinctrl_driver); 1512 1513 MODULE_LICENSE("GPL"); 1514 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 1515 MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); 1516 MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); 1517 MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC"); 1518