xref: /linux/include/linux/mlx5/mlx5_ifc.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68 	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72 	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74 	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75 };
76 
77 enum {
78 	MLX5_SHARED_RESOURCE_UID = 0xffff,
79 };
80 
81 enum {
82 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
84 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
85 	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
86 	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
87 	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
88 	MLX5_OBJ_TYPE_STC = 0x0040,
89 	MLX5_OBJ_TYPE_RTC = 0x0041,
90 	MLX5_OBJ_TYPE_STE = 0x0042,
91 	MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
92 	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
93 	MLX5_OBJ_TYPE_MKEY = 0xff01,
94 	MLX5_OBJ_TYPE_QP = 0xff02,
95 	MLX5_OBJ_TYPE_PSV = 0xff03,
96 	MLX5_OBJ_TYPE_RMP = 0xff04,
97 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
98 	MLX5_OBJ_TYPE_RQ = 0xff06,
99 	MLX5_OBJ_TYPE_SQ = 0xff07,
100 	MLX5_OBJ_TYPE_TIR = 0xff08,
101 	MLX5_OBJ_TYPE_TIS = 0xff09,
102 	MLX5_OBJ_TYPE_DCT = 0xff0a,
103 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
104 	MLX5_OBJ_TYPE_RQT = 0xff0e,
105 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
106 	MLX5_OBJ_TYPE_CQ = 0xff10,
107 	MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
108 };
109 
110 enum {
111 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
112 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
113 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
114 	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
115 		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
116 	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
117 };
118 
119 enum {
120 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
121 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
122 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
123 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
124 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
125 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
126 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
127 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
128 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
129 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
130 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
131 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
132 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
133 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
134 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
135 	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
136 	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
137 	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
138 	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
139 	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
140 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
141 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
142 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
143 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
144 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
145 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
146 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
147 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
148 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
149 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
150 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
151 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
152 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
153 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
154 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
155 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
156 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
157 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
158 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
159 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
160 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
161 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
162 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
163 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
164 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
165 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
166 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
167 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
168 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
169 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
170 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
171 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
172 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
173 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
174 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
175 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
176 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
177 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
178 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
179 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
180 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
181 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
182 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
183 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
184 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
185 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
186 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
187 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
188 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
189 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
190 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
191 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
192 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
193 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
194 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
195 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
196 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
197 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
198 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
199 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
200 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
201 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
202 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
203 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
204 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
205 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
206 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
207 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
208 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
209 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
210 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
211 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
212 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
213 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
214 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
215 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
216 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
217 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
218 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
219 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
220 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
221 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
222 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
223 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
224 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
225 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
226 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
227 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
228 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
229 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
230 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
231 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
232 	MLX5_CMD_OP_NOP                           = 0x80d,
233 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
234 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
235 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
236 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
237 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
238 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
239 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
240 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
241 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
242 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
243 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
244 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
245 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
246 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
247 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
248 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
249 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
250 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
251 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
252 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
253 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
254 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
255 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
256 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
257 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
258 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
259 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
260 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
261 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
262 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
263 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
264 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
265 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
266 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
267 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
268 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
269 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
270 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
271 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
272 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
273 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
274 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
275 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
276 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
277 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
278 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
279 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
280 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
281 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
282 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
283 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
284 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
285 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
286 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
287 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
288 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
289 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
290 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
291 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
292 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
293 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
294 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
295 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
296 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
297 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
298 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
299 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
300 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
301 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
302 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
303 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
304 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
305 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
306 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
307 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
308 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
309 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
310 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
311 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
312 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
313 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
314 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
315 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
316 	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
317 	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
318 	MLX5_CMD_OP_GENERATE_WQE                  = 0xb17,
319 	MLX5_CMD_OPCODE_QUERY_VUID                = 0xb22,
320 	MLX5_CMD_OP_MAX
321 };
322 
323 /* Valid range for general commands that don't work over an object */
324 enum {
325 	MLX5_CMD_OP_GENERAL_START = 0xb00,
326 	MLX5_CMD_OP_GENERAL_END = 0xd00,
327 };
328 
329 enum {
330 	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
331 	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
332 };
333 
334 enum {
335 	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
336 };
337 
338 struct mlx5_ifc_flow_table_fields_supported_bits {
339 	u8         outer_dmac[0x1];
340 	u8         outer_smac[0x1];
341 	u8         outer_ether_type[0x1];
342 	u8         outer_ip_version[0x1];
343 	u8         outer_first_prio[0x1];
344 	u8         outer_first_cfi[0x1];
345 	u8         outer_first_vid[0x1];
346 	u8         outer_ipv4_ttl[0x1];
347 	u8         outer_second_prio[0x1];
348 	u8         outer_second_cfi[0x1];
349 	u8         outer_second_vid[0x1];
350 	u8         reserved_at_b[0x1];
351 	u8         outer_sip[0x1];
352 	u8         outer_dip[0x1];
353 	u8         outer_frag[0x1];
354 	u8         outer_ip_protocol[0x1];
355 	u8         outer_ip_ecn[0x1];
356 	u8         outer_ip_dscp[0x1];
357 	u8         outer_udp_sport[0x1];
358 	u8         outer_udp_dport[0x1];
359 	u8         outer_tcp_sport[0x1];
360 	u8         outer_tcp_dport[0x1];
361 	u8         outer_tcp_flags[0x1];
362 	u8         outer_gre_protocol[0x1];
363 	u8         outer_gre_key[0x1];
364 	u8         outer_vxlan_vni[0x1];
365 	u8         outer_geneve_vni[0x1];
366 	u8         outer_geneve_oam[0x1];
367 	u8         outer_geneve_protocol_type[0x1];
368 	u8         outer_geneve_opt_len[0x1];
369 	u8         source_vhca_port[0x1];
370 	u8         source_eswitch_port[0x1];
371 
372 	u8         inner_dmac[0x1];
373 	u8         inner_smac[0x1];
374 	u8         inner_ether_type[0x1];
375 	u8         inner_ip_version[0x1];
376 	u8         inner_first_prio[0x1];
377 	u8         inner_first_cfi[0x1];
378 	u8         inner_first_vid[0x1];
379 	u8         reserved_at_27[0x1];
380 	u8         inner_second_prio[0x1];
381 	u8         inner_second_cfi[0x1];
382 	u8         inner_second_vid[0x1];
383 	u8         reserved_at_2b[0x1];
384 	u8         inner_sip[0x1];
385 	u8         inner_dip[0x1];
386 	u8         inner_frag[0x1];
387 	u8         inner_ip_protocol[0x1];
388 	u8         inner_ip_ecn[0x1];
389 	u8         inner_ip_dscp[0x1];
390 	u8         inner_udp_sport[0x1];
391 	u8         inner_udp_dport[0x1];
392 	u8         inner_tcp_sport[0x1];
393 	u8         inner_tcp_dport[0x1];
394 	u8         inner_tcp_flags[0x1];
395 	u8         reserved_at_37[0x9];
396 
397 	u8         geneve_tlv_option_0_data[0x1];
398 	u8         geneve_tlv_option_0_exist[0x1];
399 	u8         reserved_at_42[0x3];
400 	u8         outer_first_mpls_over_udp[0x4];
401 	u8         outer_first_mpls_over_gre[0x4];
402 	u8         inner_first_mpls[0x4];
403 	u8         outer_first_mpls[0x4];
404 	u8         reserved_at_55[0x2];
405 	u8	   outer_esp_spi[0x1];
406 	u8         reserved_at_58[0x2];
407 	u8         bth_dst_qp[0x1];
408 	u8         reserved_at_5b[0x5];
409 
410 	u8         reserved_at_60[0x18];
411 	u8         metadata_reg_c_7[0x1];
412 	u8         metadata_reg_c_6[0x1];
413 	u8         metadata_reg_c_5[0x1];
414 	u8         metadata_reg_c_4[0x1];
415 	u8         metadata_reg_c_3[0x1];
416 	u8         metadata_reg_c_2[0x1];
417 	u8         metadata_reg_c_1[0x1];
418 	u8         metadata_reg_c_0[0x1];
419 };
420 
421 /* Table 2170 - Flow Table Fields Supported 2 Format */
422 struct mlx5_ifc_flow_table_fields_supported_2_bits {
423 	u8         reserved_at_0[0x2];
424 	u8         inner_l4_type[0x1];
425 	u8         outer_l4_type[0x1];
426 	u8         reserved_at_4[0xa];
427 	u8         bth_opcode[0x1];
428 	u8         reserved_at_f[0x1];
429 	u8         tunnel_header_0_1[0x1];
430 	u8         reserved_at_11[0xf];
431 
432 	u8         reserved_at_20[0x60];
433 };
434 
435 struct mlx5_ifc_flow_table_prop_layout_bits {
436 	u8         ft_support[0x1];
437 	u8         reserved_at_1[0x1];
438 	u8         flow_counter[0x1];
439 	u8	   flow_modify_en[0x1];
440 	u8         modify_root[0x1];
441 	u8         identified_miss_table_mode[0x1];
442 	u8         flow_table_modify[0x1];
443 	u8         reformat[0x1];
444 	u8         decap[0x1];
445 	u8         reset_root_to_default[0x1];
446 	u8         pop_vlan[0x1];
447 	u8         push_vlan[0x1];
448 	u8         reserved_at_c[0x1];
449 	u8         pop_vlan_2[0x1];
450 	u8         push_vlan_2[0x1];
451 	u8	   reformat_and_vlan_action[0x1];
452 	u8	   reserved_at_10[0x1];
453 	u8         sw_owner[0x1];
454 	u8	   reformat_l3_tunnel_to_l2[0x1];
455 	u8	   reformat_l2_to_l3_tunnel[0x1];
456 	u8	   reformat_and_modify_action[0x1];
457 	u8	   ignore_flow_level[0x1];
458 	u8         reserved_at_16[0x1];
459 	u8	   table_miss_action_domain[0x1];
460 	u8         termination_table[0x1];
461 	u8         reformat_and_fwd_to_table[0x1];
462 	u8         reserved_at_1a[0x2];
463 	u8         ipsec_encrypt[0x1];
464 	u8         ipsec_decrypt[0x1];
465 	u8         sw_owner_v2[0x1];
466 	u8         reserved_at_1f[0x1];
467 
468 	u8         termination_table_raw_traffic[0x1];
469 	u8         reserved_at_21[0x1];
470 	u8         log_max_ft_size[0x6];
471 	u8         log_max_modify_header_context[0x8];
472 	u8         max_modify_header_actions[0x8];
473 	u8         max_ft_level[0x8];
474 
475 	u8         reformat_add_esp_trasport[0x1];
476 	u8         reformat_l2_to_l3_esp_tunnel[0x1];
477 	u8         reformat_add_esp_transport_over_udp[0x1];
478 	u8         reformat_del_esp_trasport[0x1];
479 	u8         reformat_l3_esp_tunnel_to_l2[0x1];
480 	u8         reformat_del_esp_transport_over_udp[0x1];
481 	u8         execute_aso[0x1];
482 	u8         reserved_at_47[0x19];
483 
484 	u8         reserved_at_60[0x2];
485 	u8         reformat_insert[0x1];
486 	u8         reformat_remove[0x1];
487 	u8         macsec_encrypt[0x1];
488 	u8         macsec_decrypt[0x1];
489 	u8         reserved_at_66[0x2];
490 	u8         reformat_add_macsec[0x1];
491 	u8         reformat_remove_macsec[0x1];
492 	u8         reparse[0x1];
493 	u8         reserved_at_6b[0x1];
494 	u8         cross_vhca_object[0x1];
495 	u8         reformat_l2_to_l3_audp_tunnel[0x1];
496 	u8         reformat_l3_audp_tunnel_to_l2[0x1];
497 	u8         ignore_flow_level_rtc_valid[0x1];
498 	u8         reserved_at_70[0x8];
499 	u8         log_max_ft_num[0x8];
500 
501 	u8         reserved_at_80[0x10];
502 	u8         log_max_flow_counter[0x8];
503 	u8         log_max_destination[0x8];
504 
505 	u8         reserved_at_a0[0x18];
506 	u8         log_max_flow[0x8];
507 
508 	u8         reserved_at_c0[0x40];
509 
510 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
511 
512 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
513 };
514 
515 struct mlx5_ifc_odp_per_transport_service_cap_bits {
516 	u8         send[0x1];
517 	u8         receive[0x1];
518 	u8         write[0x1];
519 	u8         read[0x1];
520 	u8         atomic[0x1];
521 	u8         srq_receive[0x1];
522 	u8         reserved_at_6[0x1a];
523 };
524 
525 struct mlx5_ifc_ipv4_layout_bits {
526 	u8         reserved_at_0[0x60];
527 
528 	u8         ipv4[0x20];
529 };
530 
531 struct mlx5_ifc_ipv6_layout_bits {
532 	u8         ipv6[16][0x8];
533 };
534 
535 struct mlx5_ifc_ipv6_simple_layout_bits {
536 	u8         ipv6_127_96[0x20];
537 	u8         ipv6_95_64[0x20];
538 	u8         ipv6_63_32[0x20];
539 	u8         ipv6_31_0[0x20];
540 };
541 
542 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
543 	struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
544 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
545 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
546 	u8         reserved_at_0[0x80];
547 };
548 
549 enum {
550 	MLX5_PACKET_L4_TYPE_NONE,
551 	MLX5_PACKET_L4_TYPE_TCP,
552 	MLX5_PACKET_L4_TYPE_UDP,
553 };
554 
555 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
556 	u8         smac_47_16[0x20];
557 
558 	u8         smac_15_0[0x10];
559 	u8         ethertype[0x10];
560 
561 	u8         dmac_47_16[0x20];
562 
563 	u8         dmac_15_0[0x10];
564 	u8         first_prio[0x3];
565 	u8         first_cfi[0x1];
566 	u8         first_vid[0xc];
567 
568 	u8         ip_protocol[0x8];
569 	u8         ip_dscp[0x6];
570 	u8         ip_ecn[0x2];
571 	u8         cvlan_tag[0x1];
572 	u8         svlan_tag[0x1];
573 	u8         frag[0x1];
574 	u8         ip_version[0x4];
575 	u8         tcp_flags[0x9];
576 
577 	u8         tcp_sport[0x10];
578 	u8         tcp_dport[0x10];
579 
580 	u8         l4_type[0x2];
581 	u8         reserved_at_c2[0xe];
582 	u8         ipv4_ihl[0x4];
583 	u8         reserved_at_c4[0x4];
584 
585 	u8         ttl_hoplimit[0x8];
586 
587 	u8         udp_sport[0x10];
588 	u8         udp_dport[0x10];
589 
590 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
591 
592 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
593 };
594 
595 struct mlx5_ifc_nvgre_key_bits {
596 	u8 hi[0x18];
597 	u8 lo[0x8];
598 };
599 
600 union mlx5_ifc_gre_key_bits {
601 	struct mlx5_ifc_nvgre_key_bits nvgre;
602 	u8 key[0x20];
603 };
604 
605 struct mlx5_ifc_fte_match_set_misc_bits {
606 	u8         gre_c_present[0x1];
607 	u8         reserved_at_1[0x1];
608 	u8         gre_k_present[0x1];
609 	u8         gre_s_present[0x1];
610 	u8         source_vhca_port[0x4];
611 	u8         source_sqn[0x18];
612 
613 	u8         source_eswitch_owner_vhca_id[0x10];
614 	u8         source_port[0x10];
615 
616 	u8         outer_second_prio[0x3];
617 	u8         outer_second_cfi[0x1];
618 	u8         outer_second_vid[0xc];
619 	u8         inner_second_prio[0x3];
620 	u8         inner_second_cfi[0x1];
621 	u8         inner_second_vid[0xc];
622 
623 	u8         outer_second_cvlan_tag[0x1];
624 	u8         inner_second_cvlan_tag[0x1];
625 	u8         outer_second_svlan_tag[0x1];
626 	u8         inner_second_svlan_tag[0x1];
627 	u8         reserved_at_64[0xc];
628 	u8         gre_protocol[0x10];
629 
630 	union mlx5_ifc_gre_key_bits gre_key;
631 
632 	u8         vxlan_vni[0x18];
633 	u8         bth_opcode[0x8];
634 
635 	u8         geneve_vni[0x18];
636 	u8         reserved_at_d8[0x6];
637 	u8         geneve_tlv_option_0_exist[0x1];
638 	u8         geneve_oam[0x1];
639 
640 	u8         reserved_at_e0[0xc];
641 	u8         outer_ipv6_flow_label[0x14];
642 
643 	u8         reserved_at_100[0xc];
644 	u8         inner_ipv6_flow_label[0x14];
645 
646 	u8         reserved_at_120[0xa];
647 	u8         geneve_opt_len[0x6];
648 	u8         geneve_protocol_type[0x10];
649 
650 	u8         reserved_at_140[0x8];
651 	u8         bth_dst_qp[0x18];
652 	u8	   inner_esp_spi[0x20];
653 	u8	   outer_esp_spi[0x20];
654 	u8         reserved_at_1a0[0x60];
655 };
656 
657 struct mlx5_ifc_fte_match_mpls_bits {
658 	u8         mpls_label[0x14];
659 	u8         mpls_exp[0x3];
660 	u8         mpls_s_bos[0x1];
661 	u8         mpls_ttl[0x8];
662 };
663 
664 struct mlx5_ifc_fte_match_set_misc2_bits {
665 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
666 
667 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
668 
669 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
670 
671 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
672 
673 	u8         metadata_reg_c_7[0x20];
674 
675 	u8         metadata_reg_c_6[0x20];
676 
677 	u8         metadata_reg_c_5[0x20];
678 
679 	u8         metadata_reg_c_4[0x20];
680 
681 	u8         metadata_reg_c_3[0x20];
682 
683 	u8         metadata_reg_c_2[0x20];
684 
685 	u8         metadata_reg_c_1[0x20];
686 
687 	u8         metadata_reg_c_0[0x20];
688 
689 	u8         metadata_reg_a[0x20];
690 
691 	u8         reserved_at_1a0[0x8];
692 
693 	u8         macsec_syndrome[0x8];
694 	u8         ipsec_syndrome[0x8];
695 	u8         reserved_at_1b8[0x8];
696 
697 	u8         reserved_at_1c0[0x40];
698 };
699 
700 struct mlx5_ifc_fte_match_set_misc3_bits {
701 	u8         inner_tcp_seq_num[0x20];
702 
703 	u8         outer_tcp_seq_num[0x20];
704 
705 	u8         inner_tcp_ack_num[0x20];
706 
707 	u8         outer_tcp_ack_num[0x20];
708 
709 	u8	   reserved_at_80[0x8];
710 	u8         outer_vxlan_gpe_vni[0x18];
711 
712 	u8         outer_vxlan_gpe_next_protocol[0x8];
713 	u8         outer_vxlan_gpe_flags[0x8];
714 	u8	   reserved_at_b0[0x10];
715 
716 	u8	   icmp_header_data[0x20];
717 
718 	u8	   icmpv6_header_data[0x20];
719 
720 	u8	   icmp_type[0x8];
721 	u8	   icmp_code[0x8];
722 	u8	   icmpv6_type[0x8];
723 	u8	   icmpv6_code[0x8];
724 
725 	u8         geneve_tlv_option_0_data[0x20];
726 
727 	u8	   gtpu_teid[0x20];
728 
729 	u8	   gtpu_msg_type[0x8];
730 	u8	   gtpu_msg_flags[0x8];
731 	u8	   reserved_at_170[0x10];
732 
733 	u8	   gtpu_dw_2[0x20];
734 
735 	u8	   gtpu_first_ext_dw_0[0x20];
736 
737 	u8	   gtpu_dw_0[0x20];
738 
739 	u8	   reserved_at_1e0[0x20];
740 };
741 
742 struct mlx5_ifc_fte_match_set_misc4_bits {
743 	u8         prog_sample_field_value_0[0x20];
744 
745 	u8         prog_sample_field_id_0[0x20];
746 
747 	u8         prog_sample_field_value_1[0x20];
748 
749 	u8         prog_sample_field_id_1[0x20];
750 
751 	u8         prog_sample_field_value_2[0x20];
752 
753 	u8         prog_sample_field_id_2[0x20];
754 
755 	u8         prog_sample_field_value_3[0x20];
756 
757 	u8         prog_sample_field_id_3[0x20];
758 
759 	u8         reserved_at_100[0x100];
760 };
761 
762 struct mlx5_ifc_fte_match_set_misc5_bits {
763 	u8         macsec_tag_0[0x20];
764 
765 	u8         macsec_tag_1[0x20];
766 
767 	u8         macsec_tag_2[0x20];
768 
769 	u8         macsec_tag_3[0x20];
770 
771 	u8         tunnel_header_0[0x20];
772 
773 	u8         tunnel_header_1[0x20];
774 
775 	u8         tunnel_header_2[0x20];
776 
777 	u8         tunnel_header_3[0x20];
778 
779 	u8         reserved_at_100[0x100];
780 };
781 
782 struct mlx5_ifc_cmd_pas_bits {
783 	u8         pa_h[0x20];
784 
785 	u8         pa_l[0x14];
786 	u8         reserved_at_34[0xc];
787 };
788 
789 struct mlx5_ifc_uint64_bits {
790 	u8         hi[0x20];
791 
792 	u8         lo[0x20];
793 };
794 
795 enum {
796 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
797 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
798 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
799 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
800 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
801 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
802 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
803 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
804 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
805 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
806 };
807 
808 struct mlx5_ifc_ads_bits {
809 	u8         fl[0x1];
810 	u8         free_ar[0x1];
811 	u8         reserved_at_2[0xe];
812 	u8         pkey_index[0x10];
813 
814 	u8         plane_index[0x8];
815 	u8         grh[0x1];
816 	u8         mlid[0x7];
817 	u8         rlid[0x10];
818 
819 	u8         ack_timeout[0x5];
820 	u8         reserved_at_45[0x3];
821 	u8         src_addr_index[0x8];
822 	u8         reserved_at_50[0x4];
823 	u8         stat_rate[0x4];
824 	u8         hop_limit[0x8];
825 
826 	u8         reserved_at_60[0x4];
827 	u8         tclass[0x8];
828 	u8         flow_label[0x14];
829 
830 	u8         rgid_rip[16][0x8];
831 
832 	u8         reserved_at_100[0x4];
833 	u8         f_dscp[0x1];
834 	u8         f_ecn[0x1];
835 	u8         reserved_at_106[0x1];
836 	u8         f_eth_prio[0x1];
837 	u8         ecn[0x2];
838 	u8         dscp[0x6];
839 	u8         udp_sport[0x10];
840 
841 	u8         dei_cfi[0x1];
842 	u8         eth_prio[0x3];
843 	u8         sl[0x4];
844 	u8         vhca_port_num[0x8];
845 	u8         rmac_47_32[0x10];
846 
847 	u8         rmac_31_0[0x20];
848 };
849 
850 struct mlx5_ifc_flow_table_nic_cap_bits {
851 	u8         nic_rx_multi_path_tirs[0x1];
852 	u8         nic_rx_multi_path_tirs_fts[0x1];
853 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
854 	u8	   reserved_at_3[0x4];
855 	u8	   sw_owner_reformat_supported[0x1];
856 	u8	   reserved_at_8[0x18];
857 
858 	u8	   encap_general_header[0x1];
859 	u8	   reserved_at_21[0xa];
860 	u8	   log_max_packet_reformat_context[0x5];
861 	u8	   reserved_at_30[0x6];
862 	u8	   max_encap_header_size[0xa];
863 	u8	   reserved_at_40[0x1c0];
864 
865 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
866 
867 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
868 
869 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
870 
871 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
872 
873 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
874 
875 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
876 
877 	u8         reserved_at_e00[0x600];
878 
879 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
880 
881 	u8         reserved_at_1480[0x80];
882 
883 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
884 
885 	u8         reserved_at_1580[0x280];
886 
887 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
888 
889 	u8         reserved_at_1880[0x780];
890 
891 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
892 
893 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
894 
895 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
896 
897 	u8         reserved_at_20c0[0x5f40];
898 };
899 
900 struct mlx5_ifc_port_selection_cap_bits {
901 	u8         reserved_at_0[0x10];
902 	u8         port_select_flow_table[0x1];
903 	u8         reserved_at_11[0x1];
904 	u8         port_select_flow_table_bypass[0x1];
905 	u8         reserved_at_13[0xd];
906 
907 	u8         reserved_at_20[0x1e0];
908 
909 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
910 
911 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
912 
913 	u8         reserved_at_480[0x7b80];
914 };
915 
916 enum {
917 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
918 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
919 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
920 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
921 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
922 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
923 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
924 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
925 };
926 
927 struct mlx5_ifc_flow_table_eswitch_cap_bits {
928 	u8      fdb_to_vport_reg_c_id[0x8];
929 	u8      reserved_at_8[0x5];
930 	u8      fdb_uplink_hairpin[0x1];
931 	u8      fdb_multi_path_any_table_limit_regc[0x1];
932 	u8      reserved_at_f[0x1];
933 	u8      fdb_dynamic_tunnel[0x1];
934 	u8      reserved_at_11[0x1];
935 	u8      fdb_multi_path_any_table[0x1];
936 	u8      reserved_at_13[0x2];
937 	u8      fdb_modify_header_fwd_to_table[0x1];
938 	u8      fdb_ipv4_ttl_modify[0x1];
939 	u8      flow_source[0x1];
940 	u8      reserved_at_18[0x2];
941 	u8      multi_fdb_encap[0x1];
942 	u8      egress_acl_forward_to_vport[0x1];
943 	u8      fdb_multi_path_to_table[0x1];
944 	u8      reserved_at_1d[0x3];
945 
946 	u8      reserved_at_20[0x1e0];
947 
948 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
949 
950 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
951 
952 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
953 
954 	u8      reserved_at_800[0xC00];
955 
956 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
957 
958 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
959 
960 	u8      reserved_at_1500[0x300];
961 
962 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
963 
964 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
965 
966 	u8      sw_steering_uplink_icm_address_rx[0x40];
967 
968 	u8      sw_steering_uplink_icm_address_tx[0x40];
969 
970 	u8      reserved_at_1900[0x6700];
971 };
972 
973 struct mlx5_ifc_wqe_based_flow_table_cap_bits {
974 	u8         reserved_at_0[0x3];
975 	u8         log_max_num_ste[0x5];
976 	u8         reserved_at_8[0x3];
977 	u8         log_max_num_stc[0x5];
978 	u8         reserved_at_10[0x3];
979 	u8         log_max_num_rtc[0x5];
980 	u8         reserved_at_18[0x3];
981 	u8         log_max_num_header_modify_pattern[0x5];
982 
983 	u8         rtc_hash_split_table[0x1];
984 	u8         rtc_linear_lookup_table[0x1];
985 	u8         reserved_at_22[0x1];
986 	u8         stc_alloc_log_granularity[0x5];
987 	u8         reserved_at_28[0x3];
988 	u8         stc_alloc_log_max[0x5];
989 	u8         reserved_at_30[0x3];
990 	u8         ste_alloc_log_granularity[0x5];
991 	u8         reserved_at_38[0x3];
992 	u8         ste_alloc_log_max[0x5];
993 
994 	u8         reserved_at_40[0xb];
995 	u8         rtc_reparse_mode[0x5];
996 	u8         reserved_at_50[0x3];
997 	u8         rtc_index_mode[0x5];
998 	u8         reserved_at_58[0x3];
999 	u8         rtc_log_depth_max[0x5];
1000 
1001 	u8         reserved_at_60[0x10];
1002 	u8         ste_format[0x10];
1003 
1004 	u8         stc_action_type[0x80];
1005 
1006 	u8         header_insert_type[0x10];
1007 	u8         header_remove_type[0x10];
1008 
1009 	u8         trivial_match_definer[0x20];
1010 
1011 	u8         reserved_at_140[0x1b];
1012 	u8         rtc_max_num_hash_definer_gen_wqe[0x5];
1013 
1014 	u8         reserved_at_160[0x18];
1015 	u8         access_index_mode[0x8];
1016 
1017 	u8         reserved_at_180[0x10];
1018 	u8         ste_format_gen_wqe[0x10];
1019 
1020 	u8         linear_match_definer_reg_c3[0x20];
1021 
1022 	u8         fdb_jump_to_tir_stc[0x1];
1023 	u8         reserved_at_1c1[0x1f];
1024 };
1025 
1026 struct mlx5_ifc_esw_cap_bits {
1027 	u8         reserved_at_0[0x1d];
1028 	u8         merged_eswitch[0x1];
1029 	u8         reserved_at_1e[0x2];
1030 
1031 	u8         reserved_at_20[0x40];
1032 
1033 	u8         esw_manager_vport_number_valid[0x1];
1034 	u8         reserved_at_61[0xf];
1035 	u8         esw_manager_vport_number[0x10];
1036 
1037 	u8         reserved_at_80[0x780];
1038 };
1039 
1040 enum {
1041 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
1042 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
1043 };
1044 
1045 struct mlx5_ifc_e_switch_cap_bits {
1046 	u8         vport_svlan_strip[0x1];
1047 	u8         vport_cvlan_strip[0x1];
1048 	u8         vport_svlan_insert[0x1];
1049 	u8         vport_cvlan_insert_if_not_exist[0x1];
1050 	u8         vport_cvlan_insert_overwrite[0x1];
1051 	u8         reserved_at_5[0x1];
1052 	u8         vport_cvlan_insert_always[0x1];
1053 	u8         esw_shared_ingress_acl[0x1];
1054 	u8         esw_uplink_ingress_acl[0x1];
1055 	u8         root_ft_on_other_esw[0x1];
1056 	u8         reserved_at_a[0xf];
1057 	u8         esw_functions_changed[0x1];
1058 	u8         reserved_at_1a[0x1];
1059 	u8         ecpf_vport_exists[0x1];
1060 	u8         counter_eswitch_affinity[0x1];
1061 	u8         merged_eswitch[0x1];
1062 	u8         nic_vport_node_guid_modify[0x1];
1063 	u8         nic_vport_port_guid_modify[0x1];
1064 
1065 	u8         vxlan_encap_decap[0x1];
1066 	u8         nvgre_encap_decap[0x1];
1067 	u8         reserved_at_22[0x1];
1068 	u8         log_max_fdb_encap_uplink[0x5];
1069 	u8         reserved_at_21[0x3];
1070 	u8         log_max_packet_reformat_context[0x5];
1071 	u8         reserved_2b[0x6];
1072 	u8         max_encap_header_size[0xa];
1073 
1074 	u8         reserved_at_40[0xb];
1075 	u8         log_max_esw_sf[0x5];
1076 	u8         esw_sf_base_id[0x10];
1077 
1078 	u8         reserved_at_60[0x7a0];
1079 
1080 };
1081 
1082 struct mlx5_ifc_qos_cap_bits {
1083 	u8         packet_pacing[0x1];
1084 	u8         esw_scheduling[0x1];
1085 	u8         esw_bw_share[0x1];
1086 	u8         esw_rate_limit[0x1];
1087 	u8         reserved_at_4[0x1];
1088 	u8         packet_pacing_burst_bound[0x1];
1089 	u8         packet_pacing_typical_size[0x1];
1090 	u8         reserved_at_7[0x1];
1091 	u8         nic_sq_scheduling[0x1];
1092 	u8         nic_bw_share[0x1];
1093 	u8         nic_rate_limit[0x1];
1094 	u8         packet_pacing_uid[0x1];
1095 	u8         log_esw_max_sched_depth[0x4];
1096 	u8         reserved_at_10[0x10];
1097 
1098 	u8         reserved_at_20[0x9];
1099 	u8         esw_cross_esw_sched[0x1];
1100 	u8         reserved_at_2a[0x1];
1101 	u8         log_max_qos_nic_queue_group[0x5];
1102 	u8         reserved_at_30[0x10];
1103 
1104 	u8         packet_pacing_max_rate[0x20];
1105 
1106 	u8         packet_pacing_min_rate[0x20];
1107 
1108 	u8         reserved_at_80[0xb];
1109 	u8         log_esw_max_rate_limit[0x5];
1110 	u8         packet_pacing_rate_table_size[0x10];
1111 
1112 	u8         esw_element_type[0x10];
1113 	u8         esw_tsar_type[0x10];
1114 
1115 	u8         reserved_at_c0[0x10];
1116 	u8         max_qos_para_vport[0x10];
1117 
1118 	u8         max_tsar_bw_share[0x20];
1119 
1120 	u8         nic_element_type[0x10];
1121 	u8         nic_tsar_type[0x10];
1122 
1123 	u8         reserved_at_120[0x3];
1124 	u8         log_meter_aso_granularity[0x5];
1125 	u8         reserved_at_128[0x3];
1126 	u8         log_meter_aso_max_alloc[0x5];
1127 	u8         reserved_at_130[0x3];
1128 	u8         log_max_num_meter_aso[0x5];
1129 	u8         reserved_at_138[0x8];
1130 
1131 	u8         reserved_at_140[0x6c0];
1132 };
1133 
1134 struct mlx5_ifc_debug_cap_bits {
1135 	u8         core_dump_general[0x1];
1136 	u8         core_dump_qp[0x1];
1137 	u8         reserved_at_2[0x7];
1138 	u8         resource_dump[0x1];
1139 	u8         reserved_at_a[0x16];
1140 
1141 	u8         reserved_at_20[0x2];
1142 	u8         stall_detect[0x1];
1143 	u8         reserved_at_23[0x1d];
1144 
1145 	u8         reserved_at_40[0x7c0];
1146 };
1147 
1148 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1149 	u8         csum_cap[0x1];
1150 	u8         vlan_cap[0x1];
1151 	u8         lro_cap[0x1];
1152 	u8         lro_psh_flag[0x1];
1153 	u8         lro_time_stamp[0x1];
1154 	u8         reserved_at_5[0x2];
1155 	u8         wqe_vlan_insert[0x1];
1156 	u8         self_lb_en_modifiable[0x1];
1157 	u8         reserved_at_9[0x2];
1158 	u8         max_lso_cap[0x5];
1159 	u8         multi_pkt_send_wqe[0x2];
1160 	u8	   wqe_inline_mode[0x2];
1161 	u8         rss_ind_tbl_cap[0x4];
1162 	u8         reg_umr_sq[0x1];
1163 	u8         scatter_fcs[0x1];
1164 	u8         enhanced_multi_pkt_send_wqe[0x1];
1165 	u8         tunnel_lso_const_out_ip_id[0x1];
1166 	u8         tunnel_lro_gre[0x1];
1167 	u8         tunnel_lro_vxlan[0x1];
1168 	u8         tunnel_stateless_gre[0x1];
1169 	u8         tunnel_stateless_vxlan[0x1];
1170 
1171 	u8         swp[0x1];
1172 	u8         swp_csum[0x1];
1173 	u8         swp_lso[0x1];
1174 	u8         cqe_checksum_full[0x1];
1175 	u8         tunnel_stateless_geneve_tx[0x1];
1176 	u8         tunnel_stateless_mpls_over_udp[0x1];
1177 	u8         tunnel_stateless_mpls_over_gre[0x1];
1178 	u8         tunnel_stateless_vxlan_gpe[0x1];
1179 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1180 	u8         tunnel_stateless_ip_over_ip[0x1];
1181 	u8         insert_trailer[0x1];
1182 	u8         reserved_at_2b[0x1];
1183 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1184 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1185 	u8         reserved_at_2e[0x2];
1186 	u8         max_vxlan_udp_ports[0x8];
1187 	u8         swp_csum_l4_partial[0x1];
1188 	u8         reserved_at_39[0x5];
1189 	u8         max_geneve_opt_len[0x1];
1190 	u8         tunnel_stateless_geneve_rx[0x1];
1191 
1192 	u8         reserved_at_40[0x10];
1193 	u8         lro_min_mss_size[0x10];
1194 
1195 	u8         reserved_at_60[0x120];
1196 
1197 	u8         lro_timer_supported_periods[4][0x20];
1198 
1199 	u8         reserved_at_200[0x600];
1200 };
1201 
1202 enum {
1203 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1204 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1205 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1206 };
1207 
1208 struct mlx5_ifc_roce_cap_bits {
1209 	u8         roce_apm[0x1];
1210 	u8         reserved_at_1[0x3];
1211 	u8         sw_r_roce_src_udp_port[0x1];
1212 	u8         fl_rc_qp_when_roce_disabled[0x1];
1213 	u8         fl_rc_qp_when_roce_enabled[0x1];
1214 	u8         roce_cc_general[0x1];
1215 	u8	   qp_ooo_transmit_default[0x1];
1216 	u8         reserved_at_9[0x15];
1217 	u8	   qp_ts_format[0x2];
1218 
1219 	u8         reserved_at_20[0x60];
1220 
1221 	u8         reserved_at_80[0xc];
1222 	u8         l3_type[0x4];
1223 	u8         reserved_at_90[0x8];
1224 	u8         roce_version[0x8];
1225 
1226 	u8         reserved_at_a0[0x10];
1227 	u8         r_roce_dest_udp_port[0x10];
1228 
1229 	u8         r_roce_max_src_udp_port[0x10];
1230 	u8         r_roce_min_src_udp_port[0x10];
1231 
1232 	u8         reserved_at_e0[0x10];
1233 	u8         roce_address_table_size[0x10];
1234 
1235 	u8         reserved_at_100[0x700];
1236 };
1237 
1238 struct mlx5_ifc_sync_steering_in_bits {
1239 	u8         opcode[0x10];
1240 	u8         uid[0x10];
1241 
1242 	u8         reserved_at_20[0x10];
1243 	u8         op_mod[0x10];
1244 
1245 	u8         reserved_at_40[0xc0];
1246 };
1247 
1248 struct mlx5_ifc_sync_steering_out_bits {
1249 	u8         status[0x8];
1250 	u8         reserved_at_8[0x18];
1251 
1252 	u8         syndrome[0x20];
1253 
1254 	u8         reserved_at_40[0x40];
1255 };
1256 
1257 struct mlx5_ifc_sync_crypto_in_bits {
1258 	u8         opcode[0x10];
1259 	u8         uid[0x10];
1260 
1261 	u8         reserved_at_20[0x10];
1262 	u8         op_mod[0x10];
1263 
1264 	u8         reserved_at_40[0x20];
1265 
1266 	u8         reserved_at_60[0x10];
1267 	u8         crypto_type[0x10];
1268 
1269 	u8         reserved_at_80[0x80];
1270 };
1271 
1272 struct mlx5_ifc_sync_crypto_out_bits {
1273 	u8         status[0x8];
1274 	u8         reserved_at_8[0x18];
1275 
1276 	u8         syndrome[0x20];
1277 
1278 	u8         reserved_at_40[0x40];
1279 };
1280 
1281 struct mlx5_ifc_device_mem_cap_bits {
1282 	u8         memic[0x1];
1283 	u8         reserved_at_1[0x1f];
1284 
1285 	u8         reserved_at_20[0xb];
1286 	u8         log_min_memic_alloc_size[0x5];
1287 	u8         reserved_at_30[0x8];
1288 	u8	   log_max_memic_addr_alignment[0x8];
1289 
1290 	u8         memic_bar_start_addr[0x40];
1291 
1292 	u8         memic_bar_size[0x20];
1293 
1294 	u8         max_memic_size[0x20];
1295 
1296 	u8         steering_sw_icm_start_address[0x40];
1297 
1298 	u8         reserved_at_100[0x8];
1299 	u8         log_header_modify_sw_icm_size[0x8];
1300 	u8         reserved_at_110[0x2];
1301 	u8         log_sw_icm_alloc_granularity[0x6];
1302 	u8         log_steering_sw_icm_size[0x8];
1303 
1304 	u8         log_indirect_encap_sw_icm_size[0x8];
1305 	u8         reserved_at_128[0x10];
1306 	u8         log_header_modify_pattern_sw_icm_size[0x8];
1307 
1308 	u8         header_modify_sw_icm_start_address[0x40];
1309 
1310 	u8         reserved_at_180[0x40];
1311 
1312 	u8         header_modify_pattern_sw_icm_start_address[0x40];
1313 
1314 	u8         memic_operations[0x20];
1315 
1316 	u8         reserved_at_220[0x20];
1317 
1318 	u8         indirect_encap_sw_icm_start_address[0x40];
1319 
1320 	u8         reserved_at_280[0x580];
1321 };
1322 
1323 struct mlx5_ifc_device_event_cap_bits {
1324 	u8         user_affiliated_events[4][0x40];
1325 
1326 	u8         user_unaffiliated_events[4][0x40];
1327 };
1328 
1329 struct mlx5_ifc_virtio_emulation_cap_bits {
1330 	u8         desc_tunnel_offload_type[0x1];
1331 	u8         eth_frame_offload_type[0x1];
1332 	u8         virtio_version_1_0[0x1];
1333 	u8         device_features_bits_mask[0xd];
1334 	u8         event_mode[0x8];
1335 	u8         virtio_queue_type[0x8];
1336 
1337 	u8         max_tunnel_desc[0x10];
1338 	u8         reserved_at_30[0x3];
1339 	u8         log_doorbell_stride[0x5];
1340 	u8         reserved_at_38[0x3];
1341 	u8         log_doorbell_bar_size[0x5];
1342 
1343 	u8         doorbell_bar_offset[0x40];
1344 
1345 	u8         max_emulated_devices[0x8];
1346 	u8         max_num_virtio_queues[0x18];
1347 
1348 	u8         reserved_at_a0[0x20];
1349 
1350 	u8	   reserved_at_c0[0x13];
1351 	u8         desc_group_mkey_supported[0x1];
1352 	u8         freeze_to_rdy_supported[0x1];
1353 	u8         reserved_at_d5[0xb];
1354 
1355 	u8         reserved_at_e0[0x20];
1356 
1357 	u8         umem_1_buffer_param_a[0x20];
1358 
1359 	u8         umem_1_buffer_param_b[0x20];
1360 
1361 	u8         umem_2_buffer_param_a[0x20];
1362 
1363 	u8         umem_2_buffer_param_b[0x20];
1364 
1365 	u8         umem_3_buffer_param_a[0x20];
1366 
1367 	u8         umem_3_buffer_param_b[0x20];
1368 
1369 	u8         reserved_at_1c0[0x640];
1370 };
1371 
1372 enum {
1373 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1374 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1375 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1376 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1377 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1378 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1379 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1380 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1381 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1382 };
1383 
1384 enum {
1385 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1386 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1387 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1388 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1389 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1390 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1391 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1392 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1393 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1394 };
1395 
1396 struct mlx5_ifc_atomic_caps_bits {
1397 	u8         reserved_at_0[0x40];
1398 
1399 	u8         atomic_req_8B_endianness_mode[0x2];
1400 	u8         reserved_at_42[0x4];
1401 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1402 
1403 	u8         reserved_at_47[0x19];
1404 
1405 	u8         reserved_at_60[0x20];
1406 
1407 	u8         reserved_at_80[0x10];
1408 	u8         atomic_operations[0x10];
1409 
1410 	u8         reserved_at_a0[0x10];
1411 	u8         atomic_size_qp[0x10];
1412 
1413 	u8         reserved_at_c0[0x10];
1414 	u8         atomic_size_dc[0x10];
1415 
1416 	u8         reserved_at_e0[0x720];
1417 };
1418 
1419 struct mlx5_ifc_odp_scheme_cap_bits {
1420 	u8         reserved_at_0[0x40];
1421 
1422 	u8         sig[0x1];
1423 	u8         reserved_at_41[0x4];
1424 	u8         page_prefetch[0x1];
1425 	u8         reserved_at_46[0x1a];
1426 
1427 	u8         reserved_at_60[0x20];
1428 
1429 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1430 
1431 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1432 
1433 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1434 
1435 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1436 
1437 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1438 
1439 	u8         reserved_at_120[0xe0];
1440 };
1441 
1442 struct mlx5_ifc_odp_cap_bits {
1443 	struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap;
1444 
1445 	struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap;
1446 
1447 	u8         reserved_at_400[0x200];
1448 
1449 	u8         mem_page_fault[0x1];
1450 	u8         reserved_at_601[0x1f];
1451 
1452 	u8         reserved_at_620[0x1e0];
1453 };
1454 
1455 struct mlx5_ifc_tls_cap_bits {
1456 	u8         tls_1_2_aes_gcm_128[0x1];
1457 	u8         tls_1_3_aes_gcm_128[0x1];
1458 	u8         tls_1_2_aes_gcm_256[0x1];
1459 	u8         tls_1_3_aes_gcm_256[0x1];
1460 	u8         reserved_at_4[0x1c];
1461 
1462 	u8         reserved_at_20[0x7e0];
1463 };
1464 
1465 struct mlx5_ifc_ipsec_cap_bits {
1466 	u8         ipsec_full_offload[0x1];
1467 	u8         ipsec_crypto_offload[0x1];
1468 	u8         ipsec_esn[0x1];
1469 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1470 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1471 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1472 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1473 	u8         reserved_at_7[0x4];
1474 	u8         log_max_ipsec_offload[0x5];
1475 	u8         reserved_at_10[0x10];
1476 
1477 	u8         min_log_ipsec_full_replay_window[0x8];
1478 	u8         max_log_ipsec_full_replay_window[0x8];
1479 	u8         reserved_at_30[0x7d0];
1480 };
1481 
1482 struct mlx5_ifc_macsec_cap_bits {
1483 	u8    macsec_epn[0x1];
1484 	u8    reserved_at_1[0x2];
1485 	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1486 	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1487 	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1488 	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1489 	u8    reserved_at_7[0x4];
1490 	u8    log_max_macsec_offload[0x5];
1491 	u8    reserved_at_10[0x10];
1492 
1493 	u8    min_log_macsec_full_replay_window[0x8];
1494 	u8    max_log_macsec_full_replay_window[0x8];
1495 	u8    reserved_at_30[0x10];
1496 
1497 	u8    reserved_at_40[0x7c0];
1498 };
1499 
1500 enum {
1501 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1502 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1503 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1504 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1505 };
1506 
1507 enum {
1508 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1509 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1510 };
1511 
1512 enum {
1513 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1514 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1515 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1516 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1517 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1518 };
1519 
1520 enum {
1521 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1522 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1523 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1524 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1525 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1526 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1527 };
1528 
1529 enum {
1530 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1531 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1532 };
1533 
1534 enum {
1535 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1536 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1537 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1538 };
1539 
1540 enum {
1541 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1542 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1543 };
1544 
1545 enum {
1546 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1547 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1548 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1549 };
1550 
1551 enum {
1552 	MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED	= 1 << 0,
1553 	MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED	= 1 << 1,
1554 	MLX5_FLEX_IPV6_OVER_IP_ENABLED		= 1 << 2,
1555 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1556 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1557 	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1558 	MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED	= 1 << 6,
1559 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1560 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1561 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1562 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1563 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1564 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1565 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1566 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1567 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1568 };
1569 
1570 enum {
1571 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1572 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1573 };
1574 
1575 #define MLX5_FC_BULK_SIZE_FACTOR 128
1576 
1577 enum mlx5_fc_bulk_alloc_bitmask {
1578 	MLX5_FC_BULK_128   = (1 << 0),
1579 	MLX5_FC_BULK_256   = (1 << 1),
1580 	MLX5_FC_BULK_512   = (1 << 2),
1581 	MLX5_FC_BULK_1024  = (1 << 3),
1582 	MLX5_FC_BULK_2048  = (1 << 4),
1583 	MLX5_FC_BULK_4096  = (1 << 5),
1584 	MLX5_FC_BULK_8192  = (1 << 6),
1585 	MLX5_FC_BULK_16384 = (1 << 7),
1586 };
1587 
1588 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1589 
1590 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1591 
1592 enum {
1593 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1594 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1595 	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1596 	MLX5_STEERING_FORMAT_CONNECTX_8   = 3,
1597 };
1598 
1599 struct mlx5_ifc_cmd_hca_cap_bits {
1600 	u8         reserved_at_0[0x6];
1601 	u8         page_request_disable[0x1];
1602 	u8         abs_native_port_num[0x1];
1603 	u8         reserved_at_8[0x8];
1604 	u8         shared_object_to_user_object_allowed[0x1];
1605 	u8         reserved_at_13[0xe];
1606 	u8         vhca_resource_manager[0x1];
1607 
1608 	u8         hca_cap_2[0x1];
1609 	u8         create_lag_when_not_master_up[0x1];
1610 	u8         dtor[0x1];
1611 	u8         event_on_vhca_state_teardown_request[0x1];
1612 	u8         event_on_vhca_state_in_use[0x1];
1613 	u8         event_on_vhca_state_active[0x1];
1614 	u8         event_on_vhca_state_allocated[0x1];
1615 	u8         event_on_vhca_state_invalid[0x1];
1616 	u8         reserved_at_28[0x8];
1617 	u8         vhca_id[0x10];
1618 
1619 	u8         reserved_at_40[0x40];
1620 
1621 	u8         log_max_srq_sz[0x8];
1622 	u8         log_max_qp_sz[0x8];
1623 	u8         event_cap[0x1];
1624 	u8         reserved_at_91[0x2];
1625 	u8         isolate_vl_tc_new[0x1];
1626 	u8         reserved_at_94[0x4];
1627 	u8         prio_tag_required[0x1];
1628 	u8         reserved_at_99[0x2];
1629 	u8         log_max_qp[0x5];
1630 
1631 	u8         reserved_at_a0[0x3];
1632 	u8	   ece_support[0x1];
1633 	u8	   reserved_at_a4[0x5];
1634 	u8         reg_c_preserve[0x1];
1635 	u8         reserved_at_aa[0x1];
1636 	u8         log_max_srq[0x5];
1637 	u8         reserved_at_b0[0x1];
1638 	u8         uplink_follow[0x1];
1639 	u8         ts_cqe_to_dest_cqn[0x1];
1640 	u8         reserved_at_b3[0x6];
1641 	u8         go_back_n[0x1];
1642 	u8         reserved_at_ba[0x6];
1643 
1644 	u8         max_sgl_for_optimized_performance[0x8];
1645 	u8         log_max_cq_sz[0x8];
1646 	u8         relaxed_ordering_write_umr[0x1];
1647 	u8         relaxed_ordering_read_umr[0x1];
1648 	u8         reserved_at_d2[0x7];
1649 	u8         virtio_net_device_emualtion_manager[0x1];
1650 	u8         virtio_blk_device_emualtion_manager[0x1];
1651 	u8         log_max_cq[0x5];
1652 
1653 	u8         log_max_eq_sz[0x8];
1654 	u8         relaxed_ordering_write[0x1];
1655 	u8         relaxed_ordering_read_pci_enabled[0x1];
1656 	u8         log_max_mkey[0x6];
1657 	u8         reserved_at_f0[0x6];
1658 	u8	   terminate_scatter_list_mkey[0x1];
1659 	u8	   repeated_mkey[0x1];
1660 	u8         dump_fill_mkey[0x1];
1661 	u8         reserved_at_f9[0x2];
1662 	u8         fast_teardown[0x1];
1663 	u8         log_max_eq[0x4];
1664 
1665 	u8         max_indirection[0x8];
1666 	u8         fixed_buffer_size[0x1];
1667 	u8         log_max_mrw_sz[0x7];
1668 	u8         force_teardown[0x1];
1669 	u8         reserved_at_111[0x1];
1670 	u8         log_max_bsf_list_size[0x6];
1671 	u8         umr_extended_translation_offset[0x1];
1672 	u8         null_mkey[0x1];
1673 	u8         log_max_klm_list_size[0x6];
1674 
1675 	u8         reserved_at_120[0x2];
1676 	u8	   qpc_extension[0x1];
1677 	u8	   reserved_at_123[0x7];
1678 	u8         log_max_ra_req_dc[0x6];
1679 	u8         reserved_at_130[0x2];
1680 	u8         eth_wqe_too_small[0x1];
1681 	u8         reserved_at_133[0x6];
1682 	u8         vnic_env_cq_overrun[0x1];
1683 	u8         log_max_ra_res_dc[0x6];
1684 
1685 	u8         reserved_at_140[0x5];
1686 	u8         release_all_pages[0x1];
1687 	u8         must_not_use[0x1];
1688 	u8         reserved_at_147[0x2];
1689 	u8         roce_accl[0x1];
1690 	u8         log_max_ra_req_qp[0x6];
1691 	u8         reserved_at_150[0xa];
1692 	u8         log_max_ra_res_qp[0x6];
1693 
1694 	u8         end_pad[0x1];
1695 	u8         cc_query_allowed[0x1];
1696 	u8         cc_modify_allowed[0x1];
1697 	u8         start_pad[0x1];
1698 	u8         cache_line_128byte[0x1];
1699 	u8         reserved_at_165[0x4];
1700 	u8         rts2rts_qp_counters_set_id[0x1];
1701 	u8         reserved_at_16a[0x2];
1702 	u8         vnic_env_int_rq_oob[0x1];
1703 	u8         sbcam_reg[0x1];
1704 	u8         reserved_at_16e[0x1];
1705 	u8         qcam_reg[0x1];
1706 	u8         gid_table_size[0x10];
1707 
1708 	u8         out_of_seq_cnt[0x1];
1709 	u8         vport_counters[0x1];
1710 	u8         retransmission_q_counters[0x1];
1711 	u8         debug[0x1];
1712 	u8         modify_rq_counter_set_id[0x1];
1713 	u8         rq_delay_drop[0x1];
1714 	u8         max_qp_cnt[0xa];
1715 	u8         pkey_table_size[0x10];
1716 
1717 	u8         vport_group_manager[0x1];
1718 	u8         vhca_group_manager[0x1];
1719 	u8         ib_virt[0x1];
1720 	u8         eth_virt[0x1];
1721 	u8         vnic_env_queue_counters[0x1];
1722 	u8         ets[0x1];
1723 	u8         nic_flow_table[0x1];
1724 	u8         eswitch_manager[0x1];
1725 	u8         device_memory[0x1];
1726 	u8         mcam_reg[0x1];
1727 	u8         pcam_reg[0x1];
1728 	u8         local_ca_ack_delay[0x5];
1729 	u8         port_module_event[0x1];
1730 	u8         enhanced_error_q_counters[0x1];
1731 	u8         ports_check[0x1];
1732 	u8         reserved_at_1b3[0x1];
1733 	u8         disable_link_up[0x1];
1734 	u8         beacon_led[0x1];
1735 	u8         port_type[0x2];
1736 	u8         num_ports[0x8];
1737 
1738 	u8         reserved_at_1c0[0x1];
1739 	u8         pps[0x1];
1740 	u8         pps_modify[0x1];
1741 	u8         log_max_msg[0x5];
1742 	u8         reserved_at_1c8[0x4];
1743 	u8         max_tc[0x4];
1744 	u8         temp_warn_event[0x1];
1745 	u8         dcbx[0x1];
1746 	u8         general_notification_event[0x1];
1747 	u8         reserved_at_1d3[0x2];
1748 	u8         fpga[0x1];
1749 	u8         rol_s[0x1];
1750 	u8         rol_g[0x1];
1751 	u8         reserved_at_1d8[0x1];
1752 	u8         wol_s[0x1];
1753 	u8         wol_g[0x1];
1754 	u8         wol_a[0x1];
1755 	u8         wol_b[0x1];
1756 	u8         wol_m[0x1];
1757 	u8         wol_u[0x1];
1758 	u8         wol_p[0x1];
1759 
1760 	u8         stat_rate_support[0x10];
1761 	u8         reserved_at_1f0[0x1];
1762 	u8         pci_sync_for_fw_update_event[0x1];
1763 	u8         reserved_at_1f2[0x6];
1764 	u8         init2_lag_tx_port_affinity[0x1];
1765 	u8         reserved_at_1fa[0x2];
1766 	u8         wqe_based_flow_table_update_cap[0x1];
1767 	u8         cqe_version[0x4];
1768 
1769 	u8         compact_address_vector[0x1];
1770 	u8         striding_rq[0x1];
1771 	u8         reserved_at_202[0x1];
1772 	u8         ipoib_enhanced_offloads[0x1];
1773 	u8         ipoib_basic_offloads[0x1];
1774 	u8         reserved_at_205[0x1];
1775 	u8         repeated_block_disabled[0x1];
1776 	u8         umr_modify_entity_size_disabled[0x1];
1777 	u8         umr_modify_atomic_disabled[0x1];
1778 	u8         umr_indirect_mkey_disabled[0x1];
1779 	u8         umr_fence[0x2];
1780 	u8         dc_req_scat_data_cqe[0x1];
1781 	u8         reserved_at_20d[0x2];
1782 	u8         drain_sigerr[0x1];
1783 	u8         cmdif_checksum[0x2];
1784 	u8         sigerr_cqe[0x1];
1785 	u8         reserved_at_213[0x1];
1786 	u8         wq_signature[0x1];
1787 	u8         sctr_data_cqe[0x1];
1788 	u8         reserved_at_216[0x1];
1789 	u8         sho[0x1];
1790 	u8         tph[0x1];
1791 	u8         rf[0x1];
1792 	u8         dct[0x1];
1793 	u8         qos[0x1];
1794 	u8         eth_net_offloads[0x1];
1795 	u8         roce[0x1];
1796 	u8         atomic[0x1];
1797 	u8         reserved_at_21f[0x1];
1798 
1799 	u8         cq_oi[0x1];
1800 	u8         cq_resize[0x1];
1801 	u8         cq_moderation[0x1];
1802 	u8         cq_period_mode_modify[0x1];
1803 	u8         reserved_at_224[0x2];
1804 	u8         cq_eq_remap[0x1];
1805 	u8         pg[0x1];
1806 	u8         block_lb_mc[0x1];
1807 	u8         reserved_at_229[0x1];
1808 	u8         scqe_break_moderation[0x1];
1809 	u8         cq_period_start_from_cqe[0x1];
1810 	u8         cd[0x1];
1811 	u8         reserved_at_22d[0x1];
1812 	u8         apm[0x1];
1813 	u8         vector_calc[0x1];
1814 	u8         umr_ptr_rlky[0x1];
1815 	u8	   imaicl[0x1];
1816 	u8	   qp_packet_based[0x1];
1817 	u8         reserved_at_233[0x3];
1818 	u8         qkv[0x1];
1819 	u8         pkv[0x1];
1820 	u8         set_deth_sqpn[0x1];
1821 	u8         reserved_at_239[0x3];
1822 	u8         xrc[0x1];
1823 	u8         ud[0x1];
1824 	u8         uc[0x1];
1825 	u8         rc[0x1];
1826 
1827 	u8         uar_4k[0x1];
1828 	u8         reserved_at_241[0x7];
1829 	u8         fl_rc_qp_when_roce_disabled[0x1];
1830 	u8         regexp_params[0x1];
1831 	u8         uar_sz[0x6];
1832 	u8         port_selection_cap[0x1];
1833 	u8         nic_cap_reg[0x1];
1834 	u8         umem_uid_0[0x1];
1835 	u8         reserved_at_253[0x5];
1836 	u8         log_pg_sz[0x8];
1837 
1838 	u8         bf[0x1];
1839 	u8         driver_version[0x1];
1840 	u8         pad_tx_eth_packet[0x1];
1841 	u8         reserved_at_263[0x3];
1842 	u8         mkey_by_name[0x1];
1843 	u8         reserved_at_267[0x4];
1844 
1845 	u8         log_bf_reg_size[0x5];
1846 
1847 	u8         reserved_at_270[0x3];
1848 	u8	   qp_error_syndrome[0x1];
1849 	u8	   reserved_at_274[0x2];
1850 	u8         lag_dct[0x2];
1851 	u8         lag_tx_port_affinity[0x1];
1852 	u8         lag_native_fdb_selection[0x1];
1853 	u8         reserved_at_27a[0x1];
1854 	u8         lag_master[0x1];
1855 	u8         num_lag_ports[0x4];
1856 
1857 	u8         reserved_at_280[0x10];
1858 	u8         max_wqe_sz_sq[0x10];
1859 
1860 	u8         reserved_at_2a0[0xb];
1861 	u8         shampo[0x1];
1862 	u8         reserved_at_2ac[0x4];
1863 	u8         max_wqe_sz_rq[0x10];
1864 
1865 	u8         max_flow_counter_31_16[0x10];
1866 	u8         max_wqe_sz_sq_dc[0x10];
1867 
1868 	u8         reserved_at_2e0[0x7];
1869 	u8         max_qp_mcg[0x19];
1870 
1871 	u8         reserved_at_300[0x10];
1872 	u8         flow_counter_bulk_alloc[0x8];
1873 	u8         log_max_mcg[0x8];
1874 
1875 	u8         reserved_at_320[0x3];
1876 	u8         log_max_transport_domain[0x5];
1877 	u8         reserved_at_328[0x2];
1878 	u8	   relaxed_ordering_read[0x1];
1879 	u8         log_max_pd[0x5];
1880 	u8         dp_ordering_ooo_all_ud[0x1];
1881 	u8         dp_ordering_ooo_all_uc[0x1];
1882 	u8         dp_ordering_ooo_all_xrc[0x1];
1883 	u8         dp_ordering_ooo_all_dc[0x1];
1884 	u8         dp_ordering_ooo_all_rc[0x1];
1885 	u8         pcie_reset_using_hotreset_method[0x1];
1886 	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1887 	u8         vnic_env_cnt_steering_fail[0x1];
1888 	u8         vport_counter_local_loopback[0x1];
1889 	u8         q_counter_aggregation[0x1];
1890 	u8         q_counter_other_vport[0x1];
1891 	u8         log_max_xrcd[0x5];
1892 
1893 	u8         nic_receive_steering_discard[0x1];
1894 	u8         receive_discard_vport_down[0x1];
1895 	u8         transmit_discard_vport_down[0x1];
1896 	u8         eq_overrun_count[0x1];
1897 	u8         reserved_at_344[0x1];
1898 	u8         invalid_command_count[0x1];
1899 	u8         quota_exceeded_count[0x1];
1900 	u8         reserved_at_347[0x1];
1901 	u8         log_max_flow_counter_bulk[0x8];
1902 	u8         max_flow_counter_15_0[0x10];
1903 
1904 
1905 	u8         reserved_at_360[0x3];
1906 	u8         log_max_rq[0x5];
1907 	u8         reserved_at_368[0x3];
1908 	u8         log_max_sq[0x5];
1909 	u8         reserved_at_370[0x3];
1910 	u8         log_max_tir[0x5];
1911 	u8         reserved_at_378[0x3];
1912 	u8         log_max_tis[0x5];
1913 
1914 	u8         basic_cyclic_rcv_wqe[0x1];
1915 	u8         reserved_at_381[0x2];
1916 	u8         log_max_rmp[0x5];
1917 	u8         reserved_at_388[0x3];
1918 	u8         log_max_rqt[0x5];
1919 	u8         reserved_at_390[0x3];
1920 	u8         log_max_rqt_size[0x5];
1921 	u8         reserved_at_398[0x3];
1922 	u8         log_max_tis_per_sq[0x5];
1923 
1924 	u8         ext_stride_num_range[0x1];
1925 	u8         roce_rw_supported[0x1];
1926 	u8         log_max_current_uc_list_wr_supported[0x1];
1927 	u8         log_max_stride_sz_rq[0x5];
1928 	u8         reserved_at_3a8[0x3];
1929 	u8         log_min_stride_sz_rq[0x5];
1930 	u8         reserved_at_3b0[0x3];
1931 	u8         log_max_stride_sz_sq[0x5];
1932 	u8         reserved_at_3b8[0x3];
1933 	u8         log_min_stride_sz_sq[0x5];
1934 
1935 	u8         hairpin[0x1];
1936 	u8         reserved_at_3c1[0x2];
1937 	u8         log_max_hairpin_queues[0x5];
1938 	u8         reserved_at_3c8[0x3];
1939 	u8         log_max_hairpin_wq_data_sz[0x5];
1940 	u8         reserved_at_3d0[0x3];
1941 	u8         log_max_hairpin_num_packets[0x5];
1942 	u8         reserved_at_3d8[0x3];
1943 	u8         log_max_wq_sz[0x5];
1944 
1945 	u8         nic_vport_change_event[0x1];
1946 	u8         disable_local_lb_uc[0x1];
1947 	u8         disable_local_lb_mc[0x1];
1948 	u8         log_min_hairpin_wq_data_sz[0x5];
1949 	u8         reserved_at_3e8[0x1];
1950 	u8         silent_mode[0x1];
1951 	u8         vhca_state[0x1];
1952 	u8         log_max_vlan_list[0x5];
1953 	u8         reserved_at_3f0[0x3];
1954 	u8         log_max_current_mc_list[0x5];
1955 	u8         reserved_at_3f8[0x3];
1956 	u8         log_max_current_uc_list[0x5];
1957 
1958 	u8         general_obj_types[0x40];
1959 
1960 	u8         sq_ts_format[0x2];
1961 	u8         rq_ts_format[0x2];
1962 	u8         steering_format_version[0x4];
1963 	u8         create_qp_start_hint[0x18];
1964 
1965 	u8         reserved_at_460[0x1];
1966 	u8         ats[0x1];
1967 	u8         cross_vhca_rqt[0x1];
1968 	u8         log_max_uctx[0x5];
1969 	u8         reserved_at_468[0x1];
1970 	u8         crypto[0x1];
1971 	u8         ipsec_offload[0x1];
1972 	u8         log_max_umem[0x5];
1973 	u8         max_num_eqs[0x10];
1974 
1975 	u8         reserved_at_480[0x1];
1976 	u8         tls_tx[0x1];
1977 	u8         tls_rx[0x1];
1978 	u8         log_max_l2_table[0x5];
1979 	u8         reserved_at_488[0x8];
1980 	u8         log_uar_page_sz[0x10];
1981 
1982 	u8         reserved_at_4a0[0x20];
1983 	u8         device_frequency_mhz[0x20];
1984 	u8         device_frequency_khz[0x20];
1985 
1986 	u8         reserved_at_500[0x20];
1987 	u8	   num_of_uars_per_page[0x20];
1988 
1989 	u8         flex_parser_protocols[0x20];
1990 
1991 	u8         max_geneve_tlv_options[0x8];
1992 	u8         reserved_at_568[0x3];
1993 	u8         max_geneve_tlv_option_data_len[0x5];
1994 	u8         reserved_at_570[0x9];
1995 	u8         adv_virtualization[0x1];
1996 	u8         reserved_at_57a[0x6];
1997 
1998 	u8	   reserved_at_580[0xb];
1999 	u8	   log_max_dci_stream_channels[0x5];
2000 	u8	   reserved_at_590[0x3];
2001 	u8	   log_max_dci_errored_streams[0x5];
2002 	u8	   reserved_at_598[0x8];
2003 
2004 	u8         reserved_at_5a0[0x10];
2005 	u8         enhanced_cqe_compression[0x1];
2006 	u8         reserved_at_5b1[0x1];
2007 	u8         crossing_vhca_mkey[0x1];
2008 	u8         log_max_dek[0x5];
2009 	u8         reserved_at_5b8[0x4];
2010 	u8         mini_cqe_resp_stride_index[0x1];
2011 	u8         cqe_128_always[0x1];
2012 	u8         cqe_compression_128[0x1];
2013 	u8         cqe_compression[0x1];
2014 
2015 	u8         cqe_compression_timeout[0x10];
2016 	u8         cqe_compression_max_num[0x10];
2017 
2018 	u8         reserved_at_5e0[0x8];
2019 	u8         flex_parser_id_gtpu_dw_0[0x4];
2020 	u8         reserved_at_5ec[0x4];
2021 	u8         tag_matching[0x1];
2022 	u8         rndv_offload_rc[0x1];
2023 	u8         rndv_offload_dc[0x1];
2024 	u8         log_tag_matching_list_sz[0x5];
2025 	u8         reserved_at_5f8[0x3];
2026 	u8         log_max_xrq[0x5];
2027 
2028 	u8	   affiliate_nic_vport_criteria[0x8];
2029 	u8	   native_port_num[0x8];
2030 	u8	   num_vhca_ports[0x8];
2031 	u8         flex_parser_id_gtpu_teid[0x4];
2032 	u8         reserved_at_61c[0x2];
2033 	u8	   sw_owner_id[0x1];
2034 	u8         reserved_at_61f[0x1];
2035 
2036 	u8         max_num_of_monitor_counters[0x10];
2037 	u8         num_ppcnt_monitor_counters[0x10];
2038 
2039 	u8         max_num_sf[0x10];
2040 	u8         num_q_monitor_counters[0x10];
2041 
2042 	u8         reserved_at_660[0x20];
2043 
2044 	u8         sf[0x1];
2045 	u8         sf_set_partition[0x1];
2046 	u8         reserved_at_682[0x1];
2047 	u8         log_max_sf[0x5];
2048 	u8         apu[0x1];
2049 	u8         reserved_at_689[0x4];
2050 	u8         migration[0x1];
2051 	u8         reserved_at_68e[0x2];
2052 	u8         log_min_sf_size[0x8];
2053 	u8         max_num_sf_partitions[0x8];
2054 
2055 	u8         uctx_cap[0x20];
2056 
2057 	u8         reserved_at_6c0[0x4];
2058 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
2059 	u8         flex_parser_id_icmp_dw1[0x4];
2060 	u8         flex_parser_id_icmp_dw0[0x4];
2061 	u8         flex_parser_id_icmpv6_dw1[0x4];
2062 	u8         flex_parser_id_icmpv6_dw0[0x4];
2063 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
2064 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
2065 
2066 	u8         max_num_match_definer[0x10];
2067 	u8	   sf_base_id[0x10];
2068 
2069 	u8         flex_parser_id_gtpu_dw_2[0x4];
2070 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
2071 	u8	   num_total_dynamic_vf_msix[0x18];
2072 	u8	   reserved_at_720[0x14];
2073 	u8	   dynamic_msix_table_size[0xc];
2074 	u8	   reserved_at_740[0xc];
2075 	u8	   min_dynamic_vf_msix_table_size[0x4];
2076 	u8	   reserved_at_750[0x2];
2077 	u8	   data_direct[0x1];
2078 	u8	   reserved_at_753[0x1];
2079 	u8	   max_dynamic_vf_msix_table_size[0xc];
2080 
2081 	u8         reserved_at_760[0x3];
2082 	u8         log_max_num_header_modify_argument[0x5];
2083 	u8         log_header_modify_argument_granularity_offset[0x4];
2084 	u8         log_header_modify_argument_granularity[0x4];
2085 	u8         reserved_at_770[0x3];
2086 	u8         log_header_modify_argument_max_alloc[0x5];
2087 	u8         reserved_at_778[0x8];
2088 
2089 	u8	   vhca_tunnel_commands[0x40];
2090 	u8         match_definer_format_supported[0x40];
2091 };
2092 
2093 enum {
2094 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS  = 0x80000,
2095 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE  = (1ULL << 20),
2096 };
2097 
2098 enum {
2099 	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE       = 0x200,
2100 };
2101 
2102 struct mlx5_ifc_cmd_hca_cap_2_bits {
2103 	u8	   reserved_at_0[0x80];
2104 
2105 	u8         migratable[0x1];
2106 	u8         reserved_at_81[0x7];
2107 	u8         dp_ordering_force[0x1];
2108 	u8         reserved_at_89[0x9];
2109 	u8         query_vuid[0x1];
2110 	u8         reserved_at_93[0x5];
2111 	u8         umr_log_entity_size_5[0x1];
2112 	u8         reserved_at_99[0x7];
2113 
2114 	u8	   max_reformat_insert_size[0x8];
2115 	u8	   max_reformat_insert_offset[0x8];
2116 	u8	   max_reformat_remove_size[0x8];
2117 	u8	   max_reformat_remove_offset[0x8];
2118 
2119 	u8	   reserved_at_c0[0x8];
2120 	u8	   migration_multi_load[0x1];
2121 	u8	   migration_tracking_state[0x1];
2122 	u8	   multiplane_qp_ud[0x1];
2123 	u8	   reserved_at_cb[0x5];
2124 	u8	   migration_in_chunks[0x1];
2125 	u8	   reserved_at_d1[0x1];
2126 	u8	   sf_eq_usage[0x1];
2127 	u8	   reserved_at_d3[0x5];
2128 	u8	   multiplane[0x1];
2129 	u8	   reserved_at_d9[0x7];
2130 
2131 	u8	   cross_vhca_object_to_object_supported[0x20];
2132 
2133 	u8	   allowed_object_for_other_vhca_access[0x40];
2134 
2135 	u8	   reserved_at_140[0x60];
2136 
2137 	u8	   flow_table_type_2_type[0x8];
2138 	u8	   reserved_at_1a8[0x2];
2139 	u8         format_select_dw_8_6_ext[0x1];
2140 	u8	   log_min_mkey_entity_size[0x5];
2141 	u8	   reserved_at_1b0[0x10];
2142 
2143 	u8	   reserved_at_1c0[0x60];
2144 
2145 	u8	   reserved_at_220[0x1];
2146 	u8	   sw_vhca_id_valid[0x1];
2147 	u8	   sw_vhca_id[0xe];
2148 	u8	   reserved_at_230[0x10];
2149 
2150 	u8	   reserved_at_240[0xb];
2151 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
2152 	u8	   reserved_at_250[0x10];
2153 
2154 	u8	   reserved_at_260[0x20];
2155 
2156 	u8	   format_select_dw_gtpu_dw_0[0x8];
2157 	u8	   format_select_dw_gtpu_dw_1[0x8];
2158 	u8	   format_select_dw_gtpu_dw_2[0x8];
2159 	u8	   format_select_dw_gtpu_first_ext_dw_0[0x8];
2160 
2161 	u8	   generate_wqe_type[0x20];
2162 
2163 	u8	   reserved_at_2c0[0xc0];
2164 
2165 	u8	   reserved_at_380[0xb];
2166 	u8	   min_mkey_log_entity_size_fixed_buffer[0x5];
2167 	u8	   ec_vf_vport_base[0x10];
2168 
2169 	u8	   reserved_at_3a0[0xa];
2170 	u8	   max_mkey_log_entity_size_mtt[0x6];
2171 	u8	   max_rqt_vhca_id[0x10];
2172 
2173 	u8	   reserved_at_3c0[0x20];
2174 
2175 	u8	   reserved_at_3e0[0x10];
2176 	u8	   pcc_ifa2[0x1];
2177 	u8	   reserved_at_3f1[0xf];
2178 
2179 	u8	   reserved_at_400[0x1];
2180 	u8	   min_mkey_log_entity_size_fixed_buffer_valid[0x1];
2181 	u8	   reserved_at_402[0xe];
2182 	u8	   return_reg_id[0x10];
2183 
2184 	u8	   reserved_at_420[0x1c];
2185 	u8	   flow_table_hash_type[0x4];
2186 
2187 	u8	   reserved_at_440[0x8];
2188 	u8	   max_num_eqs_24b[0x18];
2189 	u8	   reserved_at_460[0x3a0];
2190 };
2191 
2192 enum mlx5_ifc_flow_destination_type {
2193 	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2194 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2195 	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2196 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2197 	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2198 	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2199 };
2200 
2201 enum mlx5_flow_table_miss_action {
2202 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2203 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2204 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2205 };
2206 
2207 struct mlx5_ifc_dest_format_struct_bits {
2208 	u8         destination_type[0x8];
2209 	u8         destination_id[0x18];
2210 
2211 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
2212 	u8         packet_reformat[0x1];
2213 	u8         reserved_at_22[0x6];
2214 	u8         destination_table_type[0x8];
2215 	u8         destination_eswitch_owner_vhca_id[0x10];
2216 };
2217 
2218 struct mlx5_ifc_flow_counter_list_bits {
2219 	u8         flow_counter_id[0x20];
2220 
2221 	u8         reserved_at_20[0x20];
2222 };
2223 
2224 struct mlx5_ifc_extended_dest_format_bits {
2225 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2226 
2227 	u8         packet_reformat_id[0x20];
2228 
2229 	u8         reserved_at_60[0x20];
2230 };
2231 
2232 union mlx5_ifc_dest_format_flow_counter_list_auto_bits {
2233 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2234 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2235 };
2236 
2237 struct mlx5_ifc_fte_match_param_bits {
2238 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2239 
2240 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2241 
2242 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2243 
2244 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2245 
2246 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2247 
2248 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2249 
2250 	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2251 
2252 	u8         reserved_at_e00[0x200];
2253 };
2254 
2255 enum {
2256 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2257 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2258 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2259 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2260 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2261 };
2262 
2263 struct mlx5_ifc_rx_hash_field_select_bits {
2264 	u8         l3_prot_type[0x1];
2265 	u8         l4_prot_type[0x1];
2266 	u8         selected_fields[0x1e];
2267 };
2268 
2269 enum {
2270 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2271 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2272 };
2273 
2274 enum {
2275 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2276 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2277 };
2278 
2279 struct mlx5_ifc_wq_bits {
2280 	u8         wq_type[0x4];
2281 	u8         wq_signature[0x1];
2282 	u8         end_padding_mode[0x2];
2283 	u8         cd_slave[0x1];
2284 	u8         reserved_at_8[0x18];
2285 
2286 	u8         hds_skip_first_sge[0x1];
2287 	u8         log2_hds_buf_size[0x3];
2288 	u8         reserved_at_24[0x7];
2289 	u8         page_offset[0x5];
2290 	u8         lwm[0x10];
2291 
2292 	u8         reserved_at_40[0x8];
2293 	u8         pd[0x18];
2294 
2295 	u8         reserved_at_60[0x8];
2296 	u8         uar_page[0x18];
2297 
2298 	u8         dbr_addr[0x40];
2299 
2300 	u8         hw_counter[0x20];
2301 
2302 	u8         sw_counter[0x20];
2303 
2304 	u8         reserved_at_100[0xc];
2305 	u8         log_wq_stride[0x4];
2306 	u8         reserved_at_110[0x3];
2307 	u8         log_wq_pg_sz[0x5];
2308 	u8         reserved_at_118[0x3];
2309 	u8         log_wq_sz[0x5];
2310 
2311 	u8         dbr_umem_valid[0x1];
2312 	u8         wq_umem_valid[0x1];
2313 	u8         reserved_at_122[0x1];
2314 	u8         log_hairpin_num_packets[0x5];
2315 	u8         reserved_at_128[0x3];
2316 	u8         log_hairpin_data_sz[0x5];
2317 
2318 	u8         reserved_at_130[0x4];
2319 	u8         log_wqe_num_of_strides[0x4];
2320 	u8         two_byte_shift_en[0x1];
2321 	u8         reserved_at_139[0x4];
2322 	u8         log_wqe_stride_size[0x3];
2323 
2324 	u8         dbr_umem_id[0x20];
2325 	u8         wq_umem_id[0x20];
2326 
2327 	u8         wq_umem_offset[0x40];
2328 
2329 	u8         headers_mkey[0x20];
2330 
2331 	u8         shampo_enable[0x1];
2332 	u8         reserved_at_1e1[0x1];
2333 	u8         shampo_mode[0x2];
2334 	u8         reserved_at_1e4[0x1];
2335 	u8         log_reservation_size[0x3];
2336 	u8         reserved_at_1e8[0x5];
2337 	u8         log_max_num_of_packets_per_reservation[0x3];
2338 	u8         reserved_at_1f0[0x6];
2339 	u8         log_headers_entry_size[0x2];
2340 	u8         reserved_at_1f8[0x4];
2341 	u8         log_headers_buffer_entry_num[0x4];
2342 
2343 	u8         reserved_at_200[0x400];
2344 
2345 	struct mlx5_ifc_cmd_pas_bits pas[];
2346 };
2347 
2348 struct mlx5_ifc_rq_num_bits {
2349 	u8         reserved_at_0[0x8];
2350 	u8         rq_num[0x18];
2351 };
2352 
2353 struct mlx5_ifc_rq_vhca_bits {
2354 	u8         reserved_at_0[0x8];
2355 	u8         rq_num[0x18];
2356 	u8         reserved_at_20[0x10];
2357 	u8         rq_vhca_id[0x10];
2358 };
2359 
2360 struct mlx5_ifc_mac_address_layout_bits {
2361 	u8         reserved_at_0[0x10];
2362 	u8         mac_addr_47_32[0x10];
2363 
2364 	u8         mac_addr_31_0[0x20];
2365 };
2366 
2367 struct mlx5_ifc_vlan_layout_bits {
2368 	u8         reserved_at_0[0x14];
2369 	u8         vlan[0x0c];
2370 
2371 	u8         reserved_at_20[0x20];
2372 };
2373 
2374 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2375 	u8         reserved_at_0[0xa0];
2376 
2377 	u8         min_time_between_cnps[0x20];
2378 
2379 	u8         reserved_at_c0[0x12];
2380 	u8         cnp_dscp[0x6];
2381 	u8         reserved_at_d8[0x4];
2382 	u8         cnp_prio_mode[0x1];
2383 	u8         cnp_802p_prio[0x3];
2384 
2385 	u8         reserved_at_e0[0x720];
2386 };
2387 
2388 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2389 	u8         reserved_at_0[0x60];
2390 
2391 	u8         reserved_at_60[0x4];
2392 	u8         clamp_tgt_rate[0x1];
2393 	u8         reserved_at_65[0x3];
2394 	u8         clamp_tgt_rate_after_time_inc[0x1];
2395 	u8         reserved_at_69[0x17];
2396 
2397 	u8         reserved_at_80[0x20];
2398 
2399 	u8         rpg_time_reset[0x20];
2400 
2401 	u8         rpg_byte_reset[0x20];
2402 
2403 	u8         rpg_threshold[0x20];
2404 
2405 	u8         rpg_max_rate[0x20];
2406 
2407 	u8         rpg_ai_rate[0x20];
2408 
2409 	u8         rpg_hai_rate[0x20];
2410 
2411 	u8         rpg_gd[0x20];
2412 
2413 	u8         rpg_min_dec_fac[0x20];
2414 
2415 	u8         rpg_min_rate[0x20];
2416 
2417 	u8         reserved_at_1c0[0xe0];
2418 
2419 	u8         rate_to_set_on_first_cnp[0x20];
2420 
2421 	u8         dce_tcp_g[0x20];
2422 
2423 	u8         dce_tcp_rtt[0x20];
2424 
2425 	u8         rate_reduce_monitor_period[0x20];
2426 
2427 	u8         reserved_at_320[0x20];
2428 
2429 	u8         initial_alpha_value[0x20];
2430 
2431 	u8         reserved_at_360[0x4a0];
2432 };
2433 
2434 struct mlx5_ifc_cong_control_r_roce_general_bits {
2435 	u8         reserved_at_0[0x80];
2436 
2437 	u8         reserved_at_80[0x10];
2438 	u8         rtt_resp_dscp_valid[0x1];
2439 	u8         reserved_at_91[0x9];
2440 	u8         rtt_resp_dscp[0x6];
2441 
2442 	u8         reserved_at_a0[0x760];
2443 };
2444 
2445 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2446 	u8         reserved_at_0[0x80];
2447 
2448 	u8         rppp_max_rps[0x20];
2449 
2450 	u8         rpg_time_reset[0x20];
2451 
2452 	u8         rpg_byte_reset[0x20];
2453 
2454 	u8         rpg_threshold[0x20];
2455 
2456 	u8         rpg_max_rate[0x20];
2457 
2458 	u8         rpg_ai_rate[0x20];
2459 
2460 	u8         rpg_hai_rate[0x20];
2461 
2462 	u8         rpg_gd[0x20];
2463 
2464 	u8         rpg_min_dec_fac[0x20];
2465 
2466 	u8         rpg_min_rate[0x20];
2467 
2468 	u8         reserved_at_1c0[0x640];
2469 };
2470 
2471 enum {
2472 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2473 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2474 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2475 };
2476 
2477 struct mlx5_ifc_resize_field_select_bits {
2478 	u8         resize_field_select[0x20];
2479 };
2480 
2481 struct mlx5_ifc_resource_dump_bits {
2482 	u8         more_dump[0x1];
2483 	u8         inline_dump[0x1];
2484 	u8         reserved_at_2[0xa];
2485 	u8         seq_num[0x4];
2486 	u8         segment_type[0x10];
2487 
2488 	u8         reserved_at_20[0x10];
2489 	u8         vhca_id[0x10];
2490 
2491 	u8         index1[0x20];
2492 
2493 	u8         index2[0x20];
2494 
2495 	u8         num_of_obj1[0x10];
2496 	u8         num_of_obj2[0x10];
2497 
2498 	u8         reserved_at_a0[0x20];
2499 
2500 	u8         device_opaque[0x40];
2501 
2502 	u8         mkey[0x20];
2503 
2504 	u8         size[0x20];
2505 
2506 	u8         address[0x40];
2507 
2508 	u8         inline_data[52][0x20];
2509 };
2510 
2511 struct mlx5_ifc_resource_dump_menu_record_bits {
2512 	u8         reserved_at_0[0x4];
2513 	u8         num_of_obj2_supports_active[0x1];
2514 	u8         num_of_obj2_supports_all[0x1];
2515 	u8         must_have_num_of_obj2[0x1];
2516 	u8         support_num_of_obj2[0x1];
2517 	u8         num_of_obj1_supports_active[0x1];
2518 	u8         num_of_obj1_supports_all[0x1];
2519 	u8         must_have_num_of_obj1[0x1];
2520 	u8         support_num_of_obj1[0x1];
2521 	u8         must_have_index2[0x1];
2522 	u8         support_index2[0x1];
2523 	u8         must_have_index1[0x1];
2524 	u8         support_index1[0x1];
2525 	u8         segment_type[0x10];
2526 
2527 	u8         segment_name[4][0x20];
2528 
2529 	u8         index1_name[4][0x20];
2530 
2531 	u8         index2_name[4][0x20];
2532 };
2533 
2534 struct mlx5_ifc_resource_dump_segment_header_bits {
2535 	u8         length_dw[0x10];
2536 	u8         segment_type[0x10];
2537 };
2538 
2539 struct mlx5_ifc_resource_dump_command_segment_bits {
2540 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2541 
2542 	u8         segment_called[0x10];
2543 	u8         vhca_id[0x10];
2544 
2545 	u8         index1[0x20];
2546 
2547 	u8         index2[0x20];
2548 
2549 	u8         num_of_obj1[0x10];
2550 	u8         num_of_obj2[0x10];
2551 };
2552 
2553 struct mlx5_ifc_resource_dump_error_segment_bits {
2554 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2555 
2556 	u8         reserved_at_20[0x10];
2557 	u8         syndrome_id[0x10];
2558 
2559 	u8         reserved_at_40[0x40];
2560 
2561 	u8         error[8][0x20];
2562 };
2563 
2564 struct mlx5_ifc_resource_dump_info_segment_bits {
2565 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2566 
2567 	u8         reserved_at_20[0x18];
2568 	u8         dump_version[0x8];
2569 
2570 	u8         hw_version[0x20];
2571 
2572 	u8         fw_version[0x20];
2573 };
2574 
2575 struct mlx5_ifc_resource_dump_menu_segment_bits {
2576 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2577 
2578 	u8         reserved_at_20[0x10];
2579 	u8         num_of_records[0x10];
2580 
2581 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2582 };
2583 
2584 struct mlx5_ifc_resource_dump_resource_segment_bits {
2585 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2586 
2587 	u8         reserved_at_20[0x20];
2588 
2589 	u8         index1[0x20];
2590 
2591 	u8         index2[0x20];
2592 
2593 	u8         payload[][0x20];
2594 };
2595 
2596 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2597 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2598 };
2599 
2600 struct mlx5_ifc_menu_resource_dump_response_bits {
2601 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2602 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2603 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2604 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2605 };
2606 
2607 enum {
2608 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2609 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2610 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2611 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2612 };
2613 
2614 struct mlx5_ifc_modify_field_select_bits {
2615 	u8         modify_field_select[0x20];
2616 };
2617 
2618 struct mlx5_ifc_field_select_r_roce_np_bits {
2619 	u8         field_select_r_roce_np[0x20];
2620 };
2621 
2622 struct mlx5_ifc_field_select_r_roce_rp_bits {
2623 	u8         field_select_r_roce_rp[0x20];
2624 };
2625 
2626 enum {
2627 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2628 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2629 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2630 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2631 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2632 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2633 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2634 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2635 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2636 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2637 };
2638 
2639 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2640 	u8         field_select_8021qaurp[0x20];
2641 };
2642 
2643 struct mlx5_ifc_phys_layer_cntrs_bits {
2644 	u8         time_since_last_clear_high[0x20];
2645 
2646 	u8         time_since_last_clear_low[0x20];
2647 
2648 	u8         symbol_errors_high[0x20];
2649 
2650 	u8         symbol_errors_low[0x20];
2651 
2652 	u8         sync_headers_errors_high[0x20];
2653 
2654 	u8         sync_headers_errors_low[0x20];
2655 
2656 	u8         edpl_bip_errors_lane0_high[0x20];
2657 
2658 	u8         edpl_bip_errors_lane0_low[0x20];
2659 
2660 	u8         edpl_bip_errors_lane1_high[0x20];
2661 
2662 	u8         edpl_bip_errors_lane1_low[0x20];
2663 
2664 	u8         edpl_bip_errors_lane2_high[0x20];
2665 
2666 	u8         edpl_bip_errors_lane2_low[0x20];
2667 
2668 	u8         edpl_bip_errors_lane3_high[0x20];
2669 
2670 	u8         edpl_bip_errors_lane3_low[0x20];
2671 
2672 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2673 
2674 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2675 
2676 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2677 
2678 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2679 
2680 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2681 
2682 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2683 
2684 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2685 
2686 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2687 
2688 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2689 
2690 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2691 
2692 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2693 
2694 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2695 
2696 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2697 
2698 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2699 
2700 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2701 
2702 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2703 
2704 	u8         rs_fec_corrected_blocks_high[0x20];
2705 
2706 	u8         rs_fec_corrected_blocks_low[0x20];
2707 
2708 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2709 
2710 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2711 
2712 	u8         rs_fec_no_errors_blocks_high[0x20];
2713 
2714 	u8         rs_fec_no_errors_blocks_low[0x20];
2715 
2716 	u8         rs_fec_single_error_blocks_high[0x20];
2717 
2718 	u8         rs_fec_single_error_blocks_low[0x20];
2719 
2720 	u8         rs_fec_corrected_symbols_total_high[0x20];
2721 
2722 	u8         rs_fec_corrected_symbols_total_low[0x20];
2723 
2724 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2725 
2726 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2727 
2728 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2729 
2730 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2731 
2732 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2733 
2734 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2735 
2736 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2737 
2738 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2739 
2740 	u8         link_down_events[0x20];
2741 
2742 	u8         successful_recovery_events[0x20];
2743 
2744 	u8         reserved_at_640[0x180];
2745 };
2746 
2747 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2748 	u8         time_since_last_clear_high[0x20];
2749 
2750 	u8         time_since_last_clear_low[0x20];
2751 
2752 	u8         phy_received_bits_high[0x20];
2753 
2754 	u8         phy_received_bits_low[0x20];
2755 
2756 	u8         phy_symbol_errors_high[0x20];
2757 
2758 	u8         phy_symbol_errors_low[0x20];
2759 
2760 	u8         phy_corrected_bits_high[0x20];
2761 
2762 	u8         phy_corrected_bits_low[0x20];
2763 
2764 	u8         phy_corrected_bits_lane0_high[0x20];
2765 
2766 	u8         phy_corrected_bits_lane0_low[0x20];
2767 
2768 	u8         phy_corrected_bits_lane1_high[0x20];
2769 
2770 	u8         phy_corrected_bits_lane1_low[0x20];
2771 
2772 	u8         phy_corrected_bits_lane2_high[0x20];
2773 
2774 	u8         phy_corrected_bits_lane2_low[0x20];
2775 
2776 	u8         phy_corrected_bits_lane3_high[0x20];
2777 
2778 	u8         phy_corrected_bits_lane3_low[0x20];
2779 
2780 	u8         reserved_at_200[0x5c0];
2781 };
2782 
2783 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2784 	u8	   symbol_error_counter[0x10];
2785 
2786 	u8         link_error_recovery_counter[0x8];
2787 
2788 	u8         link_downed_counter[0x8];
2789 
2790 	u8         port_rcv_errors[0x10];
2791 
2792 	u8         port_rcv_remote_physical_errors[0x10];
2793 
2794 	u8         port_rcv_switch_relay_errors[0x10];
2795 
2796 	u8         port_xmit_discards[0x10];
2797 
2798 	u8         port_xmit_constraint_errors[0x8];
2799 
2800 	u8         port_rcv_constraint_errors[0x8];
2801 
2802 	u8         reserved_at_70[0x8];
2803 
2804 	u8         link_overrun_errors[0x8];
2805 
2806 	u8	   reserved_at_80[0x10];
2807 
2808 	u8         vl_15_dropped[0x10];
2809 
2810 	u8	   reserved_at_a0[0x80];
2811 
2812 	u8         port_xmit_wait[0x20];
2813 };
2814 
2815 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
2816 	u8         reserved_at_0[0x300];
2817 
2818 	u8         port_xmit_data_high[0x20];
2819 
2820 	u8         port_xmit_data_low[0x20];
2821 
2822 	u8         port_rcv_data_high[0x20];
2823 
2824 	u8         port_rcv_data_low[0x20];
2825 
2826 	u8         port_xmit_pkts_high[0x20];
2827 
2828 	u8         port_xmit_pkts_low[0x20];
2829 
2830 	u8         port_rcv_pkts_high[0x20];
2831 
2832 	u8         port_rcv_pkts_low[0x20];
2833 
2834 	u8         reserved_at_400[0x80];
2835 
2836 	u8         port_unicast_xmit_pkts_high[0x20];
2837 
2838 	u8         port_unicast_xmit_pkts_low[0x20];
2839 
2840 	u8         port_multicast_xmit_pkts_high[0x20];
2841 
2842 	u8         port_multicast_xmit_pkts_low[0x20];
2843 
2844 	u8         port_unicast_rcv_pkts_high[0x20];
2845 
2846 	u8         port_unicast_rcv_pkts_low[0x20];
2847 
2848 	u8         port_multicast_rcv_pkts_high[0x20];
2849 
2850 	u8         port_multicast_rcv_pkts_low[0x20];
2851 
2852 	u8         reserved_at_580[0x240];
2853 };
2854 
2855 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2856 	u8         transmit_queue_high[0x20];
2857 
2858 	u8         transmit_queue_low[0x20];
2859 
2860 	u8         no_buffer_discard_uc_high[0x20];
2861 
2862 	u8         no_buffer_discard_uc_low[0x20];
2863 
2864 	u8         reserved_at_80[0x740];
2865 };
2866 
2867 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2868 	u8         wred_discard_high[0x20];
2869 
2870 	u8         wred_discard_low[0x20];
2871 
2872 	u8         ecn_marked_tc_high[0x20];
2873 
2874 	u8         ecn_marked_tc_low[0x20];
2875 
2876 	u8         reserved_at_80[0x740];
2877 };
2878 
2879 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2880 	u8         rx_octets_high[0x20];
2881 
2882 	u8         rx_octets_low[0x20];
2883 
2884 	u8         reserved_at_40[0xc0];
2885 
2886 	u8         rx_frames_high[0x20];
2887 
2888 	u8         rx_frames_low[0x20];
2889 
2890 	u8         tx_octets_high[0x20];
2891 
2892 	u8         tx_octets_low[0x20];
2893 
2894 	u8         reserved_at_180[0xc0];
2895 
2896 	u8         tx_frames_high[0x20];
2897 
2898 	u8         tx_frames_low[0x20];
2899 
2900 	u8         rx_pause_high[0x20];
2901 
2902 	u8         rx_pause_low[0x20];
2903 
2904 	u8         rx_pause_duration_high[0x20];
2905 
2906 	u8         rx_pause_duration_low[0x20];
2907 
2908 	u8         tx_pause_high[0x20];
2909 
2910 	u8         tx_pause_low[0x20];
2911 
2912 	u8         tx_pause_duration_high[0x20];
2913 
2914 	u8         tx_pause_duration_low[0x20];
2915 
2916 	u8         rx_pause_transition_high[0x20];
2917 
2918 	u8         rx_pause_transition_low[0x20];
2919 
2920 	u8         rx_discards_high[0x20];
2921 
2922 	u8         rx_discards_low[0x20];
2923 
2924 	u8         device_stall_minor_watermark_cnt_high[0x20];
2925 
2926 	u8         device_stall_minor_watermark_cnt_low[0x20];
2927 
2928 	u8         device_stall_critical_watermark_cnt_high[0x20];
2929 
2930 	u8         device_stall_critical_watermark_cnt_low[0x20];
2931 
2932 	u8         reserved_at_480[0x340];
2933 };
2934 
2935 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2936 	u8         port_transmit_wait_high[0x20];
2937 
2938 	u8         port_transmit_wait_low[0x20];
2939 
2940 	u8         reserved_at_40[0x100];
2941 
2942 	u8         rx_buffer_almost_full_high[0x20];
2943 
2944 	u8         rx_buffer_almost_full_low[0x20];
2945 
2946 	u8         rx_buffer_full_high[0x20];
2947 
2948 	u8         rx_buffer_full_low[0x20];
2949 
2950 	u8         rx_icrc_encapsulated_high[0x20];
2951 
2952 	u8         rx_icrc_encapsulated_low[0x20];
2953 
2954 	u8         reserved_at_200[0x5c0];
2955 };
2956 
2957 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2958 	u8         dot3stats_alignment_errors_high[0x20];
2959 
2960 	u8         dot3stats_alignment_errors_low[0x20];
2961 
2962 	u8         dot3stats_fcs_errors_high[0x20];
2963 
2964 	u8         dot3stats_fcs_errors_low[0x20];
2965 
2966 	u8         dot3stats_single_collision_frames_high[0x20];
2967 
2968 	u8         dot3stats_single_collision_frames_low[0x20];
2969 
2970 	u8         dot3stats_multiple_collision_frames_high[0x20];
2971 
2972 	u8         dot3stats_multiple_collision_frames_low[0x20];
2973 
2974 	u8         dot3stats_sqe_test_errors_high[0x20];
2975 
2976 	u8         dot3stats_sqe_test_errors_low[0x20];
2977 
2978 	u8         dot3stats_deferred_transmissions_high[0x20];
2979 
2980 	u8         dot3stats_deferred_transmissions_low[0x20];
2981 
2982 	u8         dot3stats_late_collisions_high[0x20];
2983 
2984 	u8         dot3stats_late_collisions_low[0x20];
2985 
2986 	u8         dot3stats_excessive_collisions_high[0x20];
2987 
2988 	u8         dot3stats_excessive_collisions_low[0x20];
2989 
2990 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2991 
2992 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2993 
2994 	u8         dot3stats_carrier_sense_errors_high[0x20];
2995 
2996 	u8         dot3stats_carrier_sense_errors_low[0x20];
2997 
2998 	u8         dot3stats_frame_too_longs_high[0x20];
2999 
3000 	u8         dot3stats_frame_too_longs_low[0x20];
3001 
3002 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
3003 
3004 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
3005 
3006 	u8         dot3stats_symbol_errors_high[0x20];
3007 
3008 	u8         dot3stats_symbol_errors_low[0x20];
3009 
3010 	u8         dot3control_in_unknown_opcodes_high[0x20];
3011 
3012 	u8         dot3control_in_unknown_opcodes_low[0x20];
3013 
3014 	u8         dot3in_pause_frames_high[0x20];
3015 
3016 	u8         dot3in_pause_frames_low[0x20];
3017 
3018 	u8         dot3out_pause_frames_high[0x20];
3019 
3020 	u8         dot3out_pause_frames_low[0x20];
3021 
3022 	u8         reserved_at_400[0x3c0];
3023 };
3024 
3025 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
3026 	u8         ether_stats_drop_events_high[0x20];
3027 
3028 	u8         ether_stats_drop_events_low[0x20];
3029 
3030 	u8         ether_stats_octets_high[0x20];
3031 
3032 	u8         ether_stats_octets_low[0x20];
3033 
3034 	u8         ether_stats_pkts_high[0x20];
3035 
3036 	u8         ether_stats_pkts_low[0x20];
3037 
3038 	u8         ether_stats_broadcast_pkts_high[0x20];
3039 
3040 	u8         ether_stats_broadcast_pkts_low[0x20];
3041 
3042 	u8         ether_stats_multicast_pkts_high[0x20];
3043 
3044 	u8         ether_stats_multicast_pkts_low[0x20];
3045 
3046 	u8         ether_stats_crc_align_errors_high[0x20];
3047 
3048 	u8         ether_stats_crc_align_errors_low[0x20];
3049 
3050 	u8         ether_stats_undersize_pkts_high[0x20];
3051 
3052 	u8         ether_stats_undersize_pkts_low[0x20];
3053 
3054 	u8         ether_stats_oversize_pkts_high[0x20];
3055 
3056 	u8         ether_stats_oversize_pkts_low[0x20];
3057 
3058 	u8         ether_stats_fragments_high[0x20];
3059 
3060 	u8         ether_stats_fragments_low[0x20];
3061 
3062 	u8         ether_stats_jabbers_high[0x20];
3063 
3064 	u8         ether_stats_jabbers_low[0x20];
3065 
3066 	u8         ether_stats_collisions_high[0x20];
3067 
3068 	u8         ether_stats_collisions_low[0x20];
3069 
3070 	u8         ether_stats_pkts64octets_high[0x20];
3071 
3072 	u8         ether_stats_pkts64octets_low[0x20];
3073 
3074 	u8         ether_stats_pkts65to127octets_high[0x20];
3075 
3076 	u8         ether_stats_pkts65to127octets_low[0x20];
3077 
3078 	u8         ether_stats_pkts128to255octets_high[0x20];
3079 
3080 	u8         ether_stats_pkts128to255octets_low[0x20];
3081 
3082 	u8         ether_stats_pkts256to511octets_high[0x20];
3083 
3084 	u8         ether_stats_pkts256to511octets_low[0x20];
3085 
3086 	u8         ether_stats_pkts512to1023octets_high[0x20];
3087 
3088 	u8         ether_stats_pkts512to1023octets_low[0x20];
3089 
3090 	u8         ether_stats_pkts1024to1518octets_high[0x20];
3091 
3092 	u8         ether_stats_pkts1024to1518octets_low[0x20];
3093 
3094 	u8         ether_stats_pkts1519to2047octets_high[0x20];
3095 
3096 	u8         ether_stats_pkts1519to2047octets_low[0x20];
3097 
3098 	u8         ether_stats_pkts2048to4095octets_high[0x20];
3099 
3100 	u8         ether_stats_pkts2048to4095octets_low[0x20];
3101 
3102 	u8         ether_stats_pkts4096to8191octets_high[0x20];
3103 
3104 	u8         ether_stats_pkts4096to8191octets_low[0x20];
3105 
3106 	u8         ether_stats_pkts8192to10239octets_high[0x20];
3107 
3108 	u8         ether_stats_pkts8192to10239octets_low[0x20];
3109 
3110 	u8         reserved_at_540[0x280];
3111 };
3112 
3113 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
3114 	u8         if_in_octets_high[0x20];
3115 
3116 	u8         if_in_octets_low[0x20];
3117 
3118 	u8         if_in_ucast_pkts_high[0x20];
3119 
3120 	u8         if_in_ucast_pkts_low[0x20];
3121 
3122 	u8         if_in_discards_high[0x20];
3123 
3124 	u8         if_in_discards_low[0x20];
3125 
3126 	u8         if_in_errors_high[0x20];
3127 
3128 	u8         if_in_errors_low[0x20];
3129 
3130 	u8         if_in_unknown_protos_high[0x20];
3131 
3132 	u8         if_in_unknown_protos_low[0x20];
3133 
3134 	u8         if_out_octets_high[0x20];
3135 
3136 	u8         if_out_octets_low[0x20];
3137 
3138 	u8         if_out_ucast_pkts_high[0x20];
3139 
3140 	u8         if_out_ucast_pkts_low[0x20];
3141 
3142 	u8         if_out_discards_high[0x20];
3143 
3144 	u8         if_out_discards_low[0x20];
3145 
3146 	u8         if_out_errors_high[0x20];
3147 
3148 	u8         if_out_errors_low[0x20];
3149 
3150 	u8         if_in_multicast_pkts_high[0x20];
3151 
3152 	u8         if_in_multicast_pkts_low[0x20];
3153 
3154 	u8         if_in_broadcast_pkts_high[0x20];
3155 
3156 	u8         if_in_broadcast_pkts_low[0x20];
3157 
3158 	u8         if_out_multicast_pkts_high[0x20];
3159 
3160 	u8         if_out_multicast_pkts_low[0x20];
3161 
3162 	u8         if_out_broadcast_pkts_high[0x20];
3163 
3164 	u8         if_out_broadcast_pkts_low[0x20];
3165 
3166 	u8         reserved_at_340[0x480];
3167 };
3168 
3169 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
3170 	u8         a_frames_transmitted_ok_high[0x20];
3171 
3172 	u8         a_frames_transmitted_ok_low[0x20];
3173 
3174 	u8         a_frames_received_ok_high[0x20];
3175 
3176 	u8         a_frames_received_ok_low[0x20];
3177 
3178 	u8         a_frame_check_sequence_errors_high[0x20];
3179 
3180 	u8         a_frame_check_sequence_errors_low[0x20];
3181 
3182 	u8         a_alignment_errors_high[0x20];
3183 
3184 	u8         a_alignment_errors_low[0x20];
3185 
3186 	u8         a_octets_transmitted_ok_high[0x20];
3187 
3188 	u8         a_octets_transmitted_ok_low[0x20];
3189 
3190 	u8         a_octets_received_ok_high[0x20];
3191 
3192 	u8         a_octets_received_ok_low[0x20];
3193 
3194 	u8         a_multicast_frames_xmitted_ok_high[0x20];
3195 
3196 	u8         a_multicast_frames_xmitted_ok_low[0x20];
3197 
3198 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
3199 
3200 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
3201 
3202 	u8         a_multicast_frames_received_ok_high[0x20];
3203 
3204 	u8         a_multicast_frames_received_ok_low[0x20];
3205 
3206 	u8         a_broadcast_frames_received_ok_high[0x20];
3207 
3208 	u8         a_broadcast_frames_received_ok_low[0x20];
3209 
3210 	u8         a_in_range_length_errors_high[0x20];
3211 
3212 	u8         a_in_range_length_errors_low[0x20];
3213 
3214 	u8         a_out_of_range_length_field_high[0x20];
3215 
3216 	u8         a_out_of_range_length_field_low[0x20];
3217 
3218 	u8         a_frame_too_long_errors_high[0x20];
3219 
3220 	u8         a_frame_too_long_errors_low[0x20];
3221 
3222 	u8         a_symbol_error_during_carrier_high[0x20];
3223 
3224 	u8         a_symbol_error_during_carrier_low[0x20];
3225 
3226 	u8         a_mac_control_frames_transmitted_high[0x20];
3227 
3228 	u8         a_mac_control_frames_transmitted_low[0x20];
3229 
3230 	u8         a_mac_control_frames_received_high[0x20];
3231 
3232 	u8         a_mac_control_frames_received_low[0x20];
3233 
3234 	u8         a_unsupported_opcodes_received_high[0x20];
3235 
3236 	u8         a_unsupported_opcodes_received_low[0x20];
3237 
3238 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
3239 
3240 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
3241 
3242 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3243 
3244 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3245 
3246 	u8         reserved_at_4c0[0x300];
3247 };
3248 
3249 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3250 	u8         life_time_counter_high[0x20];
3251 
3252 	u8         life_time_counter_low[0x20];
3253 
3254 	u8         rx_errors[0x20];
3255 
3256 	u8         tx_errors[0x20];
3257 
3258 	u8         l0_to_recovery_eieos[0x20];
3259 
3260 	u8         l0_to_recovery_ts[0x20];
3261 
3262 	u8         l0_to_recovery_framing[0x20];
3263 
3264 	u8         l0_to_recovery_retrain[0x20];
3265 
3266 	u8         crc_error_dllp[0x20];
3267 
3268 	u8         crc_error_tlp[0x20];
3269 
3270 	u8         tx_overflow_buffer_pkt_high[0x20];
3271 
3272 	u8         tx_overflow_buffer_pkt_low[0x20];
3273 
3274 	u8         outbound_stalled_reads[0x20];
3275 
3276 	u8         outbound_stalled_writes[0x20];
3277 
3278 	u8         outbound_stalled_reads_events[0x20];
3279 
3280 	u8         outbound_stalled_writes_events[0x20];
3281 
3282 	u8         reserved_at_200[0x5c0];
3283 };
3284 
3285 struct mlx5_ifc_cmd_inter_comp_event_bits {
3286 	u8         command_completion_vector[0x20];
3287 
3288 	u8         reserved_at_20[0xc0];
3289 };
3290 
3291 struct mlx5_ifc_stall_vl_event_bits {
3292 	u8         reserved_at_0[0x18];
3293 	u8         port_num[0x1];
3294 	u8         reserved_at_19[0x3];
3295 	u8         vl[0x4];
3296 
3297 	u8         reserved_at_20[0xa0];
3298 };
3299 
3300 struct mlx5_ifc_db_bf_congestion_event_bits {
3301 	u8         event_subtype[0x8];
3302 	u8         reserved_at_8[0x8];
3303 	u8         congestion_level[0x8];
3304 	u8         reserved_at_18[0x8];
3305 
3306 	u8         reserved_at_20[0xa0];
3307 };
3308 
3309 struct mlx5_ifc_gpio_event_bits {
3310 	u8         reserved_at_0[0x60];
3311 
3312 	u8         gpio_event_hi[0x20];
3313 
3314 	u8         gpio_event_lo[0x20];
3315 
3316 	u8         reserved_at_a0[0x40];
3317 };
3318 
3319 struct mlx5_ifc_port_state_change_event_bits {
3320 	u8         reserved_at_0[0x40];
3321 
3322 	u8         port_num[0x4];
3323 	u8         reserved_at_44[0x1c];
3324 
3325 	u8         reserved_at_60[0x80];
3326 };
3327 
3328 struct mlx5_ifc_dropped_packet_logged_bits {
3329 	u8         reserved_at_0[0xe0];
3330 };
3331 
3332 struct mlx5_ifc_nic_cap_reg_bits {
3333 	u8	   reserved_at_0[0x1a];
3334 	u8	   vhca_icm_ctrl[0x1];
3335 	u8	   reserved_at_1b[0x5];
3336 
3337 	u8	   reserved_at_20[0x60];
3338 };
3339 
3340 struct mlx5_ifc_default_timeout_bits {
3341 	u8         to_multiplier[0x3];
3342 	u8         reserved_at_3[0x9];
3343 	u8         to_value[0x14];
3344 };
3345 
3346 struct mlx5_ifc_dtor_reg_bits {
3347 	u8         reserved_at_0[0x20];
3348 
3349 	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3350 
3351 	u8         reserved_at_40[0x60];
3352 
3353 	struct mlx5_ifc_default_timeout_bits health_poll_to;
3354 
3355 	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3356 
3357 	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3358 
3359 	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3360 
3361 	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3362 
3363 	struct mlx5_ifc_default_timeout_bits tear_down_to;
3364 
3365 	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3366 
3367 	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3368 
3369 	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3370 
3371 	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3372 
3373 	u8         reserved_at_1c0[0x20];
3374 };
3375 
3376 struct mlx5_ifc_vhca_icm_ctrl_reg_bits {
3377 	u8	   vhca_id_valid[0x1];
3378 	u8	   reserved_at_1[0xf];
3379 	u8	   vhca_id[0x10];
3380 
3381 	u8	   reserved_at_20[0xa0];
3382 
3383 	u8	   cur_alloc_icm[0x20];
3384 
3385 	u8	   reserved_at_e0[0x120];
3386 };
3387 
3388 enum {
3389 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3390 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3391 };
3392 
3393 struct mlx5_ifc_cq_error_bits {
3394 	u8         reserved_at_0[0x8];
3395 	u8         cqn[0x18];
3396 
3397 	u8         reserved_at_20[0x20];
3398 
3399 	u8         reserved_at_40[0x18];
3400 	u8         syndrome[0x8];
3401 
3402 	u8         reserved_at_60[0x80];
3403 };
3404 
3405 struct mlx5_ifc_rdma_page_fault_event_bits {
3406 	u8         bytes_committed[0x20];
3407 
3408 	u8         r_key[0x20];
3409 
3410 	u8         reserved_at_40[0x10];
3411 	u8         packet_len[0x10];
3412 
3413 	u8         rdma_op_len[0x20];
3414 
3415 	u8         rdma_va[0x40];
3416 
3417 	u8         reserved_at_c0[0x5];
3418 	u8         rdma[0x1];
3419 	u8         write[0x1];
3420 	u8         requestor[0x1];
3421 	u8         qp_number[0x18];
3422 };
3423 
3424 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3425 	u8         bytes_committed[0x20];
3426 
3427 	u8         reserved_at_20[0x10];
3428 	u8         wqe_index[0x10];
3429 
3430 	u8         reserved_at_40[0x10];
3431 	u8         len[0x10];
3432 
3433 	u8         reserved_at_60[0x60];
3434 
3435 	u8         reserved_at_c0[0x5];
3436 	u8         rdma[0x1];
3437 	u8         write_read[0x1];
3438 	u8         requestor[0x1];
3439 	u8         qpn[0x18];
3440 };
3441 
3442 struct mlx5_ifc_qp_events_bits {
3443 	u8         reserved_at_0[0xa0];
3444 
3445 	u8         type[0x8];
3446 	u8         reserved_at_a8[0x18];
3447 
3448 	u8         reserved_at_c0[0x8];
3449 	u8         qpn_rqn_sqn[0x18];
3450 };
3451 
3452 struct mlx5_ifc_dct_events_bits {
3453 	u8         reserved_at_0[0xc0];
3454 
3455 	u8         reserved_at_c0[0x8];
3456 	u8         dct_number[0x18];
3457 };
3458 
3459 struct mlx5_ifc_comp_event_bits {
3460 	u8         reserved_at_0[0xc0];
3461 
3462 	u8         reserved_at_c0[0x8];
3463 	u8         cq_number[0x18];
3464 };
3465 
3466 enum {
3467 	MLX5_QPC_STATE_RST        = 0x0,
3468 	MLX5_QPC_STATE_INIT       = 0x1,
3469 	MLX5_QPC_STATE_RTR        = 0x2,
3470 	MLX5_QPC_STATE_RTS        = 0x3,
3471 	MLX5_QPC_STATE_SQER       = 0x4,
3472 	MLX5_QPC_STATE_ERR        = 0x6,
3473 	MLX5_QPC_STATE_SQD        = 0x7,
3474 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3475 };
3476 
3477 enum {
3478 	MLX5_QPC_ST_RC            = 0x0,
3479 	MLX5_QPC_ST_UC            = 0x1,
3480 	MLX5_QPC_ST_UD            = 0x2,
3481 	MLX5_QPC_ST_XRC           = 0x3,
3482 	MLX5_QPC_ST_DCI           = 0x5,
3483 	MLX5_QPC_ST_QP0           = 0x7,
3484 	MLX5_QPC_ST_QP1           = 0x8,
3485 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3486 	MLX5_QPC_ST_REG_UMR       = 0xc,
3487 };
3488 
3489 enum {
3490 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3491 	MLX5_QPC_PM_STATE_REARM     = 0x1,
3492 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3493 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3494 };
3495 
3496 enum {
3497 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3498 };
3499 
3500 enum {
3501 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3502 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3503 };
3504 
3505 enum {
3506 	MLX5_QPC_MTU_256_BYTES        = 0x1,
3507 	MLX5_QPC_MTU_512_BYTES        = 0x2,
3508 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3509 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3510 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3511 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3512 };
3513 
3514 enum {
3515 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3516 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3517 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3518 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3519 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3520 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3521 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3522 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3523 };
3524 
3525 enum {
3526 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3527 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3528 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3529 };
3530 
3531 enum {
3532 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3533 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3534 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3535 };
3536 
3537 enum {
3538 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3539 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3540 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3541 };
3542 
3543 struct mlx5_ifc_qpc_bits {
3544 	u8         state[0x4];
3545 	u8         lag_tx_port_affinity[0x4];
3546 	u8         st[0x8];
3547 	u8         reserved_at_10[0x2];
3548 	u8	   isolate_vl_tc[0x1];
3549 	u8         pm_state[0x2];
3550 	u8         reserved_at_15[0x1];
3551 	u8         req_e2e_credit_mode[0x2];
3552 	u8         offload_type[0x4];
3553 	u8         end_padding_mode[0x2];
3554 	u8         reserved_at_1e[0x2];
3555 
3556 	u8         wq_signature[0x1];
3557 	u8         block_lb_mc[0x1];
3558 	u8         atomic_like_write_en[0x1];
3559 	u8         latency_sensitive[0x1];
3560 	u8         reserved_at_24[0x1];
3561 	u8         drain_sigerr[0x1];
3562 	u8         reserved_at_26[0x1];
3563 	u8         dp_ordering_force[0x1];
3564 	u8         pd[0x18];
3565 
3566 	u8         mtu[0x3];
3567 	u8         log_msg_max[0x5];
3568 	u8         reserved_at_48[0x1];
3569 	u8         log_rq_size[0x4];
3570 	u8         log_rq_stride[0x3];
3571 	u8         no_sq[0x1];
3572 	u8         log_sq_size[0x4];
3573 	u8         reserved_at_55[0x1];
3574 	u8	   retry_mode[0x2];
3575 	u8	   ts_format[0x2];
3576 	u8         reserved_at_5a[0x1];
3577 	u8         rlky[0x1];
3578 	u8         ulp_stateless_offload_mode[0x4];
3579 
3580 	u8         counter_set_id[0x8];
3581 	u8         uar_page[0x18];
3582 
3583 	u8         reserved_at_80[0x8];
3584 	u8         user_index[0x18];
3585 
3586 	u8         reserved_at_a0[0x3];
3587 	u8         log_page_size[0x5];
3588 	u8         remote_qpn[0x18];
3589 
3590 	struct mlx5_ifc_ads_bits primary_address_path;
3591 
3592 	struct mlx5_ifc_ads_bits secondary_address_path;
3593 
3594 	u8         log_ack_req_freq[0x4];
3595 	u8         reserved_at_384[0x4];
3596 	u8         log_sra_max[0x3];
3597 	u8         reserved_at_38b[0x2];
3598 	u8         retry_count[0x3];
3599 	u8         rnr_retry[0x3];
3600 	u8         reserved_at_393[0x1];
3601 	u8         fre[0x1];
3602 	u8         cur_rnr_retry[0x3];
3603 	u8         cur_retry_count[0x3];
3604 	u8         reserved_at_39b[0x5];
3605 
3606 	u8         reserved_at_3a0[0x20];
3607 
3608 	u8         reserved_at_3c0[0x8];
3609 	u8         next_send_psn[0x18];
3610 
3611 	u8         reserved_at_3e0[0x3];
3612 	u8	   log_num_dci_stream_channels[0x5];
3613 	u8         cqn_snd[0x18];
3614 
3615 	u8         reserved_at_400[0x3];
3616 	u8	   log_num_dci_errored_streams[0x5];
3617 	u8         deth_sqpn[0x18];
3618 
3619 	u8         reserved_at_420[0x20];
3620 
3621 	u8         reserved_at_440[0x8];
3622 	u8         last_acked_psn[0x18];
3623 
3624 	u8         reserved_at_460[0x8];
3625 	u8         ssn[0x18];
3626 
3627 	u8         reserved_at_480[0x8];
3628 	u8         log_rra_max[0x3];
3629 	u8         reserved_at_48b[0x1];
3630 	u8         atomic_mode[0x4];
3631 	u8         rre[0x1];
3632 	u8         rwe[0x1];
3633 	u8         rae[0x1];
3634 	u8         reserved_at_493[0x1];
3635 	u8         page_offset[0x6];
3636 	u8         reserved_at_49a[0x2];
3637 	u8         dp_ordering_1[0x1];
3638 	u8         cd_slave_receive[0x1];
3639 	u8         cd_slave_send[0x1];
3640 	u8         cd_master[0x1];
3641 
3642 	u8         reserved_at_4a0[0x3];
3643 	u8         min_rnr_nak[0x5];
3644 	u8         next_rcv_psn[0x18];
3645 
3646 	u8         reserved_at_4c0[0x8];
3647 	u8         xrcd[0x18];
3648 
3649 	u8         reserved_at_4e0[0x8];
3650 	u8         cqn_rcv[0x18];
3651 
3652 	u8         dbr_addr[0x40];
3653 
3654 	u8         q_key[0x20];
3655 
3656 	u8         reserved_at_560[0x5];
3657 	u8         rq_type[0x3];
3658 	u8         srqn_rmpn_xrqn[0x18];
3659 
3660 	u8         reserved_at_580[0x8];
3661 	u8         rmsn[0x18];
3662 
3663 	u8         hw_sq_wqebb_counter[0x10];
3664 	u8         sw_sq_wqebb_counter[0x10];
3665 
3666 	u8         hw_rq_counter[0x20];
3667 
3668 	u8         sw_rq_counter[0x20];
3669 
3670 	u8         reserved_at_600[0x20];
3671 
3672 	u8         reserved_at_620[0xf];
3673 	u8         cgs[0x1];
3674 	u8         cs_req[0x8];
3675 	u8         cs_res[0x8];
3676 
3677 	u8         dc_access_key[0x40];
3678 
3679 	u8         reserved_at_680[0x3];
3680 	u8         dbr_umem_valid[0x1];
3681 
3682 	u8         reserved_at_684[0xbc];
3683 };
3684 
3685 struct mlx5_ifc_roce_addr_layout_bits {
3686 	u8         source_l3_address[16][0x8];
3687 
3688 	u8         reserved_at_80[0x3];
3689 	u8         vlan_valid[0x1];
3690 	u8         vlan_id[0xc];
3691 	u8         source_mac_47_32[0x10];
3692 
3693 	u8         source_mac_31_0[0x20];
3694 
3695 	u8         reserved_at_c0[0x14];
3696 	u8         roce_l3_type[0x4];
3697 	u8         roce_version[0x8];
3698 
3699 	u8         reserved_at_e0[0x20];
3700 };
3701 
3702 struct mlx5_ifc_crypto_cap_bits {
3703 	u8    reserved_at_0[0x3];
3704 	u8    synchronize_dek[0x1];
3705 	u8    int_kek_manual[0x1];
3706 	u8    int_kek_auto[0x1];
3707 	u8    reserved_at_6[0x1a];
3708 
3709 	u8    reserved_at_20[0x3];
3710 	u8    log_dek_max_alloc[0x5];
3711 	u8    reserved_at_28[0x3];
3712 	u8    log_max_num_deks[0x5];
3713 	u8    reserved_at_30[0x10];
3714 
3715 	u8    reserved_at_40[0x20];
3716 
3717 	u8    reserved_at_60[0x3];
3718 	u8    log_dek_granularity[0x5];
3719 	u8    reserved_at_68[0x3];
3720 	u8    log_max_num_int_kek[0x5];
3721 	u8    sw_wrapped_dek[0x10];
3722 
3723 	u8    reserved_at_80[0x780];
3724 };
3725 
3726 struct mlx5_ifc_shampo_cap_bits {
3727 	u8    reserved_at_0[0x3];
3728 	u8    shampo_log_max_reservation_size[0x5];
3729 	u8    reserved_at_8[0x3];
3730 	u8    shampo_log_min_reservation_size[0x5];
3731 	u8    shampo_min_mss_size[0x10];
3732 
3733 	u8    shampo_header_split[0x1];
3734 	u8    shampo_header_split_data_merge[0x1];
3735 	u8    reserved_at_22[0x1];
3736 	u8    shampo_log_max_headers_entry_size[0x5];
3737 	u8    reserved_at_28[0x18];
3738 
3739 	u8    reserved_at_40[0x7c0];
3740 };
3741 
3742 union mlx5_ifc_hca_cap_union_bits {
3743 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3744 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3745 	struct mlx5_ifc_odp_cap_bits odp_cap;
3746 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3747 	struct mlx5_ifc_roce_cap_bits roce_cap;
3748 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3749 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3750 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3751 	struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
3752 	struct mlx5_ifc_esw_cap_bits esw_cap;
3753 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3754 	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3755 	struct mlx5_ifc_qos_cap_bits qos_cap;
3756 	struct mlx5_ifc_debug_cap_bits debug_cap;
3757 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3758 	struct mlx5_ifc_tls_cap_bits tls_cap;
3759 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3760 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3761 	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3762 	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3763 	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3764 	u8         reserved_at_0[0x8000];
3765 };
3766 
3767 enum {
3768 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3769 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3770 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3771 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3772 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3773 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3774 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3775 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3776 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3777 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3778 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3779 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3780 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3781 	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3782 };
3783 
3784 enum {
3785 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3786 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3787 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3788 };
3789 
3790 enum {
3791 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3792 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3793 };
3794 
3795 struct mlx5_ifc_vlan_bits {
3796 	u8         ethtype[0x10];
3797 	u8         prio[0x3];
3798 	u8         cfi[0x1];
3799 	u8         vid[0xc];
3800 };
3801 
3802 enum {
3803 	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3804 	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3805 	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3806 	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3807 };
3808 
3809 enum {
3810 	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3811 };
3812 
3813 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3814 	u8        return_reg_id[0x4];
3815 	u8        aso_type[0x4];
3816 	u8        reserved_at_8[0x14];
3817 	u8        action[0x1];
3818 	u8        init_color[0x2];
3819 	u8        meter_id[0x1];
3820 };
3821 
3822 union mlx5_ifc_exe_aso_ctrl {
3823 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3824 };
3825 
3826 struct mlx5_ifc_execute_aso_bits {
3827 	u8        valid[0x1];
3828 	u8        reserved_at_1[0x7];
3829 	u8        aso_object_id[0x18];
3830 
3831 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3832 };
3833 
3834 struct mlx5_ifc_flow_context_bits {
3835 	struct mlx5_ifc_vlan_bits push_vlan;
3836 
3837 	u8         group_id[0x20];
3838 
3839 	u8         reserved_at_40[0x8];
3840 	u8         flow_tag[0x18];
3841 
3842 	u8         reserved_at_60[0x10];
3843 	u8         action[0x10];
3844 
3845 	u8         extended_destination[0x1];
3846 	u8         uplink_hairpin_en[0x1];
3847 	u8         flow_source[0x2];
3848 	u8         encrypt_decrypt_type[0x4];
3849 	u8         destination_list_size[0x18];
3850 
3851 	u8         reserved_at_a0[0x8];
3852 	u8         flow_counter_list_size[0x18];
3853 
3854 	u8         packet_reformat_id[0x20];
3855 
3856 	u8         modify_header_id[0x20];
3857 
3858 	struct mlx5_ifc_vlan_bits push_vlan_2;
3859 
3860 	u8         encrypt_decrypt_obj_id[0x20];
3861 	u8         reserved_at_140[0xc0];
3862 
3863 	struct mlx5_ifc_fte_match_param_bits match_value;
3864 
3865 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3866 
3867 	u8         reserved_at_1300[0x500];
3868 
3869 	union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[];
3870 };
3871 
3872 enum {
3873 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3874 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3875 };
3876 
3877 struct mlx5_ifc_xrc_srqc_bits {
3878 	u8         state[0x4];
3879 	u8         log_xrc_srq_size[0x4];
3880 	u8         reserved_at_8[0x18];
3881 
3882 	u8         wq_signature[0x1];
3883 	u8         cont_srq[0x1];
3884 	u8         reserved_at_22[0x1];
3885 	u8         rlky[0x1];
3886 	u8         basic_cyclic_rcv_wqe[0x1];
3887 	u8         log_rq_stride[0x3];
3888 	u8         xrcd[0x18];
3889 
3890 	u8         page_offset[0x6];
3891 	u8         reserved_at_46[0x1];
3892 	u8         dbr_umem_valid[0x1];
3893 	u8         cqn[0x18];
3894 
3895 	u8         reserved_at_60[0x20];
3896 
3897 	u8         user_index_equal_xrc_srqn[0x1];
3898 	u8         reserved_at_81[0x1];
3899 	u8         log_page_size[0x6];
3900 	u8         user_index[0x18];
3901 
3902 	u8         reserved_at_a0[0x20];
3903 
3904 	u8         reserved_at_c0[0x8];
3905 	u8         pd[0x18];
3906 
3907 	u8         lwm[0x10];
3908 	u8         wqe_cnt[0x10];
3909 
3910 	u8         reserved_at_100[0x40];
3911 
3912 	u8         db_record_addr_h[0x20];
3913 
3914 	u8         db_record_addr_l[0x1e];
3915 	u8         reserved_at_17e[0x2];
3916 
3917 	u8         reserved_at_180[0x80];
3918 };
3919 
3920 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3921 	u8         counter_error_queues[0x20];
3922 
3923 	u8         total_error_queues[0x20];
3924 
3925 	u8         send_queue_priority_update_flow[0x20];
3926 
3927 	u8         reserved_at_60[0x20];
3928 
3929 	u8         nic_receive_steering_discard[0x40];
3930 
3931 	u8         receive_discard_vport_down[0x40];
3932 
3933 	u8         transmit_discard_vport_down[0x40];
3934 
3935 	u8         async_eq_overrun[0x20];
3936 
3937 	u8         comp_eq_overrun[0x20];
3938 
3939 	u8         reserved_at_180[0x20];
3940 
3941 	u8         invalid_command[0x20];
3942 
3943 	u8         quota_exceeded_command[0x20];
3944 
3945 	u8         internal_rq_out_of_buffer[0x20];
3946 
3947 	u8         cq_overrun[0x20];
3948 
3949 	u8         eth_wqe_too_small[0x20];
3950 
3951 	u8         reserved_at_220[0xc0];
3952 
3953 	u8         generated_pkt_steering_fail[0x40];
3954 
3955 	u8         handled_pkt_steering_fail[0x40];
3956 
3957 	u8         reserved_at_360[0xc80];
3958 };
3959 
3960 struct mlx5_ifc_traffic_counter_bits {
3961 	u8         packets[0x40];
3962 
3963 	u8         octets[0x40];
3964 };
3965 
3966 struct mlx5_ifc_tisc_bits {
3967 	u8         strict_lag_tx_port_affinity[0x1];
3968 	u8         tls_en[0x1];
3969 	u8         reserved_at_2[0x2];
3970 	u8         lag_tx_port_affinity[0x04];
3971 
3972 	u8         reserved_at_8[0x4];
3973 	u8         prio[0x4];
3974 	u8         reserved_at_10[0x10];
3975 
3976 	u8         reserved_at_20[0x100];
3977 
3978 	u8         reserved_at_120[0x8];
3979 	u8         transport_domain[0x18];
3980 
3981 	u8         reserved_at_140[0x8];
3982 	u8         underlay_qpn[0x18];
3983 
3984 	u8         reserved_at_160[0x8];
3985 	u8         pd[0x18];
3986 
3987 	u8         reserved_at_180[0x380];
3988 };
3989 
3990 enum {
3991 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3992 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3993 };
3994 
3995 enum {
3996 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3997 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3998 };
3999 
4000 enum {
4001 	MLX5_RX_HASH_FN_NONE           = 0x0,
4002 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
4003 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
4004 };
4005 
4006 enum {
4007 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
4008 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
4009 };
4010 
4011 struct mlx5_ifc_tirc_bits {
4012 	u8         reserved_at_0[0x20];
4013 
4014 	u8         disp_type[0x4];
4015 	u8         tls_en[0x1];
4016 	u8         reserved_at_25[0x1b];
4017 
4018 	u8         reserved_at_40[0x40];
4019 
4020 	u8         reserved_at_80[0x4];
4021 	u8         lro_timeout_period_usecs[0x10];
4022 	u8         packet_merge_mask[0x4];
4023 	u8         lro_max_ip_payload_size[0x8];
4024 
4025 	u8         reserved_at_a0[0x40];
4026 
4027 	u8         reserved_at_e0[0x8];
4028 	u8         inline_rqn[0x18];
4029 
4030 	u8         rx_hash_symmetric[0x1];
4031 	u8         reserved_at_101[0x1];
4032 	u8         tunneled_offload_en[0x1];
4033 	u8         reserved_at_103[0x5];
4034 	u8         indirect_table[0x18];
4035 
4036 	u8         rx_hash_fn[0x4];
4037 	u8         reserved_at_124[0x2];
4038 	u8         self_lb_block[0x2];
4039 	u8         transport_domain[0x18];
4040 
4041 	u8         rx_hash_toeplitz_key[10][0x20];
4042 
4043 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
4044 
4045 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
4046 
4047 	u8         reserved_at_2c0[0x4c0];
4048 };
4049 
4050 enum {
4051 	MLX5_SRQC_STATE_GOOD   = 0x0,
4052 	MLX5_SRQC_STATE_ERROR  = 0x1,
4053 };
4054 
4055 struct mlx5_ifc_srqc_bits {
4056 	u8         state[0x4];
4057 	u8         log_srq_size[0x4];
4058 	u8         reserved_at_8[0x18];
4059 
4060 	u8         wq_signature[0x1];
4061 	u8         cont_srq[0x1];
4062 	u8         reserved_at_22[0x1];
4063 	u8         rlky[0x1];
4064 	u8         reserved_at_24[0x1];
4065 	u8         log_rq_stride[0x3];
4066 	u8         xrcd[0x18];
4067 
4068 	u8         page_offset[0x6];
4069 	u8         reserved_at_46[0x2];
4070 	u8         cqn[0x18];
4071 
4072 	u8         reserved_at_60[0x20];
4073 
4074 	u8         reserved_at_80[0x2];
4075 	u8         log_page_size[0x6];
4076 	u8         reserved_at_88[0x18];
4077 
4078 	u8         reserved_at_a0[0x20];
4079 
4080 	u8         reserved_at_c0[0x8];
4081 	u8         pd[0x18];
4082 
4083 	u8         lwm[0x10];
4084 	u8         wqe_cnt[0x10];
4085 
4086 	u8         reserved_at_100[0x40];
4087 
4088 	u8         dbr_addr[0x40];
4089 
4090 	u8         reserved_at_180[0x80];
4091 };
4092 
4093 enum {
4094 	MLX5_SQC_STATE_RST  = 0x0,
4095 	MLX5_SQC_STATE_RDY  = 0x1,
4096 	MLX5_SQC_STATE_ERR  = 0x3,
4097 };
4098 
4099 struct mlx5_ifc_sqc_bits {
4100 	u8         rlky[0x1];
4101 	u8         cd_master[0x1];
4102 	u8         fre[0x1];
4103 	u8         flush_in_error_en[0x1];
4104 	u8         allow_multi_pkt_send_wqe[0x1];
4105 	u8	   min_wqe_inline_mode[0x3];
4106 	u8         state[0x4];
4107 	u8         reg_umr[0x1];
4108 	u8         allow_swp[0x1];
4109 	u8         hairpin[0x1];
4110 	u8         non_wire[0x1];
4111 	u8         reserved_at_10[0xa];
4112 	u8	   ts_format[0x2];
4113 	u8	   reserved_at_1c[0x4];
4114 
4115 	u8         reserved_at_20[0x8];
4116 	u8         user_index[0x18];
4117 
4118 	u8         reserved_at_40[0x8];
4119 	u8         cqn[0x18];
4120 
4121 	u8         reserved_at_60[0x8];
4122 	u8         hairpin_peer_rq[0x18];
4123 
4124 	u8         reserved_at_80[0x10];
4125 	u8         hairpin_peer_vhca[0x10];
4126 
4127 	u8         reserved_at_a0[0x20];
4128 
4129 	u8         reserved_at_c0[0x8];
4130 	u8         ts_cqe_to_dest_cqn[0x18];
4131 
4132 	u8         reserved_at_e0[0x10];
4133 	u8         packet_pacing_rate_limit_index[0x10];
4134 	u8         tis_lst_sz[0x10];
4135 	u8         qos_queue_group_id[0x10];
4136 
4137 	u8         reserved_at_120[0x40];
4138 
4139 	u8         reserved_at_160[0x8];
4140 	u8         tis_num_0[0x18];
4141 
4142 	struct mlx5_ifc_wq_bits wq;
4143 };
4144 
4145 enum {
4146 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
4147 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
4148 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
4149 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
4150 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
4151 	SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5,
4152 };
4153 
4154 enum {
4155 	ELEMENT_TYPE_CAP_MASK_TSAR		= 1 << 0,
4156 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
4157 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
4158 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
4159 	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,
4160 	ELEMENT_TYPE_CAP_MASK_RATE_LIMIT	= 1 << 5,
4161 };
4162 
4163 enum {
4164 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4165 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4166 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4167 	TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3,
4168 };
4169 
4170 enum {
4171 	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,
4172 	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,
4173 	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,
4174 	TSAR_TYPE_CAP_MASK_TC_ARB       = 1 << 3,
4175 };
4176 
4177 struct mlx5_ifc_tsar_element_bits {
4178 	u8         traffic_class[0x4];
4179 	u8         reserved_at_4[0x4];
4180 	u8         tsar_type[0x8];
4181 	u8         reserved_at_10[0x10];
4182 };
4183 
4184 struct mlx5_ifc_vport_element_bits {
4185 	u8         reserved_at_0[0x4];
4186 	u8         eswitch_owner_vhca_id_valid[0x1];
4187 	u8         eswitch_owner_vhca_id[0xb];
4188 	u8         vport_number[0x10];
4189 };
4190 
4191 struct mlx5_ifc_vport_tc_element_bits {
4192 	u8         traffic_class[0x4];
4193 	u8         eswitch_owner_vhca_id_valid[0x1];
4194 	u8         eswitch_owner_vhca_id[0xb];
4195 	u8         vport_number[0x10];
4196 };
4197 
4198 union mlx5_ifc_element_attributes_bits {
4199 	struct mlx5_ifc_tsar_element_bits tsar;
4200 	struct mlx5_ifc_vport_element_bits vport;
4201 	struct mlx5_ifc_vport_tc_element_bits vport_tc;
4202 	u8 reserved_at_0[0x20];
4203 };
4204 
4205 struct mlx5_ifc_scheduling_context_bits {
4206 	u8         element_type[0x8];
4207 	u8         reserved_at_8[0x18];
4208 
4209 	union mlx5_ifc_element_attributes_bits element_attributes;
4210 
4211 	u8         parent_element_id[0x20];
4212 
4213 	u8         reserved_at_60[0x40];
4214 
4215 	u8         bw_share[0x20];
4216 
4217 	u8         max_average_bw[0x20];
4218 
4219 	u8         max_bw_obj_id[0x20];
4220 
4221 	u8         reserved_at_100[0x100];
4222 };
4223 
4224 struct mlx5_ifc_rqtc_bits {
4225 	u8    reserved_at_0[0xa0];
4226 
4227 	u8    reserved_at_a0[0x5];
4228 	u8    list_q_type[0x3];
4229 	u8    reserved_at_a8[0x8];
4230 	u8    rqt_max_size[0x10];
4231 
4232 	u8    rq_vhca_id_format[0x1];
4233 	u8    reserved_at_c1[0xf];
4234 	u8    rqt_actual_size[0x10];
4235 
4236 	u8    reserved_at_e0[0x6a0];
4237 
4238 	union {
4239 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
4240 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
4241 	};
4242 };
4243 
4244 enum {
4245 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
4246 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
4247 };
4248 
4249 enum {
4250 	MLX5_RQC_STATE_RST  = 0x0,
4251 	MLX5_RQC_STATE_RDY  = 0x1,
4252 	MLX5_RQC_STATE_ERR  = 0x3,
4253 };
4254 
4255 enum {
4256 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
4257 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
4258 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
4259 };
4260 
4261 enum {
4262 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
4263 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
4264 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
4265 };
4266 
4267 struct mlx5_ifc_rqc_bits {
4268 	u8         rlky[0x1];
4269 	u8	   delay_drop_en[0x1];
4270 	u8         scatter_fcs[0x1];
4271 	u8         vsd[0x1];
4272 	u8         mem_rq_type[0x4];
4273 	u8         state[0x4];
4274 	u8         reserved_at_c[0x1];
4275 	u8         flush_in_error_en[0x1];
4276 	u8         hairpin[0x1];
4277 	u8         reserved_at_f[0xb];
4278 	u8	   ts_format[0x2];
4279 	u8	   reserved_at_1c[0x4];
4280 
4281 	u8         reserved_at_20[0x8];
4282 	u8         user_index[0x18];
4283 
4284 	u8         reserved_at_40[0x8];
4285 	u8         cqn[0x18];
4286 
4287 	u8         counter_set_id[0x8];
4288 	u8         reserved_at_68[0x18];
4289 
4290 	u8         reserved_at_80[0x8];
4291 	u8         rmpn[0x18];
4292 
4293 	u8         reserved_at_a0[0x8];
4294 	u8         hairpin_peer_sq[0x18];
4295 
4296 	u8         reserved_at_c0[0x10];
4297 	u8         hairpin_peer_vhca[0x10];
4298 
4299 	u8         reserved_at_e0[0x46];
4300 	u8         shampo_no_match_alignment_granularity[0x2];
4301 	u8         reserved_at_128[0x6];
4302 	u8         shampo_match_criteria_type[0x2];
4303 	u8         reservation_timeout[0x10];
4304 
4305 	u8         reserved_at_140[0x40];
4306 
4307 	struct mlx5_ifc_wq_bits wq;
4308 };
4309 
4310 enum {
4311 	MLX5_RMPC_STATE_RDY  = 0x1,
4312 	MLX5_RMPC_STATE_ERR  = 0x3,
4313 };
4314 
4315 struct mlx5_ifc_rmpc_bits {
4316 	u8         reserved_at_0[0x8];
4317 	u8         state[0x4];
4318 	u8         reserved_at_c[0x14];
4319 
4320 	u8         basic_cyclic_rcv_wqe[0x1];
4321 	u8         reserved_at_21[0x1f];
4322 
4323 	u8         reserved_at_40[0x140];
4324 
4325 	struct mlx5_ifc_wq_bits wq;
4326 };
4327 
4328 enum {
4329 	VHCA_ID_TYPE_HW = 0,
4330 	VHCA_ID_TYPE_SW = 1,
4331 };
4332 
4333 struct mlx5_ifc_nic_vport_context_bits {
4334 	u8         reserved_at_0[0x5];
4335 	u8         min_wqe_inline_mode[0x3];
4336 	u8         reserved_at_8[0x15];
4337 	u8         disable_mc_local_lb[0x1];
4338 	u8         disable_uc_local_lb[0x1];
4339 	u8         roce_en[0x1];
4340 
4341 	u8         arm_change_event[0x1];
4342 	u8         reserved_at_21[0x1a];
4343 	u8         event_on_mtu[0x1];
4344 	u8         event_on_promisc_change[0x1];
4345 	u8         event_on_vlan_change[0x1];
4346 	u8         event_on_mc_address_change[0x1];
4347 	u8         event_on_uc_address_change[0x1];
4348 
4349 	u8         vhca_id_type[0x1];
4350 	u8         reserved_at_41[0xb];
4351 	u8	   affiliation_criteria[0x4];
4352 	u8	   affiliated_vhca_id[0x10];
4353 
4354 	u8	   reserved_at_60[0xa0];
4355 
4356 	u8	   reserved_at_100[0x1];
4357 	u8         sd_group[0x3];
4358 	u8	   reserved_at_104[0x1c];
4359 
4360 	u8	   reserved_at_120[0x10];
4361 	u8         mtu[0x10];
4362 
4363 	u8         system_image_guid[0x40];
4364 	u8         port_guid[0x40];
4365 	u8         node_guid[0x40];
4366 
4367 	u8         reserved_at_200[0x140];
4368 	u8         qkey_violation_counter[0x10];
4369 	u8         reserved_at_350[0x430];
4370 
4371 	u8         promisc_uc[0x1];
4372 	u8         promisc_mc[0x1];
4373 	u8         promisc_all[0x1];
4374 	u8         reserved_at_783[0x2];
4375 	u8         allowed_list_type[0x3];
4376 	u8         reserved_at_788[0xc];
4377 	u8         allowed_list_size[0xc];
4378 
4379 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4380 
4381 	u8         reserved_at_7e0[0x20];
4382 
4383 	u8         current_uc_mac_address[][0x40];
4384 };
4385 
4386 enum {
4387 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4388 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4389 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4390 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4391 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4392 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4393 	MLX5_MKC_ACCESS_MODE_CROSSING = 0x6,
4394 };
4395 
4396 struct mlx5_ifc_mkc_bits {
4397 	u8         reserved_at_0[0x1];
4398 	u8         free[0x1];
4399 	u8         reserved_at_2[0x1];
4400 	u8         access_mode_4_2[0x3];
4401 	u8         reserved_at_6[0x7];
4402 	u8         relaxed_ordering_write[0x1];
4403 	u8         reserved_at_e[0x1];
4404 	u8         small_fence_on_rdma_read_response[0x1];
4405 	u8         umr_en[0x1];
4406 	u8         a[0x1];
4407 	u8         rw[0x1];
4408 	u8         rr[0x1];
4409 	u8         lw[0x1];
4410 	u8         lr[0x1];
4411 	u8         access_mode_1_0[0x2];
4412 	u8         reserved_at_18[0x2];
4413 	u8         ma_translation_mode[0x2];
4414 	u8         reserved_at_1c[0x4];
4415 
4416 	u8         qpn[0x18];
4417 	u8         mkey_7_0[0x8];
4418 
4419 	u8         reserved_at_40[0x20];
4420 
4421 	u8         length64[0x1];
4422 	u8         bsf_en[0x1];
4423 	u8         sync_umr[0x1];
4424 	u8         reserved_at_63[0x2];
4425 	u8         expected_sigerr_count[0x1];
4426 	u8         reserved_at_66[0x1];
4427 	u8         en_rinval[0x1];
4428 	u8         pd[0x18];
4429 
4430 	u8         start_addr[0x40];
4431 
4432 	u8         len[0x40];
4433 
4434 	u8         bsf_octword_size[0x20];
4435 
4436 	u8         reserved_at_120[0x60];
4437 
4438 	u8         crossing_target_vhca_id[0x10];
4439 	u8         reserved_at_190[0x10];
4440 
4441 	u8         translations_octword_size[0x20];
4442 
4443 	u8         reserved_at_1c0[0x19];
4444 	u8         relaxed_ordering_read[0x1];
4445 	u8         log_page_size[0x6];
4446 
4447 	u8         reserved_at_1e0[0x20];
4448 };
4449 
4450 struct mlx5_ifc_pkey_bits {
4451 	u8         reserved_at_0[0x10];
4452 	u8         pkey[0x10];
4453 };
4454 
4455 struct mlx5_ifc_array128_auto_bits {
4456 	u8         array128_auto[16][0x8];
4457 };
4458 
4459 struct mlx5_ifc_hca_vport_context_bits {
4460 	u8         field_select[0x20];
4461 
4462 	u8         reserved_at_20[0xe0];
4463 
4464 	u8         sm_virt_aware[0x1];
4465 	u8         has_smi[0x1];
4466 	u8         has_raw[0x1];
4467 	u8         grh_required[0x1];
4468 	u8         reserved_at_104[0x4];
4469 	u8         num_port_plane[0x8];
4470 	u8         port_physical_state[0x4];
4471 	u8         vport_state_policy[0x4];
4472 	u8         port_state[0x4];
4473 	u8         vport_state[0x4];
4474 
4475 	u8         reserved_at_120[0x20];
4476 
4477 	u8         system_image_guid[0x40];
4478 
4479 	u8         port_guid[0x40];
4480 
4481 	u8         node_guid[0x40];
4482 
4483 	u8         cap_mask1[0x20];
4484 
4485 	u8         cap_mask1_field_select[0x20];
4486 
4487 	u8         cap_mask2[0x20];
4488 
4489 	u8         cap_mask2_field_select[0x20];
4490 
4491 	u8         reserved_at_280[0x80];
4492 
4493 	u8         lid[0x10];
4494 	u8         reserved_at_310[0x4];
4495 	u8         init_type_reply[0x4];
4496 	u8         lmc[0x3];
4497 	u8         subnet_timeout[0x5];
4498 
4499 	u8         sm_lid[0x10];
4500 	u8         sm_sl[0x4];
4501 	u8         reserved_at_334[0xc];
4502 
4503 	u8         qkey_violation_counter[0x10];
4504 	u8         pkey_violation_counter[0x10];
4505 
4506 	u8         reserved_at_360[0xca0];
4507 };
4508 
4509 struct mlx5_ifc_esw_vport_context_bits {
4510 	u8         fdb_to_vport_reg_c[0x1];
4511 	u8         reserved_at_1[0x2];
4512 	u8         vport_svlan_strip[0x1];
4513 	u8         vport_cvlan_strip[0x1];
4514 	u8         vport_svlan_insert[0x1];
4515 	u8         vport_cvlan_insert[0x2];
4516 	u8         fdb_to_vport_reg_c_id[0x8];
4517 	u8         reserved_at_10[0x10];
4518 
4519 	u8         reserved_at_20[0x20];
4520 
4521 	u8         svlan_cfi[0x1];
4522 	u8         svlan_pcp[0x3];
4523 	u8         svlan_id[0xc];
4524 	u8         cvlan_cfi[0x1];
4525 	u8         cvlan_pcp[0x3];
4526 	u8         cvlan_id[0xc];
4527 
4528 	u8         reserved_at_60[0x720];
4529 
4530 	u8         sw_steering_vport_icm_address_rx[0x40];
4531 
4532 	u8         sw_steering_vport_icm_address_tx[0x40];
4533 };
4534 
4535 enum {
4536 	MLX5_EQC_STATUS_OK                = 0x0,
4537 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4538 };
4539 
4540 enum {
4541 	MLX5_EQC_ST_ARMED  = 0x9,
4542 	MLX5_EQC_ST_FIRED  = 0xa,
4543 };
4544 
4545 struct mlx5_ifc_eqc_bits {
4546 	u8         status[0x4];
4547 	u8         reserved_at_4[0x9];
4548 	u8         ec[0x1];
4549 	u8         oi[0x1];
4550 	u8         reserved_at_f[0x5];
4551 	u8         st[0x4];
4552 	u8         reserved_at_18[0x8];
4553 
4554 	u8         reserved_at_20[0x20];
4555 
4556 	u8         reserved_at_40[0x14];
4557 	u8         page_offset[0x6];
4558 	u8         reserved_at_5a[0x6];
4559 
4560 	u8         reserved_at_60[0x3];
4561 	u8         log_eq_size[0x5];
4562 	u8         uar_page[0x18];
4563 
4564 	u8         reserved_at_80[0x20];
4565 
4566 	u8         reserved_at_a0[0x14];
4567 	u8         intr[0xc];
4568 
4569 	u8         reserved_at_c0[0x3];
4570 	u8         log_page_size[0x5];
4571 	u8         reserved_at_c8[0x18];
4572 
4573 	u8         reserved_at_e0[0x60];
4574 
4575 	u8         reserved_at_140[0x8];
4576 	u8         consumer_counter[0x18];
4577 
4578 	u8         reserved_at_160[0x8];
4579 	u8         producer_counter[0x18];
4580 
4581 	u8         reserved_at_180[0x80];
4582 };
4583 
4584 enum {
4585 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4586 	MLX5_DCTC_STATE_DRAINING  = 0x1,
4587 	MLX5_DCTC_STATE_DRAINED   = 0x2,
4588 };
4589 
4590 enum {
4591 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4592 	MLX5_DCTC_CS_RES_NA         = 0x1,
4593 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4594 };
4595 
4596 enum {
4597 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4598 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4599 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4600 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4601 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4602 };
4603 
4604 struct mlx5_ifc_dctc_bits {
4605 	u8         reserved_at_0[0x4];
4606 	u8         state[0x4];
4607 	u8         reserved_at_8[0x18];
4608 
4609 	u8         reserved_at_20[0x7];
4610 	u8         dp_ordering_force[0x1];
4611 	u8         user_index[0x18];
4612 
4613 	u8         reserved_at_40[0x8];
4614 	u8         cqn[0x18];
4615 
4616 	u8         counter_set_id[0x8];
4617 	u8         atomic_mode[0x4];
4618 	u8         rre[0x1];
4619 	u8         rwe[0x1];
4620 	u8         rae[0x1];
4621 	u8         atomic_like_write_en[0x1];
4622 	u8         latency_sensitive[0x1];
4623 	u8         rlky[0x1];
4624 	u8         free_ar[0x1];
4625 	u8         reserved_at_73[0x1];
4626 	u8         dp_ordering_1[0x1];
4627 	u8         reserved_at_75[0xb];
4628 
4629 	u8         reserved_at_80[0x8];
4630 	u8         cs_res[0x8];
4631 	u8         reserved_at_90[0x3];
4632 	u8         min_rnr_nak[0x5];
4633 	u8         reserved_at_98[0x8];
4634 
4635 	u8         reserved_at_a0[0x8];
4636 	u8         srqn_xrqn[0x18];
4637 
4638 	u8         reserved_at_c0[0x8];
4639 	u8         pd[0x18];
4640 
4641 	u8         tclass[0x8];
4642 	u8         reserved_at_e8[0x4];
4643 	u8         flow_label[0x14];
4644 
4645 	u8         dc_access_key[0x40];
4646 
4647 	u8         reserved_at_140[0x5];
4648 	u8         mtu[0x3];
4649 	u8         port[0x8];
4650 	u8         pkey_index[0x10];
4651 
4652 	u8         reserved_at_160[0x8];
4653 	u8         my_addr_index[0x8];
4654 	u8         reserved_at_170[0x8];
4655 	u8         hop_limit[0x8];
4656 
4657 	u8         dc_access_key_violation_count[0x20];
4658 
4659 	u8         reserved_at_1a0[0x14];
4660 	u8         dei_cfi[0x1];
4661 	u8         eth_prio[0x3];
4662 	u8         ecn[0x2];
4663 	u8         dscp[0x6];
4664 
4665 	u8         reserved_at_1c0[0x20];
4666 	u8         ece[0x20];
4667 };
4668 
4669 enum {
4670 	MLX5_CQC_STATUS_OK             = 0x0,
4671 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4672 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4673 };
4674 
4675 enum {
4676 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4677 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4678 };
4679 
4680 enum {
4681 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4682 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4683 	MLX5_CQC_ST_FIRED                                 = 0xa,
4684 };
4685 
4686 enum mlx5_cq_period_mode {
4687 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4688 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4689 	MLX5_CQ_PERIOD_NUM_MODES,
4690 };
4691 
4692 struct mlx5_ifc_cqc_bits {
4693 	u8         status[0x4];
4694 	u8         reserved_at_4[0x2];
4695 	u8         dbr_umem_valid[0x1];
4696 	u8         apu_cq[0x1];
4697 	u8         cqe_sz[0x3];
4698 	u8         cc[0x1];
4699 	u8         reserved_at_c[0x1];
4700 	u8         scqe_break_moderation_en[0x1];
4701 	u8         oi[0x1];
4702 	u8         cq_period_mode[0x2];
4703 	u8         cqe_comp_en[0x1];
4704 	u8         mini_cqe_res_format[0x2];
4705 	u8         st[0x4];
4706 	u8         reserved_at_18[0x6];
4707 	u8         cqe_compression_layout[0x2];
4708 
4709 	u8         reserved_at_20[0x20];
4710 
4711 	u8         reserved_at_40[0x14];
4712 	u8         page_offset[0x6];
4713 	u8         reserved_at_5a[0x6];
4714 
4715 	u8         reserved_at_60[0x3];
4716 	u8         log_cq_size[0x5];
4717 	u8         uar_page[0x18];
4718 
4719 	u8         reserved_at_80[0x4];
4720 	u8         cq_period[0xc];
4721 	u8         cq_max_count[0x10];
4722 
4723 	u8         c_eqn_or_apu_element[0x20];
4724 
4725 	u8         reserved_at_c0[0x3];
4726 	u8         log_page_size[0x5];
4727 	u8         reserved_at_c8[0x18];
4728 
4729 	u8         reserved_at_e0[0x20];
4730 
4731 	u8         reserved_at_100[0x8];
4732 	u8         last_notified_index[0x18];
4733 
4734 	u8         reserved_at_120[0x8];
4735 	u8         last_solicit_index[0x18];
4736 
4737 	u8         reserved_at_140[0x8];
4738 	u8         consumer_counter[0x18];
4739 
4740 	u8         reserved_at_160[0x8];
4741 	u8         producer_counter[0x18];
4742 
4743 	u8         reserved_at_180[0x40];
4744 
4745 	u8         dbr_addr[0x40];
4746 };
4747 
4748 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4749 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4750 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4751 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4752 	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4753 	u8         reserved_at_0[0x800];
4754 };
4755 
4756 struct mlx5_ifc_query_adapter_param_block_bits {
4757 	u8         reserved_at_0[0xc0];
4758 
4759 	u8         reserved_at_c0[0x8];
4760 	u8         ieee_vendor_id[0x18];
4761 
4762 	u8         reserved_at_e0[0x10];
4763 	u8         vsd_vendor_id[0x10];
4764 
4765 	u8         vsd[208][0x8];
4766 
4767 	u8         vsd_contd_psid[16][0x8];
4768 };
4769 
4770 enum {
4771 	MLX5_XRQC_STATE_GOOD   = 0x0,
4772 	MLX5_XRQC_STATE_ERROR  = 0x1,
4773 };
4774 
4775 enum {
4776 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4777 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4778 };
4779 
4780 enum {
4781 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4782 };
4783 
4784 struct mlx5_ifc_tag_matching_topology_context_bits {
4785 	u8         log_matching_list_sz[0x4];
4786 	u8         reserved_at_4[0xc];
4787 	u8         append_next_index[0x10];
4788 
4789 	u8         sw_phase_cnt[0x10];
4790 	u8         hw_phase_cnt[0x10];
4791 
4792 	u8         reserved_at_40[0x40];
4793 };
4794 
4795 struct mlx5_ifc_xrqc_bits {
4796 	u8         state[0x4];
4797 	u8         rlkey[0x1];
4798 	u8         reserved_at_5[0xf];
4799 	u8         topology[0x4];
4800 	u8         reserved_at_18[0x4];
4801 	u8         offload[0x4];
4802 
4803 	u8         reserved_at_20[0x8];
4804 	u8         user_index[0x18];
4805 
4806 	u8         reserved_at_40[0x8];
4807 	u8         cqn[0x18];
4808 
4809 	u8         reserved_at_60[0xa0];
4810 
4811 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4812 
4813 	u8         reserved_at_180[0x280];
4814 
4815 	struct mlx5_ifc_wq_bits wq;
4816 };
4817 
4818 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4819 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4820 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4821 	u8         reserved_at_0[0x20];
4822 };
4823 
4824 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4825 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4826 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4827 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4828 	u8         reserved_at_0[0x20];
4829 };
4830 
4831 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4832 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4833 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4834 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4835 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4836 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4837 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4838 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4839 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4840 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4841 	struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4842 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4843 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4844 	u8         reserved_at_0[0x7c0];
4845 };
4846 
4847 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4848 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4849 	u8         reserved_at_0[0x7c0];
4850 };
4851 
4852 union mlx5_ifc_event_auto_bits {
4853 	struct mlx5_ifc_comp_event_bits comp_event;
4854 	struct mlx5_ifc_dct_events_bits dct_events;
4855 	struct mlx5_ifc_qp_events_bits qp_events;
4856 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4857 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4858 	struct mlx5_ifc_cq_error_bits cq_error;
4859 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4860 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4861 	struct mlx5_ifc_gpio_event_bits gpio_event;
4862 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4863 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4864 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4865 	u8         reserved_at_0[0xe0];
4866 };
4867 
4868 struct mlx5_ifc_health_buffer_bits {
4869 	u8         reserved_at_0[0x100];
4870 
4871 	u8         assert_existptr[0x20];
4872 
4873 	u8         assert_callra[0x20];
4874 
4875 	u8         reserved_at_140[0x20];
4876 
4877 	u8         time[0x20];
4878 
4879 	u8         fw_version[0x20];
4880 
4881 	u8         hw_id[0x20];
4882 
4883 	u8         rfr[0x1];
4884 	u8         reserved_at_1c1[0x3];
4885 	u8         valid[0x1];
4886 	u8         severity[0x3];
4887 	u8         reserved_at_1c8[0x18];
4888 
4889 	u8         irisc_index[0x8];
4890 	u8         synd[0x8];
4891 	u8         ext_synd[0x10];
4892 };
4893 
4894 struct mlx5_ifc_register_loopback_control_bits {
4895 	u8         no_lb[0x1];
4896 	u8         reserved_at_1[0x7];
4897 	u8         port[0x8];
4898 	u8         reserved_at_10[0x10];
4899 
4900 	u8         reserved_at_20[0x60];
4901 };
4902 
4903 enum {
4904 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4905 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4906 };
4907 
4908 struct mlx5_ifc_teardown_hca_out_bits {
4909 	u8         status[0x8];
4910 	u8         reserved_at_8[0x18];
4911 
4912 	u8         syndrome[0x20];
4913 
4914 	u8         reserved_at_40[0x3f];
4915 
4916 	u8         state[0x1];
4917 };
4918 
4919 enum {
4920 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4921 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4922 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4923 };
4924 
4925 struct mlx5_ifc_teardown_hca_in_bits {
4926 	u8         opcode[0x10];
4927 	u8         reserved_at_10[0x10];
4928 
4929 	u8         reserved_at_20[0x10];
4930 	u8         op_mod[0x10];
4931 
4932 	u8         reserved_at_40[0x10];
4933 	u8         profile[0x10];
4934 
4935 	u8         reserved_at_60[0x20];
4936 };
4937 
4938 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4939 	u8         status[0x8];
4940 	u8         reserved_at_8[0x18];
4941 
4942 	u8         syndrome[0x20];
4943 
4944 	u8         reserved_at_40[0x40];
4945 };
4946 
4947 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4948 	u8         opcode[0x10];
4949 	u8         uid[0x10];
4950 
4951 	u8         reserved_at_20[0x10];
4952 	u8         op_mod[0x10];
4953 
4954 	u8         reserved_at_40[0x8];
4955 	u8         qpn[0x18];
4956 
4957 	u8         reserved_at_60[0x20];
4958 
4959 	u8         opt_param_mask[0x20];
4960 
4961 	u8         reserved_at_a0[0x20];
4962 
4963 	struct mlx5_ifc_qpc_bits qpc;
4964 
4965 	u8         reserved_at_800[0x80];
4966 };
4967 
4968 struct mlx5_ifc_sqd2rts_qp_out_bits {
4969 	u8         status[0x8];
4970 	u8         reserved_at_8[0x18];
4971 
4972 	u8         syndrome[0x20];
4973 
4974 	u8         reserved_at_40[0x40];
4975 };
4976 
4977 struct mlx5_ifc_sqd2rts_qp_in_bits {
4978 	u8         opcode[0x10];
4979 	u8         uid[0x10];
4980 
4981 	u8         reserved_at_20[0x10];
4982 	u8         op_mod[0x10];
4983 
4984 	u8         reserved_at_40[0x8];
4985 	u8         qpn[0x18];
4986 
4987 	u8         reserved_at_60[0x20];
4988 
4989 	u8         opt_param_mask[0x20];
4990 
4991 	u8         reserved_at_a0[0x20];
4992 
4993 	struct mlx5_ifc_qpc_bits qpc;
4994 
4995 	u8         reserved_at_800[0x80];
4996 };
4997 
4998 struct mlx5_ifc_set_roce_address_out_bits {
4999 	u8         status[0x8];
5000 	u8         reserved_at_8[0x18];
5001 
5002 	u8         syndrome[0x20];
5003 
5004 	u8         reserved_at_40[0x40];
5005 };
5006 
5007 struct mlx5_ifc_set_roce_address_in_bits {
5008 	u8         opcode[0x10];
5009 	u8         reserved_at_10[0x10];
5010 
5011 	u8         reserved_at_20[0x10];
5012 	u8         op_mod[0x10];
5013 
5014 	u8         roce_address_index[0x10];
5015 	u8         reserved_at_50[0xc];
5016 	u8	   vhca_port_num[0x4];
5017 
5018 	u8         reserved_at_60[0x20];
5019 
5020 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5021 };
5022 
5023 struct mlx5_ifc_set_mad_demux_out_bits {
5024 	u8         status[0x8];
5025 	u8         reserved_at_8[0x18];
5026 
5027 	u8         syndrome[0x20];
5028 
5029 	u8         reserved_at_40[0x40];
5030 };
5031 
5032 enum {
5033 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
5034 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
5035 };
5036 
5037 struct mlx5_ifc_set_mad_demux_in_bits {
5038 	u8         opcode[0x10];
5039 	u8         reserved_at_10[0x10];
5040 
5041 	u8         reserved_at_20[0x10];
5042 	u8         op_mod[0x10];
5043 
5044 	u8         reserved_at_40[0x20];
5045 
5046 	u8         reserved_at_60[0x6];
5047 	u8         demux_mode[0x2];
5048 	u8         reserved_at_68[0x18];
5049 };
5050 
5051 struct mlx5_ifc_set_l2_table_entry_out_bits {
5052 	u8         status[0x8];
5053 	u8         reserved_at_8[0x18];
5054 
5055 	u8         syndrome[0x20];
5056 
5057 	u8         reserved_at_40[0x40];
5058 };
5059 
5060 struct mlx5_ifc_set_l2_table_entry_in_bits {
5061 	u8         opcode[0x10];
5062 	u8         reserved_at_10[0x10];
5063 
5064 	u8         reserved_at_20[0x10];
5065 	u8         op_mod[0x10];
5066 
5067 	u8         reserved_at_40[0x60];
5068 
5069 	u8         reserved_at_a0[0x8];
5070 	u8         table_index[0x18];
5071 
5072 	u8         reserved_at_c0[0x20];
5073 
5074 	u8         reserved_at_e0[0x10];
5075 	u8         silent_mode_valid[0x1];
5076 	u8         silent_mode[0x1];
5077 	u8         reserved_at_f2[0x1];
5078 	u8         vlan_valid[0x1];
5079 	u8         vlan[0xc];
5080 
5081 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5082 
5083 	u8         reserved_at_140[0xc0];
5084 };
5085 
5086 struct mlx5_ifc_set_issi_out_bits {
5087 	u8         status[0x8];
5088 	u8         reserved_at_8[0x18];
5089 
5090 	u8         syndrome[0x20];
5091 
5092 	u8         reserved_at_40[0x40];
5093 };
5094 
5095 struct mlx5_ifc_set_issi_in_bits {
5096 	u8         opcode[0x10];
5097 	u8         reserved_at_10[0x10];
5098 
5099 	u8         reserved_at_20[0x10];
5100 	u8         op_mod[0x10];
5101 
5102 	u8         reserved_at_40[0x10];
5103 	u8         current_issi[0x10];
5104 
5105 	u8         reserved_at_60[0x20];
5106 };
5107 
5108 struct mlx5_ifc_set_hca_cap_out_bits {
5109 	u8         status[0x8];
5110 	u8         reserved_at_8[0x18];
5111 
5112 	u8         syndrome[0x20];
5113 
5114 	u8         reserved_at_40[0x40];
5115 };
5116 
5117 struct mlx5_ifc_set_hca_cap_in_bits {
5118 	u8         opcode[0x10];
5119 	u8         reserved_at_10[0x10];
5120 
5121 	u8         reserved_at_20[0x10];
5122 	u8         op_mod[0x10];
5123 
5124 	u8         other_function[0x1];
5125 	u8         ec_vf_function[0x1];
5126 	u8         reserved_at_42[0xe];
5127 	u8         function_id[0x10];
5128 
5129 	u8         reserved_at_60[0x20];
5130 
5131 	union mlx5_ifc_hca_cap_union_bits capability;
5132 };
5133 
5134 enum {
5135 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
5136 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
5137 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
5138 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
5139 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
5140 };
5141 
5142 struct mlx5_ifc_set_fte_out_bits {
5143 	u8         status[0x8];
5144 	u8         reserved_at_8[0x18];
5145 
5146 	u8         syndrome[0x20];
5147 
5148 	u8         reserved_at_40[0x40];
5149 };
5150 
5151 struct mlx5_ifc_set_fte_in_bits {
5152 	u8         opcode[0x10];
5153 	u8         reserved_at_10[0x10];
5154 
5155 	u8         reserved_at_20[0x10];
5156 	u8         op_mod[0x10];
5157 
5158 	u8         other_vport[0x1];
5159 	u8         reserved_at_41[0xf];
5160 	u8         vport_number[0x10];
5161 
5162 	u8         reserved_at_60[0x20];
5163 
5164 	u8         table_type[0x8];
5165 	u8         reserved_at_88[0x18];
5166 
5167 	u8         reserved_at_a0[0x8];
5168 	u8         table_id[0x18];
5169 
5170 	u8         ignore_flow_level[0x1];
5171 	u8         reserved_at_c1[0x17];
5172 	u8         modify_enable_mask[0x8];
5173 
5174 	u8         reserved_at_e0[0x20];
5175 
5176 	u8         flow_index[0x20];
5177 
5178 	u8         reserved_at_120[0xe0];
5179 
5180 	struct mlx5_ifc_flow_context_bits flow_context;
5181 };
5182 
5183 struct mlx5_ifc_dest_format_bits {
5184 	u8         destination_type[0x8];
5185 	u8         destination_id[0x18];
5186 
5187 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
5188 	u8         packet_reformat[0x1];
5189 	u8         reserved_at_22[0xe];
5190 	u8         destination_eswitch_owner_vhca_id[0x10];
5191 };
5192 
5193 struct mlx5_ifc_rts2rts_qp_out_bits {
5194 	u8         status[0x8];
5195 	u8         reserved_at_8[0x18];
5196 
5197 	u8         syndrome[0x20];
5198 
5199 	u8         reserved_at_40[0x20];
5200 	u8         ece[0x20];
5201 };
5202 
5203 struct mlx5_ifc_rts2rts_qp_in_bits {
5204 	u8         opcode[0x10];
5205 	u8         uid[0x10];
5206 
5207 	u8         reserved_at_20[0x10];
5208 	u8         op_mod[0x10];
5209 
5210 	u8         reserved_at_40[0x8];
5211 	u8         qpn[0x18];
5212 
5213 	u8         reserved_at_60[0x20];
5214 
5215 	u8         opt_param_mask[0x20];
5216 
5217 	u8         ece[0x20];
5218 
5219 	struct mlx5_ifc_qpc_bits qpc;
5220 
5221 	u8         reserved_at_800[0x80];
5222 };
5223 
5224 struct mlx5_ifc_rtr2rts_qp_out_bits {
5225 	u8         status[0x8];
5226 	u8         reserved_at_8[0x18];
5227 
5228 	u8         syndrome[0x20];
5229 
5230 	u8         reserved_at_40[0x20];
5231 	u8         ece[0x20];
5232 };
5233 
5234 struct mlx5_ifc_rtr2rts_qp_in_bits {
5235 	u8         opcode[0x10];
5236 	u8         uid[0x10];
5237 
5238 	u8         reserved_at_20[0x10];
5239 	u8         op_mod[0x10];
5240 
5241 	u8         reserved_at_40[0x8];
5242 	u8         qpn[0x18];
5243 
5244 	u8         reserved_at_60[0x20];
5245 
5246 	u8         opt_param_mask[0x20];
5247 
5248 	u8         ece[0x20];
5249 
5250 	struct mlx5_ifc_qpc_bits qpc;
5251 
5252 	u8         reserved_at_800[0x80];
5253 };
5254 
5255 struct mlx5_ifc_rst2init_qp_out_bits {
5256 	u8         status[0x8];
5257 	u8         reserved_at_8[0x18];
5258 
5259 	u8         syndrome[0x20];
5260 
5261 	u8         reserved_at_40[0x20];
5262 	u8         ece[0x20];
5263 };
5264 
5265 struct mlx5_ifc_rst2init_qp_in_bits {
5266 	u8         opcode[0x10];
5267 	u8         uid[0x10];
5268 
5269 	u8         reserved_at_20[0x10];
5270 	u8         op_mod[0x10];
5271 
5272 	u8         reserved_at_40[0x8];
5273 	u8         qpn[0x18];
5274 
5275 	u8         reserved_at_60[0x20];
5276 
5277 	u8         opt_param_mask[0x20];
5278 
5279 	u8         ece[0x20];
5280 
5281 	struct mlx5_ifc_qpc_bits qpc;
5282 
5283 	u8         reserved_at_800[0x80];
5284 };
5285 
5286 struct mlx5_ifc_query_xrq_out_bits {
5287 	u8         status[0x8];
5288 	u8         reserved_at_8[0x18];
5289 
5290 	u8         syndrome[0x20];
5291 
5292 	u8         reserved_at_40[0x40];
5293 
5294 	struct mlx5_ifc_xrqc_bits xrq_context;
5295 };
5296 
5297 struct mlx5_ifc_query_xrq_in_bits {
5298 	u8         opcode[0x10];
5299 	u8         reserved_at_10[0x10];
5300 
5301 	u8         reserved_at_20[0x10];
5302 	u8         op_mod[0x10];
5303 
5304 	u8         reserved_at_40[0x8];
5305 	u8         xrqn[0x18];
5306 
5307 	u8         reserved_at_60[0x20];
5308 };
5309 
5310 struct mlx5_ifc_query_xrc_srq_out_bits {
5311 	u8         status[0x8];
5312 	u8         reserved_at_8[0x18];
5313 
5314 	u8         syndrome[0x20];
5315 
5316 	u8         reserved_at_40[0x40];
5317 
5318 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5319 
5320 	u8         reserved_at_280[0x600];
5321 
5322 	u8         pas[][0x40];
5323 };
5324 
5325 struct mlx5_ifc_query_xrc_srq_in_bits {
5326 	u8         opcode[0x10];
5327 	u8         reserved_at_10[0x10];
5328 
5329 	u8         reserved_at_20[0x10];
5330 	u8         op_mod[0x10];
5331 
5332 	u8         reserved_at_40[0x8];
5333 	u8         xrc_srqn[0x18];
5334 
5335 	u8         reserved_at_60[0x20];
5336 };
5337 
5338 enum {
5339 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5340 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5341 };
5342 
5343 struct mlx5_ifc_query_vport_state_out_bits {
5344 	u8         status[0x8];
5345 	u8         reserved_at_8[0x18];
5346 
5347 	u8         syndrome[0x20];
5348 
5349 	u8         reserved_at_40[0x20];
5350 
5351 	u8         reserved_at_60[0x18];
5352 	u8         admin_state[0x4];
5353 	u8         state[0x4];
5354 };
5355 
5356 struct mlx5_ifc_array1024_auto_bits {
5357 	u8         array1024_auto[32][0x20];
5358 };
5359 
5360 struct mlx5_ifc_query_vuid_in_bits {
5361 	u8         opcode[0x10];
5362 	u8         uid[0x10];
5363 
5364 	u8         reserved_at_20[0x40];
5365 
5366 	u8         query_vfs_vuid[0x1];
5367 	u8         data_direct[0x1];
5368 	u8         reserved_at_62[0xe];
5369 	u8         vhca_id[0x10];
5370 };
5371 
5372 struct mlx5_ifc_query_vuid_out_bits {
5373 	u8        status[0x8];
5374 	u8        reserved_at_8[0x18];
5375 
5376 	u8        syndrome[0x20];
5377 
5378 	u8        reserved_at_40[0x1a0];
5379 
5380 	u8        reserved_at_1e0[0x10];
5381 	u8        num_of_entries[0x10];
5382 
5383 	struct mlx5_ifc_array1024_auto_bits vuid[];
5384 };
5385 
5386 enum {
5387 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5388 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5389 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5390 };
5391 
5392 struct mlx5_ifc_arm_monitor_counter_in_bits {
5393 	u8         opcode[0x10];
5394 	u8         uid[0x10];
5395 
5396 	u8         reserved_at_20[0x10];
5397 	u8         op_mod[0x10];
5398 
5399 	u8         reserved_at_40[0x20];
5400 
5401 	u8         reserved_at_60[0x20];
5402 };
5403 
5404 struct mlx5_ifc_arm_monitor_counter_out_bits {
5405 	u8         status[0x8];
5406 	u8         reserved_at_8[0x18];
5407 
5408 	u8         syndrome[0x20];
5409 
5410 	u8         reserved_at_40[0x40];
5411 };
5412 
5413 enum {
5414 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5415 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5416 };
5417 
5418 enum mlx5_monitor_counter_ppcnt {
5419 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5420 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5421 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5422 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5423 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5424 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5425 };
5426 
5427 enum {
5428 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5429 };
5430 
5431 struct mlx5_ifc_monitor_counter_output_bits {
5432 	u8         reserved_at_0[0x4];
5433 	u8         type[0x4];
5434 	u8         reserved_at_8[0x8];
5435 	u8         counter[0x10];
5436 
5437 	u8         counter_group_id[0x20];
5438 };
5439 
5440 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5441 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5442 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5443 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5444 
5445 struct mlx5_ifc_set_monitor_counter_in_bits {
5446 	u8         opcode[0x10];
5447 	u8         uid[0x10];
5448 
5449 	u8         reserved_at_20[0x10];
5450 	u8         op_mod[0x10];
5451 
5452 	u8         reserved_at_40[0x10];
5453 	u8         num_of_counters[0x10];
5454 
5455 	u8         reserved_at_60[0x20];
5456 
5457 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5458 };
5459 
5460 struct mlx5_ifc_set_monitor_counter_out_bits {
5461 	u8         status[0x8];
5462 	u8         reserved_at_8[0x18];
5463 
5464 	u8         syndrome[0x20];
5465 
5466 	u8         reserved_at_40[0x40];
5467 };
5468 
5469 struct mlx5_ifc_query_vport_state_in_bits {
5470 	u8         opcode[0x10];
5471 	u8         reserved_at_10[0x10];
5472 
5473 	u8         reserved_at_20[0x10];
5474 	u8         op_mod[0x10];
5475 
5476 	u8         other_vport[0x1];
5477 	u8         reserved_at_41[0xf];
5478 	u8         vport_number[0x10];
5479 
5480 	u8         reserved_at_60[0x20];
5481 };
5482 
5483 struct mlx5_ifc_query_vnic_env_out_bits {
5484 	u8         status[0x8];
5485 	u8         reserved_at_8[0x18];
5486 
5487 	u8         syndrome[0x20];
5488 
5489 	u8         reserved_at_40[0x40];
5490 
5491 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5492 };
5493 
5494 enum {
5495 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5496 };
5497 
5498 struct mlx5_ifc_query_vnic_env_in_bits {
5499 	u8         opcode[0x10];
5500 	u8         reserved_at_10[0x10];
5501 
5502 	u8         reserved_at_20[0x10];
5503 	u8         op_mod[0x10];
5504 
5505 	u8         other_vport[0x1];
5506 	u8         reserved_at_41[0xf];
5507 	u8         vport_number[0x10];
5508 
5509 	u8         reserved_at_60[0x20];
5510 };
5511 
5512 struct mlx5_ifc_query_vport_counter_out_bits {
5513 	u8         status[0x8];
5514 	u8         reserved_at_8[0x18];
5515 
5516 	u8         syndrome[0x20];
5517 
5518 	u8         reserved_at_40[0x40];
5519 
5520 	struct mlx5_ifc_traffic_counter_bits received_errors;
5521 
5522 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5523 
5524 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5525 
5526 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5527 
5528 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5529 
5530 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5531 
5532 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5533 
5534 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5535 
5536 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5537 
5538 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5539 
5540 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5541 
5542 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5543 
5544 	struct mlx5_ifc_traffic_counter_bits local_loopback;
5545 
5546 	u8         reserved_at_700[0x980];
5547 };
5548 
5549 enum {
5550 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5551 };
5552 
5553 struct mlx5_ifc_query_vport_counter_in_bits {
5554 	u8         opcode[0x10];
5555 	u8         reserved_at_10[0x10];
5556 
5557 	u8         reserved_at_20[0x10];
5558 	u8         op_mod[0x10];
5559 
5560 	u8         other_vport[0x1];
5561 	u8         reserved_at_41[0xb];
5562 	u8	   port_num[0x4];
5563 	u8         vport_number[0x10];
5564 
5565 	u8         reserved_at_60[0x60];
5566 
5567 	u8         clear[0x1];
5568 	u8         reserved_at_c1[0x1f];
5569 
5570 	u8         reserved_at_e0[0x20];
5571 };
5572 
5573 struct mlx5_ifc_query_tis_out_bits {
5574 	u8         status[0x8];
5575 	u8         reserved_at_8[0x18];
5576 
5577 	u8         syndrome[0x20];
5578 
5579 	u8         reserved_at_40[0x40];
5580 
5581 	struct mlx5_ifc_tisc_bits tis_context;
5582 };
5583 
5584 struct mlx5_ifc_query_tis_in_bits {
5585 	u8         opcode[0x10];
5586 	u8         reserved_at_10[0x10];
5587 
5588 	u8         reserved_at_20[0x10];
5589 	u8         op_mod[0x10];
5590 
5591 	u8         reserved_at_40[0x8];
5592 	u8         tisn[0x18];
5593 
5594 	u8         reserved_at_60[0x20];
5595 };
5596 
5597 struct mlx5_ifc_query_tir_out_bits {
5598 	u8         status[0x8];
5599 	u8         reserved_at_8[0x18];
5600 
5601 	u8         syndrome[0x20];
5602 
5603 	u8         reserved_at_40[0xc0];
5604 
5605 	struct mlx5_ifc_tirc_bits tir_context;
5606 };
5607 
5608 struct mlx5_ifc_query_tir_in_bits {
5609 	u8         opcode[0x10];
5610 	u8         reserved_at_10[0x10];
5611 
5612 	u8         reserved_at_20[0x10];
5613 	u8         op_mod[0x10];
5614 
5615 	u8         reserved_at_40[0x8];
5616 	u8         tirn[0x18];
5617 
5618 	u8         reserved_at_60[0x20];
5619 };
5620 
5621 struct mlx5_ifc_query_srq_out_bits {
5622 	u8         status[0x8];
5623 	u8         reserved_at_8[0x18];
5624 
5625 	u8         syndrome[0x20];
5626 
5627 	u8         reserved_at_40[0x40];
5628 
5629 	struct mlx5_ifc_srqc_bits srq_context_entry;
5630 
5631 	u8         reserved_at_280[0x600];
5632 
5633 	u8         pas[][0x40];
5634 };
5635 
5636 struct mlx5_ifc_query_srq_in_bits {
5637 	u8         opcode[0x10];
5638 	u8         reserved_at_10[0x10];
5639 
5640 	u8         reserved_at_20[0x10];
5641 	u8         op_mod[0x10];
5642 
5643 	u8         reserved_at_40[0x8];
5644 	u8         srqn[0x18];
5645 
5646 	u8         reserved_at_60[0x20];
5647 };
5648 
5649 struct mlx5_ifc_query_sq_out_bits {
5650 	u8         status[0x8];
5651 	u8         reserved_at_8[0x18];
5652 
5653 	u8         syndrome[0x20];
5654 
5655 	u8         reserved_at_40[0xc0];
5656 
5657 	struct mlx5_ifc_sqc_bits sq_context;
5658 };
5659 
5660 struct mlx5_ifc_query_sq_in_bits {
5661 	u8         opcode[0x10];
5662 	u8         reserved_at_10[0x10];
5663 
5664 	u8         reserved_at_20[0x10];
5665 	u8         op_mod[0x10];
5666 
5667 	u8         reserved_at_40[0x8];
5668 	u8         sqn[0x18];
5669 
5670 	u8         reserved_at_60[0x20];
5671 };
5672 
5673 struct mlx5_ifc_query_special_contexts_out_bits {
5674 	u8         status[0x8];
5675 	u8         reserved_at_8[0x18];
5676 
5677 	u8         syndrome[0x20];
5678 
5679 	u8         dump_fill_mkey[0x20];
5680 
5681 	u8         resd_lkey[0x20];
5682 
5683 	u8         null_mkey[0x20];
5684 
5685 	u8	   terminate_scatter_list_mkey[0x20];
5686 
5687 	u8	   repeated_mkey[0x20];
5688 
5689 	u8         reserved_at_a0[0x20];
5690 };
5691 
5692 struct mlx5_ifc_query_special_contexts_in_bits {
5693 	u8         opcode[0x10];
5694 	u8         reserved_at_10[0x10];
5695 
5696 	u8         reserved_at_20[0x10];
5697 	u8         op_mod[0x10];
5698 
5699 	u8         reserved_at_40[0x40];
5700 };
5701 
5702 struct mlx5_ifc_query_scheduling_element_out_bits {
5703 	u8         opcode[0x10];
5704 	u8         reserved_at_10[0x10];
5705 
5706 	u8         reserved_at_20[0x10];
5707 	u8         op_mod[0x10];
5708 
5709 	u8         reserved_at_40[0xc0];
5710 
5711 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5712 
5713 	u8         reserved_at_300[0x100];
5714 };
5715 
5716 enum {
5717 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5718 	SCHEDULING_HIERARCHY_NIC = 0x3,
5719 };
5720 
5721 struct mlx5_ifc_query_scheduling_element_in_bits {
5722 	u8         opcode[0x10];
5723 	u8         reserved_at_10[0x10];
5724 
5725 	u8         reserved_at_20[0x10];
5726 	u8         op_mod[0x10];
5727 
5728 	u8         scheduling_hierarchy[0x8];
5729 	u8         reserved_at_48[0x18];
5730 
5731 	u8         scheduling_element_id[0x20];
5732 
5733 	u8         reserved_at_80[0x180];
5734 };
5735 
5736 struct mlx5_ifc_query_rqt_out_bits {
5737 	u8         status[0x8];
5738 	u8         reserved_at_8[0x18];
5739 
5740 	u8         syndrome[0x20];
5741 
5742 	u8         reserved_at_40[0xc0];
5743 
5744 	struct mlx5_ifc_rqtc_bits rqt_context;
5745 };
5746 
5747 struct mlx5_ifc_query_rqt_in_bits {
5748 	u8         opcode[0x10];
5749 	u8         reserved_at_10[0x10];
5750 
5751 	u8         reserved_at_20[0x10];
5752 	u8         op_mod[0x10];
5753 
5754 	u8         reserved_at_40[0x8];
5755 	u8         rqtn[0x18];
5756 
5757 	u8         reserved_at_60[0x20];
5758 };
5759 
5760 struct mlx5_ifc_query_rq_out_bits {
5761 	u8         status[0x8];
5762 	u8         reserved_at_8[0x18];
5763 
5764 	u8         syndrome[0x20];
5765 
5766 	u8         reserved_at_40[0xc0];
5767 
5768 	struct mlx5_ifc_rqc_bits rq_context;
5769 };
5770 
5771 struct mlx5_ifc_query_rq_in_bits {
5772 	u8         opcode[0x10];
5773 	u8         reserved_at_10[0x10];
5774 
5775 	u8         reserved_at_20[0x10];
5776 	u8         op_mod[0x10];
5777 
5778 	u8         reserved_at_40[0x8];
5779 	u8         rqn[0x18];
5780 
5781 	u8         reserved_at_60[0x20];
5782 };
5783 
5784 struct mlx5_ifc_query_roce_address_out_bits {
5785 	u8         status[0x8];
5786 	u8         reserved_at_8[0x18];
5787 
5788 	u8         syndrome[0x20];
5789 
5790 	u8         reserved_at_40[0x40];
5791 
5792 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5793 };
5794 
5795 struct mlx5_ifc_query_roce_address_in_bits {
5796 	u8         opcode[0x10];
5797 	u8         reserved_at_10[0x10];
5798 
5799 	u8         reserved_at_20[0x10];
5800 	u8         op_mod[0x10];
5801 
5802 	u8         roce_address_index[0x10];
5803 	u8         reserved_at_50[0xc];
5804 	u8	   vhca_port_num[0x4];
5805 
5806 	u8         reserved_at_60[0x20];
5807 };
5808 
5809 struct mlx5_ifc_query_rmp_out_bits {
5810 	u8         status[0x8];
5811 	u8         reserved_at_8[0x18];
5812 
5813 	u8         syndrome[0x20];
5814 
5815 	u8         reserved_at_40[0xc0];
5816 
5817 	struct mlx5_ifc_rmpc_bits rmp_context;
5818 };
5819 
5820 struct mlx5_ifc_query_rmp_in_bits {
5821 	u8         opcode[0x10];
5822 	u8         reserved_at_10[0x10];
5823 
5824 	u8         reserved_at_20[0x10];
5825 	u8         op_mod[0x10];
5826 
5827 	u8         reserved_at_40[0x8];
5828 	u8         rmpn[0x18];
5829 
5830 	u8         reserved_at_60[0x20];
5831 };
5832 
5833 struct mlx5_ifc_cqe_error_syndrome_bits {
5834 	u8         hw_error_syndrome[0x8];
5835 	u8         hw_syndrome_type[0x4];
5836 	u8         reserved_at_c[0x4];
5837 	u8         vendor_error_syndrome[0x8];
5838 	u8         syndrome[0x8];
5839 };
5840 
5841 struct mlx5_ifc_qp_context_extension_bits {
5842 	u8         reserved_at_0[0x60];
5843 
5844 	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5845 
5846 	u8         reserved_at_80[0x580];
5847 };
5848 
5849 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5850 	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5851 
5852 	u8         pas[0][0x40];
5853 };
5854 
5855 struct mlx5_ifc_qp_pas_list_in_bits {
5856 	struct mlx5_ifc_cmd_pas_bits pas[0];
5857 };
5858 
5859 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5860 	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5861 	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5862 };
5863 
5864 struct mlx5_ifc_query_qp_out_bits {
5865 	u8         status[0x8];
5866 	u8         reserved_at_8[0x18];
5867 
5868 	u8         syndrome[0x20];
5869 
5870 	u8         reserved_at_40[0x40];
5871 
5872 	u8         opt_param_mask[0x20];
5873 
5874 	u8         ece[0x20];
5875 
5876 	struct mlx5_ifc_qpc_bits qpc;
5877 
5878 	u8         reserved_at_800[0x80];
5879 
5880 	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5881 };
5882 
5883 struct mlx5_ifc_query_qp_in_bits {
5884 	u8         opcode[0x10];
5885 	u8         reserved_at_10[0x10];
5886 
5887 	u8         reserved_at_20[0x10];
5888 	u8         op_mod[0x10];
5889 
5890 	u8         qpc_ext[0x1];
5891 	u8         reserved_at_41[0x7];
5892 	u8         qpn[0x18];
5893 
5894 	u8         reserved_at_60[0x20];
5895 };
5896 
5897 struct mlx5_ifc_query_q_counter_out_bits {
5898 	u8         status[0x8];
5899 	u8         reserved_at_8[0x18];
5900 
5901 	u8         syndrome[0x20];
5902 
5903 	u8         reserved_at_40[0x40];
5904 
5905 	u8         rx_write_requests[0x20];
5906 
5907 	u8         reserved_at_a0[0x20];
5908 
5909 	u8         rx_read_requests[0x20];
5910 
5911 	u8         reserved_at_e0[0x20];
5912 
5913 	u8         rx_atomic_requests[0x20];
5914 
5915 	u8         reserved_at_120[0x20];
5916 
5917 	u8         rx_dct_connect[0x20];
5918 
5919 	u8         reserved_at_160[0x20];
5920 
5921 	u8         out_of_buffer[0x20];
5922 
5923 	u8         reserved_at_1a0[0x20];
5924 
5925 	u8         out_of_sequence[0x20];
5926 
5927 	u8         reserved_at_1e0[0x20];
5928 
5929 	u8         duplicate_request[0x20];
5930 
5931 	u8         reserved_at_220[0x20];
5932 
5933 	u8         rnr_nak_retry_err[0x20];
5934 
5935 	u8         reserved_at_260[0x20];
5936 
5937 	u8         packet_seq_err[0x20];
5938 
5939 	u8         reserved_at_2a0[0x20];
5940 
5941 	u8         implied_nak_seq_err[0x20];
5942 
5943 	u8         reserved_at_2e0[0x20];
5944 
5945 	u8         local_ack_timeout_err[0x20];
5946 
5947 	u8         reserved_at_320[0x60];
5948 
5949 	u8         req_rnr_retries_exceeded[0x20];
5950 
5951 	u8         reserved_at_3a0[0x20];
5952 
5953 	u8         resp_local_length_error[0x20];
5954 
5955 	u8         req_local_length_error[0x20];
5956 
5957 	u8         resp_local_qp_error[0x20];
5958 
5959 	u8         local_operation_error[0x20];
5960 
5961 	u8         resp_local_protection[0x20];
5962 
5963 	u8         req_local_protection[0x20];
5964 
5965 	u8         resp_cqe_error[0x20];
5966 
5967 	u8         req_cqe_error[0x20];
5968 
5969 	u8         req_mw_binding[0x20];
5970 
5971 	u8         req_bad_response[0x20];
5972 
5973 	u8         req_remote_invalid_request[0x20];
5974 
5975 	u8         resp_remote_invalid_request[0x20];
5976 
5977 	u8         req_remote_access_errors[0x20];
5978 
5979 	u8	   resp_remote_access_errors[0x20];
5980 
5981 	u8         req_remote_operation_errors[0x20];
5982 
5983 	u8         req_transport_retries_exceeded[0x20];
5984 
5985 	u8         cq_overflow[0x20];
5986 
5987 	u8         resp_cqe_flush_error[0x20];
5988 
5989 	u8         req_cqe_flush_error[0x20];
5990 
5991 	u8         reserved_at_620[0x20];
5992 
5993 	u8         roce_adp_retrans[0x20];
5994 
5995 	u8         roce_adp_retrans_to[0x20];
5996 
5997 	u8         roce_slow_restart[0x20];
5998 
5999 	u8         roce_slow_restart_cnps[0x20];
6000 
6001 	u8         roce_slow_restart_trans[0x20];
6002 
6003 	u8         reserved_at_6e0[0x120];
6004 };
6005 
6006 struct mlx5_ifc_query_q_counter_in_bits {
6007 	u8         opcode[0x10];
6008 	u8         reserved_at_10[0x10];
6009 
6010 	u8         reserved_at_20[0x10];
6011 	u8         op_mod[0x10];
6012 
6013 	u8         other_vport[0x1];
6014 	u8         reserved_at_41[0xf];
6015 	u8         vport_number[0x10];
6016 
6017 	u8         reserved_at_60[0x60];
6018 
6019 	u8         clear[0x1];
6020 	u8         aggregate[0x1];
6021 	u8         reserved_at_c2[0x1e];
6022 
6023 	u8         reserved_at_e0[0x18];
6024 	u8         counter_set_id[0x8];
6025 };
6026 
6027 struct mlx5_ifc_query_pages_out_bits {
6028 	u8         status[0x8];
6029 	u8         reserved_at_8[0x18];
6030 
6031 	u8         syndrome[0x20];
6032 
6033 	u8         embedded_cpu_function[0x1];
6034 	u8         reserved_at_41[0xf];
6035 	u8         function_id[0x10];
6036 
6037 	u8         num_pages[0x20];
6038 };
6039 
6040 enum {
6041 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
6042 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
6043 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
6044 };
6045 
6046 struct mlx5_ifc_query_pages_in_bits {
6047 	u8         opcode[0x10];
6048 	u8         reserved_at_10[0x10];
6049 
6050 	u8         reserved_at_20[0x10];
6051 	u8         op_mod[0x10];
6052 
6053 	u8         embedded_cpu_function[0x1];
6054 	u8         reserved_at_41[0xf];
6055 	u8         function_id[0x10];
6056 
6057 	u8         reserved_at_60[0x20];
6058 };
6059 
6060 struct mlx5_ifc_query_nic_vport_context_out_bits {
6061 	u8         status[0x8];
6062 	u8         reserved_at_8[0x18];
6063 
6064 	u8         syndrome[0x20];
6065 
6066 	u8         reserved_at_40[0x40];
6067 
6068 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6069 };
6070 
6071 struct mlx5_ifc_query_nic_vport_context_in_bits {
6072 	u8         opcode[0x10];
6073 	u8         reserved_at_10[0x10];
6074 
6075 	u8         reserved_at_20[0x10];
6076 	u8         op_mod[0x10];
6077 
6078 	u8         other_vport[0x1];
6079 	u8         reserved_at_41[0xf];
6080 	u8         vport_number[0x10];
6081 
6082 	u8         reserved_at_60[0x5];
6083 	u8         allowed_list_type[0x3];
6084 	u8         reserved_at_68[0x18];
6085 };
6086 
6087 struct mlx5_ifc_query_mkey_out_bits {
6088 	u8         status[0x8];
6089 	u8         reserved_at_8[0x18];
6090 
6091 	u8         syndrome[0x20];
6092 
6093 	u8         reserved_at_40[0x40];
6094 
6095 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6096 
6097 	u8         reserved_at_280[0x600];
6098 
6099 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
6100 
6101 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
6102 };
6103 
6104 struct mlx5_ifc_query_mkey_in_bits {
6105 	u8         opcode[0x10];
6106 	u8         reserved_at_10[0x10];
6107 
6108 	u8         reserved_at_20[0x10];
6109 	u8         op_mod[0x10];
6110 
6111 	u8         reserved_at_40[0x8];
6112 	u8         mkey_index[0x18];
6113 
6114 	u8         pg_access[0x1];
6115 	u8         reserved_at_61[0x1f];
6116 };
6117 
6118 struct mlx5_ifc_query_mad_demux_out_bits {
6119 	u8         status[0x8];
6120 	u8         reserved_at_8[0x18];
6121 
6122 	u8         syndrome[0x20];
6123 
6124 	u8         reserved_at_40[0x40];
6125 
6126 	u8         mad_dumux_parameters_block[0x20];
6127 };
6128 
6129 struct mlx5_ifc_query_mad_demux_in_bits {
6130 	u8         opcode[0x10];
6131 	u8         reserved_at_10[0x10];
6132 
6133 	u8         reserved_at_20[0x10];
6134 	u8         op_mod[0x10];
6135 
6136 	u8         reserved_at_40[0x40];
6137 };
6138 
6139 struct mlx5_ifc_query_l2_table_entry_out_bits {
6140 	u8         status[0x8];
6141 	u8         reserved_at_8[0x18];
6142 
6143 	u8         syndrome[0x20];
6144 
6145 	u8         reserved_at_40[0xa0];
6146 
6147 	u8         reserved_at_e0[0x13];
6148 	u8         vlan_valid[0x1];
6149 	u8         vlan[0xc];
6150 
6151 	struct mlx5_ifc_mac_address_layout_bits mac_address;
6152 
6153 	u8         reserved_at_140[0xc0];
6154 };
6155 
6156 struct mlx5_ifc_query_l2_table_entry_in_bits {
6157 	u8         opcode[0x10];
6158 	u8         reserved_at_10[0x10];
6159 
6160 	u8         reserved_at_20[0x10];
6161 	u8         op_mod[0x10];
6162 
6163 	u8         reserved_at_40[0x60];
6164 
6165 	u8         reserved_at_a0[0x8];
6166 	u8         table_index[0x18];
6167 
6168 	u8         reserved_at_c0[0x140];
6169 };
6170 
6171 struct mlx5_ifc_query_issi_out_bits {
6172 	u8         status[0x8];
6173 	u8         reserved_at_8[0x18];
6174 
6175 	u8         syndrome[0x20];
6176 
6177 	u8         reserved_at_40[0x10];
6178 	u8         current_issi[0x10];
6179 
6180 	u8         reserved_at_60[0xa0];
6181 
6182 	u8         reserved_at_100[76][0x8];
6183 	u8         supported_issi_dw0[0x20];
6184 };
6185 
6186 struct mlx5_ifc_query_issi_in_bits {
6187 	u8         opcode[0x10];
6188 	u8         reserved_at_10[0x10];
6189 
6190 	u8         reserved_at_20[0x10];
6191 	u8         op_mod[0x10];
6192 
6193 	u8         reserved_at_40[0x40];
6194 };
6195 
6196 struct mlx5_ifc_set_driver_version_out_bits {
6197 	u8         status[0x8];
6198 	u8         reserved_0[0x18];
6199 
6200 	u8         syndrome[0x20];
6201 	u8         reserved_1[0x40];
6202 };
6203 
6204 struct mlx5_ifc_set_driver_version_in_bits {
6205 	u8         opcode[0x10];
6206 	u8         reserved_0[0x10];
6207 
6208 	u8         reserved_1[0x10];
6209 	u8         op_mod[0x10];
6210 
6211 	u8         reserved_2[0x40];
6212 	u8         driver_version[64][0x8];
6213 };
6214 
6215 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
6216 	u8         status[0x8];
6217 	u8         reserved_at_8[0x18];
6218 
6219 	u8         syndrome[0x20];
6220 
6221 	u8         reserved_at_40[0x40];
6222 
6223 	struct mlx5_ifc_pkey_bits pkey[];
6224 };
6225 
6226 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
6227 	u8         opcode[0x10];
6228 	u8         reserved_at_10[0x10];
6229 
6230 	u8         reserved_at_20[0x10];
6231 	u8         op_mod[0x10];
6232 
6233 	u8         other_vport[0x1];
6234 	u8         reserved_at_41[0xb];
6235 	u8         port_num[0x4];
6236 	u8         vport_number[0x10];
6237 
6238 	u8         reserved_at_60[0x10];
6239 	u8         pkey_index[0x10];
6240 };
6241 
6242 enum {
6243 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
6244 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
6245 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
6246 };
6247 
6248 struct mlx5_ifc_query_hca_vport_gid_out_bits {
6249 	u8         status[0x8];
6250 	u8         reserved_at_8[0x18];
6251 
6252 	u8         syndrome[0x20];
6253 
6254 	u8         reserved_at_40[0x20];
6255 
6256 	u8         gids_num[0x10];
6257 	u8         reserved_at_70[0x10];
6258 
6259 	struct mlx5_ifc_array128_auto_bits gid[];
6260 };
6261 
6262 struct mlx5_ifc_query_hca_vport_gid_in_bits {
6263 	u8         opcode[0x10];
6264 	u8         reserved_at_10[0x10];
6265 
6266 	u8         reserved_at_20[0x10];
6267 	u8         op_mod[0x10];
6268 
6269 	u8         other_vport[0x1];
6270 	u8         reserved_at_41[0xb];
6271 	u8         port_num[0x4];
6272 	u8         vport_number[0x10];
6273 
6274 	u8         reserved_at_60[0x10];
6275 	u8         gid_index[0x10];
6276 };
6277 
6278 struct mlx5_ifc_query_hca_vport_context_out_bits {
6279 	u8         status[0x8];
6280 	u8         reserved_at_8[0x18];
6281 
6282 	u8         syndrome[0x20];
6283 
6284 	u8         reserved_at_40[0x40];
6285 
6286 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6287 };
6288 
6289 struct mlx5_ifc_query_hca_vport_context_in_bits {
6290 	u8         opcode[0x10];
6291 	u8         reserved_at_10[0x10];
6292 
6293 	u8         reserved_at_20[0x10];
6294 	u8         op_mod[0x10];
6295 
6296 	u8         other_vport[0x1];
6297 	u8         reserved_at_41[0xb];
6298 	u8         port_num[0x4];
6299 	u8         vport_number[0x10];
6300 
6301 	u8         reserved_at_60[0x20];
6302 };
6303 
6304 struct mlx5_ifc_query_hca_cap_out_bits {
6305 	u8         status[0x8];
6306 	u8         reserved_at_8[0x18];
6307 
6308 	u8         syndrome[0x20];
6309 
6310 	u8         reserved_at_40[0x40];
6311 
6312 	union mlx5_ifc_hca_cap_union_bits capability;
6313 };
6314 
6315 struct mlx5_ifc_query_hca_cap_in_bits {
6316 	u8         opcode[0x10];
6317 	u8         reserved_at_10[0x10];
6318 
6319 	u8         reserved_at_20[0x10];
6320 	u8         op_mod[0x10];
6321 
6322 	u8         other_function[0x1];
6323 	u8         ec_vf_function[0x1];
6324 	u8         reserved_at_42[0xe];
6325 	u8         function_id[0x10];
6326 
6327 	u8         reserved_at_60[0x20];
6328 };
6329 
6330 struct mlx5_ifc_other_hca_cap_bits {
6331 	u8         roce[0x1];
6332 	u8         reserved_at_1[0x27f];
6333 };
6334 
6335 struct mlx5_ifc_query_other_hca_cap_out_bits {
6336 	u8         status[0x8];
6337 	u8         reserved_at_8[0x18];
6338 
6339 	u8         syndrome[0x20];
6340 
6341 	u8         reserved_at_40[0x40];
6342 
6343 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6344 };
6345 
6346 struct mlx5_ifc_query_other_hca_cap_in_bits {
6347 	u8         opcode[0x10];
6348 	u8         reserved_at_10[0x10];
6349 
6350 	u8         reserved_at_20[0x10];
6351 	u8         op_mod[0x10];
6352 
6353 	u8         reserved_at_40[0x10];
6354 	u8         function_id[0x10];
6355 
6356 	u8         reserved_at_60[0x20];
6357 };
6358 
6359 struct mlx5_ifc_modify_other_hca_cap_out_bits {
6360 	u8         status[0x8];
6361 	u8         reserved_at_8[0x18];
6362 
6363 	u8         syndrome[0x20];
6364 
6365 	u8         reserved_at_40[0x40];
6366 };
6367 
6368 struct mlx5_ifc_modify_other_hca_cap_in_bits {
6369 	u8         opcode[0x10];
6370 	u8         reserved_at_10[0x10];
6371 
6372 	u8         reserved_at_20[0x10];
6373 	u8         op_mod[0x10];
6374 
6375 	u8         reserved_at_40[0x10];
6376 	u8         function_id[0x10];
6377 	u8         field_select[0x20];
6378 
6379 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6380 };
6381 
6382 struct mlx5_ifc_sw_owner_icm_root_params_bits {
6383 	u8         sw_owner_icm_root_1[0x40];
6384 
6385 	u8         sw_owner_icm_root_0[0x40];
6386 };
6387 
6388 struct mlx5_ifc_rtc_params_bits {
6389 	u8         rtc_id_0[0x20];
6390 
6391 	u8         rtc_id_1[0x20];
6392 
6393 	u8         reserved_at_40[0x40];
6394 };
6395 
6396 struct mlx5_ifc_flow_table_context_bits {
6397 	u8         reformat_en[0x1];
6398 	u8         decap_en[0x1];
6399 	u8         sw_owner[0x1];
6400 	u8         termination_table[0x1];
6401 	u8         table_miss_action[0x4];
6402 	u8         level[0x8];
6403 	u8         rtc_valid[0x1];
6404 	u8         reserved_at_11[0x7];
6405 	u8         log_size[0x8];
6406 
6407 	u8         reserved_at_20[0x8];
6408 	u8         table_miss_id[0x18];
6409 
6410 	u8         reserved_at_40[0x8];
6411 	u8         lag_master_next_table_id[0x18];
6412 
6413 	u8         reserved_at_60[0x60];
6414 
6415 	union {
6416 		struct mlx5_ifc_sw_owner_icm_root_params_bits sws;
6417 		struct mlx5_ifc_rtc_params_bits hws;
6418 	};
6419 };
6420 
6421 struct mlx5_ifc_query_flow_table_out_bits {
6422 	u8         status[0x8];
6423 	u8         reserved_at_8[0x18];
6424 
6425 	u8         syndrome[0x20];
6426 
6427 	u8         reserved_at_40[0x80];
6428 
6429 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6430 };
6431 
6432 struct mlx5_ifc_query_flow_table_in_bits {
6433 	u8         opcode[0x10];
6434 	u8         reserved_at_10[0x10];
6435 
6436 	u8         reserved_at_20[0x10];
6437 	u8         op_mod[0x10];
6438 
6439 	u8         reserved_at_40[0x40];
6440 
6441 	u8         table_type[0x8];
6442 	u8         reserved_at_88[0x18];
6443 
6444 	u8         reserved_at_a0[0x8];
6445 	u8         table_id[0x18];
6446 
6447 	u8         reserved_at_c0[0x140];
6448 };
6449 
6450 struct mlx5_ifc_query_fte_out_bits {
6451 	u8         status[0x8];
6452 	u8         reserved_at_8[0x18];
6453 
6454 	u8         syndrome[0x20];
6455 
6456 	u8         reserved_at_40[0x1c0];
6457 
6458 	struct mlx5_ifc_flow_context_bits flow_context;
6459 };
6460 
6461 struct mlx5_ifc_query_fte_in_bits {
6462 	u8         opcode[0x10];
6463 	u8         reserved_at_10[0x10];
6464 
6465 	u8         reserved_at_20[0x10];
6466 	u8         op_mod[0x10];
6467 
6468 	u8         reserved_at_40[0x40];
6469 
6470 	u8         table_type[0x8];
6471 	u8         reserved_at_88[0x18];
6472 
6473 	u8         reserved_at_a0[0x8];
6474 	u8         table_id[0x18];
6475 
6476 	u8         reserved_at_c0[0x40];
6477 
6478 	u8         flow_index[0x20];
6479 
6480 	u8         reserved_at_120[0xe0];
6481 };
6482 
6483 struct mlx5_ifc_match_definer_format_0_bits {
6484 	u8         reserved_at_0[0x100];
6485 
6486 	u8         metadata_reg_c_0[0x20];
6487 
6488 	u8         metadata_reg_c_1[0x20];
6489 
6490 	u8         outer_dmac_47_16[0x20];
6491 
6492 	u8         outer_dmac_15_0[0x10];
6493 	u8         outer_ethertype[0x10];
6494 
6495 	u8         reserved_at_180[0x1];
6496 	u8         sx_sniffer[0x1];
6497 	u8         functional_lb[0x1];
6498 	u8         outer_ip_frag[0x1];
6499 	u8         outer_qp_type[0x2];
6500 	u8         outer_encap_type[0x2];
6501 	u8         port_number[0x2];
6502 	u8         outer_l3_type[0x2];
6503 	u8         outer_l4_type[0x2];
6504 	u8         outer_first_vlan_type[0x2];
6505 	u8         outer_first_vlan_prio[0x3];
6506 	u8         outer_first_vlan_cfi[0x1];
6507 	u8         outer_first_vlan_vid[0xc];
6508 
6509 	u8         outer_l4_type_ext[0x4];
6510 	u8         reserved_at_1a4[0x2];
6511 	u8         outer_ipsec_layer[0x2];
6512 	u8         outer_l2_type[0x2];
6513 	u8         force_lb[0x1];
6514 	u8         outer_l2_ok[0x1];
6515 	u8         outer_l3_ok[0x1];
6516 	u8         outer_l4_ok[0x1];
6517 	u8         outer_second_vlan_type[0x2];
6518 	u8         outer_second_vlan_prio[0x3];
6519 	u8         outer_second_vlan_cfi[0x1];
6520 	u8         outer_second_vlan_vid[0xc];
6521 
6522 	u8         outer_smac_47_16[0x20];
6523 
6524 	u8         outer_smac_15_0[0x10];
6525 	u8         inner_ipv4_checksum_ok[0x1];
6526 	u8         inner_l4_checksum_ok[0x1];
6527 	u8         outer_ipv4_checksum_ok[0x1];
6528 	u8         outer_l4_checksum_ok[0x1];
6529 	u8         inner_l3_ok[0x1];
6530 	u8         inner_l4_ok[0x1];
6531 	u8         outer_l3_ok_duplicate[0x1];
6532 	u8         outer_l4_ok_duplicate[0x1];
6533 	u8         outer_tcp_cwr[0x1];
6534 	u8         outer_tcp_ece[0x1];
6535 	u8         outer_tcp_urg[0x1];
6536 	u8         outer_tcp_ack[0x1];
6537 	u8         outer_tcp_psh[0x1];
6538 	u8         outer_tcp_rst[0x1];
6539 	u8         outer_tcp_syn[0x1];
6540 	u8         outer_tcp_fin[0x1];
6541 };
6542 
6543 struct mlx5_ifc_match_definer_format_22_bits {
6544 	u8         reserved_at_0[0x100];
6545 
6546 	u8         outer_ip_src_addr[0x20];
6547 
6548 	u8         outer_ip_dest_addr[0x20];
6549 
6550 	u8         outer_l4_sport[0x10];
6551 	u8         outer_l4_dport[0x10];
6552 
6553 	u8         reserved_at_160[0x1];
6554 	u8         sx_sniffer[0x1];
6555 	u8         functional_lb[0x1];
6556 	u8         outer_ip_frag[0x1];
6557 	u8         outer_qp_type[0x2];
6558 	u8         outer_encap_type[0x2];
6559 	u8         port_number[0x2];
6560 	u8         outer_l3_type[0x2];
6561 	u8         outer_l4_type[0x2];
6562 	u8         outer_first_vlan_type[0x2];
6563 	u8         outer_first_vlan_prio[0x3];
6564 	u8         outer_first_vlan_cfi[0x1];
6565 	u8         outer_first_vlan_vid[0xc];
6566 
6567 	u8         metadata_reg_c_0[0x20];
6568 
6569 	u8         outer_dmac_47_16[0x20];
6570 
6571 	u8         outer_smac_47_16[0x20];
6572 
6573 	u8         outer_smac_15_0[0x10];
6574 	u8         outer_dmac_15_0[0x10];
6575 };
6576 
6577 struct mlx5_ifc_match_definer_format_23_bits {
6578 	u8         reserved_at_0[0x100];
6579 
6580 	u8         inner_ip_src_addr[0x20];
6581 
6582 	u8         inner_ip_dest_addr[0x20];
6583 
6584 	u8         inner_l4_sport[0x10];
6585 	u8         inner_l4_dport[0x10];
6586 
6587 	u8         reserved_at_160[0x1];
6588 	u8         sx_sniffer[0x1];
6589 	u8         functional_lb[0x1];
6590 	u8         inner_ip_frag[0x1];
6591 	u8         inner_qp_type[0x2];
6592 	u8         inner_encap_type[0x2];
6593 	u8         port_number[0x2];
6594 	u8         inner_l3_type[0x2];
6595 	u8         inner_l4_type[0x2];
6596 	u8         inner_first_vlan_type[0x2];
6597 	u8         inner_first_vlan_prio[0x3];
6598 	u8         inner_first_vlan_cfi[0x1];
6599 	u8         inner_first_vlan_vid[0xc];
6600 
6601 	u8         tunnel_header_0[0x20];
6602 
6603 	u8         inner_dmac_47_16[0x20];
6604 
6605 	u8         inner_smac_47_16[0x20];
6606 
6607 	u8         inner_smac_15_0[0x10];
6608 	u8         inner_dmac_15_0[0x10];
6609 };
6610 
6611 struct mlx5_ifc_match_definer_format_29_bits {
6612 	u8         reserved_at_0[0xc0];
6613 
6614 	u8         outer_ip_dest_addr[0x80];
6615 
6616 	u8         outer_ip_src_addr[0x80];
6617 
6618 	u8         outer_l4_sport[0x10];
6619 	u8         outer_l4_dport[0x10];
6620 
6621 	u8         reserved_at_1e0[0x20];
6622 };
6623 
6624 struct mlx5_ifc_match_definer_format_30_bits {
6625 	u8         reserved_at_0[0xa0];
6626 
6627 	u8         outer_ip_dest_addr[0x80];
6628 
6629 	u8         outer_ip_src_addr[0x80];
6630 
6631 	u8         outer_dmac_47_16[0x20];
6632 
6633 	u8         outer_smac_47_16[0x20];
6634 
6635 	u8         outer_smac_15_0[0x10];
6636 	u8         outer_dmac_15_0[0x10];
6637 };
6638 
6639 struct mlx5_ifc_match_definer_format_31_bits {
6640 	u8         reserved_at_0[0xc0];
6641 
6642 	u8         inner_ip_dest_addr[0x80];
6643 
6644 	u8         inner_ip_src_addr[0x80];
6645 
6646 	u8         inner_l4_sport[0x10];
6647 	u8         inner_l4_dport[0x10];
6648 
6649 	u8         reserved_at_1e0[0x20];
6650 };
6651 
6652 struct mlx5_ifc_match_definer_format_32_bits {
6653 	u8         reserved_at_0[0xa0];
6654 
6655 	u8         inner_ip_dest_addr[0x80];
6656 
6657 	u8         inner_ip_src_addr[0x80];
6658 
6659 	u8         inner_dmac_47_16[0x20];
6660 
6661 	u8         inner_smac_47_16[0x20];
6662 
6663 	u8         inner_smac_15_0[0x10];
6664 	u8         inner_dmac_15_0[0x10];
6665 };
6666 
6667 enum {
6668 	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6669 };
6670 
6671 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6672 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6673 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6674 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6675 
6676 struct mlx5_ifc_match_definer_match_mask_bits {
6677 	u8         reserved_at_1c0[5][0x20];
6678 	u8         match_dw_8[0x20];
6679 	u8         match_dw_7[0x20];
6680 	u8         match_dw_6[0x20];
6681 	u8         match_dw_5[0x20];
6682 	u8         match_dw_4[0x20];
6683 	u8         match_dw_3[0x20];
6684 	u8         match_dw_2[0x20];
6685 	u8         match_dw_1[0x20];
6686 	u8         match_dw_0[0x20];
6687 
6688 	u8         match_byte_7[0x8];
6689 	u8         match_byte_6[0x8];
6690 	u8         match_byte_5[0x8];
6691 	u8         match_byte_4[0x8];
6692 
6693 	u8         match_byte_3[0x8];
6694 	u8         match_byte_2[0x8];
6695 	u8         match_byte_1[0x8];
6696 	u8         match_byte_0[0x8];
6697 };
6698 
6699 struct mlx5_ifc_match_definer_bits {
6700 	u8         modify_field_select[0x40];
6701 
6702 	u8         reserved_at_40[0x40];
6703 
6704 	u8         reserved_at_80[0x10];
6705 	u8         format_id[0x10];
6706 
6707 	u8         reserved_at_a0[0x60];
6708 
6709 	u8         format_select_dw3[0x8];
6710 	u8         format_select_dw2[0x8];
6711 	u8         format_select_dw1[0x8];
6712 	u8         format_select_dw0[0x8];
6713 
6714 	u8         format_select_dw7[0x8];
6715 	u8         format_select_dw6[0x8];
6716 	u8         format_select_dw5[0x8];
6717 	u8         format_select_dw4[0x8];
6718 
6719 	u8         reserved_at_100[0x18];
6720 	u8         format_select_dw8[0x8];
6721 
6722 	u8         reserved_at_120[0x20];
6723 
6724 	u8         format_select_byte3[0x8];
6725 	u8         format_select_byte2[0x8];
6726 	u8         format_select_byte1[0x8];
6727 	u8         format_select_byte0[0x8];
6728 
6729 	u8         format_select_byte7[0x8];
6730 	u8         format_select_byte6[0x8];
6731 	u8         format_select_byte5[0x8];
6732 	u8         format_select_byte4[0x8];
6733 
6734 	u8         reserved_at_180[0x40];
6735 
6736 	union {
6737 		struct {
6738 			u8         match_mask[16][0x20];
6739 		};
6740 		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6741 	};
6742 };
6743 
6744 struct mlx5_ifc_general_obj_create_param_bits {
6745 	u8         alias_object[0x1];
6746 	u8         reserved_at_1[0x2];
6747 	u8         log_obj_range[0x5];
6748 	u8         reserved_at_8[0x18];
6749 };
6750 
6751 struct mlx5_ifc_general_obj_query_param_bits {
6752 	u8         alias_object[0x1];
6753 	u8         obj_offset[0x1f];
6754 };
6755 
6756 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6757 	u8         opcode[0x10];
6758 	u8         uid[0x10];
6759 
6760 	u8         vhca_tunnel_id[0x10];
6761 	u8         obj_type[0x10];
6762 
6763 	u8         obj_id[0x20];
6764 
6765 	union {
6766 		struct mlx5_ifc_general_obj_create_param_bits create;
6767 		struct mlx5_ifc_general_obj_query_param_bits query;
6768 	} op_param;
6769 };
6770 
6771 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6772 	u8         status[0x8];
6773 	u8         reserved_at_8[0x18];
6774 
6775 	u8         syndrome[0x20];
6776 
6777 	u8         obj_id[0x20];
6778 
6779 	u8         reserved_at_60[0x20];
6780 };
6781 
6782 struct mlx5_ifc_allow_other_vhca_access_in_bits {
6783 	u8 opcode[0x10];
6784 	u8 uid[0x10];
6785 	u8 reserved_at_20[0x10];
6786 	u8 op_mod[0x10];
6787 	u8 reserved_at_40[0x50];
6788 	u8 object_type_to_be_accessed[0x10];
6789 	u8 object_id_to_be_accessed[0x20];
6790 	u8 reserved_at_c0[0x40];
6791 	union {
6792 		u8 access_key_raw[0x100];
6793 		u8 access_key[8][0x20];
6794 	};
6795 };
6796 
6797 struct mlx5_ifc_allow_other_vhca_access_out_bits {
6798 	u8 status[0x8];
6799 	u8 reserved_at_8[0x18];
6800 	u8 syndrome[0x20];
6801 	u8 reserved_at_40[0x40];
6802 };
6803 
6804 struct mlx5_ifc_modify_header_arg_bits {
6805 	u8         reserved_at_0[0x80];
6806 
6807 	u8         reserved_at_80[0x8];
6808 	u8         access_pd[0x18];
6809 };
6810 
6811 struct mlx5_ifc_create_modify_header_arg_in_bits {
6812 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6813 	struct mlx5_ifc_modify_header_arg_bits arg;
6814 };
6815 
6816 struct mlx5_ifc_create_match_definer_in_bits {
6817 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6818 
6819 	struct mlx5_ifc_match_definer_bits obj_context;
6820 };
6821 
6822 struct mlx5_ifc_create_match_definer_out_bits {
6823 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6824 };
6825 
6826 struct mlx5_ifc_alias_context_bits {
6827 	u8 vhca_id_to_be_accessed[0x10];
6828 	u8 reserved_at_10[0xd];
6829 	u8 status[0x3];
6830 	u8 object_id_to_be_accessed[0x20];
6831 	u8 reserved_at_40[0x40];
6832 	union {
6833 		u8 access_key_raw[0x100];
6834 		u8 access_key[8][0x20];
6835 	};
6836 	u8 metadata[0x80];
6837 };
6838 
6839 struct mlx5_ifc_create_alias_obj_in_bits {
6840 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6841 	struct mlx5_ifc_alias_context_bits alias_ctx;
6842 };
6843 
6844 enum {
6845 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6846 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6847 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6848 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6849 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6850 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6851 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6852 };
6853 
6854 struct mlx5_ifc_query_flow_group_out_bits {
6855 	u8         status[0x8];
6856 	u8         reserved_at_8[0x18];
6857 
6858 	u8         syndrome[0x20];
6859 
6860 	u8         reserved_at_40[0xa0];
6861 
6862 	u8         start_flow_index[0x20];
6863 
6864 	u8         reserved_at_100[0x20];
6865 
6866 	u8         end_flow_index[0x20];
6867 
6868 	u8         reserved_at_140[0xa0];
6869 
6870 	u8         reserved_at_1e0[0x18];
6871 	u8         match_criteria_enable[0x8];
6872 
6873 	struct mlx5_ifc_fte_match_param_bits match_criteria;
6874 
6875 	u8         reserved_at_1200[0xe00];
6876 };
6877 
6878 struct mlx5_ifc_query_flow_group_in_bits {
6879 	u8         opcode[0x10];
6880 	u8         reserved_at_10[0x10];
6881 
6882 	u8         reserved_at_20[0x10];
6883 	u8         op_mod[0x10];
6884 
6885 	u8         reserved_at_40[0x40];
6886 
6887 	u8         table_type[0x8];
6888 	u8         reserved_at_88[0x18];
6889 
6890 	u8         reserved_at_a0[0x8];
6891 	u8         table_id[0x18];
6892 
6893 	u8         group_id[0x20];
6894 
6895 	u8         reserved_at_e0[0x120];
6896 };
6897 
6898 struct mlx5_ifc_query_flow_counter_out_bits {
6899 	u8         status[0x8];
6900 	u8         reserved_at_8[0x18];
6901 
6902 	u8         syndrome[0x20];
6903 
6904 	u8         reserved_at_40[0x40];
6905 
6906 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6907 };
6908 
6909 struct mlx5_ifc_query_flow_counter_in_bits {
6910 	u8         opcode[0x10];
6911 	u8         reserved_at_10[0x10];
6912 
6913 	u8         reserved_at_20[0x10];
6914 	u8         op_mod[0x10];
6915 
6916 	u8         reserved_at_40[0x80];
6917 
6918 	u8         clear[0x1];
6919 	u8         reserved_at_c1[0xf];
6920 	u8         num_of_counters[0x10];
6921 
6922 	u8         flow_counter_id[0x20];
6923 };
6924 
6925 struct mlx5_ifc_query_esw_vport_context_out_bits {
6926 	u8         status[0x8];
6927 	u8         reserved_at_8[0x18];
6928 
6929 	u8         syndrome[0x20];
6930 
6931 	u8         reserved_at_40[0x40];
6932 
6933 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6934 };
6935 
6936 struct mlx5_ifc_query_esw_vport_context_in_bits {
6937 	u8         opcode[0x10];
6938 	u8         reserved_at_10[0x10];
6939 
6940 	u8         reserved_at_20[0x10];
6941 	u8         op_mod[0x10];
6942 
6943 	u8         other_vport[0x1];
6944 	u8         reserved_at_41[0xf];
6945 	u8         vport_number[0x10];
6946 
6947 	u8         reserved_at_60[0x20];
6948 };
6949 
6950 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6951 	u8         status[0x8];
6952 	u8         reserved_at_8[0x18];
6953 
6954 	u8         syndrome[0x20];
6955 
6956 	u8         reserved_at_40[0x40];
6957 };
6958 
6959 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6960 	u8         reserved_at_0[0x1b];
6961 	u8         fdb_to_vport_reg_c_id[0x1];
6962 	u8         vport_cvlan_insert[0x1];
6963 	u8         vport_svlan_insert[0x1];
6964 	u8         vport_cvlan_strip[0x1];
6965 	u8         vport_svlan_strip[0x1];
6966 };
6967 
6968 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6969 	u8         opcode[0x10];
6970 	u8         reserved_at_10[0x10];
6971 
6972 	u8         reserved_at_20[0x10];
6973 	u8         op_mod[0x10];
6974 
6975 	u8         other_vport[0x1];
6976 	u8         reserved_at_41[0xf];
6977 	u8         vport_number[0x10];
6978 
6979 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6980 
6981 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6982 };
6983 
6984 struct mlx5_ifc_query_eq_out_bits {
6985 	u8         status[0x8];
6986 	u8         reserved_at_8[0x18];
6987 
6988 	u8         syndrome[0x20];
6989 
6990 	u8         reserved_at_40[0x40];
6991 
6992 	struct mlx5_ifc_eqc_bits eq_context_entry;
6993 
6994 	u8         reserved_at_280[0x40];
6995 
6996 	u8         event_bitmask[0x40];
6997 
6998 	u8         reserved_at_300[0x580];
6999 
7000 	u8         pas[][0x40];
7001 };
7002 
7003 struct mlx5_ifc_query_eq_in_bits {
7004 	u8         opcode[0x10];
7005 	u8         reserved_at_10[0x10];
7006 
7007 	u8         reserved_at_20[0x10];
7008 	u8         op_mod[0x10];
7009 
7010 	u8         reserved_at_40[0x18];
7011 	u8         eq_number[0x8];
7012 
7013 	u8         reserved_at_60[0x20];
7014 };
7015 
7016 struct mlx5_ifc_packet_reformat_context_in_bits {
7017 	u8         reformat_type[0x8];
7018 	u8         reserved_at_8[0x4];
7019 	u8         reformat_param_0[0x4];
7020 	u8         reserved_at_10[0x6];
7021 	u8         reformat_data_size[0xa];
7022 
7023 	u8         reformat_param_1[0x8];
7024 	u8         reserved_at_28[0x8];
7025 	u8         reformat_data[2][0x8];
7026 
7027 	u8         more_reformat_data[][0x8];
7028 };
7029 
7030 struct mlx5_ifc_query_packet_reformat_context_out_bits {
7031 	u8         status[0x8];
7032 	u8         reserved_at_8[0x18];
7033 
7034 	u8         syndrome[0x20];
7035 
7036 	u8         reserved_at_40[0xa0];
7037 
7038 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7039 };
7040 
7041 struct mlx5_ifc_query_packet_reformat_context_in_bits {
7042 	u8         opcode[0x10];
7043 	u8         reserved_at_10[0x10];
7044 
7045 	u8         reserved_at_20[0x10];
7046 	u8         op_mod[0x10];
7047 
7048 	u8         packet_reformat_id[0x20];
7049 
7050 	u8         reserved_at_60[0xa0];
7051 };
7052 
7053 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7054 	u8         status[0x8];
7055 	u8         reserved_at_8[0x18];
7056 
7057 	u8         syndrome[0x20];
7058 
7059 	u8         packet_reformat_id[0x20];
7060 
7061 	u8         reserved_at_60[0x20];
7062 };
7063 
7064 enum {
7065 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
7066 	MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2,
7067 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
7068 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
7069 };
7070 
7071 enum mlx5_reformat_ctx_type {
7072 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
7073 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
7074 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
7075 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
7076 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
7077 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
7078 	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
7079 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
7080 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
7081 	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
7082 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
7083 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
7084 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
7085 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
7086 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
7087 	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
7088 	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
7089 };
7090 
7091 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7092 	u8         opcode[0x10];
7093 	u8         reserved_at_10[0x10];
7094 
7095 	u8         reserved_at_20[0x10];
7096 	u8         op_mod[0x10];
7097 
7098 	u8         reserved_at_40[0xa0];
7099 
7100 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7101 };
7102 
7103 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7104 	u8         status[0x8];
7105 	u8         reserved_at_8[0x18];
7106 
7107 	u8         syndrome[0x20];
7108 
7109 	u8         reserved_at_40[0x40];
7110 };
7111 
7112 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7113 	u8         opcode[0x10];
7114 	u8         reserved_at_10[0x10];
7115 
7116 	u8         reserved_20[0x10];
7117 	u8         op_mod[0x10];
7118 
7119 	u8         packet_reformat_id[0x20];
7120 
7121 	u8         reserved_60[0x20];
7122 };
7123 
7124 struct mlx5_ifc_set_action_in_bits {
7125 	u8         action_type[0x4];
7126 	u8         field[0xc];
7127 	u8         reserved_at_10[0x3];
7128 	u8         offset[0x5];
7129 	u8         reserved_at_18[0x3];
7130 	u8         length[0x5];
7131 
7132 	u8         data[0x20];
7133 };
7134 
7135 struct mlx5_ifc_add_action_in_bits {
7136 	u8         action_type[0x4];
7137 	u8         field[0xc];
7138 	u8         reserved_at_10[0x10];
7139 
7140 	u8         data[0x20];
7141 };
7142 
7143 struct mlx5_ifc_copy_action_in_bits {
7144 	u8         action_type[0x4];
7145 	u8         src_field[0xc];
7146 	u8         reserved_at_10[0x3];
7147 	u8         src_offset[0x5];
7148 	u8         reserved_at_18[0x3];
7149 	u8         length[0x5];
7150 
7151 	u8         reserved_at_20[0x4];
7152 	u8         dst_field[0xc];
7153 	u8         reserved_at_30[0x3];
7154 	u8         dst_offset[0x5];
7155 	u8         reserved_at_38[0x8];
7156 };
7157 
7158 union mlx5_ifc_set_add_copy_action_in_auto_bits {
7159 	struct mlx5_ifc_set_action_in_bits  set_action_in;
7160 	struct mlx5_ifc_add_action_in_bits  add_action_in;
7161 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
7162 	u8         reserved_at_0[0x40];
7163 };
7164 
7165 enum {
7166 	MLX5_ACTION_TYPE_SET   = 0x1,
7167 	MLX5_ACTION_TYPE_ADD   = 0x2,
7168 	MLX5_ACTION_TYPE_COPY  = 0x3,
7169 };
7170 
7171 enum {
7172 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
7173 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
7174 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
7175 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
7176 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
7177 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
7178 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
7179 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
7180 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
7181 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
7182 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
7183 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
7184 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
7185 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
7186 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
7187 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
7188 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
7189 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
7190 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
7191 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
7192 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
7193 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
7194 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
7195 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
7196 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
7197 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
7198 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
7199 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
7200 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
7201 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
7202 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
7203 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
7204 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
7205 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
7206 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
7207 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
7208 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
7209 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
7210 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
7211 };
7212 
7213 struct mlx5_ifc_alloc_modify_header_context_out_bits {
7214 	u8         status[0x8];
7215 	u8         reserved_at_8[0x18];
7216 
7217 	u8         syndrome[0x20];
7218 
7219 	u8         modify_header_id[0x20];
7220 
7221 	u8         reserved_at_60[0x20];
7222 };
7223 
7224 struct mlx5_ifc_alloc_modify_header_context_in_bits {
7225 	u8         opcode[0x10];
7226 	u8         reserved_at_10[0x10];
7227 
7228 	u8         reserved_at_20[0x10];
7229 	u8         op_mod[0x10];
7230 
7231 	u8         reserved_at_40[0x20];
7232 
7233 	u8         table_type[0x8];
7234 	u8         reserved_at_68[0x10];
7235 	u8         num_of_actions[0x8];
7236 
7237 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
7238 };
7239 
7240 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
7241 	u8         status[0x8];
7242 	u8         reserved_at_8[0x18];
7243 
7244 	u8         syndrome[0x20];
7245 
7246 	u8         reserved_at_40[0x40];
7247 };
7248 
7249 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
7250 	u8         opcode[0x10];
7251 	u8         reserved_at_10[0x10];
7252 
7253 	u8         reserved_at_20[0x10];
7254 	u8         op_mod[0x10];
7255 
7256 	u8         modify_header_id[0x20];
7257 
7258 	u8         reserved_at_60[0x20];
7259 };
7260 
7261 struct mlx5_ifc_query_modify_header_context_in_bits {
7262 	u8         opcode[0x10];
7263 	u8         uid[0x10];
7264 
7265 	u8         reserved_at_20[0x10];
7266 	u8         op_mod[0x10];
7267 
7268 	u8         modify_header_id[0x20];
7269 
7270 	u8         reserved_at_60[0xa0];
7271 };
7272 
7273 struct mlx5_ifc_query_dct_out_bits {
7274 	u8         status[0x8];
7275 	u8         reserved_at_8[0x18];
7276 
7277 	u8         syndrome[0x20];
7278 
7279 	u8         reserved_at_40[0x40];
7280 
7281 	struct mlx5_ifc_dctc_bits dct_context_entry;
7282 
7283 	u8         reserved_at_280[0x180];
7284 };
7285 
7286 struct mlx5_ifc_query_dct_in_bits {
7287 	u8         opcode[0x10];
7288 	u8         reserved_at_10[0x10];
7289 
7290 	u8         reserved_at_20[0x10];
7291 	u8         op_mod[0x10];
7292 
7293 	u8         reserved_at_40[0x8];
7294 	u8         dctn[0x18];
7295 
7296 	u8         reserved_at_60[0x20];
7297 };
7298 
7299 struct mlx5_ifc_query_cq_out_bits {
7300 	u8         status[0x8];
7301 	u8         reserved_at_8[0x18];
7302 
7303 	u8         syndrome[0x20];
7304 
7305 	u8         reserved_at_40[0x40];
7306 
7307 	struct mlx5_ifc_cqc_bits cq_context;
7308 
7309 	u8         reserved_at_280[0x600];
7310 
7311 	u8         pas[][0x40];
7312 };
7313 
7314 struct mlx5_ifc_query_cq_in_bits {
7315 	u8         opcode[0x10];
7316 	u8         reserved_at_10[0x10];
7317 
7318 	u8         reserved_at_20[0x10];
7319 	u8         op_mod[0x10];
7320 
7321 	u8         reserved_at_40[0x8];
7322 	u8         cqn[0x18];
7323 
7324 	u8         reserved_at_60[0x20];
7325 };
7326 
7327 struct mlx5_ifc_query_cong_status_out_bits {
7328 	u8         status[0x8];
7329 	u8         reserved_at_8[0x18];
7330 
7331 	u8         syndrome[0x20];
7332 
7333 	u8         reserved_at_40[0x20];
7334 
7335 	u8         enable[0x1];
7336 	u8         tag_enable[0x1];
7337 	u8         reserved_at_62[0x1e];
7338 };
7339 
7340 struct mlx5_ifc_query_cong_status_in_bits {
7341 	u8         opcode[0x10];
7342 	u8         reserved_at_10[0x10];
7343 
7344 	u8         reserved_at_20[0x10];
7345 	u8         op_mod[0x10];
7346 
7347 	u8         reserved_at_40[0x18];
7348 	u8         priority[0x4];
7349 	u8         cong_protocol[0x4];
7350 
7351 	u8         reserved_at_60[0x20];
7352 };
7353 
7354 struct mlx5_ifc_query_cong_statistics_out_bits {
7355 	u8         status[0x8];
7356 	u8         reserved_at_8[0x18];
7357 
7358 	u8         syndrome[0x20];
7359 
7360 	u8         reserved_at_40[0x40];
7361 
7362 	u8         rp_cur_flows[0x20];
7363 
7364 	u8         sum_flows[0x20];
7365 
7366 	u8         rp_cnp_ignored_high[0x20];
7367 
7368 	u8         rp_cnp_ignored_low[0x20];
7369 
7370 	u8         rp_cnp_handled_high[0x20];
7371 
7372 	u8         rp_cnp_handled_low[0x20];
7373 
7374 	u8         reserved_at_140[0x100];
7375 
7376 	u8         time_stamp_high[0x20];
7377 
7378 	u8         time_stamp_low[0x20];
7379 
7380 	u8         accumulators_period[0x20];
7381 
7382 	u8         np_ecn_marked_roce_packets_high[0x20];
7383 
7384 	u8         np_ecn_marked_roce_packets_low[0x20];
7385 
7386 	u8         np_cnp_sent_high[0x20];
7387 
7388 	u8         np_cnp_sent_low[0x20];
7389 
7390 	u8         reserved_at_320[0x560];
7391 };
7392 
7393 struct mlx5_ifc_query_cong_statistics_in_bits {
7394 	u8         opcode[0x10];
7395 	u8         reserved_at_10[0x10];
7396 
7397 	u8         reserved_at_20[0x10];
7398 	u8         op_mod[0x10];
7399 
7400 	u8         clear[0x1];
7401 	u8         reserved_at_41[0x1f];
7402 
7403 	u8         reserved_at_60[0x20];
7404 };
7405 
7406 struct mlx5_ifc_query_cong_params_out_bits {
7407 	u8         status[0x8];
7408 	u8         reserved_at_8[0x18];
7409 
7410 	u8         syndrome[0x20];
7411 
7412 	u8         reserved_at_40[0x40];
7413 
7414 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7415 };
7416 
7417 struct mlx5_ifc_query_cong_params_in_bits {
7418 	u8         opcode[0x10];
7419 	u8         reserved_at_10[0x10];
7420 
7421 	u8         reserved_at_20[0x10];
7422 	u8         op_mod[0x10];
7423 
7424 	u8         reserved_at_40[0x1c];
7425 	u8         cong_protocol[0x4];
7426 
7427 	u8         reserved_at_60[0x20];
7428 };
7429 
7430 struct mlx5_ifc_query_adapter_out_bits {
7431 	u8         status[0x8];
7432 	u8         reserved_at_8[0x18];
7433 
7434 	u8         syndrome[0x20];
7435 
7436 	u8         reserved_at_40[0x40];
7437 
7438 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7439 };
7440 
7441 struct mlx5_ifc_query_adapter_in_bits {
7442 	u8         opcode[0x10];
7443 	u8         reserved_at_10[0x10];
7444 
7445 	u8         reserved_at_20[0x10];
7446 	u8         op_mod[0x10];
7447 
7448 	u8         reserved_at_40[0x40];
7449 };
7450 
7451 struct mlx5_ifc_qp_2rst_out_bits {
7452 	u8         status[0x8];
7453 	u8         reserved_at_8[0x18];
7454 
7455 	u8         syndrome[0x20];
7456 
7457 	u8         reserved_at_40[0x40];
7458 };
7459 
7460 struct mlx5_ifc_qp_2rst_in_bits {
7461 	u8         opcode[0x10];
7462 	u8         uid[0x10];
7463 
7464 	u8         reserved_at_20[0x10];
7465 	u8         op_mod[0x10];
7466 
7467 	u8         reserved_at_40[0x8];
7468 	u8         qpn[0x18];
7469 
7470 	u8         reserved_at_60[0x20];
7471 };
7472 
7473 struct mlx5_ifc_qp_2err_out_bits {
7474 	u8         status[0x8];
7475 	u8         reserved_at_8[0x18];
7476 
7477 	u8         syndrome[0x20];
7478 
7479 	u8         reserved_at_40[0x40];
7480 };
7481 
7482 struct mlx5_ifc_qp_2err_in_bits {
7483 	u8         opcode[0x10];
7484 	u8         uid[0x10];
7485 
7486 	u8         reserved_at_20[0x10];
7487 	u8         op_mod[0x10];
7488 
7489 	u8         reserved_at_40[0x8];
7490 	u8         qpn[0x18];
7491 
7492 	u8         reserved_at_60[0x20];
7493 };
7494 
7495 struct mlx5_ifc_trans_page_fault_info_bits {
7496 	u8         error[0x1];
7497 	u8         reserved_at_1[0x4];
7498 	u8         page_fault_type[0x3];
7499 	u8         wq_number[0x18];
7500 
7501 	u8         reserved_at_20[0x8];
7502 	u8         fault_token[0x18];
7503 };
7504 
7505 struct mlx5_ifc_mem_page_fault_info_bits {
7506 	u8          error[0x1];
7507 	u8          reserved_at_1[0xf];
7508 	u8          fault_token_47_32[0x10];
7509 
7510 	u8          fault_token_31_0[0x20];
7511 };
7512 
7513 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits {
7514 	struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info;
7515 	struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info;
7516 	u8          reserved_at_0[0x40];
7517 };
7518 
7519 struct mlx5_ifc_page_fault_resume_out_bits {
7520 	u8         status[0x8];
7521 	u8         reserved_at_8[0x18];
7522 
7523 	u8         syndrome[0x20];
7524 
7525 	u8         reserved_at_40[0x40];
7526 };
7527 
7528 struct mlx5_ifc_page_fault_resume_in_bits {
7529 	u8         opcode[0x10];
7530 	u8         reserved_at_10[0x10];
7531 
7532 	u8         reserved_at_20[0x10];
7533 	u8         op_mod[0x10];
7534 
7535 	union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits
7536 		page_fault_info;
7537 };
7538 
7539 struct mlx5_ifc_nop_out_bits {
7540 	u8         status[0x8];
7541 	u8         reserved_at_8[0x18];
7542 
7543 	u8         syndrome[0x20];
7544 
7545 	u8         reserved_at_40[0x40];
7546 };
7547 
7548 struct mlx5_ifc_nop_in_bits {
7549 	u8         opcode[0x10];
7550 	u8         reserved_at_10[0x10];
7551 
7552 	u8         reserved_at_20[0x10];
7553 	u8         op_mod[0x10];
7554 
7555 	u8         reserved_at_40[0x40];
7556 };
7557 
7558 struct mlx5_ifc_modify_vport_state_out_bits {
7559 	u8         status[0x8];
7560 	u8         reserved_at_8[0x18];
7561 
7562 	u8         syndrome[0x20];
7563 
7564 	u8         reserved_at_40[0x40];
7565 };
7566 
7567 struct mlx5_ifc_modify_vport_state_in_bits {
7568 	u8         opcode[0x10];
7569 	u8         reserved_at_10[0x10];
7570 
7571 	u8         reserved_at_20[0x10];
7572 	u8         op_mod[0x10];
7573 
7574 	u8         other_vport[0x1];
7575 	u8         reserved_at_41[0xf];
7576 	u8         vport_number[0x10];
7577 
7578 	u8         reserved_at_60[0x18];
7579 	u8         admin_state[0x4];
7580 	u8         reserved_at_7c[0x4];
7581 };
7582 
7583 struct mlx5_ifc_modify_tis_out_bits {
7584 	u8         status[0x8];
7585 	u8         reserved_at_8[0x18];
7586 
7587 	u8         syndrome[0x20];
7588 
7589 	u8         reserved_at_40[0x40];
7590 };
7591 
7592 struct mlx5_ifc_modify_tis_bitmask_bits {
7593 	u8         reserved_at_0[0x20];
7594 
7595 	u8         reserved_at_20[0x1d];
7596 	u8         lag_tx_port_affinity[0x1];
7597 	u8         strict_lag_tx_port_affinity[0x1];
7598 	u8         prio[0x1];
7599 };
7600 
7601 struct mlx5_ifc_modify_tis_in_bits {
7602 	u8         opcode[0x10];
7603 	u8         uid[0x10];
7604 
7605 	u8         reserved_at_20[0x10];
7606 	u8         op_mod[0x10];
7607 
7608 	u8         reserved_at_40[0x8];
7609 	u8         tisn[0x18];
7610 
7611 	u8         reserved_at_60[0x20];
7612 
7613 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7614 
7615 	u8         reserved_at_c0[0x40];
7616 
7617 	struct mlx5_ifc_tisc_bits ctx;
7618 };
7619 
7620 struct mlx5_ifc_modify_tir_bitmask_bits {
7621 	u8	   reserved_at_0[0x20];
7622 
7623 	u8         reserved_at_20[0x1b];
7624 	u8         self_lb_en[0x1];
7625 	u8         reserved_at_3c[0x1];
7626 	u8         hash[0x1];
7627 	u8         reserved_at_3e[0x1];
7628 	u8         packet_merge[0x1];
7629 };
7630 
7631 struct mlx5_ifc_modify_tir_out_bits {
7632 	u8         status[0x8];
7633 	u8         reserved_at_8[0x18];
7634 
7635 	u8         syndrome[0x20];
7636 
7637 	u8         reserved_at_40[0x40];
7638 };
7639 
7640 struct mlx5_ifc_modify_tir_in_bits {
7641 	u8         opcode[0x10];
7642 	u8         uid[0x10];
7643 
7644 	u8         reserved_at_20[0x10];
7645 	u8         op_mod[0x10];
7646 
7647 	u8         reserved_at_40[0x8];
7648 	u8         tirn[0x18];
7649 
7650 	u8         reserved_at_60[0x20];
7651 
7652 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7653 
7654 	u8         reserved_at_c0[0x40];
7655 
7656 	struct mlx5_ifc_tirc_bits ctx;
7657 };
7658 
7659 struct mlx5_ifc_modify_sq_out_bits {
7660 	u8         status[0x8];
7661 	u8         reserved_at_8[0x18];
7662 
7663 	u8         syndrome[0x20];
7664 
7665 	u8         reserved_at_40[0x40];
7666 };
7667 
7668 struct mlx5_ifc_modify_sq_in_bits {
7669 	u8         opcode[0x10];
7670 	u8         uid[0x10];
7671 
7672 	u8         reserved_at_20[0x10];
7673 	u8         op_mod[0x10];
7674 
7675 	u8         sq_state[0x4];
7676 	u8         reserved_at_44[0x4];
7677 	u8         sqn[0x18];
7678 
7679 	u8         reserved_at_60[0x20];
7680 
7681 	u8         modify_bitmask[0x40];
7682 
7683 	u8         reserved_at_c0[0x40];
7684 
7685 	struct mlx5_ifc_sqc_bits ctx;
7686 };
7687 
7688 struct mlx5_ifc_modify_scheduling_element_out_bits {
7689 	u8         status[0x8];
7690 	u8         reserved_at_8[0x18];
7691 
7692 	u8         syndrome[0x20];
7693 
7694 	u8         reserved_at_40[0x1c0];
7695 };
7696 
7697 enum {
7698 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7699 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7700 };
7701 
7702 struct mlx5_ifc_modify_scheduling_element_in_bits {
7703 	u8         opcode[0x10];
7704 	u8         reserved_at_10[0x10];
7705 
7706 	u8         reserved_at_20[0x10];
7707 	u8         op_mod[0x10];
7708 
7709 	u8         scheduling_hierarchy[0x8];
7710 	u8         reserved_at_48[0x18];
7711 
7712 	u8         scheduling_element_id[0x20];
7713 
7714 	u8         reserved_at_80[0x20];
7715 
7716 	u8         modify_bitmask[0x20];
7717 
7718 	u8         reserved_at_c0[0x40];
7719 
7720 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7721 
7722 	u8         reserved_at_300[0x100];
7723 };
7724 
7725 struct mlx5_ifc_modify_rqt_out_bits {
7726 	u8         status[0x8];
7727 	u8         reserved_at_8[0x18];
7728 
7729 	u8         syndrome[0x20];
7730 
7731 	u8         reserved_at_40[0x40];
7732 };
7733 
7734 struct mlx5_ifc_rqt_bitmask_bits {
7735 	u8	   reserved_at_0[0x20];
7736 
7737 	u8         reserved_at_20[0x1f];
7738 	u8         rqn_list[0x1];
7739 };
7740 
7741 struct mlx5_ifc_modify_rqt_in_bits {
7742 	u8         opcode[0x10];
7743 	u8         uid[0x10];
7744 
7745 	u8         reserved_at_20[0x10];
7746 	u8         op_mod[0x10];
7747 
7748 	u8         reserved_at_40[0x8];
7749 	u8         rqtn[0x18];
7750 
7751 	u8         reserved_at_60[0x20];
7752 
7753 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7754 
7755 	u8         reserved_at_c0[0x40];
7756 
7757 	struct mlx5_ifc_rqtc_bits ctx;
7758 };
7759 
7760 struct mlx5_ifc_modify_rq_out_bits {
7761 	u8         status[0x8];
7762 	u8         reserved_at_8[0x18];
7763 
7764 	u8         syndrome[0x20];
7765 
7766 	u8         reserved_at_40[0x40];
7767 };
7768 
7769 enum {
7770 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7771 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7772 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7773 };
7774 
7775 struct mlx5_ifc_modify_rq_in_bits {
7776 	u8         opcode[0x10];
7777 	u8         uid[0x10];
7778 
7779 	u8         reserved_at_20[0x10];
7780 	u8         op_mod[0x10];
7781 
7782 	u8         rq_state[0x4];
7783 	u8         reserved_at_44[0x4];
7784 	u8         rqn[0x18];
7785 
7786 	u8         reserved_at_60[0x20];
7787 
7788 	u8         modify_bitmask[0x40];
7789 
7790 	u8         reserved_at_c0[0x40];
7791 
7792 	struct mlx5_ifc_rqc_bits ctx;
7793 };
7794 
7795 struct mlx5_ifc_modify_rmp_out_bits {
7796 	u8         status[0x8];
7797 	u8         reserved_at_8[0x18];
7798 
7799 	u8         syndrome[0x20];
7800 
7801 	u8         reserved_at_40[0x40];
7802 };
7803 
7804 struct mlx5_ifc_rmp_bitmask_bits {
7805 	u8	   reserved_at_0[0x20];
7806 
7807 	u8         reserved_at_20[0x1f];
7808 	u8         lwm[0x1];
7809 };
7810 
7811 struct mlx5_ifc_modify_rmp_in_bits {
7812 	u8         opcode[0x10];
7813 	u8         uid[0x10];
7814 
7815 	u8         reserved_at_20[0x10];
7816 	u8         op_mod[0x10];
7817 
7818 	u8         rmp_state[0x4];
7819 	u8         reserved_at_44[0x4];
7820 	u8         rmpn[0x18];
7821 
7822 	u8         reserved_at_60[0x20];
7823 
7824 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7825 
7826 	u8         reserved_at_c0[0x40];
7827 
7828 	struct mlx5_ifc_rmpc_bits ctx;
7829 };
7830 
7831 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7832 	u8         status[0x8];
7833 	u8         reserved_at_8[0x18];
7834 
7835 	u8         syndrome[0x20];
7836 
7837 	u8         reserved_at_40[0x40];
7838 };
7839 
7840 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7841 	u8         reserved_at_0[0x12];
7842 	u8	   affiliation[0x1];
7843 	u8	   reserved_at_13[0x1];
7844 	u8         disable_uc_local_lb[0x1];
7845 	u8         disable_mc_local_lb[0x1];
7846 	u8         node_guid[0x1];
7847 	u8         port_guid[0x1];
7848 	u8         min_inline[0x1];
7849 	u8         mtu[0x1];
7850 	u8         change_event[0x1];
7851 	u8         promisc[0x1];
7852 	u8         permanent_address[0x1];
7853 	u8         addresses_list[0x1];
7854 	u8         roce_en[0x1];
7855 	u8         reserved_at_1f[0x1];
7856 };
7857 
7858 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7859 	u8         opcode[0x10];
7860 	u8         reserved_at_10[0x10];
7861 
7862 	u8         reserved_at_20[0x10];
7863 	u8         op_mod[0x10];
7864 
7865 	u8         other_vport[0x1];
7866 	u8         reserved_at_41[0xf];
7867 	u8         vport_number[0x10];
7868 
7869 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7870 
7871 	u8         reserved_at_80[0x780];
7872 
7873 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7874 };
7875 
7876 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7877 	u8         status[0x8];
7878 	u8         reserved_at_8[0x18];
7879 
7880 	u8         syndrome[0x20];
7881 
7882 	u8         reserved_at_40[0x40];
7883 };
7884 
7885 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7886 	u8         opcode[0x10];
7887 	u8         reserved_at_10[0x10];
7888 
7889 	u8         reserved_at_20[0x10];
7890 	u8         op_mod[0x10];
7891 
7892 	u8         other_vport[0x1];
7893 	u8         reserved_at_41[0xb];
7894 	u8         port_num[0x4];
7895 	u8         vport_number[0x10];
7896 
7897 	u8         reserved_at_60[0x20];
7898 
7899 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7900 };
7901 
7902 struct mlx5_ifc_modify_cq_out_bits {
7903 	u8         status[0x8];
7904 	u8         reserved_at_8[0x18];
7905 
7906 	u8         syndrome[0x20];
7907 
7908 	u8         reserved_at_40[0x40];
7909 };
7910 
7911 enum {
7912 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7913 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7914 };
7915 
7916 struct mlx5_ifc_modify_cq_in_bits {
7917 	u8         opcode[0x10];
7918 	u8         uid[0x10];
7919 
7920 	u8         reserved_at_20[0x10];
7921 	u8         op_mod[0x10];
7922 
7923 	u8         reserved_at_40[0x8];
7924 	u8         cqn[0x18];
7925 
7926 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7927 
7928 	struct mlx5_ifc_cqc_bits cq_context;
7929 
7930 	u8         reserved_at_280[0x60];
7931 
7932 	u8         cq_umem_valid[0x1];
7933 	u8         reserved_at_2e1[0x1f];
7934 
7935 	u8         reserved_at_300[0x580];
7936 
7937 	u8         pas[][0x40];
7938 };
7939 
7940 struct mlx5_ifc_modify_cong_status_out_bits {
7941 	u8         status[0x8];
7942 	u8         reserved_at_8[0x18];
7943 
7944 	u8         syndrome[0x20];
7945 
7946 	u8         reserved_at_40[0x40];
7947 };
7948 
7949 struct mlx5_ifc_modify_cong_status_in_bits {
7950 	u8         opcode[0x10];
7951 	u8         reserved_at_10[0x10];
7952 
7953 	u8         reserved_at_20[0x10];
7954 	u8         op_mod[0x10];
7955 
7956 	u8         reserved_at_40[0x18];
7957 	u8         priority[0x4];
7958 	u8         cong_protocol[0x4];
7959 
7960 	u8         enable[0x1];
7961 	u8         tag_enable[0x1];
7962 	u8         reserved_at_62[0x1e];
7963 };
7964 
7965 struct mlx5_ifc_modify_cong_params_out_bits {
7966 	u8         status[0x8];
7967 	u8         reserved_at_8[0x18];
7968 
7969 	u8         syndrome[0x20];
7970 
7971 	u8         reserved_at_40[0x40];
7972 };
7973 
7974 struct mlx5_ifc_modify_cong_params_in_bits {
7975 	u8         opcode[0x10];
7976 	u8         reserved_at_10[0x10];
7977 
7978 	u8         reserved_at_20[0x10];
7979 	u8         op_mod[0x10];
7980 
7981 	u8         reserved_at_40[0x1c];
7982 	u8         cong_protocol[0x4];
7983 
7984 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7985 
7986 	u8         reserved_at_80[0x80];
7987 
7988 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7989 };
7990 
7991 struct mlx5_ifc_manage_pages_out_bits {
7992 	u8         status[0x8];
7993 	u8         reserved_at_8[0x18];
7994 
7995 	u8         syndrome[0x20];
7996 
7997 	u8         output_num_entries[0x20];
7998 
7999 	u8         reserved_at_60[0x20];
8000 
8001 	u8         pas[][0x40];
8002 };
8003 
8004 enum {
8005 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
8006 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
8007 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
8008 };
8009 
8010 struct mlx5_ifc_manage_pages_in_bits {
8011 	u8         opcode[0x10];
8012 	u8         reserved_at_10[0x10];
8013 
8014 	u8         reserved_at_20[0x10];
8015 	u8         op_mod[0x10];
8016 
8017 	u8         embedded_cpu_function[0x1];
8018 	u8         reserved_at_41[0xf];
8019 	u8         function_id[0x10];
8020 
8021 	u8         input_num_entries[0x20];
8022 
8023 	u8         pas[][0x40];
8024 };
8025 
8026 struct mlx5_ifc_mad_ifc_out_bits {
8027 	u8         status[0x8];
8028 	u8         reserved_at_8[0x18];
8029 
8030 	u8         syndrome[0x20];
8031 
8032 	u8         reserved_at_40[0x40];
8033 
8034 	u8         response_mad_packet[256][0x8];
8035 };
8036 
8037 struct mlx5_ifc_mad_ifc_in_bits {
8038 	u8         opcode[0x10];
8039 	u8         reserved_at_10[0x10];
8040 
8041 	u8         reserved_at_20[0x10];
8042 	u8         op_mod[0x10];
8043 
8044 	u8         remote_lid[0x10];
8045 	u8         plane_index[0x8];
8046 	u8         port[0x8];
8047 
8048 	u8         reserved_at_60[0x20];
8049 
8050 	u8         mad[256][0x8];
8051 };
8052 
8053 struct mlx5_ifc_init_hca_out_bits {
8054 	u8         status[0x8];
8055 	u8         reserved_at_8[0x18];
8056 
8057 	u8         syndrome[0x20];
8058 
8059 	u8         reserved_at_40[0x40];
8060 };
8061 
8062 struct mlx5_ifc_init_hca_in_bits {
8063 	u8         opcode[0x10];
8064 	u8         reserved_at_10[0x10];
8065 
8066 	u8         reserved_at_20[0x10];
8067 	u8         op_mod[0x10];
8068 
8069 	u8         reserved_at_40[0x20];
8070 
8071 	u8         reserved_at_60[0x2];
8072 	u8         sw_vhca_id[0xe];
8073 	u8         reserved_at_70[0x10];
8074 
8075 	u8	   sw_owner_id[4][0x20];
8076 };
8077 
8078 struct mlx5_ifc_init2rtr_qp_out_bits {
8079 	u8         status[0x8];
8080 	u8         reserved_at_8[0x18];
8081 
8082 	u8         syndrome[0x20];
8083 
8084 	u8         reserved_at_40[0x20];
8085 	u8         ece[0x20];
8086 };
8087 
8088 struct mlx5_ifc_init2rtr_qp_in_bits {
8089 	u8         opcode[0x10];
8090 	u8         uid[0x10];
8091 
8092 	u8         reserved_at_20[0x10];
8093 	u8         op_mod[0x10];
8094 
8095 	u8         reserved_at_40[0x8];
8096 	u8         qpn[0x18];
8097 
8098 	u8         reserved_at_60[0x20];
8099 
8100 	u8         opt_param_mask[0x20];
8101 
8102 	u8         ece[0x20];
8103 
8104 	struct mlx5_ifc_qpc_bits qpc;
8105 
8106 	u8         reserved_at_800[0x80];
8107 };
8108 
8109 struct mlx5_ifc_init2init_qp_out_bits {
8110 	u8         status[0x8];
8111 	u8         reserved_at_8[0x18];
8112 
8113 	u8         syndrome[0x20];
8114 
8115 	u8         reserved_at_40[0x20];
8116 	u8         ece[0x20];
8117 };
8118 
8119 struct mlx5_ifc_init2init_qp_in_bits {
8120 	u8         opcode[0x10];
8121 	u8         uid[0x10];
8122 
8123 	u8         reserved_at_20[0x10];
8124 	u8         op_mod[0x10];
8125 
8126 	u8         reserved_at_40[0x8];
8127 	u8         qpn[0x18];
8128 
8129 	u8         reserved_at_60[0x20];
8130 
8131 	u8         opt_param_mask[0x20];
8132 
8133 	u8         ece[0x20];
8134 
8135 	struct mlx5_ifc_qpc_bits qpc;
8136 
8137 	u8         reserved_at_800[0x80];
8138 };
8139 
8140 struct mlx5_ifc_get_dropped_packet_log_out_bits {
8141 	u8         status[0x8];
8142 	u8         reserved_at_8[0x18];
8143 
8144 	u8         syndrome[0x20];
8145 
8146 	u8         reserved_at_40[0x40];
8147 
8148 	u8         packet_headers_log[128][0x8];
8149 
8150 	u8         packet_syndrome[64][0x8];
8151 };
8152 
8153 struct mlx5_ifc_get_dropped_packet_log_in_bits {
8154 	u8         opcode[0x10];
8155 	u8         reserved_at_10[0x10];
8156 
8157 	u8         reserved_at_20[0x10];
8158 	u8         op_mod[0x10];
8159 
8160 	u8         reserved_at_40[0x40];
8161 };
8162 
8163 struct mlx5_ifc_gen_eqe_in_bits {
8164 	u8         opcode[0x10];
8165 	u8         reserved_at_10[0x10];
8166 
8167 	u8         reserved_at_20[0x10];
8168 	u8         op_mod[0x10];
8169 
8170 	u8         reserved_at_40[0x18];
8171 	u8         eq_number[0x8];
8172 
8173 	u8         reserved_at_60[0x20];
8174 
8175 	u8         eqe[64][0x8];
8176 };
8177 
8178 struct mlx5_ifc_gen_eq_out_bits {
8179 	u8         status[0x8];
8180 	u8         reserved_at_8[0x18];
8181 
8182 	u8         syndrome[0x20];
8183 
8184 	u8         reserved_at_40[0x40];
8185 };
8186 
8187 struct mlx5_ifc_enable_hca_out_bits {
8188 	u8         status[0x8];
8189 	u8         reserved_at_8[0x18];
8190 
8191 	u8         syndrome[0x20];
8192 
8193 	u8         reserved_at_40[0x20];
8194 };
8195 
8196 struct mlx5_ifc_enable_hca_in_bits {
8197 	u8         opcode[0x10];
8198 	u8         reserved_at_10[0x10];
8199 
8200 	u8         reserved_at_20[0x10];
8201 	u8         op_mod[0x10];
8202 
8203 	u8         embedded_cpu_function[0x1];
8204 	u8         reserved_at_41[0xf];
8205 	u8         function_id[0x10];
8206 
8207 	u8         reserved_at_60[0x20];
8208 };
8209 
8210 struct mlx5_ifc_drain_dct_out_bits {
8211 	u8         status[0x8];
8212 	u8         reserved_at_8[0x18];
8213 
8214 	u8         syndrome[0x20];
8215 
8216 	u8         reserved_at_40[0x40];
8217 };
8218 
8219 struct mlx5_ifc_drain_dct_in_bits {
8220 	u8         opcode[0x10];
8221 	u8         uid[0x10];
8222 
8223 	u8         reserved_at_20[0x10];
8224 	u8         op_mod[0x10];
8225 
8226 	u8         reserved_at_40[0x8];
8227 	u8         dctn[0x18];
8228 
8229 	u8         reserved_at_60[0x20];
8230 };
8231 
8232 struct mlx5_ifc_disable_hca_out_bits {
8233 	u8         status[0x8];
8234 	u8         reserved_at_8[0x18];
8235 
8236 	u8         syndrome[0x20];
8237 
8238 	u8         reserved_at_40[0x20];
8239 };
8240 
8241 struct mlx5_ifc_disable_hca_in_bits {
8242 	u8         opcode[0x10];
8243 	u8         reserved_at_10[0x10];
8244 
8245 	u8         reserved_at_20[0x10];
8246 	u8         op_mod[0x10];
8247 
8248 	u8         embedded_cpu_function[0x1];
8249 	u8         reserved_at_41[0xf];
8250 	u8         function_id[0x10];
8251 
8252 	u8         reserved_at_60[0x20];
8253 };
8254 
8255 struct mlx5_ifc_detach_from_mcg_out_bits {
8256 	u8         status[0x8];
8257 	u8         reserved_at_8[0x18];
8258 
8259 	u8         syndrome[0x20];
8260 
8261 	u8         reserved_at_40[0x40];
8262 };
8263 
8264 struct mlx5_ifc_detach_from_mcg_in_bits {
8265 	u8         opcode[0x10];
8266 	u8         uid[0x10];
8267 
8268 	u8         reserved_at_20[0x10];
8269 	u8         op_mod[0x10];
8270 
8271 	u8         reserved_at_40[0x8];
8272 	u8         qpn[0x18];
8273 
8274 	u8         reserved_at_60[0x20];
8275 
8276 	u8         multicast_gid[16][0x8];
8277 };
8278 
8279 struct mlx5_ifc_destroy_xrq_out_bits {
8280 	u8         status[0x8];
8281 	u8         reserved_at_8[0x18];
8282 
8283 	u8         syndrome[0x20];
8284 
8285 	u8         reserved_at_40[0x40];
8286 };
8287 
8288 struct mlx5_ifc_destroy_xrq_in_bits {
8289 	u8         opcode[0x10];
8290 	u8         uid[0x10];
8291 
8292 	u8         reserved_at_20[0x10];
8293 	u8         op_mod[0x10];
8294 
8295 	u8         reserved_at_40[0x8];
8296 	u8         xrqn[0x18];
8297 
8298 	u8         reserved_at_60[0x20];
8299 };
8300 
8301 struct mlx5_ifc_destroy_xrc_srq_out_bits {
8302 	u8         status[0x8];
8303 	u8         reserved_at_8[0x18];
8304 
8305 	u8         syndrome[0x20];
8306 
8307 	u8         reserved_at_40[0x40];
8308 };
8309 
8310 struct mlx5_ifc_destroy_xrc_srq_in_bits {
8311 	u8         opcode[0x10];
8312 	u8         uid[0x10];
8313 
8314 	u8         reserved_at_20[0x10];
8315 	u8         op_mod[0x10];
8316 
8317 	u8         reserved_at_40[0x8];
8318 	u8         xrc_srqn[0x18];
8319 
8320 	u8         reserved_at_60[0x20];
8321 };
8322 
8323 struct mlx5_ifc_destroy_tis_out_bits {
8324 	u8         status[0x8];
8325 	u8         reserved_at_8[0x18];
8326 
8327 	u8         syndrome[0x20];
8328 
8329 	u8         reserved_at_40[0x40];
8330 };
8331 
8332 struct mlx5_ifc_destroy_tis_in_bits {
8333 	u8         opcode[0x10];
8334 	u8         uid[0x10];
8335 
8336 	u8         reserved_at_20[0x10];
8337 	u8         op_mod[0x10];
8338 
8339 	u8         reserved_at_40[0x8];
8340 	u8         tisn[0x18];
8341 
8342 	u8         reserved_at_60[0x20];
8343 };
8344 
8345 struct mlx5_ifc_destroy_tir_out_bits {
8346 	u8         status[0x8];
8347 	u8         reserved_at_8[0x18];
8348 
8349 	u8         syndrome[0x20];
8350 
8351 	u8         reserved_at_40[0x40];
8352 };
8353 
8354 struct mlx5_ifc_destroy_tir_in_bits {
8355 	u8         opcode[0x10];
8356 	u8         uid[0x10];
8357 
8358 	u8         reserved_at_20[0x10];
8359 	u8         op_mod[0x10];
8360 
8361 	u8         reserved_at_40[0x8];
8362 	u8         tirn[0x18];
8363 
8364 	u8         reserved_at_60[0x20];
8365 };
8366 
8367 struct mlx5_ifc_destroy_srq_out_bits {
8368 	u8         status[0x8];
8369 	u8         reserved_at_8[0x18];
8370 
8371 	u8         syndrome[0x20];
8372 
8373 	u8         reserved_at_40[0x40];
8374 };
8375 
8376 struct mlx5_ifc_destroy_srq_in_bits {
8377 	u8         opcode[0x10];
8378 	u8         uid[0x10];
8379 
8380 	u8         reserved_at_20[0x10];
8381 	u8         op_mod[0x10];
8382 
8383 	u8         reserved_at_40[0x8];
8384 	u8         srqn[0x18];
8385 
8386 	u8         reserved_at_60[0x20];
8387 };
8388 
8389 struct mlx5_ifc_destroy_sq_out_bits {
8390 	u8         status[0x8];
8391 	u8         reserved_at_8[0x18];
8392 
8393 	u8         syndrome[0x20];
8394 
8395 	u8         reserved_at_40[0x40];
8396 };
8397 
8398 struct mlx5_ifc_destroy_sq_in_bits {
8399 	u8         opcode[0x10];
8400 	u8         uid[0x10];
8401 
8402 	u8         reserved_at_20[0x10];
8403 	u8         op_mod[0x10];
8404 
8405 	u8         reserved_at_40[0x8];
8406 	u8         sqn[0x18];
8407 
8408 	u8         reserved_at_60[0x20];
8409 };
8410 
8411 struct mlx5_ifc_destroy_scheduling_element_out_bits {
8412 	u8         status[0x8];
8413 	u8         reserved_at_8[0x18];
8414 
8415 	u8         syndrome[0x20];
8416 
8417 	u8         reserved_at_40[0x1c0];
8418 };
8419 
8420 struct mlx5_ifc_destroy_scheduling_element_in_bits {
8421 	u8         opcode[0x10];
8422 	u8         reserved_at_10[0x10];
8423 
8424 	u8         reserved_at_20[0x10];
8425 	u8         op_mod[0x10];
8426 
8427 	u8         scheduling_hierarchy[0x8];
8428 	u8         reserved_at_48[0x18];
8429 
8430 	u8         scheduling_element_id[0x20];
8431 
8432 	u8         reserved_at_80[0x180];
8433 };
8434 
8435 struct mlx5_ifc_destroy_rqt_out_bits {
8436 	u8         status[0x8];
8437 	u8         reserved_at_8[0x18];
8438 
8439 	u8         syndrome[0x20];
8440 
8441 	u8         reserved_at_40[0x40];
8442 };
8443 
8444 struct mlx5_ifc_destroy_rqt_in_bits {
8445 	u8         opcode[0x10];
8446 	u8         uid[0x10];
8447 
8448 	u8         reserved_at_20[0x10];
8449 	u8         op_mod[0x10];
8450 
8451 	u8         reserved_at_40[0x8];
8452 	u8         rqtn[0x18];
8453 
8454 	u8         reserved_at_60[0x20];
8455 };
8456 
8457 struct mlx5_ifc_destroy_rq_out_bits {
8458 	u8         status[0x8];
8459 	u8         reserved_at_8[0x18];
8460 
8461 	u8         syndrome[0x20];
8462 
8463 	u8         reserved_at_40[0x40];
8464 };
8465 
8466 struct mlx5_ifc_destroy_rq_in_bits {
8467 	u8         opcode[0x10];
8468 	u8         uid[0x10];
8469 
8470 	u8         reserved_at_20[0x10];
8471 	u8         op_mod[0x10];
8472 
8473 	u8         reserved_at_40[0x8];
8474 	u8         rqn[0x18];
8475 
8476 	u8         reserved_at_60[0x20];
8477 };
8478 
8479 struct mlx5_ifc_set_delay_drop_params_in_bits {
8480 	u8         opcode[0x10];
8481 	u8         reserved_at_10[0x10];
8482 
8483 	u8         reserved_at_20[0x10];
8484 	u8         op_mod[0x10];
8485 
8486 	u8         reserved_at_40[0x20];
8487 
8488 	u8         reserved_at_60[0x10];
8489 	u8         delay_drop_timeout[0x10];
8490 };
8491 
8492 struct mlx5_ifc_set_delay_drop_params_out_bits {
8493 	u8         status[0x8];
8494 	u8         reserved_at_8[0x18];
8495 
8496 	u8         syndrome[0x20];
8497 
8498 	u8         reserved_at_40[0x40];
8499 };
8500 
8501 struct mlx5_ifc_destroy_rmp_out_bits {
8502 	u8         status[0x8];
8503 	u8         reserved_at_8[0x18];
8504 
8505 	u8         syndrome[0x20];
8506 
8507 	u8         reserved_at_40[0x40];
8508 };
8509 
8510 struct mlx5_ifc_destroy_rmp_in_bits {
8511 	u8         opcode[0x10];
8512 	u8         uid[0x10];
8513 
8514 	u8         reserved_at_20[0x10];
8515 	u8         op_mod[0x10];
8516 
8517 	u8         reserved_at_40[0x8];
8518 	u8         rmpn[0x18];
8519 
8520 	u8         reserved_at_60[0x20];
8521 };
8522 
8523 struct mlx5_ifc_destroy_qp_out_bits {
8524 	u8         status[0x8];
8525 	u8         reserved_at_8[0x18];
8526 
8527 	u8         syndrome[0x20];
8528 
8529 	u8         reserved_at_40[0x40];
8530 };
8531 
8532 struct mlx5_ifc_destroy_qp_in_bits {
8533 	u8         opcode[0x10];
8534 	u8         uid[0x10];
8535 
8536 	u8         reserved_at_20[0x10];
8537 	u8         op_mod[0x10];
8538 
8539 	u8         reserved_at_40[0x8];
8540 	u8         qpn[0x18];
8541 
8542 	u8         reserved_at_60[0x20];
8543 };
8544 
8545 struct mlx5_ifc_destroy_psv_out_bits {
8546 	u8         status[0x8];
8547 	u8         reserved_at_8[0x18];
8548 
8549 	u8         syndrome[0x20];
8550 
8551 	u8         reserved_at_40[0x40];
8552 };
8553 
8554 struct mlx5_ifc_destroy_psv_in_bits {
8555 	u8         opcode[0x10];
8556 	u8         reserved_at_10[0x10];
8557 
8558 	u8         reserved_at_20[0x10];
8559 	u8         op_mod[0x10];
8560 
8561 	u8         reserved_at_40[0x8];
8562 	u8         psvn[0x18];
8563 
8564 	u8         reserved_at_60[0x20];
8565 };
8566 
8567 struct mlx5_ifc_destroy_mkey_out_bits {
8568 	u8         status[0x8];
8569 	u8         reserved_at_8[0x18];
8570 
8571 	u8         syndrome[0x20];
8572 
8573 	u8         reserved_at_40[0x40];
8574 };
8575 
8576 struct mlx5_ifc_destroy_mkey_in_bits {
8577 	u8         opcode[0x10];
8578 	u8         uid[0x10];
8579 
8580 	u8         reserved_at_20[0x10];
8581 	u8         op_mod[0x10];
8582 
8583 	u8         reserved_at_40[0x8];
8584 	u8         mkey_index[0x18];
8585 
8586 	u8         reserved_at_60[0x20];
8587 };
8588 
8589 struct mlx5_ifc_destroy_flow_table_out_bits {
8590 	u8         status[0x8];
8591 	u8         reserved_at_8[0x18];
8592 
8593 	u8         syndrome[0x20];
8594 
8595 	u8         reserved_at_40[0x40];
8596 };
8597 
8598 struct mlx5_ifc_destroy_flow_table_in_bits {
8599 	u8         opcode[0x10];
8600 	u8         reserved_at_10[0x10];
8601 
8602 	u8         reserved_at_20[0x10];
8603 	u8         op_mod[0x10];
8604 
8605 	u8         other_vport[0x1];
8606 	u8         reserved_at_41[0xf];
8607 	u8         vport_number[0x10];
8608 
8609 	u8         reserved_at_60[0x20];
8610 
8611 	u8         table_type[0x8];
8612 	u8         reserved_at_88[0x18];
8613 
8614 	u8         reserved_at_a0[0x8];
8615 	u8         table_id[0x18];
8616 
8617 	u8         reserved_at_c0[0x140];
8618 };
8619 
8620 struct mlx5_ifc_destroy_flow_group_out_bits {
8621 	u8         status[0x8];
8622 	u8         reserved_at_8[0x18];
8623 
8624 	u8         syndrome[0x20];
8625 
8626 	u8         reserved_at_40[0x40];
8627 };
8628 
8629 struct mlx5_ifc_destroy_flow_group_in_bits {
8630 	u8         opcode[0x10];
8631 	u8         reserved_at_10[0x10];
8632 
8633 	u8         reserved_at_20[0x10];
8634 	u8         op_mod[0x10];
8635 
8636 	u8         other_vport[0x1];
8637 	u8         reserved_at_41[0xf];
8638 	u8         vport_number[0x10];
8639 
8640 	u8         reserved_at_60[0x20];
8641 
8642 	u8         table_type[0x8];
8643 	u8         reserved_at_88[0x18];
8644 
8645 	u8         reserved_at_a0[0x8];
8646 	u8         table_id[0x18];
8647 
8648 	u8         group_id[0x20];
8649 
8650 	u8         reserved_at_e0[0x120];
8651 };
8652 
8653 struct mlx5_ifc_destroy_eq_out_bits {
8654 	u8         status[0x8];
8655 	u8         reserved_at_8[0x18];
8656 
8657 	u8         syndrome[0x20];
8658 
8659 	u8         reserved_at_40[0x40];
8660 };
8661 
8662 struct mlx5_ifc_destroy_eq_in_bits {
8663 	u8         opcode[0x10];
8664 	u8         reserved_at_10[0x10];
8665 
8666 	u8         reserved_at_20[0x10];
8667 	u8         op_mod[0x10];
8668 
8669 	u8         reserved_at_40[0x18];
8670 	u8         eq_number[0x8];
8671 
8672 	u8         reserved_at_60[0x20];
8673 };
8674 
8675 struct mlx5_ifc_destroy_dct_out_bits {
8676 	u8         status[0x8];
8677 	u8         reserved_at_8[0x18];
8678 
8679 	u8         syndrome[0x20];
8680 
8681 	u8         reserved_at_40[0x40];
8682 };
8683 
8684 struct mlx5_ifc_destroy_dct_in_bits {
8685 	u8         opcode[0x10];
8686 	u8         uid[0x10];
8687 
8688 	u8         reserved_at_20[0x10];
8689 	u8         op_mod[0x10];
8690 
8691 	u8         reserved_at_40[0x8];
8692 	u8         dctn[0x18];
8693 
8694 	u8         reserved_at_60[0x20];
8695 };
8696 
8697 struct mlx5_ifc_destroy_cq_out_bits {
8698 	u8         status[0x8];
8699 	u8         reserved_at_8[0x18];
8700 
8701 	u8         syndrome[0x20];
8702 
8703 	u8         reserved_at_40[0x40];
8704 };
8705 
8706 struct mlx5_ifc_destroy_cq_in_bits {
8707 	u8         opcode[0x10];
8708 	u8         uid[0x10];
8709 
8710 	u8         reserved_at_20[0x10];
8711 	u8         op_mod[0x10];
8712 
8713 	u8         reserved_at_40[0x8];
8714 	u8         cqn[0x18];
8715 
8716 	u8         reserved_at_60[0x20];
8717 };
8718 
8719 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8720 	u8         status[0x8];
8721 	u8         reserved_at_8[0x18];
8722 
8723 	u8         syndrome[0x20];
8724 
8725 	u8         reserved_at_40[0x40];
8726 };
8727 
8728 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8729 	u8         opcode[0x10];
8730 	u8         reserved_at_10[0x10];
8731 
8732 	u8         reserved_at_20[0x10];
8733 	u8         op_mod[0x10];
8734 
8735 	u8         reserved_at_40[0x20];
8736 
8737 	u8         reserved_at_60[0x10];
8738 	u8         vxlan_udp_port[0x10];
8739 };
8740 
8741 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8742 	u8         status[0x8];
8743 	u8         reserved_at_8[0x18];
8744 
8745 	u8         syndrome[0x20];
8746 
8747 	u8         reserved_at_40[0x40];
8748 };
8749 
8750 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8751 	u8         opcode[0x10];
8752 	u8         reserved_at_10[0x10];
8753 
8754 	u8         reserved_at_20[0x10];
8755 	u8         op_mod[0x10];
8756 
8757 	u8         reserved_at_40[0x60];
8758 
8759 	u8         reserved_at_a0[0x8];
8760 	u8         table_index[0x18];
8761 
8762 	u8         reserved_at_c0[0x140];
8763 };
8764 
8765 struct mlx5_ifc_delete_fte_out_bits {
8766 	u8         status[0x8];
8767 	u8         reserved_at_8[0x18];
8768 
8769 	u8         syndrome[0x20];
8770 
8771 	u8         reserved_at_40[0x40];
8772 };
8773 
8774 struct mlx5_ifc_delete_fte_in_bits {
8775 	u8         opcode[0x10];
8776 	u8         reserved_at_10[0x10];
8777 
8778 	u8         reserved_at_20[0x10];
8779 	u8         op_mod[0x10];
8780 
8781 	u8         other_vport[0x1];
8782 	u8         reserved_at_41[0xf];
8783 	u8         vport_number[0x10];
8784 
8785 	u8         reserved_at_60[0x20];
8786 
8787 	u8         table_type[0x8];
8788 	u8         reserved_at_88[0x18];
8789 
8790 	u8         reserved_at_a0[0x8];
8791 	u8         table_id[0x18];
8792 
8793 	u8         reserved_at_c0[0x40];
8794 
8795 	u8         flow_index[0x20];
8796 
8797 	u8         reserved_at_120[0xe0];
8798 };
8799 
8800 struct mlx5_ifc_dealloc_xrcd_out_bits {
8801 	u8         status[0x8];
8802 	u8         reserved_at_8[0x18];
8803 
8804 	u8         syndrome[0x20];
8805 
8806 	u8         reserved_at_40[0x40];
8807 };
8808 
8809 struct mlx5_ifc_dealloc_xrcd_in_bits {
8810 	u8         opcode[0x10];
8811 	u8         uid[0x10];
8812 
8813 	u8         reserved_at_20[0x10];
8814 	u8         op_mod[0x10];
8815 
8816 	u8         reserved_at_40[0x8];
8817 	u8         xrcd[0x18];
8818 
8819 	u8         reserved_at_60[0x20];
8820 };
8821 
8822 struct mlx5_ifc_dealloc_uar_out_bits {
8823 	u8         status[0x8];
8824 	u8         reserved_at_8[0x18];
8825 
8826 	u8         syndrome[0x20];
8827 
8828 	u8         reserved_at_40[0x40];
8829 };
8830 
8831 struct mlx5_ifc_dealloc_uar_in_bits {
8832 	u8         opcode[0x10];
8833 	u8         uid[0x10];
8834 
8835 	u8         reserved_at_20[0x10];
8836 	u8         op_mod[0x10];
8837 
8838 	u8         reserved_at_40[0x8];
8839 	u8         uar[0x18];
8840 
8841 	u8         reserved_at_60[0x20];
8842 };
8843 
8844 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8845 	u8         status[0x8];
8846 	u8         reserved_at_8[0x18];
8847 
8848 	u8         syndrome[0x20];
8849 
8850 	u8         reserved_at_40[0x40];
8851 };
8852 
8853 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8854 	u8         opcode[0x10];
8855 	u8         uid[0x10];
8856 
8857 	u8         reserved_at_20[0x10];
8858 	u8         op_mod[0x10];
8859 
8860 	u8         reserved_at_40[0x8];
8861 	u8         transport_domain[0x18];
8862 
8863 	u8         reserved_at_60[0x20];
8864 };
8865 
8866 struct mlx5_ifc_dealloc_q_counter_out_bits {
8867 	u8         status[0x8];
8868 	u8         reserved_at_8[0x18];
8869 
8870 	u8         syndrome[0x20];
8871 
8872 	u8         reserved_at_40[0x40];
8873 };
8874 
8875 struct mlx5_ifc_dealloc_q_counter_in_bits {
8876 	u8         opcode[0x10];
8877 	u8         reserved_at_10[0x10];
8878 
8879 	u8         reserved_at_20[0x10];
8880 	u8         op_mod[0x10];
8881 
8882 	u8         reserved_at_40[0x18];
8883 	u8         counter_set_id[0x8];
8884 
8885 	u8         reserved_at_60[0x20];
8886 };
8887 
8888 struct mlx5_ifc_dealloc_pd_out_bits {
8889 	u8         status[0x8];
8890 	u8         reserved_at_8[0x18];
8891 
8892 	u8         syndrome[0x20];
8893 
8894 	u8         reserved_at_40[0x40];
8895 };
8896 
8897 struct mlx5_ifc_dealloc_pd_in_bits {
8898 	u8         opcode[0x10];
8899 	u8         uid[0x10];
8900 
8901 	u8         reserved_at_20[0x10];
8902 	u8         op_mod[0x10];
8903 
8904 	u8         reserved_at_40[0x8];
8905 	u8         pd[0x18];
8906 
8907 	u8         reserved_at_60[0x20];
8908 };
8909 
8910 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8911 	u8         status[0x8];
8912 	u8         reserved_at_8[0x18];
8913 
8914 	u8         syndrome[0x20];
8915 
8916 	u8         reserved_at_40[0x40];
8917 };
8918 
8919 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8920 	u8         opcode[0x10];
8921 	u8         reserved_at_10[0x10];
8922 
8923 	u8         reserved_at_20[0x10];
8924 	u8         op_mod[0x10];
8925 
8926 	u8         flow_counter_id[0x20];
8927 
8928 	u8         reserved_at_60[0x20];
8929 };
8930 
8931 struct mlx5_ifc_create_xrq_out_bits {
8932 	u8         status[0x8];
8933 	u8         reserved_at_8[0x18];
8934 
8935 	u8         syndrome[0x20];
8936 
8937 	u8         reserved_at_40[0x8];
8938 	u8         xrqn[0x18];
8939 
8940 	u8         reserved_at_60[0x20];
8941 };
8942 
8943 struct mlx5_ifc_create_xrq_in_bits {
8944 	u8         opcode[0x10];
8945 	u8         uid[0x10];
8946 
8947 	u8         reserved_at_20[0x10];
8948 	u8         op_mod[0x10];
8949 
8950 	u8         reserved_at_40[0x40];
8951 
8952 	struct mlx5_ifc_xrqc_bits xrq_context;
8953 };
8954 
8955 struct mlx5_ifc_create_xrc_srq_out_bits {
8956 	u8         status[0x8];
8957 	u8         reserved_at_8[0x18];
8958 
8959 	u8         syndrome[0x20];
8960 
8961 	u8         reserved_at_40[0x8];
8962 	u8         xrc_srqn[0x18];
8963 
8964 	u8         reserved_at_60[0x20];
8965 };
8966 
8967 struct mlx5_ifc_create_xrc_srq_in_bits {
8968 	u8         opcode[0x10];
8969 	u8         uid[0x10];
8970 
8971 	u8         reserved_at_20[0x10];
8972 	u8         op_mod[0x10];
8973 
8974 	u8         reserved_at_40[0x40];
8975 
8976 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8977 
8978 	u8         reserved_at_280[0x60];
8979 
8980 	u8         xrc_srq_umem_valid[0x1];
8981 	u8         reserved_at_2e1[0x1f];
8982 
8983 	u8         reserved_at_300[0x580];
8984 
8985 	u8         pas[][0x40];
8986 };
8987 
8988 struct mlx5_ifc_create_tis_out_bits {
8989 	u8         status[0x8];
8990 	u8         reserved_at_8[0x18];
8991 
8992 	u8         syndrome[0x20];
8993 
8994 	u8         reserved_at_40[0x8];
8995 	u8         tisn[0x18];
8996 
8997 	u8         reserved_at_60[0x20];
8998 };
8999 
9000 struct mlx5_ifc_create_tis_in_bits {
9001 	u8         opcode[0x10];
9002 	u8         uid[0x10];
9003 
9004 	u8         reserved_at_20[0x10];
9005 	u8         op_mod[0x10];
9006 
9007 	u8         reserved_at_40[0xc0];
9008 
9009 	struct mlx5_ifc_tisc_bits ctx;
9010 };
9011 
9012 struct mlx5_ifc_create_tir_out_bits {
9013 	u8         status[0x8];
9014 	u8         icm_address_63_40[0x18];
9015 
9016 	u8         syndrome[0x20];
9017 
9018 	u8         icm_address_39_32[0x8];
9019 	u8         tirn[0x18];
9020 
9021 	u8         icm_address_31_0[0x20];
9022 };
9023 
9024 struct mlx5_ifc_create_tir_in_bits {
9025 	u8         opcode[0x10];
9026 	u8         uid[0x10];
9027 
9028 	u8         reserved_at_20[0x10];
9029 	u8         op_mod[0x10];
9030 
9031 	u8         reserved_at_40[0xc0];
9032 
9033 	struct mlx5_ifc_tirc_bits ctx;
9034 };
9035 
9036 struct mlx5_ifc_create_srq_out_bits {
9037 	u8         status[0x8];
9038 	u8         reserved_at_8[0x18];
9039 
9040 	u8         syndrome[0x20];
9041 
9042 	u8         reserved_at_40[0x8];
9043 	u8         srqn[0x18];
9044 
9045 	u8         reserved_at_60[0x20];
9046 };
9047 
9048 struct mlx5_ifc_create_srq_in_bits {
9049 	u8         opcode[0x10];
9050 	u8         uid[0x10];
9051 
9052 	u8         reserved_at_20[0x10];
9053 	u8         op_mod[0x10];
9054 
9055 	u8         reserved_at_40[0x40];
9056 
9057 	struct mlx5_ifc_srqc_bits srq_context_entry;
9058 
9059 	u8         reserved_at_280[0x600];
9060 
9061 	u8         pas[][0x40];
9062 };
9063 
9064 struct mlx5_ifc_create_sq_out_bits {
9065 	u8         status[0x8];
9066 	u8         reserved_at_8[0x18];
9067 
9068 	u8         syndrome[0x20];
9069 
9070 	u8         reserved_at_40[0x8];
9071 	u8         sqn[0x18];
9072 
9073 	u8         reserved_at_60[0x20];
9074 };
9075 
9076 struct mlx5_ifc_create_sq_in_bits {
9077 	u8         opcode[0x10];
9078 	u8         uid[0x10];
9079 
9080 	u8         reserved_at_20[0x10];
9081 	u8         op_mod[0x10];
9082 
9083 	u8         reserved_at_40[0xc0];
9084 
9085 	struct mlx5_ifc_sqc_bits ctx;
9086 };
9087 
9088 struct mlx5_ifc_create_scheduling_element_out_bits {
9089 	u8         status[0x8];
9090 	u8         reserved_at_8[0x18];
9091 
9092 	u8         syndrome[0x20];
9093 
9094 	u8         reserved_at_40[0x40];
9095 
9096 	u8         scheduling_element_id[0x20];
9097 
9098 	u8         reserved_at_a0[0x160];
9099 };
9100 
9101 struct mlx5_ifc_create_scheduling_element_in_bits {
9102 	u8         opcode[0x10];
9103 	u8         reserved_at_10[0x10];
9104 
9105 	u8         reserved_at_20[0x10];
9106 	u8         op_mod[0x10];
9107 
9108 	u8         scheduling_hierarchy[0x8];
9109 	u8         reserved_at_48[0x18];
9110 
9111 	u8         reserved_at_60[0xa0];
9112 
9113 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
9114 
9115 	u8         reserved_at_300[0x100];
9116 };
9117 
9118 struct mlx5_ifc_create_rqt_out_bits {
9119 	u8         status[0x8];
9120 	u8         reserved_at_8[0x18];
9121 
9122 	u8         syndrome[0x20];
9123 
9124 	u8         reserved_at_40[0x8];
9125 	u8         rqtn[0x18];
9126 
9127 	u8         reserved_at_60[0x20];
9128 };
9129 
9130 struct mlx5_ifc_create_rqt_in_bits {
9131 	u8         opcode[0x10];
9132 	u8         uid[0x10];
9133 
9134 	u8         reserved_at_20[0x10];
9135 	u8         op_mod[0x10];
9136 
9137 	u8         reserved_at_40[0xc0];
9138 
9139 	struct mlx5_ifc_rqtc_bits rqt_context;
9140 };
9141 
9142 struct mlx5_ifc_create_rq_out_bits {
9143 	u8         status[0x8];
9144 	u8         reserved_at_8[0x18];
9145 
9146 	u8         syndrome[0x20];
9147 
9148 	u8         reserved_at_40[0x8];
9149 	u8         rqn[0x18];
9150 
9151 	u8         reserved_at_60[0x20];
9152 };
9153 
9154 struct mlx5_ifc_create_rq_in_bits {
9155 	u8         opcode[0x10];
9156 	u8         uid[0x10];
9157 
9158 	u8         reserved_at_20[0x10];
9159 	u8         op_mod[0x10];
9160 
9161 	u8         reserved_at_40[0xc0];
9162 
9163 	struct mlx5_ifc_rqc_bits ctx;
9164 };
9165 
9166 struct mlx5_ifc_create_rmp_out_bits {
9167 	u8         status[0x8];
9168 	u8         reserved_at_8[0x18];
9169 
9170 	u8         syndrome[0x20];
9171 
9172 	u8         reserved_at_40[0x8];
9173 	u8         rmpn[0x18];
9174 
9175 	u8         reserved_at_60[0x20];
9176 };
9177 
9178 struct mlx5_ifc_create_rmp_in_bits {
9179 	u8         opcode[0x10];
9180 	u8         uid[0x10];
9181 
9182 	u8         reserved_at_20[0x10];
9183 	u8         op_mod[0x10];
9184 
9185 	u8         reserved_at_40[0xc0];
9186 
9187 	struct mlx5_ifc_rmpc_bits ctx;
9188 };
9189 
9190 struct mlx5_ifc_create_qp_out_bits {
9191 	u8         status[0x8];
9192 	u8         reserved_at_8[0x18];
9193 
9194 	u8         syndrome[0x20];
9195 
9196 	u8         reserved_at_40[0x8];
9197 	u8         qpn[0x18];
9198 
9199 	u8         ece[0x20];
9200 };
9201 
9202 struct mlx5_ifc_create_qp_in_bits {
9203 	u8         opcode[0x10];
9204 	u8         uid[0x10];
9205 
9206 	u8         reserved_at_20[0x10];
9207 	u8         op_mod[0x10];
9208 
9209 	u8         qpc_ext[0x1];
9210 	u8         reserved_at_41[0x7];
9211 	u8         input_qpn[0x18];
9212 
9213 	u8         reserved_at_60[0x20];
9214 	u8         opt_param_mask[0x20];
9215 
9216 	u8         ece[0x20];
9217 
9218 	struct mlx5_ifc_qpc_bits qpc;
9219 
9220 	u8         wq_umem_offset[0x40];
9221 
9222 	u8         wq_umem_id[0x20];
9223 
9224 	u8         wq_umem_valid[0x1];
9225 	u8         reserved_at_861[0x1f];
9226 
9227 	u8         pas[][0x40];
9228 };
9229 
9230 struct mlx5_ifc_create_psv_out_bits {
9231 	u8         status[0x8];
9232 	u8         reserved_at_8[0x18];
9233 
9234 	u8         syndrome[0x20];
9235 
9236 	u8         reserved_at_40[0x40];
9237 
9238 	u8         reserved_at_80[0x8];
9239 	u8         psv0_index[0x18];
9240 
9241 	u8         reserved_at_a0[0x8];
9242 	u8         psv1_index[0x18];
9243 
9244 	u8         reserved_at_c0[0x8];
9245 	u8         psv2_index[0x18];
9246 
9247 	u8         reserved_at_e0[0x8];
9248 	u8         psv3_index[0x18];
9249 };
9250 
9251 struct mlx5_ifc_create_psv_in_bits {
9252 	u8         opcode[0x10];
9253 	u8         reserved_at_10[0x10];
9254 
9255 	u8         reserved_at_20[0x10];
9256 	u8         op_mod[0x10];
9257 
9258 	u8         num_psv[0x4];
9259 	u8         reserved_at_44[0x4];
9260 	u8         pd[0x18];
9261 
9262 	u8         reserved_at_60[0x20];
9263 };
9264 
9265 struct mlx5_ifc_create_mkey_out_bits {
9266 	u8         status[0x8];
9267 	u8         reserved_at_8[0x18];
9268 
9269 	u8         syndrome[0x20];
9270 
9271 	u8         reserved_at_40[0x8];
9272 	u8         mkey_index[0x18];
9273 
9274 	u8         reserved_at_60[0x20];
9275 };
9276 
9277 struct mlx5_ifc_create_mkey_in_bits {
9278 	u8         opcode[0x10];
9279 	u8         uid[0x10];
9280 
9281 	u8         reserved_at_20[0x10];
9282 	u8         op_mod[0x10];
9283 
9284 	u8         reserved_at_40[0x20];
9285 
9286 	u8         pg_access[0x1];
9287 	u8         mkey_umem_valid[0x1];
9288 	u8         data_direct[0x1];
9289 	u8         reserved_at_63[0x1d];
9290 
9291 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
9292 
9293 	u8         reserved_at_280[0x80];
9294 
9295 	u8         translations_octword_actual_size[0x20];
9296 
9297 	u8         reserved_at_320[0x560];
9298 
9299 	u8         klm_pas_mtt[][0x20];
9300 };
9301 
9302 enum {
9303 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
9304 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
9305 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
9306 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
9307 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
9308 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
9309 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
9310 };
9311 
9312 struct mlx5_ifc_create_flow_table_out_bits {
9313 	u8         status[0x8];
9314 	u8         icm_address_63_40[0x18];
9315 
9316 	u8         syndrome[0x20];
9317 
9318 	u8         icm_address_39_32[0x8];
9319 	u8         table_id[0x18];
9320 
9321 	u8         icm_address_31_0[0x20];
9322 };
9323 
9324 struct mlx5_ifc_create_flow_table_in_bits {
9325 	u8         opcode[0x10];
9326 	u8         uid[0x10];
9327 
9328 	u8         reserved_at_20[0x10];
9329 	u8         op_mod[0x10];
9330 
9331 	u8         other_vport[0x1];
9332 	u8         reserved_at_41[0xf];
9333 	u8         vport_number[0x10];
9334 
9335 	u8         reserved_at_60[0x20];
9336 
9337 	u8         table_type[0x8];
9338 	u8         reserved_at_88[0x18];
9339 
9340 	u8         reserved_at_a0[0x20];
9341 
9342 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
9343 };
9344 
9345 struct mlx5_ifc_create_flow_group_out_bits {
9346 	u8         status[0x8];
9347 	u8         reserved_at_8[0x18];
9348 
9349 	u8         syndrome[0x20];
9350 
9351 	u8         reserved_at_40[0x8];
9352 	u8         group_id[0x18];
9353 
9354 	u8         reserved_at_60[0x20];
9355 };
9356 
9357 enum {
9358 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
9359 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
9360 };
9361 
9362 enum {
9363 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
9364 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
9365 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
9366 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
9367 };
9368 
9369 struct mlx5_ifc_create_flow_group_in_bits {
9370 	u8         opcode[0x10];
9371 	u8         reserved_at_10[0x10];
9372 
9373 	u8         reserved_at_20[0x10];
9374 	u8         op_mod[0x10];
9375 
9376 	u8         other_vport[0x1];
9377 	u8         reserved_at_41[0xf];
9378 	u8         vport_number[0x10];
9379 
9380 	u8         reserved_at_60[0x20];
9381 
9382 	u8         table_type[0x8];
9383 	u8         reserved_at_88[0x4];
9384 	u8         group_type[0x4];
9385 	u8         reserved_at_90[0x10];
9386 
9387 	u8         reserved_at_a0[0x8];
9388 	u8         table_id[0x18];
9389 
9390 	u8         source_eswitch_owner_vhca_id_valid[0x1];
9391 
9392 	u8         reserved_at_c1[0x1f];
9393 
9394 	u8         start_flow_index[0x20];
9395 
9396 	u8         reserved_at_100[0x20];
9397 
9398 	u8         end_flow_index[0x20];
9399 
9400 	u8         reserved_at_140[0x10];
9401 	u8         match_definer_id[0x10];
9402 
9403 	u8         reserved_at_160[0x80];
9404 
9405 	u8         reserved_at_1e0[0x18];
9406 	u8         match_criteria_enable[0x8];
9407 
9408 	struct mlx5_ifc_fte_match_param_bits match_criteria;
9409 
9410 	u8         reserved_at_1200[0xe00];
9411 };
9412 
9413 struct mlx5_ifc_create_eq_out_bits {
9414 	u8         status[0x8];
9415 	u8         reserved_at_8[0x18];
9416 
9417 	u8         syndrome[0x20];
9418 
9419 	u8         reserved_at_40[0x18];
9420 	u8         eq_number[0x8];
9421 
9422 	u8         reserved_at_60[0x20];
9423 };
9424 
9425 struct mlx5_ifc_create_eq_in_bits {
9426 	u8         opcode[0x10];
9427 	u8         uid[0x10];
9428 
9429 	u8         reserved_at_20[0x10];
9430 	u8         op_mod[0x10];
9431 
9432 	u8         reserved_at_40[0x40];
9433 
9434 	struct mlx5_ifc_eqc_bits eq_context_entry;
9435 
9436 	u8         reserved_at_280[0x40];
9437 
9438 	u8         event_bitmask[4][0x40];
9439 
9440 	u8         reserved_at_3c0[0x4c0];
9441 
9442 	u8         pas[][0x40];
9443 };
9444 
9445 struct mlx5_ifc_create_dct_out_bits {
9446 	u8         status[0x8];
9447 	u8         reserved_at_8[0x18];
9448 
9449 	u8         syndrome[0x20];
9450 
9451 	u8         reserved_at_40[0x8];
9452 	u8         dctn[0x18];
9453 
9454 	u8         ece[0x20];
9455 };
9456 
9457 struct mlx5_ifc_create_dct_in_bits {
9458 	u8         opcode[0x10];
9459 	u8         uid[0x10];
9460 
9461 	u8         reserved_at_20[0x10];
9462 	u8         op_mod[0x10];
9463 
9464 	u8         reserved_at_40[0x40];
9465 
9466 	struct mlx5_ifc_dctc_bits dct_context_entry;
9467 
9468 	u8         reserved_at_280[0x180];
9469 };
9470 
9471 struct mlx5_ifc_create_cq_out_bits {
9472 	u8         status[0x8];
9473 	u8         reserved_at_8[0x18];
9474 
9475 	u8         syndrome[0x20];
9476 
9477 	u8         reserved_at_40[0x8];
9478 	u8         cqn[0x18];
9479 
9480 	u8         reserved_at_60[0x20];
9481 };
9482 
9483 struct mlx5_ifc_create_cq_in_bits {
9484 	u8         opcode[0x10];
9485 	u8         uid[0x10];
9486 
9487 	u8         reserved_at_20[0x10];
9488 	u8         op_mod[0x10];
9489 
9490 	u8         reserved_at_40[0x40];
9491 
9492 	struct mlx5_ifc_cqc_bits cq_context;
9493 
9494 	u8         reserved_at_280[0x60];
9495 
9496 	u8         cq_umem_valid[0x1];
9497 	u8         reserved_at_2e1[0x59f];
9498 
9499 	u8         pas[][0x40];
9500 };
9501 
9502 struct mlx5_ifc_config_int_moderation_out_bits {
9503 	u8         status[0x8];
9504 	u8         reserved_at_8[0x18];
9505 
9506 	u8         syndrome[0x20];
9507 
9508 	u8         reserved_at_40[0x4];
9509 	u8         min_delay[0xc];
9510 	u8         int_vector[0x10];
9511 
9512 	u8         reserved_at_60[0x20];
9513 };
9514 
9515 enum {
9516 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9517 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9518 };
9519 
9520 struct mlx5_ifc_config_int_moderation_in_bits {
9521 	u8         opcode[0x10];
9522 	u8         reserved_at_10[0x10];
9523 
9524 	u8         reserved_at_20[0x10];
9525 	u8         op_mod[0x10];
9526 
9527 	u8         reserved_at_40[0x4];
9528 	u8         min_delay[0xc];
9529 	u8         int_vector[0x10];
9530 
9531 	u8         reserved_at_60[0x20];
9532 };
9533 
9534 struct mlx5_ifc_attach_to_mcg_out_bits {
9535 	u8         status[0x8];
9536 	u8         reserved_at_8[0x18];
9537 
9538 	u8         syndrome[0x20];
9539 
9540 	u8         reserved_at_40[0x40];
9541 };
9542 
9543 struct mlx5_ifc_attach_to_mcg_in_bits {
9544 	u8         opcode[0x10];
9545 	u8         uid[0x10];
9546 
9547 	u8         reserved_at_20[0x10];
9548 	u8         op_mod[0x10];
9549 
9550 	u8         reserved_at_40[0x8];
9551 	u8         qpn[0x18];
9552 
9553 	u8         reserved_at_60[0x20];
9554 
9555 	u8         multicast_gid[16][0x8];
9556 };
9557 
9558 struct mlx5_ifc_arm_xrq_out_bits {
9559 	u8         status[0x8];
9560 	u8         reserved_at_8[0x18];
9561 
9562 	u8         syndrome[0x20];
9563 
9564 	u8         reserved_at_40[0x40];
9565 };
9566 
9567 struct mlx5_ifc_arm_xrq_in_bits {
9568 	u8         opcode[0x10];
9569 	u8         reserved_at_10[0x10];
9570 
9571 	u8         reserved_at_20[0x10];
9572 	u8         op_mod[0x10];
9573 
9574 	u8         reserved_at_40[0x8];
9575 	u8         xrqn[0x18];
9576 
9577 	u8         reserved_at_60[0x10];
9578 	u8         lwm[0x10];
9579 };
9580 
9581 struct mlx5_ifc_arm_xrc_srq_out_bits {
9582 	u8         status[0x8];
9583 	u8         reserved_at_8[0x18];
9584 
9585 	u8         syndrome[0x20];
9586 
9587 	u8         reserved_at_40[0x40];
9588 };
9589 
9590 enum {
9591 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9592 };
9593 
9594 struct mlx5_ifc_arm_xrc_srq_in_bits {
9595 	u8         opcode[0x10];
9596 	u8         uid[0x10];
9597 
9598 	u8         reserved_at_20[0x10];
9599 	u8         op_mod[0x10];
9600 
9601 	u8         reserved_at_40[0x8];
9602 	u8         xrc_srqn[0x18];
9603 
9604 	u8         reserved_at_60[0x10];
9605 	u8         lwm[0x10];
9606 };
9607 
9608 struct mlx5_ifc_arm_rq_out_bits {
9609 	u8         status[0x8];
9610 	u8         reserved_at_8[0x18];
9611 
9612 	u8         syndrome[0x20];
9613 
9614 	u8         reserved_at_40[0x40];
9615 };
9616 
9617 enum {
9618 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9619 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9620 };
9621 
9622 struct mlx5_ifc_arm_rq_in_bits {
9623 	u8         opcode[0x10];
9624 	u8         uid[0x10];
9625 
9626 	u8         reserved_at_20[0x10];
9627 	u8         op_mod[0x10];
9628 
9629 	u8         reserved_at_40[0x8];
9630 	u8         srq_number[0x18];
9631 
9632 	u8         reserved_at_60[0x10];
9633 	u8         lwm[0x10];
9634 };
9635 
9636 struct mlx5_ifc_arm_dct_out_bits {
9637 	u8         status[0x8];
9638 	u8         reserved_at_8[0x18];
9639 
9640 	u8         syndrome[0x20];
9641 
9642 	u8         reserved_at_40[0x40];
9643 };
9644 
9645 struct mlx5_ifc_arm_dct_in_bits {
9646 	u8         opcode[0x10];
9647 	u8         reserved_at_10[0x10];
9648 
9649 	u8         reserved_at_20[0x10];
9650 	u8         op_mod[0x10];
9651 
9652 	u8         reserved_at_40[0x8];
9653 	u8         dct_number[0x18];
9654 
9655 	u8         reserved_at_60[0x20];
9656 };
9657 
9658 struct mlx5_ifc_alloc_xrcd_out_bits {
9659 	u8         status[0x8];
9660 	u8         reserved_at_8[0x18];
9661 
9662 	u8         syndrome[0x20];
9663 
9664 	u8         reserved_at_40[0x8];
9665 	u8         xrcd[0x18];
9666 
9667 	u8         reserved_at_60[0x20];
9668 };
9669 
9670 struct mlx5_ifc_alloc_xrcd_in_bits {
9671 	u8         opcode[0x10];
9672 	u8         uid[0x10];
9673 
9674 	u8         reserved_at_20[0x10];
9675 	u8         op_mod[0x10];
9676 
9677 	u8         reserved_at_40[0x40];
9678 };
9679 
9680 struct mlx5_ifc_alloc_uar_out_bits {
9681 	u8         status[0x8];
9682 	u8         reserved_at_8[0x18];
9683 
9684 	u8         syndrome[0x20];
9685 
9686 	u8         reserved_at_40[0x8];
9687 	u8         uar[0x18];
9688 
9689 	u8         reserved_at_60[0x20];
9690 };
9691 
9692 struct mlx5_ifc_alloc_uar_in_bits {
9693 	u8         opcode[0x10];
9694 	u8         uid[0x10];
9695 
9696 	u8         reserved_at_20[0x10];
9697 	u8         op_mod[0x10];
9698 
9699 	u8         reserved_at_40[0x40];
9700 };
9701 
9702 struct mlx5_ifc_alloc_transport_domain_out_bits {
9703 	u8         status[0x8];
9704 	u8         reserved_at_8[0x18];
9705 
9706 	u8         syndrome[0x20];
9707 
9708 	u8         reserved_at_40[0x8];
9709 	u8         transport_domain[0x18];
9710 
9711 	u8         reserved_at_60[0x20];
9712 };
9713 
9714 struct mlx5_ifc_alloc_transport_domain_in_bits {
9715 	u8         opcode[0x10];
9716 	u8         uid[0x10];
9717 
9718 	u8         reserved_at_20[0x10];
9719 	u8         op_mod[0x10];
9720 
9721 	u8         reserved_at_40[0x40];
9722 };
9723 
9724 struct mlx5_ifc_alloc_q_counter_out_bits {
9725 	u8         status[0x8];
9726 	u8         reserved_at_8[0x18];
9727 
9728 	u8         syndrome[0x20];
9729 
9730 	u8         reserved_at_40[0x18];
9731 	u8         counter_set_id[0x8];
9732 
9733 	u8         reserved_at_60[0x20];
9734 };
9735 
9736 struct mlx5_ifc_alloc_q_counter_in_bits {
9737 	u8         opcode[0x10];
9738 	u8         uid[0x10];
9739 
9740 	u8         reserved_at_20[0x10];
9741 	u8         op_mod[0x10];
9742 
9743 	u8         reserved_at_40[0x40];
9744 };
9745 
9746 struct mlx5_ifc_alloc_pd_out_bits {
9747 	u8         status[0x8];
9748 	u8         reserved_at_8[0x18];
9749 
9750 	u8         syndrome[0x20];
9751 
9752 	u8         reserved_at_40[0x8];
9753 	u8         pd[0x18];
9754 
9755 	u8         reserved_at_60[0x20];
9756 };
9757 
9758 struct mlx5_ifc_alloc_pd_in_bits {
9759 	u8         opcode[0x10];
9760 	u8         uid[0x10];
9761 
9762 	u8         reserved_at_20[0x10];
9763 	u8         op_mod[0x10];
9764 
9765 	u8         reserved_at_40[0x40];
9766 };
9767 
9768 struct mlx5_ifc_alloc_flow_counter_out_bits {
9769 	u8         status[0x8];
9770 	u8         reserved_at_8[0x18];
9771 
9772 	u8         syndrome[0x20];
9773 
9774 	u8         flow_counter_id[0x20];
9775 
9776 	u8         reserved_at_60[0x20];
9777 };
9778 
9779 struct mlx5_ifc_alloc_flow_counter_in_bits {
9780 	u8         opcode[0x10];
9781 	u8         reserved_at_10[0x10];
9782 
9783 	u8         reserved_at_20[0x10];
9784 	u8         op_mod[0x10];
9785 
9786 	u8         reserved_at_40[0x33];
9787 	u8         flow_counter_bulk_log_size[0x5];
9788 	u8         flow_counter_bulk[0x8];
9789 };
9790 
9791 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9792 	u8         status[0x8];
9793 	u8         reserved_at_8[0x18];
9794 
9795 	u8         syndrome[0x20];
9796 
9797 	u8         reserved_at_40[0x40];
9798 };
9799 
9800 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9801 	u8         opcode[0x10];
9802 	u8         reserved_at_10[0x10];
9803 
9804 	u8         reserved_at_20[0x10];
9805 	u8         op_mod[0x10];
9806 
9807 	u8         reserved_at_40[0x20];
9808 
9809 	u8         reserved_at_60[0x10];
9810 	u8         vxlan_udp_port[0x10];
9811 };
9812 
9813 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9814 	u8         status[0x8];
9815 	u8         reserved_at_8[0x18];
9816 
9817 	u8         syndrome[0x20];
9818 
9819 	u8         reserved_at_40[0x40];
9820 };
9821 
9822 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9823 	u8         rate_limit[0x20];
9824 
9825 	u8	   burst_upper_bound[0x20];
9826 
9827 	u8         reserved_at_40[0x10];
9828 	u8	   typical_packet_size[0x10];
9829 
9830 	u8         reserved_at_60[0x120];
9831 };
9832 
9833 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9834 	u8         opcode[0x10];
9835 	u8         uid[0x10];
9836 
9837 	u8         reserved_at_20[0x10];
9838 	u8         op_mod[0x10];
9839 
9840 	u8         reserved_at_40[0x10];
9841 	u8         rate_limit_index[0x10];
9842 
9843 	u8         reserved_at_60[0x20];
9844 
9845 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9846 };
9847 
9848 struct mlx5_ifc_access_register_out_bits {
9849 	u8         status[0x8];
9850 	u8         reserved_at_8[0x18];
9851 
9852 	u8         syndrome[0x20];
9853 
9854 	u8         reserved_at_40[0x40];
9855 
9856 	u8         register_data[][0x20];
9857 };
9858 
9859 enum {
9860 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9861 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9862 };
9863 
9864 struct mlx5_ifc_access_register_in_bits {
9865 	u8         opcode[0x10];
9866 	u8         reserved_at_10[0x10];
9867 
9868 	u8         reserved_at_20[0x10];
9869 	u8         op_mod[0x10];
9870 
9871 	u8         reserved_at_40[0x10];
9872 	u8         register_id[0x10];
9873 
9874 	u8         argument[0x20];
9875 
9876 	u8         register_data[][0x20];
9877 };
9878 
9879 struct mlx5_ifc_sltp_reg_bits {
9880 	u8         status[0x4];
9881 	u8         version[0x4];
9882 	u8         local_port[0x8];
9883 	u8         pnat[0x2];
9884 	u8         reserved_at_12[0x2];
9885 	u8         lane[0x4];
9886 	u8         reserved_at_18[0x8];
9887 
9888 	u8         reserved_at_20[0x20];
9889 
9890 	u8         reserved_at_40[0x7];
9891 	u8         polarity[0x1];
9892 	u8         ob_tap0[0x8];
9893 	u8         ob_tap1[0x8];
9894 	u8         ob_tap2[0x8];
9895 
9896 	u8         reserved_at_60[0xc];
9897 	u8         ob_preemp_mode[0x4];
9898 	u8         ob_reg[0x8];
9899 	u8         ob_bias[0x8];
9900 
9901 	u8         reserved_at_80[0x20];
9902 };
9903 
9904 struct mlx5_ifc_slrg_reg_bits {
9905 	u8         status[0x4];
9906 	u8         version[0x4];
9907 	u8         local_port[0x8];
9908 	u8         pnat[0x2];
9909 	u8         reserved_at_12[0x2];
9910 	u8         lane[0x4];
9911 	u8         reserved_at_18[0x8];
9912 
9913 	u8         time_to_link_up[0x10];
9914 	u8         reserved_at_30[0xc];
9915 	u8         grade_lane_speed[0x4];
9916 
9917 	u8         grade_version[0x8];
9918 	u8         grade[0x18];
9919 
9920 	u8         reserved_at_60[0x4];
9921 	u8         height_grade_type[0x4];
9922 	u8         height_grade[0x18];
9923 
9924 	u8         height_dz[0x10];
9925 	u8         height_dv[0x10];
9926 
9927 	u8         reserved_at_a0[0x10];
9928 	u8         height_sigma[0x10];
9929 
9930 	u8         reserved_at_c0[0x20];
9931 
9932 	u8         reserved_at_e0[0x4];
9933 	u8         phase_grade_type[0x4];
9934 	u8         phase_grade[0x18];
9935 
9936 	u8         reserved_at_100[0x8];
9937 	u8         phase_eo_pos[0x8];
9938 	u8         reserved_at_110[0x8];
9939 	u8         phase_eo_neg[0x8];
9940 
9941 	u8         ffe_set_tested[0x10];
9942 	u8         test_errors_per_lane[0x10];
9943 };
9944 
9945 struct mlx5_ifc_pvlc_reg_bits {
9946 	u8         reserved_at_0[0x8];
9947 	u8         local_port[0x8];
9948 	u8         reserved_at_10[0x10];
9949 
9950 	u8         reserved_at_20[0x1c];
9951 	u8         vl_hw_cap[0x4];
9952 
9953 	u8         reserved_at_40[0x1c];
9954 	u8         vl_admin[0x4];
9955 
9956 	u8         reserved_at_60[0x1c];
9957 	u8         vl_operational[0x4];
9958 };
9959 
9960 struct mlx5_ifc_pude_reg_bits {
9961 	u8         swid[0x8];
9962 	u8         local_port[0x8];
9963 	u8         reserved_at_10[0x4];
9964 	u8         admin_status[0x4];
9965 	u8         reserved_at_18[0x4];
9966 	u8         oper_status[0x4];
9967 
9968 	u8         reserved_at_20[0x60];
9969 };
9970 
9971 struct mlx5_ifc_ptys_reg_bits {
9972 	u8         reserved_at_0[0x1];
9973 	u8         an_disable_admin[0x1];
9974 	u8         an_disable_cap[0x1];
9975 	u8         reserved_at_3[0x5];
9976 	u8         local_port[0x8];
9977 	u8         reserved_at_10[0x8];
9978 	u8         plane_ind[0x4];
9979 	u8         reserved_at_1c[0x1];
9980 	u8         proto_mask[0x3];
9981 
9982 	u8         an_status[0x4];
9983 	u8         reserved_at_24[0xc];
9984 	u8         data_rate_oper[0x10];
9985 
9986 	u8         ext_eth_proto_capability[0x20];
9987 
9988 	u8         eth_proto_capability[0x20];
9989 
9990 	u8         ib_link_width_capability[0x10];
9991 	u8         ib_proto_capability[0x10];
9992 
9993 	u8         ext_eth_proto_admin[0x20];
9994 
9995 	u8         eth_proto_admin[0x20];
9996 
9997 	u8         ib_link_width_admin[0x10];
9998 	u8         ib_proto_admin[0x10];
9999 
10000 	u8         ext_eth_proto_oper[0x20];
10001 
10002 	u8         eth_proto_oper[0x20];
10003 
10004 	u8         ib_link_width_oper[0x10];
10005 	u8         ib_proto_oper[0x10];
10006 
10007 	u8         reserved_at_160[0x1c];
10008 	u8         connector_type[0x4];
10009 
10010 	u8         eth_proto_lp_advertise[0x20];
10011 
10012 	u8         reserved_at_1a0[0x60];
10013 };
10014 
10015 struct mlx5_ifc_mlcr_reg_bits {
10016 	u8         reserved_at_0[0x8];
10017 	u8         local_port[0x8];
10018 	u8         reserved_at_10[0x20];
10019 
10020 	u8         beacon_duration[0x10];
10021 	u8         reserved_at_40[0x10];
10022 
10023 	u8         beacon_remain[0x10];
10024 };
10025 
10026 struct mlx5_ifc_ptas_reg_bits {
10027 	u8         reserved_at_0[0x20];
10028 
10029 	u8         algorithm_options[0x10];
10030 	u8         reserved_at_30[0x4];
10031 	u8         repetitions_mode[0x4];
10032 	u8         num_of_repetitions[0x8];
10033 
10034 	u8         grade_version[0x8];
10035 	u8         height_grade_type[0x4];
10036 	u8         phase_grade_type[0x4];
10037 	u8         height_grade_weight[0x8];
10038 	u8         phase_grade_weight[0x8];
10039 
10040 	u8         gisim_measure_bits[0x10];
10041 	u8         adaptive_tap_measure_bits[0x10];
10042 
10043 	u8         ber_bath_high_error_threshold[0x10];
10044 	u8         ber_bath_mid_error_threshold[0x10];
10045 
10046 	u8         ber_bath_low_error_threshold[0x10];
10047 	u8         one_ratio_high_threshold[0x10];
10048 
10049 	u8         one_ratio_high_mid_threshold[0x10];
10050 	u8         one_ratio_low_mid_threshold[0x10];
10051 
10052 	u8         one_ratio_low_threshold[0x10];
10053 	u8         ndeo_error_threshold[0x10];
10054 
10055 	u8         mixer_offset_step_size[0x10];
10056 	u8         reserved_at_110[0x8];
10057 	u8         mix90_phase_for_voltage_bath[0x8];
10058 
10059 	u8         mixer_offset_start[0x10];
10060 	u8         mixer_offset_end[0x10];
10061 
10062 	u8         reserved_at_140[0x15];
10063 	u8         ber_test_time[0xb];
10064 };
10065 
10066 struct mlx5_ifc_pspa_reg_bits {
10067 	u8         swid[0x8];
10068 	u8         local_port[0x8];
10069 	u8         sub_port[0x8];
10070 	u8         reserved_at_18[0x8];
10071 
10072 	u8         reserved_at_20[0x20];
10073 };
10074 
10075 struct mlx5_ifc_pqdr_reg_bits {
10076 	u8         reserved_at_0[0x8];
10077 	u8         local_port[0x8];
10078 	u8         reserved_at_10[0x5];
10079 	u8         prio[0x3];
10080 	u8         reserved_at_18[0x6];
10081 	u8         mode[0x2];
10082 
10083 	u8         reserved_at_20[0x20];
10084 
10085 	u8         reserved_at_40[0x10];
10086 	u8         min_threshold[0x10];
10087 
10088 	u8         reserved_at_60[0x10];
10089 	u8         max_threshold[0x10];
10090 
10091 	u8         reserved_at_80[0x10];
10092 	u8         mark_probability_denominator[0x10];
10093 
10094 	u8         reserved_at_a0[0x60];
10095 };
10096 
10097 struct mlx5_ifc_ppsc_reg_bits {
10098 	u8         reserved_at_0[0x8];
10099 	u8         local_port[0x8];
10100 	u8         reserved_at_10[0x10];
10101 
10102 	u8         reserved_at_20[0x60];
10103 
10104 	u8         reserved_at_80[0x1c];
10105 	u8         wrps_admin[0x4];
10106 
10107 	u8         reserved_at_a0[0x1c];
10108 	u8         wrps_status[0x4];
10109 
10110 	u8         reserved_at_c0[0x8];
10111 	u8         up_threshold[0x8];
10112 	u8         reserved_at_d0[0x8];
10113 	u8         down_threshold[0x8];
10114 
10115 	u8         reserved_at_e0[0x20];
10116 
10117 	u8         reserved_at_100[0x1c];
10118 	u8         srps_admin[0x4];
10119 
10120 	u8         reserved_at_120[0x1c];
10121 	u8         srps_status[0x4];
10122 
10123 	u8         reserved_at_140[0x40];
10124 };
10125 
10126 struct mlx5_ifc_pplr_reg_bits {
10127 	u8         reserved_at_0[0x8];
10128 	u8         local_port[0x8];
10129 	u8         reserved_at_10[0x10];
10130 
10131 	u8         reserved_at_20[0x8];
10132 	u8         lb_cap[0x8];
10133 	u8         reserved_at_30[0x8];
10134 	u8         lb_en[0x8];
10135 };
10136 
10137 struct mlx5_ifc_pplm_reg_bits {
10138 	u8         reserved_at_0[0x8];
10139 	u8	   local_port[0x8];
10140 	u8	   reserved_at_10[0x10];
10141 
10142 	u8	   reserved_at_20[0x20];
10143 
10144 	u8	   port_profile_mode[0x8];
10145 	u8	   static_port_profile[0x8];
10146 	u8	   active_port_profile[0x8];
10147 	u8	   reserved_at_58[0x8];
10148 
10149 	u8	   retransmission_active[0x8];
10150 	u8	   fec_mode_active[0x18];
10151 
10152 	u8	   rs_fec_correction_bypass_cap[0x4];
10153 	u8	   reserved_at_84[0x8];
10154 	u8	   fec_override_cap_56g[0x4];
10155 	u8	   fec_override_cap_100g[0x4];
10156 	u8	   fec_override_cap_50g[0x4];
10157 	u8	   fec_override_cap_25g[0x4];
10158 	u8	   fec_override_cap_10g_40g[0x4];
10159 
10160 	u8	   rs_fec_correction_bypass_admin[0x4];
10161 	u8	   reserved_at_a4[0x8];
10162 	u8	   fec_override_admin_56g[0x4];
10163 	u8	   fec_override_admin_100g[0x4];
10164 	u8	   fec_override_admin_50g[0x4];
10165 	u8	   fec_override_admin_25g[0x4];
10166 	u8	   fec_override_admin_10g_40g[0x4];
10167 
10168 	u8         fec_override_cap_400g_8x[0x10];
10169 	u8         fec_override_cap_200g_4x[0x10];
10170 
10171 	u8         fec_override_cap_100g_2x[0x10];
10172 	u8         fec_override_cap_50g_1x[0x10];
10173 
10174 	u8         fec_override_admin_400g_8x[0x10];
10175 	u8         fec_override_admin_200g_4x[0x10];
10176 
10177 	u8         fec_override_admin_100g_2x[0x10];
10178 	u8         fec_override_admin_50g_1x[0x10];
10179 
10180 	u8         fec_override_cap_800g_8x[0x10];
10181 	u8         fec_override_cap_400g_4x[0x10];
10182 
10183 	u8         fec_override_cap_200g_2x[0x10];
10184 	u8         fec_override_cap_100g_1x[0x10];
10185 
10186 	u8         reserved_at_180[0xa0];
10187 
10188 	u8         fec_override_admin_800g_8x[0x10];
10189 	u8         fec_override_admin_400g_4x[0x10];
10190 
10191 	u8         fec_override_admin_200g_2x[0x10];
10192 	u8         fec_override_admin_100g_1x[0x10];
10193 
10194 	u8         reserved_at_260[0x60];
10195 
10196 	u8         fec_override_cap_1600g_8x[0x10];
10197 	u8         fec_override_cap_800g_4x[0x10];
10198 
10199 	u8         fec_override_cap_400g_2x[0x10];
10200 	u8         fec_override_cap_200g_1x[0x10];
10201 
10202 	u8         fec_override_admin_1600g_8x[0x10];
10203 	u8         fec_override_admin_800g_4x[0x10];
10204 
10205 	u8         fec_override_admin_400g_2x[0x10];
10206 	u8         fec_override_admin_200g_1x[0x10];
10207 
10208 	u8         reserved_at_340[0x80];
10209 };
10210 
10211 struct mlx5_ifc_ppcnt_reg_bits {
10212 	u8         swid[0x8];
10213 	u8         local_port[0x8];
10214 	u8         pnat[0x2];
10215 	u8         reserved_at_12[0x8];
10216 	u8         grp[0x6];
10217 
10218 	u8         clr[0x1];
10219 	u8         reserved_at_21[0x13];
10220 	u8         plane_ind[0x4];
10221 	u8         reserved_at_38[0x3];
10222 	u8         prio_tc[0x5];
10223 
10224 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10225 };
10226 
10227 struct mlx5_ifc_mpein_reg_bits {
10228 	u8         reserved_at_0[0x2];
10229 	u8         depth[0x6];
10230 	u8         pcie_index[0x8];
10231 	u8         node[0x8];
10232 	u8         reserved_at_18[0x8];
10233 
10234 	u8         capability_mask[0x20];
10235 
10236 	u8         reserved_at_40[0x8];
10237 	u8         link_width_enabled[0x8];
10238 	u8         link_speed_enabled[0x10];
10239 
10240 	u8         lane0_physical_position[0x8];
10241 	u8         link_width_active[0x8];
10242 	u8         link_speed_active[0x10];
10243 
10244 	u8         num_of_pfs[0x10];
10245 	u8         num_of_vfs[0x10];
10246 
10247 	u8         bdf0[0x10];
10248 	u8         reserved_at_b0[0x10];
10249 
10250 	u8         max_read_request_size[0x4];
10251 	u8         max_payload_size[0x4];
10252 	u8         reserved_at_c8[0x5];
10253 	u8         pwr_status[0x3];
10254 	u8         port_type[0x4];
10255 	u8         reserved_at_d4[0xb];
10256 	u8         lane_reversal[0x1];
10257 
10258 	u8         reserved_at_e0[0x14];
10259 	u8         pci_power[0xc];
10260 
10261 	u8         reserved_at_100[0x20];
10262 
10263 	u8         device_status[0x10];
10264 	u8         port_state[0x8];
10265 	u8         reserved_at_138[0x8];
10266 
10267 	u8         reserved_at_140[0x10];
10268 	u8         receiver_detect_result[0x10];
10269 
10270 	u8         reserved_at_160[0x20];
10271 };
10272 
10273 struct mlx5_ifc_mpcnt_reg_bits {
10274 	u8         reserved_at_0[0x8];
10275 	u8         pcie_index[0x8];
10276 	u8         reserved_at_10[0xa];
10277 	u8         grp[0x6];
10278 
10279 	u8         clr[0x1];
10280 	u8         reserved_at_21[0x1f];
10281 
10282 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
10283 };
10284 
10285 struct mlx5_ifc_ppad_reg_bits {
10286 	u8         reserved_at_0[0x3];
10287 	u8         single_mac[0x1];
10288 	u8         reserved_at_4[0x4];
10289 	u8         local_port[0x8];
10290 	u8         mac_47_32[0x10];
10291 
10292 	u8         mac_31_0[0x20];
10293 
10294 	u8         reserved_at_40[0x40];
10295 };
10296 
10297 struct mlx5_ifc_pmtu_reg_bits {
10298 	u8         reserved_at_0[0x8];
10299 	u8         local_port[0x8];
10300 	u8         reserved_at_10[0x10];
10301 
10302 	u8         max_mtu[0x10];
10303 	u8         reserved_at_30[0x10];
10304 
10305 	u8         admin_mtu[0x10];
10306 	u8         reserved_at_50[0x10];
10307 
10308 	u8         oper_mtu[0x10];
10309 	u8         reserved_at_70[0x10];
10310 };
10311 
10312 struct mlx5_ifc_pmpr_reg_bits {
10313 	u8         reserved_at_0[0x8];
10314 	u8         module[0x8];
10315 	u8         reserved_at_10[0x10];
10316 
10317 	u8         reserved_at_20[0x18];
10318 	u8         attenuation_5g[0x8];
10319 
10320 	u8         reserved_at_40[0x18];
10321 	u8         attenuation_7g[0x8];
10322 
10323 	u8         reserved_at_60[0x18];
10324 	u8         attenuation_12g[0x8];
10325 };
10326 
10327 struct mlx5_ifc_pmpe_reg_bits {
10328 	u8         reserved_at_0[0x8];
10329 	u8         module[0x8];
10330 	u8         reserved_at_10[0xc];
10331 	u8         module_status[0x4];
10332 
10333 	u8         reserved_at_20[0x60];
10334 };
10335 
10336 struct mlx5_ifc_pmpc_reg_bits {
10337 	u8         module_state_updated[32][0x8];
10338 };
10339 
10340 struct mlx5_ifc_pmlpn_reg_bits {
10341 	u8         reserved_at_0[0x4];
10342 	u8         mlpn_status[0x4];
10343 	u8         local_port[0x8];
10344 	u8         reserved_at_10[0x10];
10345 
10346 	u8         e[0x1];
10347 	u8         reserved_at_21[0x1f];
10348 };
10349 
10350 struct mlx5_ifc_pmlp_reg_bits {
10351 	u8         rxtx[0x1];
10352 	u8         reserved_at_1[0x7];
10353 	u8         local_port[0x8];
10354 	u8         reserved_at_10[0x8];
10355 	u8         width[0x8];
10356 
10357 	u8         lane0_module_mapping[0x20];
10358 
10359 	u8         lane1_module_mapping[0x20];
10360 
10361 	u8         lane2_module_mapping[0x20];
10362 
10363 	u8         lane3_module_mapping[0x20];
10364 
10365 	u8         reserved_at_a0[0x160];
10366 };
10367 
10368 struct mlx5_ifc_pmaos_reg_bits {
10369 	u8         reserved_at_0[0x8];
10370 	u8         module[0x8];
10371 	u8         reserved_at_10[0x4];
10372 	u8         admin_status[0x4];
10373 	u8         reserved_at_18[0x4];
10374 	u8         oper_status[0x4];
10375 
10376 	u8         ase[0x1];
10377 	u8         ee[0x1];
10378 	u8         reserved_at_22[0x1c];
10379 	u8         e[0x2];
10380 
10381 	u8         reserved_at_40[0x40];
10382 };
10383 
10384 struct mlx5_ifc_plpc_reg_bits {
10385 	u8         reserved_at_0[0x4];
10386 	u8         profile_id[0xc];
10387 	u8         reserved_at_10[0x4];
10388 	u8         proto_mask[0x4];
10389 	u8         reserved_at_18[0x8];
10390 
10391 	u8         reserved_at_20[0x10];
10392 	u8         lane_speed[0x10];
10393 
10394 	u8         reserved_at_40[0x17];
10395 	u8         lpbf[0x1];
10396 	u8         fec_mode_policy[0x8];
10397 
10398 	u8         retransmission_capability[0x8];
10399 	u8         fec_mode_capability[0x18];
10400 
10401 	u8         retransmission_support_admin[0x8];
10402 	u8         fec_mode_support_admin[0x18];
10403 
10404 	u8         retransmission_request_admin[0x8];
10405 	u8         fec_mode_request_admin[0x18];
10406 
10407 	u8         reserved_at_c0[0x80];
10408 };
10409 
10410 struct mlx5_ifc_plib_reg_bits {
10411 	u8         reserved_at_0[0x8];
10412 	u8         local_port[0x8];
10413 	u8         reserved_at_10[0x8];
10414 	u8         ib_port[0x8];
10415 
10416 	u8         reserved_at_20[0x60];
10417 };
10418 
10419 struct mlx5_ifc_plbf_reg_bits {
10420 	u8         reserved_at_0[0x8];
10421 	u8         local_port[0x8];
10422 	u8         reserved_at_10[0xd];
10423 	u8         lbf_mode[0x3];
10424 
10425 	u8         reserved_at_20[0x20];
10426 };
10427 
10428 struct mlx5_ifc_pipg_reg_bits {
10429 	u8         reserved_at_0[0x8];
10430 	u8         local_port[0x8];
10431 	u8         reserved_at_10[0x10];
10432 
10433 	u8         dic[0x1];
10434 	u8         reserved_at_21[0x19];
10435 	u8         ipg[0x4];
10436 	u8         reserved_at_3e[0x2];
10437 };
10438 
10439 struct mlx5_ifc_pifr_reg_bits {
10440 	u8         reserved_at_0[0x8];
10441 	u8         local_port[0x8];
10442 	u8         reserved_at_10[0x10];
10443 
10444 	u8         reserved_at_20[0xe0];
10445 
10446 	u8         port_filter[8][0x20];
10447 
10448 	u8         port_filter_update_en[8][0x20];
10449 };
10450 
10451 struct mlx5_ifc_pfcc_reg_bits {
10452 	u8         reserved_at_0[0x8];
10453 	u8         local_port[0x8];
10454 	u8         reserved_at_10[0xb];
10455 	u8         ppan_mask_n[0x1];
10456 	u8         minor_stall_mask[0x1];
10457 	u8         critical_stall_mask[0x1];
10458 	u8         reserved_at_1e[0x2];
10459 
10460 	u8         ppan[0x4];
10461 	u8         reserved_at_24[0x4];
10462 	u8         prio_mask_tx[0x8];
10463 	u8         reserved_at_30[0x8];
10464 	u8         prio_mask_rx[0x8];
10465 
10466 	u8         pptx[0x1];
10467 	u8         aptx[0x1];
10468 	u8         pptx_mask_n[0x1];
10469 	u8         reserved_at_43[0x5];
10470 	u8         pfctx[0x8];
10471 	u8         reserved_at_50[0x10];
10472 
10473 	u8         pprx[0x1];
10474 	u8         aprx[0x1];
10475 	u8         pprx_mask_n[0x1];
10476 	u8         reserved_at_63[0x5];
10477 	u8         pfcrx[0x8];
10478 	u8         reserved_at_70[0x10];
10479 
10480 	u8         device_stall_minor_watermark[0x10];
10481 	u8         device_stall_critical_watermark[0x10];
10482 
10483 	u8         reserved_at_a0[0x60];
10484 };
10485 
10486 struct mlx5_ifc_pelc_reg_bits {
10487 	u8         op[0x4];
10488 	u8         reserved_at_4[0x4];
10489 	u8         local_port[0x8];
10490 	u8         reserved_at_10[0x10];
10491 
10492 	u8         op_admin[0x8];
10493 	u8         op_capability[0x8];
10494 	u8         op_request[0x8];
10495 	u8         op_active[0x8];
10496 
10497 	u8         admin[0x40];
10498 
10499 	u8         capability[0x40];
10500 
10501 	u8         request[0x40];
10502 
10503 	u8         active[0x40];
10504 
10505 	u8         reserved_at_140[0x80];
10506 };
10507 
10508 struct mlx5_ifc_peir_reg_bits {
10509 	u8         reserved_at_0[0x8];
10510 	u8         local_port[0x8];
10511 	u8         reserved_at_10[0x10];
10512 
10513 	u8         reserved_at_20[0xc];
10514 	u8         error_count[0x4];
10515 	u8         reserved_at_30[0x10];
10516 
10517 	u8         reserved_at_40[0xc];
10518 	u8         lane[0x4];
10519 	u8         reserved_at_50[0x8];
10520 	u8         error_type[0x8];
10521 };
10522 
10523 struct mlx5_ifc_mpegc_reg_bits {
10524 	u8         reserved_at_0[0x30];
10525 	u8         field_select[0x10];
10526 
10527 	u8         tx_overflow_sense[0x1];
10528 	u8         mark_cqe[0x1];
10529 	u8         mark_cnp[0x1];
10530 	u8         reserved_at_43[0x1b];
10531 	u8         tx_lossy_overflow_oper[0x2];
10532 
10533 	u8         reserved_at_60[0x100];
10534 };
10535 
10536 struct mlx5_ifc_mpir_reg_bits {
10537 	u8         sdm[0x1];
10538 	u8         reserved_at_1[0x1b];
10539 	u8         host_buses[0x4];
10540 
10541 	u8         reserved_at_20[0x20];
10542 
10543 	u8         local_port[0x8];
10544 	u8         reserved_at_28[0x18];
10545 
10546 	u8         reserved_at_60[0x20];
10547 };
10548 
10549 enum {
10550 	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10551 	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10552 };
10553 
10554 enum {
10555 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10556 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10557 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10558 };
10559 
10560 struct mlx5_ifc_mtutc_reg_bits {
10561 	u8         reserved_at_0[0x5];
10562 	u8         freq_adj_units[0x3];
10563 	u8         reserved_at_8[0x3];
10564 	u8         log_max_freq_adjustment[0x5];
10565 
10566 	u8         reserved_at_10[0xc];
10567 	u8         operation[0x4];
10568 
10569 	u8         freq_adjustment[0x20];
10570 
10571 	u8         reserved_at_40[0x40];
10572 
10573 	u8         utc_sec[0x20];
10574 
10575 	u8         reserved_at_a0[0x2];
10576 	u8         utc_nsec[0x1e];
10577 
10578 	u8         time_adjustment[0x20];
10579 };
10580 
10581 struct mlx5_ifc_pcam_enhanced_features_bits {
10582 	u8         reserved_at_0[0x1d];
10583 	u8         fec_200G_per_lane_in_pplm[0x1];
10584 	u8         reserved_at_1e[0x2a];
10585 	u8         fec_100G_per_lane_in_pplm[0x1];
10586 	u8         reserved_at_49[0x1f];
10587 	u8         fec_50G_per_lane_in_pplm[0x1];
10588 	u8         reserved_at_69[0x4];
10589 	u8         rx_icrc_encapsulated_counter[0x1];
10590 	u8	   reserved_at_6e[0x4];
10591 	u8         ptys_extended_ethernet[0x1];
10592 	u8	   reserved_at_73[0x3];
10593 	u8         pfcc_mask[0x1];
10594 	u8         reserved_at_77[0x3];
10595 	u8         per_lane_error_counters[0x1];
10596 	u8         rx_buffer_fullness_counters[0x1];
10597 	u8         ptys_connector_type[0x1];
10598 	u8         reserved_at_7d[0x1];
10599 	u8         ppcnt_discard_group[0x1];
10600 	u8         ppcnt_statistical_group[0x1];
10601 };
10602 
10603 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10604 	u8         port_access_reg_cap_mask_127_to_96[0x20];
10605 	u8         port_access_reg_cap_mask_95_to_64[0x20];
10606 
10607 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
10608 	u8         pplm[0x1];
10609 	u8         port_access_reg_cap_mask_34_to_32[0x3];
10610 
10611 	u8         port_access_reg_cap_mask_31_to_13[0x13];
10612 	u8         pbmc[0x1];
10613 	u8         pptb[0x1];
10614 	u8         port_access_reg_cap_mask_10_to_09[0x2];
10615 	u8         ppcnt[0x1];
10616 	u8         port_access_reg_cap_mask_07_to_00[0x8];
10617 };
10618 
10619 struct mlx5_ifc_pcam_reg_bits {
10620 	u8         reserved_at_0[0x8];
10621 	u8         feature_group[0x8];
10622 	u8         reserved_at_10[0x8];
10623 	u8         access_reg_group[0x8];
10624 
10625 	u8         reserved_at_20[0x20];
10626 
10627 	union {
10628 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10629 		u8         reserved_at_0[0x80];
10630 	} port_access_reg_cap_mask;
10631 
10632 	u8         reserved_at_c0[0x80];
10633 
10634 	union {
10635 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10636 		u8         reserved_at_0[0x80];
10637 	} feature_cap_mask;
10638 
10639 	u8         reserved_at_1c0[0xc0];
10640 };
10641 
10642 struct mlx5_ifc_mcam_enhanced_features_bits {
10643 	u8         reserved_at_0[0x50];
10644 	u8         mtutc_freq_adj_units[0x1];
10645 	u8         mtutc_time_adjustment_extended_range[0x1];
10646 	u8         reserved_at_52[0xb];
10647 	u8         mcia_32dwords[0x1];
10648 	u8         out_pulse_duration_ns[0x1];
10649 	u8         npps_period[0x1];
10650 	u8         reserved_at_60[0xa];
10651 	u8         reset_state[0x1];
10652 	u8         ptpcyc2realtime_modify[0x1];
10653 	u8         reserved_at_6c[0x2];
10654 	u8         pci_status_and_power[0x1];
10655 	u8         reserved_at_6f[0x5];
10656 	u8         mark_tx_action_cnp[0x1];
10657 	u8         mark_tx_action_cqe[0x1];
10658 	u8         dynamic_tx_overflow[0x1];
10659 	u8         reserved_at_77[0x4];
10660 	u8         pcie_outbound_stalled[0x1];
10661 	u8         tx_overflow_buffer_pkt[0x1];
10662 	u8         mtpps_enh_out_per_adj[0x1];
10663 	u8         mtpps_fs[0x1];
10664 	u8         pcie_performance_group[0x1];
10665 };
10666 
10667 struct mlx5_ifc_mcam_access_reg_bits {
10668 	u8         reserved_at_0[0x1c];
10669 	u8         mcda[0x1];
10670 	u8         mcc[0x1];
10671 	u8         mcqi[0x1];
10672 	u8         mcqs[0x1];
10673 
10674 	u8         regs_95_to_90[0x6];
10675 	u8         mpir[0x1];
10676 	u8         regs_88_to_87[0x2];
10677 	u8         mpegc[0x1];
10678 	u8         mtutc[0x1];
10679 	u8         regs_84_to_68[0x11];
10680 	u8         tracer_registers[0x4];
10681 
10682 	u8         regs_63_to_46[0x12];
10683 	u8         mrtc[0x1];
10684 	u8         regs_44_to_41[0x4];
10685 	u8         mfrl[0x1];
10686 	u8         regs_39_to_32[0x8];
10687 
10688 	u8         regs_31_to_11[0x15];
10689 	u8         mtmp[0x1];
10690 	u8         regs_9_to_0[0xa];
10691 };
10692 
10693 struct mlx5_ifc_mcam_access_reg_bits1 {
10694 	u8         regs_127_to_96[0x20];
10695 
10696 	u8         regs_95_to_64[0x20];
10697 
10698 	u8         regs_63_to_32[0x20];
10699 
10700 	u8         regs_31_to_0[0x20];
10701 };
10702 
10703 struct mlx5_ifc_mcam_access_reg_bits2 {
10704 	u8         regs_127_to_99[0x1d];
10705 	u8         mirc[0x1];
10706 	u8         regs_97_to_96[0x2];
10707 
10708 	u8         regs_95_to_87[0x09];
10709 	u8         synce_registers[0x2];
10710 	u8         regs_84_to_64[0x15];
10711 
10712 	u8         regs_63_to_32[0x20];
10713 
10714 	u8         regs_31_to_0[0x20];
10715 };
10716 
10717 struct mlx5_ifc_mcam_access_reg_bits3 {
10718 	u8         regs_127_to_96[0x20];
10719 
10720 	u8         regs_95_to_64[0x20];
10721 
10722 	u8         regs_63_to_32[0x20];
10723 
10724 	u8         regs_31_to_3[0x1d];
10725 	u8         mrtcq[0x1];
10726 	u8         mtctr[0x1];
10727 	u8         mtptm[0x1];
10728 };
10729 
10730 struct mlx5_ifc_mcam_reg_bits {
10731 	u8         reserved_at_0[0x8];
10732 	u8         feature_group[0x8];
10733 	u8         reserved_at_10[0x8];
10734 	u8         access_reg_group[0x8];
10735 
10736 	u8         reserved_at_20[0x20];
10737 
10738 	union {
10739 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
10740 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10741 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10742 		struct mlx5_ifc_mcam_access_reg_bits3 access_regs3;
10743 		u8         reserved_at_0[0x80];
10744 	} mng_access_reg_cap_mask;
10745 
10746 	u8         reserved_at_c0[0x80];
10747 
10748 	union {
10749 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10750 		u8         reserved_at_0[0x80];
10751 	} mng_feature_cap_mask;
10752 
10753 	u8         reserved_at_1c0[0x80];
10754 };
10755 
10756 struct mlx5_ifc_qcam_access_reg_cap_mask {
10757 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10758 	u8         qpdpm[0x1];
10759 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10760 	u8         qdpm[0x1];
10761 	u8         qpts[0x1];
10762 	u8         qcap[0x1];
10763 	u8         qcam_access_reg_cap_mask_0[0x1];
10764 };
10765 
10766 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10767 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10768 	u8         qpts_trust_both[0x1];
10769 };
10770 
10771 struct mlx5_ifc_qcam_reg_bits {
10772 	u8         reserved_at_0[0x8];
10773 	u8         feature_group[0x8];
10774 	u8         reserved_at_10[0x8];
10775 	u8         access_reg_group[0x8];
10776 	u8         reserved_at_20[0x20];
10777 
10778 	union {
10779 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10780 		u8  reserved_at_0[0x80];
10781 	} qos_access_reg_cap_mask;
10782 
10783 	u8         reserved_at_c0[0x80];
10784 
10785 	union {
10786 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10787 		u8  reserved_at_0[0x80];
10788 	} qos_feature_cap_mask;
10789 
10790 	u8         reserved_at_1c0[0x80];
10791 };
10792 
10793 struct mlx5_ifc_core_dump_reg_bits {
10794 	u8         reserved_at_0[0x18];
10795 	u8         core_dump_type[0x8];
10796 
10797 	u8         reserved_at_20[0x30];
10798 	u8         vhca_id[0x10];
10799 
10800 	u8         reserved_at_60[0x8];
10801 	u8         qpn[0x18];
10802 	u8         reserved_at_80[0x180];
10803 };
10804 
10805 struct mlx5_ifc_pcap_reg_bits {
10806 	u8         reserved_at_0[0x8];
10807 	u8         local_port[0x8];
10808 	u8         reserved_at_10[0x10];
10809 
10810 	u8         port_capability_mask[4][0x20];
10811 };
10812 
10813 struct mlx5_ifc_paos_reg_bits {
10814 	u8         swid[0x8];
10815 	u8         local_port[0x8];
10816 	u8         reserved_at_10[0x4];
10817 	u8         admin_status[0x4];
10818 	u8         reserved_at_18[0x4];
10819 	u8         oper_status[0x4];
10820 
10821 	u8         ase[0x1];
10822 	u8         ee[0x1];
10823 	u8         reserved_at_22[0x1c];
10824 	u8         e[0x2];
10825 
10826 	u8         reserved_at_40[0x40];
10827 };
10828 
10829 struct mlx5_ifc_pamp_reg_bits {
10830 	u8         reserved_at_0[0x8];
10831 	u8         opamp_group[0x8];
10832 	u8         reserved_at_10[0xc];
10833 	u8         opamp_group_type[0x4];
10834 
10835 	u8         start_index[0x10];
10836 	u8         reserved_at_30[0x4];
10837 	u8         num_of_indices[0xc];
10838 
10839 	u8         index_data[18][0x10];
10840 };
10841 
10842 struct mlx5_ifc_pcmr_reg_bits {
10843 	u8         reserved_at_0[0x8];
10844 	u8         local_port[0x8];
10845 	u8         reserved_at_10[0x10];
10846 
10847 	u8         entropy_force_cap[0x1];
10848 	u8         entropy_calc_cap[0x1];
10849 	u8         entropy_gre_calc_cap[0x1];
10850 	u8         reserved_at_23[0xf];
10851 	u8         rx_ts_over_crc_cap[0x1];
10852 	u8         reserved_at_33[0xb];
10853 	u8         fcs_cap[0x1];
10854 	u8         reserved_at_3f[0x1];
10855 
10856 	u8         entropy_force[0x1];
10857 	u8         entropy_calc[0x1];
10858 	u8         entropy_gre_calc[0x1];
10859 	u8         reserved_at_43[0xf];
10860 	u8         rx_ts_over_crc[0x1];
10861 	u8         reserved_at_53[0xb];
10862 	u8         fcs_chk[0x1];
10863 	u8         reserved_at_5f[0x1];
10864 };
10865 
10866 struct mlx5_ifc_lane_2_module_mapping_bits {
10867 	u8         reserved_at_0[0x4];
10868 	u8         rx_lane[0x4];
10869 	u8         reserved_at_8[0x4];
10870 	u8         tx_lane[0x4];
10871 	u8         reserved_at_10[0x8];
10872 	u8         module[0x8];
10873 };
10874 
10875 struct mlx5_ifc_bufferx_reg_bits {
10876 	u8         reserved_at_0[0x6];
10877 	u8         lossy[0x1];
10878 	u8         epsb[0x1];
10879 	u8         reserved_at_8[0x8];
10880 	u8         size[0x10];
10881 
10882 	u8         xoff_threshold[0x10];
10883 	u8         xon_threshold[0x10];
10884 };
10885 
10886 struct mlx5_ifc_set_node_in_bits {
10887 	u8         node_description[64][0x8];
10888 };
10889 
10890 struct mlx5_ifc_register_power_settings_bits {
10891 	u8         reserved_at_0[0x18];
10892 	u8         power_settings_level[0x8];
10893 
10894 	u8         reserved_at_20[0x60];
10895 };
10896 
10897 struct mlx5_ifc_register_host_endianness_bits {
10898 	u8         he[0x1];
10899 	u8         reserved_at_1[0x1f];
10900 
10901 	u8         reserved_at_20[0x60];
10902 };
10903 
10904 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10905 	u8         reserved_at_0[0x20];
10906 
10907 	u8         mkey[0x20];
10908 
10909 	u8         addressh_63_32[0x20];
10910 
10911 	u8         addressl_31_0[0x20];
10912 };
10913 
10914 struct mlx5_ifc_ud_adrs_vector_bits {
10915 	u8         dc_key[0x40];
10916 
10917 	u8         ext[0x1];
10918 	u8         reserved_at_41[0x7];
10919 	u8         destination_qp_dct[0x18];
10920 
10921 	u8         static_rate[0x4];
10922 	u8         sl_eth_prio[0x4];
10923 	u8         fl[0x1];
10924 	u8         mlid[0x7];
10925 	u8         rlid_udp_sport[0x10];
10926 
10927 	u8         reserved_at_80[0x20];
10928 
10929 	u8         rmac_47_16[0x20];
10930 
10931 	u8         rmac_15_0[0x10];
10932 	u8         tclass[0x8];
10933 	u8         hop_limit[0x8];
10934 
10935 	u8         reserved_at_e0[0x1];
10936 	u8         grh[0x1];
10937 	u8         reserved_at_e2[0x2];
10938 	u8         src_addr_index[0x8];
10939 	u8         flow_label[0x14];
10940 
10941 	u8         rgid_rip[16][0x8];
10942 };
10943 
10944 struct mlx5_ifc_pages_req_event_bits {
10945 	u8         reserved_at_0[0x10];
10946 	u8         function_id[0x10];
10947 
10948 	u8         num_pages[0x20];
10949 
10950 	u8         reserved_at_40[0xa0];
10951 };
10952 
10953 struct mlx5_ifc_eqe_bits {
10954 	u8         reserved_at_0[0x8];
10955 	u8         event_type[0x8];
10956 	u8         reserved_at_10[0x8];
10957 	u8         event_sub_type[0x8];
10958 
10959 	u8         reserved_at_20[0xe0];
10960 
10961 	union mlx5_ifc_event_auto_bits event_data;
10962 
10963 	u8         reserved_at_1e0[0x10];
10964 	u8         signature[0x8];
10965 	u8         reserved_at_1f8[0x7];
10966 	u8         owner[0x1];
10967 };
10968 
10969 enum {
10970 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10971 };
10972 
10973 struct mlx5_ifc_cmd_queue_entry_bits {
10974 	u8         type[0x8];
10975 	u8         reserved_at_8[0x18];
10976 
10977 	u8         input_length[0x20];
10978 
10979 	u8         input_mailbox_pointer_63_32[0x20];
10980 
10981 	u8         input_mailbox_pointer_31_9[0x17];
10982 	u8         reserved_at_77[0x9];
10983 
10984 	u8         command_input_inline_data[16][0x8];
10985 
10986 	u8         command_output_inline_data[16][0x8];
10987 
10988 	u8         output_mailbox_pointer_63_32[0x20];
10989 
10990 	u8         output_mailbox_pointer_31_9[0x17];
10991 	u8         reserved_at_1b7[0x9];
10992 
10993 	u8         output_length[0x20];
10994 
10995 	u8         token[0x8];
10996 	u8         signature[0x8];
10997 	u8         reserved_at_1f0[0x8];
10998 	u8         status[0x7];
10999 	u8         ownership[0x1];
11000 };
11001 
11002 struct mlx5_ifc_cmd_out_bits {
11003 	u8         status[0x8];
11004 	u8         reserved_at_8[0x18];
11005 
11006 	u8         syndrome[0x20];
11007 
11008 	u8         command_output[0x20];
11009 };
11010 
11011 struct mlx5_ifc_cmd_in_bits {
11012 	u8         opcode[0x10];
11013 	u8         reserved_at_10[0x10];
11014 
11015 	u8         reserved_at_20[0x10];
11016 	u8         op_mod[0x10];
11017 
11018 	u8         command[][0x20];
11019 };
11020 
11021 struct mlx5_ifc_cmd_if_box_bits {
11022 	u8         mailbox_data[512][0x8];
11023 
11024 	u8         reserved_at_1000[0x180];
11025 
11026 	u8         next_pointer_63_32[0x20];
11027 
11028 	u8         next_pointer_31_10[0x16];
11029 	u8         reserved_at_11b6[0xa];
11030 
11031 	u8         block_number[0x20];
11032 
11033 	u8         reserved_at_11e0[0x8];
11034 	u8         token[0x8];
11035 	u8         ctrl_signature[0x8];
11036 	u8         signature[0x8];
11037 };
11038 
11039 struct mlx5_ifc_mtt_bits {
11040 	u8         ptag_63_32[0x20];
11041 
11042 	u8         ptag_31_8[0x18];
11043 	u8         reserved_at_38[0x6];
11044 	u8         wr_en[0x1];
11045 	u8         rd_en[0x1];
11046 };
11047 
11048 struct mlx5_ifc_query_wol_rol_out_bits {
11049 	u8         status[0x8];
11050 	u8         reserved_at_8[0x18];
11051 
11052 	u8         syndrome[0x20];
11053 
11054 	u8         reserved_at_40[0x10];
11055 	u8         rol_mode[0x8];
11056 	u8         wol_mode[0x8];
11057 
11058 	u8         reserved_at_60[0x20];
11059 };
11060 
11061 struct mlx5_ifc_query_wol_rol_in_bits {
11062 	u8         opcode[0x10];
11063 	u8         reserved_at_10[0x10];
11064 
11065 	u8         reserved_at_20[0x10];
11066 	u8         op_mod[0x10];
11067 
11068 	u8         reserved_at_40[0x40];
11069 };
11070 
11071 struct mlx5_ifc_set_wol_rol_out_bits {
11072 	u8         status[0x8];
11073 	u8         reserved_at_8[0x18];
11074 
11075 	u8         syndrome[0x20];
11076 
11077 	u8         reserved_at_40[0x40];
11078 };
11079 
11080 struct mlx5_ifc_set_wol_rol_in_bits {
11081 	u8         opcode[0x10];
11082 	u8         reserved_at_10[0x10];
11083 
11084 	u8         reserved_at_20[0x10];
11085 	u8         op_mod[0x10];
11086 
11087 	u8         rol_mode_valid[0x1];
11088 	u8         wol_mode_valid[0x1];
11089 	u8         reserved_at_42[0xe];
11090 	u8         rol_mode[0x8];
11091 	u8         wol_mode[0x8];
11092 
11093 	u8         reserved_at_60[0x20];
11094 };
11095 
11096 enum {
11097 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
11098 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
11099 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
11100 	MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET     = 0x7,
11101 };
11102 
11103 enum {
11104 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
11105 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
11106 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
11107 };
11108 
11109 enum {
11110 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
11111 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
11112 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
11113 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
11114 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
11115 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
11116 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
11117 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
11118 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
11119 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
11120 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
11121 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR         = 0x12,
11122 };
11123 
11124 struct mlx5_ifc_initial_seg_bits {
11125 	u8         fw_rev_minor[0x10];
11126 	u8         fw_rev_major[0x10];
11127 
11128 	u8         cmd_interface_rev[0x10];
11129 	u8         fw_rev_subminor[0x10];
11130 
11131 	u8         reserved_at_40[0x40];
11132 
11133 	u8         cmdq_phy_addr_63_32[0x20];
11134 
11135 	u8         cmdq_phy_addr_31_12[0x14];
11136 	u8         reserved_at_b4[0x2];
11137 	u8         nic_interface[0x2];
11138 	u8         log_cmdq_size[0x4];
11139 	u8         log_cmdq_stride[0x4];
11140 
11141 	u8         command_doorbell_vector[0x20];
11142 
11143 	u8         reserved_at_e0[0xf00];
11144 
11145 	u8         initializing[0x1];
11146 	u8         reserved_at_fe1[0x4];
11147 	u8         nic_interface_supported[0x3];
11148 	u8         embedded_cpu[0x1];
11149 	u8         reserved_at_fe9[0x17];
11150 
11151 	struct mlx5_ifc_health_buffer_bits health_buffer;
11152 
11153 	u8         no_dram_nic_offset[0x20];
11154 
11155 	u8         reserved_at_1220[0x6e40];
11156 
11157 	u8         reserved_at_8060[0x1f];
11158 	u8         clear_int[0x1];
11159 
11160 	u8         health_syndrome[0x8];
11161 	u8         health_counter[0x18];
11162 
11163 	u8         reserved_at_80a0[0x17fc0];
11164 };
11165 
11166 struct mlx5_ifc_mtpps_reg_bits {
11167 	u8         reserved_at_0[0xc];
11168 	u8         cap_number_of_pps_pins[0x4];
11169 	u8         reserved_at_10[0x4];
11170 	u8         cap_max_num_of_pps_in_pins[0x4];
11171 	u8         reserved_at_18[0x4];
11172 	u8         cap_max_num_of_pps_out_pins[0x4];
11173 
11174 	u8         reserved_at_20[0x13];
11175 	u8         cap_log_min_npps_period[0x5];
11176 	u8         reserved_at_38[0x3];
11177 	u8         cap_log_min_out_pulse_duration_ns[0x5];
11178 
11179 	u8         reserved_at_40[0x4];
11180 	u8         cap_pin_3_mode[0x4];
11181 	u8         reserved_at_48[0x4];
11182 	u8         cap_pin_2_mode[0x4];
11183 	u8         reserved_at_50[0x4];
11184 	u8         cap_pin_1_mode[0x4];
11185 	u8         reserved_at_58[0x4];
11186 	u8         cap_pin_0_mode[0x4];
11187 
11188 	u8         reserved_at_60[0x4];
11189 	u8         cap_pin_7_mode[0x4];
11190 	u8         reserved_at_68[0x4];
11191 	u8         cap_pin_6_mode[0x4];
11192 	u8         reserved_at_70[0x4];
11193 	u8         cap_pin_5_mode[0x4];
11194 	u8         reserved_at_78[0x4];
11195 	u8         cap_pin_4_mode[0x4];
11196 
11197 	u8         field_select[0x20];
11198 	u8         reserved_at_a0[0x20];
11199 
11200 	u8         npps_period[0x40];
11201 
11202 	u8         enable[0x1];
11203 	u8         reserved_at_101[0xb];
11204 	u8         pattern[0x4];
11205 	u8         reserved_at_110[0x4];
11206 	u8         pin_mode[0x4];
11207 	u8         pin[0x8];
11208 
11209 	u8         reserved_at_120[0x2];
11210 	u8         out_pulse_duration_ns[0x1e];
11211 
11212 	u8         time_stamp[0x40];
11213 
11214 	u8         out_pulse_duration[0x10];
11215 	u8         out_periodic_adjustment[0x10];
11216 	u8         enhanced_out_periodic_adjustment[0x20];
11217 
11218 	u8         reserved_at_1c0[0x20];
11219 };
11220 
11221 struct mlx5_ifc_mtppse_reg_bits {
11222 	u8         reserved_at_0[0x18];
11223 	u8         pin[0x8];
11224 	u8         event_arm[0x1];
11225 	u8         reserved_at_21[0x1b];
11226 	u8         event_generation_mode[0x4];
11227 	u8         reserved_at_40[0x40];
11228 };
11229 
11230 struct mlx5_ifc_mcqs_reg_bits {
11231 	u8         last_index_flag[0x1];
11232 	u8         reserved_at_1[0x7];
11233 	u8         fw_device[0x8];
11234 	u8         component_index[0x10];
11235 
11236 	u8         reserved_at_20[0x10];
11237 	u8         identifier[0x10];
11238 
11239 	u8         reserved_at_40[0x17];
11240 	u8         component_status[0x5];
11241 	u8         component_update_state[0x4];
11242 
11243 	u8         last_update_state_changer_type[0x4];
11244 	u8         last_update_state_changer_host_id[0x4];
11245 	u8         reserved_at_68[0x18];
11246 };
11247 
11248 struct mlx5_ifc_mcqi_cap_bits {
11249 	u8         supported_info_bitmask[0x20];
11250 
11251 	u8         component_size[0x20];
11252 
11253 	u8         max_component_size[0x20];
11254 
11255 	u8         log_mcda_word_size[0x4];
11256 	u8         reserved_at_64[0xc];
11257 	u8         mcda_max_write_size[0x10];
11258 
11259 	u8         rd_en[0x1];
11260 	u8         reserved_at_81[0x1];
11261 	u8         match_chip_id[0x1];
11262 	u8         match_psid[0x1];
11263 	u8         check_user_timestamp[0x1];
11264 	u8         match_base_guid_mac[0x1];
11265 	u8         reserved_at_86[0x1a];
11266 };
11267 
11268 struct mlx5_ifc_mcqi_version_bits {
11269 	u8         reserved_at_0[0x2];
11270 	u8         build_time_valid[0x1];
11271 	u8         user_defined_time_valid[0x1];
11272 	u8         reserved_at_4[0x14];
11273 	u8         version_string_length[0x8];
11274 
11275 	u8         version[0x20];
11276 
11277 	u8         build_time[0x40];
11278 
11279 	u8         user_defined_time[0x40];
11280 
11281 	u8         build_tool_version[0x20];
11282 
11283 	u8         reserved_at_e0[0x20];
11284 
11285 	u8         version_string[92][0x8];
11286 };
11287 
11288 struct mlx5_ifc_mcqi_activation_method_bits {
11289 	u8         pending_server_ac_power_cycle[0x1];
11290 	u8         pending_server_dc_power_cycle[0x1];
11291 	u8         pending_server_reboot[0x1];
11292 	u8         pending_fw_reset[0x1];
11293 	u8         auto_activate[0x1];
11294 	u8         all_hosts_sync[0x1];
11295 	u8         device_hw_reset[0x1];
11296 	u8         reserved_at_7[0x19];
11297 };
11298 
11299 union mlx5_ifc_mcqi_reg_data_bits {
11300 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
11301 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
11302 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
11303 };
11304 
11305 struct mlx5_ifc_mcqi_reg_bits {
11306 	u8         read_pending_component[0x1];
11307 	u8         reserved_at_1[0xf];
11308 	u8         component_index[0x10];
11309 
11310 	u8         reserved_at_20[0x20];
11311 
11312 	u8         reserved_at_40[0x1b];
11313 	u8         info_type[0x5];
11314 
11315 	u8         info_size[0x20];
11316 
11317 	u8         offset[0x20];
11318 
11319 	u8         reserved_at_a0[0x10];
11320 	u8         data_size[0x10];
11321 
11322 	union mlx5_ifc_mcqi_reg_data_bits data[];
11323 };
11324 
11325 struct mlx5_ifc_mcc_reg_bits {
11326 	u8         reserved_at_0[0x4];
11327 	u8         time_elapsed_since_last_cmd[0xc];
11328 	u8         reserved_at_10[0x8];
11329 	u8         instruction[0x8];
11330 
11331 	u8         reserved_at_20[0x10];
11332 	u8         component_index[0x10];
11333 
11334 	u8         reserved_at_40[0x8];
11335 	u8         update_handle[0x18];
11336 
11337 	u8         handle_owner_type[0x4];
11338 	u8         handle_owner_host_id[0x4];
11339 	u8         reserved_at_68[0x1];
11340 	u8         control_progress[0x7];
11341 	u8         error_code[0x8];
11342 	u8         reserved_at_78[0x4];
11343 	u8         control_state[0x4];
11344 
11345 	u8         component_size[0x20];
11346 
11347 	u8         reserved_at_a0[0x60];
11348 };
11349 
11350 struct mlx5_ifc_mcda_reg_bits {
11351 	u8         reserved_at_0[0x8];
11352 	u8         update_handle[0x18];
11353 
11354 	u8         offset[0x20];
11355 
11356 	u8         reserved_at_40[0x10];
11357 	u8         size[0x10];
11358 
11359 	u8         reserved_at_60[0x20];
11360 
11361 	u8         data[][0x20];
11362 };
11363 
11364 enum {
11365 	MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0,
11366 	MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1,
11367 };
11368 
11369 enum {
11370 	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
11371 	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
11372 	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
11373 	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
11374 	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
11375 	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
11376 };
11377 
11378 enum {
11379 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
11380 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
11381 };
11382 
11383 enum {
11384 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
11385 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
11386 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
11387 };
11388 
11389 struct mlx5_ifc_mfrl_reg_bits {
11390 	u8         reserved_at_0[0x20];
11391 
11392 	u8         reserved_at_20[0x2];
11393 	u8         pci_sync_for_fw_update_start[0x1];
11394 	u8         pci_sync_for_fw_update_resp[0x2];
11395 	u8         rst_type_sel[0x3];
11396 	u8         pci_reset_req_method[0x3];
11397 	u8         reserved_at_2b[0x1];
11398 	u8         reset_state[0x4];
11399 	u8         reset_type[0x8];
11400 	u8         reset_level[0x8];
11401 };
11402 
11403 struct mlx5_ifc_mirc_reg_bits {
11404 	u8         reserved_at_0[0x18];
11405 	u8         status_code[0x8];
11406 
11407 	u8         reserved_at_20[0x20];
11408 };
11409 
11410 struct mlx5_ifc_pddr_monitor_opcode_bits {
11411 	u8         reserved_at_0[0x10];
11412 	u8         monitor_opcode[0x10];
11413 };
11414 
11415 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
11416 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11417 	u8         reserved_at_0[0x20];
11418 };
11419 
11420 enum {
11421 	/* Monitor opcodes */
11422 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
11423 };
11424 
11425 struct mlx5_ifc_pddr_troubleshooting_page_bits {
11426 	u8         reserved_at_0[0x10];
11427 	u8         group_opcode[0x10];
11428 
11429 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
11430 
11431 	u8         reserved_at_40[0x20];
11432 
11433 	u8         status_message[59][0x20];
11434 };
11435 
11436 union mlx5_ifc_pddr_reg_page_data_auto_bits {
11437 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11438 	u8         reserved_at_0[0x7c0];
11439 };
11440 
11441 enum {
11442 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
11443 };
11444 
11445 struct mlx5_ifc_pddr_reg_bits {
11446 	u8         reserved_at_0[0x8];
11447 	u8         local_port[0x8];
11448 	u8         pnat[0x2];
11449 	u8         reserved_at_12[0xe];
11450 
11451 	u8         reserved_at_20[0x18];
11452 	u8         page_select[0x8];
11453 
11454 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11455 };
11456 
11457 struct mlx5_ifc_mrtc_reg_bits {
11458 	u8         time_synced[0x1];
11459 	u8         reserved_at_1[0x1f];
11460 
11461 	u8         reserved_at_20[0x20];
11462 
11463 	u8         time_h[0x20];
11464 
11465 	u8         time_l[0x20];
11466 };
11467 
11468 struct mlx5_ifc_mtcap_reg_bits {
11469 	u8         reserved_at_0[0x19];
11470 	u8         sensor_count[0x7];
11471 
11472 	u8         reserved_at_20[0x20];
11473 
11474 	u8         sensor_map[0x40];
11475 };
11476 
11477 struct mlx5_ifc_mtmp_reg_bits {
11478 	u8         reserved_at_0[0x14];
11479 	u8         sensor_index[0xc];
11480 
11481 	u8         reserved_at_20[0x10];
11482 	u8         temperature[0x10];
11483 
11484 	u8         mte[0x1];
11485 	u8         mtr[0x1];
11486 	u8         reserved_at_42[0xe];
11487 	u8         max_temperature[0x10];
11488 
11489 	u8         tee[0x2];
11490 	u8         reserved_at_62[0xe];
11491 	u8         temp_threshold_hi[0x10];
11492 
11493 	u8         reserved_at_80[0x10];
11494 	u8         temp_threshold_lo[0x10];
11495 
11496 	u8         reserved_at_a0[0x20];
11497 
11498 	u8         sensor_name_hi[0x20];
11499 	u8         sensor_name_lo[0x20];
11500 };
11501 
11502 struct mlx5_ifc_mtptm_reg_bits {
11503 	u8         reserved_at_0[0x10];
11504 	u8         psta[0x1];
11505 	u8         reserved_at_11[0xf];
11506 
11507 	u8         reserved_at_20[0x60];
11508 };
11509 
11510 enum {
11511 	MLX5_MTCTR_REQUEST_NOP = 0x0,
11512 	MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1,
11513 	MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2,
11514 	MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3,
11515 };
11516 
11517 struct mlx5_ifc_mtctr_reg_bits {
11518 	u8         first_clock_timestamp_request[0x8];
11519 	u8         second_clock_timestamp_request[0x8];
11520 	u8         reserved_at_10[0x10];
11521 
11522 	u8         first_clock_valid[0x1];
11523 	u8         second_clock_valid[0x1];
11524 	u8         reserved_at_22[0x1e];
11525 
11526 	u8         first_clock_timestamp[0x40];
11527 	u8         second_clock_timestamp[0x40];
11528 };
11529 
11530 union mlx5_ifc_ports_control_registers_document_bits {
11531 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11532 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11533 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11534 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11535 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11536 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11537 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11538 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11539 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11540 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11541 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11542 	struct mlx5_ifc_paos_reg_bits paos_reg;
11543 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11544 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11545 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11546 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11547 	struct mlx5_ifc_peir_reg_bits peir_reg;
11548 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11549 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11550 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11551 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11552 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11553 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11554 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11555 	struct mlx5_ifc_plib_reg_bits plib_reg;
11556 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11557 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11558 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11559 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11560 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11561 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11562 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11563 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11564 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11565 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11566 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11567 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11568 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11569 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11570 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11571 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11572 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11573 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11574 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11575 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11576 	struct mlx5_ifc_pude_reg_bits pude_reg;
11577 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11578 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11579 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11580 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11581 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11582 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11583 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11584 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11585 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11586 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11587 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11588 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11589 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11590 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11591 	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11592 	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11593 	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11594 	struct mlx5_ifc_mtptm_reg_bits mtptm_reg;
11595 	struct mlx5_ifc_mtctr_reg_bits mtctr_reg;
11596 	u8         reserved_at_0[0x60e0];
11597 };
11598 
11599 union mlx5_ifc_debug_enhancements_document_bits {
11600 	struct mlx5_ifc_health_buffer_bits health_buffer;
11601 	u8         reserved_at_0[0x200];
11602 };
11603 
11604 union mlx5_ifc_uplink_pci_interface_document_bits {
11605 	struct mlx5_ifc_initial_seg_bits initial_seg;
11606 	u8         reserved_at_0[0x20060];
11607 };
11608 
11609 struct mlx5_ifc_set_flow_table_root_out_bits {
11610 	u8         status[0x8];
11611 	u8         reserved_at_8[0x18];
11612 
11613 	u8         syndrome[0x20];
11614 
11615 	u8         reserved_at_40[0x40];
11616 };
11617 
11618 struct mlx5_ifc_set_flow_table_root_in_bits {
11619 	u8         opcode[0x10];
11620 	u8         reserved_at_10[0x10];
11621 
11622 	u8         reserved_at_20[0x10];
11623 	u8         op_mod[0x10];
11624 
11625 	u8         other_vport[0x1];
11626 	u8         reserved_at_41[0xf];
11627 	u8         vport_number[0x10];
11628 
11629 	u8         reserved_at_60[0x20];
11630 
11631 	u8         table_type[0x8];
11632 	u8         reserved_at_88[0x7];
11633 	u8         table_of_other_vport[0x1];
11634 	u8         table_vport_number[0x10];
11635 
11636 	u8         reserved_at_a0[0x8];
11637 	u8         table_id[0x18];
11638 
11639 	u8         reserved_at_c0[0x8];
11640 	u8         underlay_qpn[0x18];
11641 	u8         table_eswitch_owner_vhca_id_valid[0x1];
11642 	u8         reserved_at_e1[0xf];
11643 	u8         table_eswitch_owner_vhca_id[0x10];
11644 	u8         reserved_at_100[0x100];
11645 };
11646 
11647 enum {
11648 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11649 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11650 };
11651 
11652 struct mlx5_ifc_modify_flow_table_out_bits {
11653 	u8         status[0x8];
11654 	u8         reserved_at_8[0x18];
11655 
11656 	u8         syndrome[0x20];
11657 
11658 	u8         reserved_at_40[0x40];
11659 };
11660 
11661 struct mlx5_ifc_modify_flow_table_in_bits {
11662 	u8         opcode[0x10];
11663 	u8         reserved_at_10[0x10];
11664 
11665 	u8         reserved_at_20[0x10];
11666 	u8         op_mod[0x10];
11667 
11668 	u8         other_vport[0x1];
11669 	u8         reserved_at_41[0xf];
11670 	u8         vport_number[0x10];
11671 
11672 	u8         reserved_at_60[0x10];
11673 	u8         modify_field_select[0x10];
11674 
11675 	u8         table_type[0x8];
11676 	u8         reserved_at_88[0x18];
11677 
11678 	u8         reserved_at_a0[0x8];
11679 	u8         table_id[0x18];
11680 
11681 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11682 };
11683 
11684 struct mlx5_ifc_ets_tcn_config_reg_bits {
11685 	u8         g[0x1];
11686 	u8         b[0x1];
11687 	u8         r[0x1];
11688 	u8         reserved_at_3[0x9];
11689 	u8         group[0x4];
11690 	u8         reserved_at_10[0x9];
11691 	u8         bw_allocation[0x7];
11692 
11693 	u8         reserved_at_20[0xc];
11694 	u8         max_bw_units[0x4];
11695 	u8         reserved_at_30[0x8];
11696 	u8         max_bw_value[0x8];
11697 };
11698 
11699 struct mlx5_ifc_ets_global_config_reg_bits {
11700 	u8         reserved_at_0[0x2];
11701 	u8         r[0x1];
11702 	u8         reserved_at_3[0x1d];
11703 
11704 	u8         reserved_at_20[0xc];
11705 	u8         max_bw_units[0x4];
11706 	u8         reserved_at_30[0x8];
11707 	u8         max_bw_value[0x8];
11708 };
11709 
11710 struct mlx5_ifc_qetc_reg_bits {
11711 	u8                                         reserved_at_0[0x8];
11712 	u8                                         port_number[0x8];
11713 	u8                                         reserved_at_10[0x30];
11714 
11715 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11716 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11717 };
11718 
11719 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11720 	u8         e[0x1];
11721 	u8         reserved_at_01[0x0b];
11722 	u8         prio[0x04];
11723 };
11724 
11725 struct mlx5_ifc_qpdpm_reg_bits {
11726 	u8                                     reserved_at_0[0x8];
11727 	u8                                     local_port[0x8];
11728 	u8                                     reserved_at_10[0x10];
11729 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11730 };
11731 
11732 struct mlx5_ifc_qpts_reg_bits {
11733 	u8         reserved_at_0[0x8];
11734 	u8         local_port[0x8];
11735 	u8         reserved_at_10[0x2d];
11736 	u8         trust_state[0x3];
11737 };
11738 
11739 struct mlx5_ifc_pptb_reg_bits {
11740 	u8         reserved_at_0[0x2];
11741 	u8         mm[0x2];
11742 	u8         reserved_at_4[0x4];
11743 	u8         local_port[0x8];
11744 	u8         reserved_at_10[0x6];
11745 	u8         cm[0x1];
11746 	u8         um[0x1];
11747 	u8         pm[0x8];
11748 
11749 	u8         prio_x_buff[0x20];
11750 
11751 	u8         pm_msb[0x8];
11752 	u8         reserved_at_48[0x10];
11753 	u8         ctrl_buff[0x4];
11754 	u8         untagged_buff[0x4];
11755 };
11756 
11757 struct mlx5_ifc_sbcam_reg_bits {
11758 	u8         reserved_at_0[0x8];
11759 	u8         feature_group[0x8];
11760 	u8         reserved_at_10[0x8];
11761 	u8         access_reg_group[0x8];
11762 
11763 	u8         reserved_at_20[0x20];
11764 
11765 	u8         sb_access_reg_cap_mask[4][0x20];
11766 
11767 	u8         reserved_at_c0[0x80];
11768 
11769 	u8         sb_feature_cap_mask[4][0x20];
11770 
11771 	u8         reserved_at_1c0[0x40];
11772 
11773 	u8         cap_total_buffer_size[0x20];
11774 
11775 	u8         cap_cell_size[0x10];
11776 	u8         cap_max_pg_buffers[0x8];
11777 	u8         cap_num_pool_supported[0x8];
11778 
11779 	u8         reserved_at_240[0x8];
11780 	u8         cap_sbsr_stat_size[0x8];
11781 	u8         cap_max_tclass_data[0x8];
11782 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
11783 };
11784 
11785 struct mlx5_ifc_pbmc_reg_bits {
11786 	u8         reserved_at_0[0x8];
11787 	u8         local_port[0x8];
11788 	u8         reserved_at_10[0x10];
11789 
11790 	u8         xoff_timer_value[0x10];
11791 	u8         xoff_refresh[0x10];
11792 
11793 	u8         reserved_at_40[0x9];
11794 	u8         fullness_threshold[0x7];
11795 	u8         port_buffer_size[0x10];
11796 
11797 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
11798 
11799 	u8         reserved_at_2e0[0x80];
11800 };
11801 
11802 struct mlx5_ifc_sbpr_reg_bits {
11803 	u8         desc[0x1];
11804 	u8         snap[0x1];
11805 	u8         reserved_at_2[0x4];
11806 	u8         dir[0x2];
11807 	u8         reserved_at_8[0x14];
11808 	u8         pool[0x4];
11809 
11810 	u8         infi_size[0x1];
11811 	u8         reserved_at_21[0x7];
11812 	u8         size[0x18];
11813 
11814 	u8         reserved_at_40[0x1c];
11815 	u8         mode[0x4];
11816 
11817 	u8         reserved_at_60[0x8];
11818 	u8         buff_occupancy[0x18];
11819 
11820 	u8         clr[0x1];
11821 	u8         reserved_at_81[0x7];
11822 	u8         max_buff_occupancy[0x18];
11823 
11824 	u8         reserved_at_a0[0x8];
11825 	u8         ext_buff_occupancy[0x18];
11826 };
11827 
11828 struct mlx5_ifc_sbcm_reg_bits {
11829 	u8         desc[0x1];
11830 	u8         snap[0x1];
11831 	u8         reserved_at_2[0x6];
11832 	u8         local_port[0x8];
11833 	u8         pnat[0x2];
11834 	u8         pg_buff[0x6];
11835 	u8         reserved_at_18[0x6];
11836 	u8         dir[0x2];
11837 
11838 	u8         reserved_at_20[0x1f];
11839 	u8         exc[0x1];
11840 
11841 	u8         reserved_at_40[0x40];
11842 
11843 	u8         reserved_at_80[0x8];
11844 	u8         buff_occupancy[0x18];
11845 
11846 	u8         clr[0x1];
11847 	u8         reserved_at_a1[0x7];
11848 	u8         max_buff_occupancy[0x18];
11849 
11850 	u8         reserved_at_c0[0x8];
11851 	u8         min_buff[0x18];
11852 
11853 	u8         infi_max[0x1];
11854 	u8         reserved_at_e1[0x7];
11855 	u8         max_buff[0x18];
11856 
11857 	u8         reserved_at_100[0x20];
11858 
11859 	u8         reserved_at_120[0x1c];
11860 	u8         pool[0x4];
11861 };
11862 
11863 struct mlx5_ifc_qtct_reg_bits {
11864 	u8         reserved_at_0[0x8];
11865 	u8         port_number[0x8];
11866 	u8         reserved_at_10[0xd];
11867 	u8         prio[0x3];
11868 
11869 	u8         reserved_at_20[0x1d];
11870 	u8         tclass[0x3];
11871 };
11872 
11873 struct mlx5_ifc_mcia_reg_bits {
11874 	u8         l[0x1];
11875 	u8         reserved_at_1[0x7];
11876 	u8         module[0x8];
11877 	u8         reserved_at_10[0x8];
11878 	u8         status[0x8];
11879 
11880 	u8         i2c_device_address[0x8];
11881 	u8         page_number[0x8];
11882 	u8         device_address[0x10];
11883 
11884 	u8         reserved_at_40[0x10];
11885 	u8         size[0x10];
11886 
11887 	u8         reserved_at_60[0x20];
11888 
11889 	u8         dword_0[0x20];
11890 	u8         dword_1[0x20];
11891 	u8         dword_2[0x20];
11892 	u8         dword_3[0x20];
11893 	u8         dword_4[0x20];
11894 	u8         dword_5[0x20];
11895 	u8         dword_6[0x20];
11896 	u8         dword_7[0x20];
11897 	u8         dword_8[0x20];
11898 	u8         dword_9[0x20];
11899 	u8         dword_10[0x20];
11900 	u8         dword_11[0x20];
11901 };
11902 
11903 struct mlx5_ifc_dcbx_param_bits {
11904 	u8         dcbx_cee_cap[0x1];
11905 	u8         dcbx_ieee_cap[0x1];
11906 	u8         dcbx_standby_cap[0x1];
11907 	u8         reserved_at_3[0x5];
11908 	u8         port_number[0x8];
11909 	u8         reserved_at_10[0xa];
11910 	u8         max_application_table_size[6];
11911 	u8         reserved_at_20[0x15];
11912 	u8         version_oper[0x3];
11913 	u8         reserved_at_38[5];
11914 	u8         version_admin[0x3];
11915 	u8         willing_admin[0x1];
11916 	u8         reserved_at_41[0x3];
11917 	u8         pfc_cap_oper[0x4];
11918 	u8         reserved_at_48[0x4];
11919 	u8         pfc_cap_admin[0x4];
11920 	u8         reserved_at_50[0x4];
11921 	u8         num_of_tc_oper[0x4];
11922 	u8         reserved_at_58[0x4];
11923 	u8         num_of_tc_admin[0x4];
11924 	u8         remote_willing[0x1];
11925 	u8         reserved_at_61[3];
11926 	u8         remote_pfc_cap[4];
11927 	u8         reserved_at_68[0x14];
11928 	u8         remote_num_of_tc[0x4];
11929 	u8         reserved_at_80[0x18];
11930 	u8         error[0x8];
11931 	u8         reserved_at_a0[0x160];
11932 };
11933 
11934 enum {
11935 	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11936 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11937 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11938 };
11939 
11940 struct mlx5_ifc_lagc_bits {
11941 	u8         fdb_selection_mode[0x1];
11942 	u8         reserved_at_1[0x14];
11943 	u8         port_select_mode[0x3];
11944 	u8         reserved_at_18[0x5];
11945 	u8         lag_state[0x3];
11946 
11947 	u8         reserved_at_20[0xc];
11948 	u8         active_port[0x4];
11949 	u8         reserved_at_30[0x4];
11950 	u8         tx_remap_affinity_2[0x4];
11951 	u8         reserved_at_38[0x4];
11952 	u8         tx_remap_affinity_1[0x4];
11953 };
11954 
11955 struct mlx5_ifc_create_lag_out_bits {
11956 	u8         status[0x8];
11957 	u8         reserved_at_8[0x18];
11958 
11959 	u8         syndrome[0x20];
11960 
11961 	u8         reserved_at_40[0x40];
11962 };
11963 
11964 struct mlx5_ifc_create_lag_in_bits {
11965 	u8         opcode[0x10];
11966 	u8         reserved_at_10[0x10];
11967 
11968 	u8         reserved_at_20[0x10];
11969 	u8         op_mod[0x10];
11970 
11971 	struct mlx5_ifc_lagc_bits ctx;
11972 };
11973 
11974 struct mlx5_ifc_modify_lag_out_bits {
11975 	u8         status[0x8];
11976 	u8         reserved_at_8[0x18];
11977 
11978 	u8         syndrome[0x20];
11979 
11980 	u8         reserved_at_40[0x40];
11981 };
11982 
11983 struct mlx5_ifc_modify_lag_in_bits {
11984 	u8         opcode[0x10];
11985 	u8         reserved_at_10[0x10];
11986 
11987 	u8         reserved_at_20[0x10];
11988 	u8         op_mod[0x10];
11989 
11990 	u8         reserved_at_40[0x20];
11991 	u8         field_select[0x20];
11992 
11993 	struct mlx5_ifc_lagc_bits ctx;
11994 };
11995 
11996 struct mlx5_ifc_query_lag_out_bits {
11997 	u8         status[0x8];
11998 	u8         reserved_at_8[0x18];
11999 
12000 	u8         syndrome[0x20];
12001 
12002 	struct mlx5_ifc_lagc_bits ctx;
12003 };
12004 
12005 struct mlx5_ifc_query_lag_in_bits {
12006 	u8         opcode[0x10];
12007 	u8         reserved_at_10[0x10];
12008 
12009 	u8         reserved_at_20[0x10];
12010 	u8         op_mod[0x10];
12011 
12012 	u8         reserved_at_40[0x40];
12013 };
12014 
12015 struct mlx5_ifc_destroy_lag_out_bits {
12016 	u8         status[0x8];
12017 	u8         reserved_at_8[0x18];
12018 
12019 	u8         syndrome[0x20];
12020 
12021 	u8         reserved_at_40[0x40];
12022 };
12023 
12024 struct mlx5_ifc_destroy_lag_in_bits {
12025 	u8         opcode[0x10];
12026 	u8         reserved_at_10[0x10];
12027 
12028 	u8         reserved_at_20[0x10];
12029 	u8         op_mod[0x10];
12030 
12031 	u8         reserved_at_40[0x40];
12032 };
12033 
12034 struct mlx5_ifc_create_vport_lag_out_bits {
12035 	u8         status[0x8];
12036 	u8         reserved_at_8[0x18];
12037 
12038 	u8         syndrome[0x20];
12039 
12040 	u8         reserved_at_40[0x40];
12041 };
12042 
12043 struct mlx5_ifc_create_vport_lag_in_bits {
12044 	u8         opcode[0x10];
12045 	u8         reserved_at_10[0x10];
12046 
12047 	u8         reserved_at_20[0x10];
12048 	u8         op_mod[0x10];
12049 
12050 	u8         reserved_at_40[0x40];
12051 };
12052 
12053 struct mlx5_ifc_destroy_vport_lag_out_bits {
12054 	u8         status[0x8];
12055 	u8         reserved_at_8[0x18];
12056 
12057 	u8         syndrome[0x20];
12058 
12059 	u8         reserved_at_40[0x40];
12060 };
12061 
12062 struct mlx5_ifc_destroy_vport_lag_in_bits {
12063 	u8         opcode[0x10];
12064 	u8         reserved_at_10[0x10];
12065 
12066 	u8         reserved_at_20[0x10];
12067 	u8         op_mod[0x10];
12068 
12069 	u8         reserved_at_40[0x40];
12070 };
12071 
12072 enum {
12073 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
12074 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
12075 };
12076 
12077 struct mlx5_ifc_modify_memic_in_bits {
12078 	u8         opcode[0x10];
12079 	u8         uid[0x10];
12080 
12081 	u8         reserved_at_20[0x10];
12082 	u8         op_mod[0x10];
12083 
12084 	u8         reserved_at_40[0x20];
12085 
12086 	u8         reserved_at_60[0x18];
12087 	u8         memic_operation_type[0x8];
12088 
12089 	u8         memic_start_addr[0x40];
12090 
12091 	u8         reserved_at_c0[0x140];
12092 };
12093 
12094 struct mlx5_ifc_modify_memic_out_bits {
12095 	u8         status[0x8];
12096 	u8         reserved_at_8[0x18];
12097 
12098 	u8         syndrome[0x20];
12099 
12100 	u8         reserved_at_40[0x40];
12101 
12102 	u8         memic_operation_addr[0x40];
12103 
12104 	u8         reserved_at_c0[0x140];
12105 };
12106 
12107 struct mlx5_ifc_alloc_memic_in_bits {
12108 	u8         opcode[0x10];
12109 	u8         reserved_at_10[0x10];
12110 
12111 	u8         reserved_at_20[0x10];
12112 	u8         op_mod[0x10];
12113 
12114 	u8         reserved_at_30[0x20];
12115 
12116 	u8	   reserved_at_40[0x18];
12117 	u8	   log_memic_addr_alignment[0x8];
12118 
12119 	u8         range_start_addr[0x40];
12120 
12121 	u8         range_size[0x20];
12122 
12123 	u8         memic_size[0x20];
12124 };
12125 
12126 struct mlx5_ifc_alloc_memic_out_bits {
12127 	u8         status[0x8];
12128 	u8         reserved_at_8[0x18];
12129 
12130 	u8         syndrome[0x20];
12131 
12132 	u8         memic_start_addr[0x40];
12133 };
12134 
12135 struct mlx5_ifc_dealloc_memic_in_bits {
12136 	u8         opcode[0x10];
12137 	u8         reserved_at_10[0x10];
12138 
12139 	u8         reserved_at_20[0x10];
12140 	u8         op_mod[0x10];
12141 
12142 	u8         reserved_at_40[0x40];
12143 
12144 	u8         memic_start_addr[0x40];
12145 
12146 	u8         memic_size[0x20];
12147 
12148 	u8         reserved_at_e0[0x20];
12149 };
12150 
12151 struct mlx5_ifc_dealloc_memic_out_bits {
12152 	u8         status[0x8];
12153 	u8         reserved_at_8[0x18];
12154 
12155 	u8         syndrome[0x20];
12156 
12157 	u8         reserved_at_40[0x40];
12158 };
12159 
12160 struct mlx5_ifc_umem_bits {
12161 	u8         reserved_at_0[0x80];
12162 
12163 	u8         ats[0x1];
12164 	u8         reserved_at_81[0x1a];
12165 	u8         log_page_size[0x5];
12166 
12167 	u8         page_offset[0x20];
12168 
12169 	u8         num_of_mtt[0x40];
12170 
12171 	struct mlx5_ifc_mtt_bits  mtt[];
12172 };
12173 
12174 struct mlx5_ifc_uctx_bits {
12175 	u8         cap[0x20];
12176 
12177 	u8         reserved_at_20[0x160];
12178 };
12179 
12180 struct mlx5_ifc_sw_icm_bits {
12181 	u8         modify_field_select[0x40];
12182 
12183 	u8	   reserved_at_40[0x18];
12184 	u8         log_sw_icm_size[0x8];
12185 
12186 	u8         reserved_at_60[0x20];
12187 
12188 	u8         sw_icm_start_addr[0x40];
12189 
12190 	u8         reserved_at_c0[0x140];
12191 };
12192 
12193 struct mlx5_ifc_geneve_tlv_option_bits {
12194 	u8         modify_field_select[0x40];
12195 
12196 	u8         reserved_at_40[0x18];
12197 	u8         geneve_option_fte_index[0x8];
12198 
12199 	u8         option_class[0x10];
12200 	u8         option_type[0x8];
12201 	u8         reserved_at_78[0x3];
12202 	u8         option_data_length[0x5];
12203 
12204 	u8         reserved_at_80[0x180];
12205 };
12206 
12207 struct mlx5_ifc_create_umem_in_bits {
12208 	u8         opcode[0x10];
12209 	u8         uid[0x10];
12210 
12211 	u8         reserved_at_20[0x10];
12212 	u8         op_mod[0x10];
12213 
12214 	u8         reserved_at_40[0x40];
12215 
12216 	struct mlx5_ifc_umem_bits  umem;
12217 };
12218 
12219 struct mlx5_ifc_create_umem_out_bits {
12220 	u8         status[0x8];
12221 	u8         reserved_at_8[0x18];
12222 
12223 	u8         syndrome[0x20];
12224 
12225 	u8         reserved_at_40[0x8];
12226 	u8         umem_id[0x18];
12227 
12228 	u8         reserved_at_60[0x20];
12229 };
12230 
12231 struct mlx5_ifc_destroy_umem_in_bits {
12232 	u8        opcode[0x10];
12233 	u8        uid[0x10];
12234 
12235 	u8        reserved_at_20[0x10];
12236 	u8        op_mod[0x10];
12237 
12238 	u8        reserved_at_40[0x8];
12239 	u8        umem_id[0x18];
12240 
12241 	u8        reserved_at_60[0x20];
12242 };
12243 
12244 struct mlx5_ifc_destroy_umem_out_bits {
12245 	u8        status[0x8];
12246 	u8        reserved_at_8[0x18];
12247 
12248 	u8        syndrome[0x20];
12249 
12250 	u8        reserved_at_40[0x40];
12251 };
12252 
12253 struct mlx5_ifc_create_uctx_in_bits {
12254 	u8         opcode[0x10];
12255 	u8         reserved_at_10[0x10];
12256 
12257 	u8         reserved_at_20[0x10];
12258 	u8         op_mod[0x10];
12259 
12260 	u8         reserved_at_40[0x40];
12261 
12262 	struct mlx5_ifc_uctx_bits  uctx;
12263 };
12264 
12265 struct mlx5_ifc_create_uctx_out_bits {
12266 	u8         status[0x8];
12267 	u8         reserved_at_8[0x18];
12268 
12269 	u8         syndrome[0x20];
12270 
12271 	u8         reserved_at_40[0x10];
12272 	u8         uid[0x10];
12273 
12274 	u8         reserved_at_60[0x20];
12275 };
12276 
12277 struct mlx5_ifc_destroy_uctx_in_bits {
12278 	u8         opcode[0x10];
12279 	u8         reserved_at_10[0x10];
12280 
12281 	u8         reserved_at_20[0x10];
12282 	u8         op_mod[0x10];
12283 
12284 	u8         reserved_at_40[0x10];
12285 	u8         uid[0x10];
12286 
12287 	u8         reserved_at_60[0x20];
12288 };
12289 
12290 struct mlx5_ifc_destroy_uctx_out_bits {
12291 	u8         status[0x8];
12292 	u8         reserved_at_8[0x18];
12293 
12294 	u8         syndrome[0x20];
12295 
12296 	u8          reserved_at_40[0x40];
12297 };
12298 
12299 struct mlx5_ifc_create_sw_icm_in_bits {
12300 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12301 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
12302 };
12303 
12304 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
12305 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12306 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
12307 };
12308 
12309 struct mlx5_ifc_mtrc_string_db_param_bits {
12310 	u8         string_db_base_address[0x20];
12311 
12312 	u8         reserved_at_20[0x8];
12313 	u8         string_db_size[0x18];
12314 };
12315 
12316 struct mlx5_ifc_mtrc_cap_bits {
12317 	u8         trace_owner[0x1];
12318 	u8         trace_to_memory[0x1];
12319 	u8         reserved_at_2[0x4];
12320 	u8         trc_ver[0x2];
12321 	u8         reserved_at_8[0x14];
12322 	u8         num_string_db[0x4];
12323 
12324 	u8         first_string_trace[0x8];
12325 	u8         num_string_trace[0x8];
12326 	u8         reserved_at_30[0x28];
12327 
12328 	u8         log_max_trace_buffer_size[0x8];
12329 
12330 	u8         reserved_at_60[0x20];
12331 
12332 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
12333 
12334 	u8         reserved_at_280[0x180];
12335 };
12336 
12337 struct mlx5_ifc_mtrc_conf_bits {
12338 	u8         reserved_at_0[0x1c];
12339 	u8         trace_mode[0x4];
12340 	u8         reserved_at_20[0x18];
12341 	u8         log_trace_buffer_size[0x8];
12342 	u8         trace_mkey[0x20];
12343 	u8         reserved_at_60[0x3a0];
12344 };
12345 
12346 struct mlx5_ifc_mtrc_stdb_bits {
12347 	u8         string_db_index[0x4];
12348 	u8         reserved_at_4[0x4];
12349 	u8         read_size[0x18];
12350 	u8         start_offset[0x20];
12351 	u8         string_db_data[];
12352 };
12353 
12354 struct mlx5_ifc_mtrc_ctrl_bits {
12355 	u8         trace_status[0x2];
12356 	u8         reserved_at_2[0x2];
12357 	u8         arm_event[0x1];
12358 	u8         reserved_at_5[0xb];
12359 	u8         modify_field_select[0x10];
12360 	u8         reserved_at_20[0x2b];
12361 	u8         current_timestamp52_32[0x15];
12362 	u8         current_timestamp31_0[0x20];
12363 	u8         reserved_at_80[0x180];
12364 };
12365 
12366 struct mlx5_ifc_host_params_context_bits {
12367 	u8         host_number[0x8];
12368 	u8         reserved_at_8[0x7];
12369 	u8         host_pf_disabled[0x1];
12370 	u8         host_num_of_vfs[0x10];
12371 
12372 	u8         host_total_vfs[0x10];
12373 	u8         host_pci_bus[0x10];
12374 
12375 	u8         reserved_at_40[0x10];
12376 	u8         host_pci_device[0x10];
12377 
12378 	u8         reserved_at_60[0x10];
12379 	u8         host_pci_function[0x10];
12380 
12381 	u8         reserved_at_80[0x180];
12382 };
12383 
12384 struct mlx5_ifc_query_esw_functions_in_bits {
12385 	u8         opcode[0x10];
12386 	u8         reserved_at_10[0x10];
12387 
12388 	u8         reserved_at_20[0x10];
12389 	u8         op_mod[0x10];
12390 
12391 	u8         reserved_at_40[0x40];
12392 };
12393 
12394 struct mlx5_ifc_query_esw_functions_out_bits {
12395 	u8         status[0x8];
12396 	u8         reserved_at_8[0x18];
12397 
12398 	u8         syndrome[0x20];
12399 
12400 	u8         reserved_at_40[0x40];
12401 
12402 	struct mlx5_ifc_host_params_context_bits host_params_context;
12403 
12404 	u8         reserved_at_280[0x180];
12405 	u8         host_sf_enable[][0x40];
12406 };
12407 
12408 struct mlx5_ifc_sf_partition_bits {
12409 	u8         reserved_at_0[0x10];
12410 	u8         log_num_sf[0x8];
12411 	u8         log_sf_bar_size[0x8];
12412 };
12413 
12414 struct mlx5_ifc_query_sf_partitions_out_bits {
12415 	u8         status[0x8];
12416 	u8         reserved_at_8[0x18];
12417 
12418 	u8         syndrome[0x20];
12419 
12420 	u8         reserved_at_40[0x18];
12421 	u8         num_sf_partitions[0x8];
12422 
12423 	u8         reserved_at_60[0x20];
12424 
12425 	struct mlx5_ifc_sf_partition_bits sf_partition[];
12426 };
12427 
12428 struct mlx5_ifc_query_sf_partitions_in_bits {
12429 	u8         opcode[0x10];
12430 	u8         reserved_at_10[0x10];
12431 
12432 	u8         reserved_at_20[0x10];
12433 	u8         op_mod[0x10];
12434 
12435 	u8         reserved_at_40[0x40];
12436 };
12437 
12438 struct mlx5_ifc_dealloc_sf_out_bits {
12439 	u8         status[0x8];
12440 	u8         reserved_at_8[0x18];
12441 
12442 	u8         syndrome[0x20];
12443 
12444 	u8         reserved_at_40[0x40];
12445 };
12446 
12447 struct mlx5_ifc_dealloc_sf_in_bits {
12448 	u8         opcode[0x10];
12449 	u8         reserved_at_10[0x10];
12450 
12451 	u8         reserved_at_20[0x10];
12452 	u8         op_mod[0x10];
12453 
12454 	u8         reserved_at_40[0x10];
12455 	u8         function_id[0x10];
12456 
12457 	u8         reserved_at_60[0x20];
12458 };
12459 
12460 struct mlx5_ifc_alloc_sf_out_bits {
12461 	u8         status[0x8];
12462 	u8         reserved_at_8[0x18];
12463 
12464 	u8         syndrome[0x20];
12465 
12466 	u8         reserved_at_40[0x40];
12467 };
12468 
12469 struct mlx5_ifc_alloc_sf_in_bits {
12470 	u8         opcode[0x10];
12471 	u8         reserved_at_10[0x10];
12472 
12473 	u8         reserved_at_20[0x10];
12474 	u8         op_mod[0x10];
12475 
12476 	u8         reserved_at_40[0x10];
12477 	u8         function_id[0x10];
12478 
12479 	u8         reserved_at_60[0x20];
12480 };
12481 
12482 struct mlx5_ifc_affiliated_event_header_bits {
12483 	u8         reserved_at_0[0x10];
12484 	u8         obj_type[0x10];
12485 
12486 	u8         obj_id[0x20];
12487 };
12488 
12489 enum {
12490 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
12491 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
12492 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
12493 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
12494 };
12495 
12496 enum {
12497 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12498 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12499 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12500 	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12501 	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12502 	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12503 	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12504 };
12505 
12506 enum {
12507 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12508 };
12509 
12510 enum {
12511 	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12512 	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12513 	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12514 	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12515 };
12516 
12517 enum {
12518 	MLX5_IPSEC_ASO_MODE              = 0x0,
12519 	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12520 	MLX5_IPSEC_ASO_INC_SN            = 0x2,
12521 };
12522 
12523 enum {
12524 	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12525 	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12526 	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12527 	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12528 };
12529 
12530 struct mlx5_ifc_ipsec_aso_bits {
12531 	u8         valid[0x1];
12532 	u8         reserved_at_201[0x1];
12533 	u8         mode[0x2];
12534 	u8         window_sz[0x2];
12535 	u8         soft_lft_arm[0x1];
12536 	u8         hard_lft_arm[0x1];
12537 	u8         remove_flow_enable[0x1];
12538 	u8         esn_event_arm[0x1];
12539 	u8         reserved_at_20a[0x16];
12540 
12541 	u8         remove_flow_pkt_cnt[0x20];
12542 
12543 	u8         remove_flow_soft_lft[0x20];
12544 
12545 	u8         reserved_at_260[0x80];
12546 
12547 	u8         mode_parameter[0x20];
12548 
12549 	u8         replay_protection_window[0x100];
12550 };
12551 
12552 struct mlx5_ifc_ipsec_obj_bits {
12553 	u8         modify_field_select[0x40];
12554 	u8         full_offload[0x1];
12555 	u8         reserved_at_41[0x1];
12556 	u8         esn_en[0x1];
12557 	u8         esn_overlap[0x1];
12558 	u8         reserved_at_44[0x2];
12559 	u8         icv_length[0x2];
12560 	u8         reserved_at_48[0x4];
12561 	u8         aso_return_reg[0x4];
12562 	u8         reserved_at_50[0x10];
12563 
12564 	u8         esn_msb[0x20];
12565 
12566 	u8         reserved_at_80[0x8];
12567 	u8         dekn[0x18];
12568 
12569 	u8         salt[0x20];
12570 
12571 	u8         implicit_iv[0x40];
12572 
12573 	u8         reserved_at_100[0x8];
12574 	u8         ipsec_aso_access_pd[0x18];
12575 	u8         reserved_at_120[0xe0];
12576 
12577 	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12578 };
12579 
12580 struct mlx5_ifc_create_ipsec_obj_in_bits {
12581 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12582 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12583 };
12584 
12585 enum {
12586 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12587 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12588 };
12589 
12590 struct mlx5_ifc_query_ipsec_obj_out_bits {
12591 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12592 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12593 };
12594 
12595 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12596 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12597 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12598 };
12599 
12600 enum {
12601 	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12602 };
12603 
12604 enum {
12605 	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12606 	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12607 	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12608 	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12609 };
12610 
12611 #define MLX5_MACSEC_ASO_INC_SN  0x2
12612 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12613 
12614 struct mlx5_ifc_macsec_aso_bits {
12615 	u8    valid[0x1];
12616 	u8    reserved_at_1[0x1];
12617 	u8    mode[0x2];
12618 	u8    window_size[0x2];
12619 	u8    soft_lifetime_arm[0x1];
12620 	u8    hard_lifetime_arm[0x1];
12621 	u8    remove_flow_enable[0x1];
12622 	u8    epn_event_arm[0x1];
12623 	u8    reserved_at_a[0x16];
12624 
12625 	u8    remove_flow_packet_count[0x20];
12626 
12627 	u8    remove_flow_soft_lifetime[0x20];
12628 
12629 	u8    reserved_at_60[0x80];
12630 
12631 	u8    mode_parameter[0x20];
12632 
12633 	u8    replay_protection_window[8][0x20];
12634 };
12635 
12636 struct mlx5_ifc_macsec_offload_obj_bits {
12637 	u8    modify_field_select[0x40];
12638 
12639 	u8    confidentiality_en[0x1];
12640 	u8    reserved_at_41[0x1];
12641 	u8    epn_en[0x1];
12642 	u8    epn_overlap[0x1];
12643 	u8    reserved_at_44[0x2];
12644 	u8    confidentiality_offset[0x2];
12645 	u8    reserved_at_48[0x4];
12646 	u8    aso_return_reg[0x4];
12647 	u8    reserved_at_50[0x10];
12648 
12649 	u8    epn_msb[0x20];
12650 
12651 	u8    reserved_at_80[0x8];
12652 	u8    dekn[0x18];
12653 
12654 	u8    reserved_at_a0[0x20];
12655 
12656 	u8    sci[0x40];
12657 
12658 	u8    reserved_at_100[0x8];
12659 	u8    macsec_aso_access_pd[0x18];
12660 
12661 	u8    reserved_at_120[0x60];
12662 
12663 	u8    salt[3][0x20];
12664 
12665 	u8    reserved_at_1e0[0x20];
12666 
12667 	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12668 };
12669 
12670 struct mlx5_ifc_create_macsec_obj_in_bits {
12671 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12672 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12673 };
12674 
12675 struct mlx5_ifc_modify_macsec_obj_in_bits {
12676 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12677 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12678 };
12679 
12680 enum {
12681 	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12682 	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12683 };
12684 
12685 struct mlx5_ifc_query_macsec_obj_out_bits {
12686 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12687 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12688 };
12689 
12690 struct mlx5_ifc_wrapped_dek_bits {
12691 	u8         gcm_iv[0x60];
12692 
12693 	u8         reserved_at_60[0x20];
12694 
12695 	u8         const0[0x1];
12696 	u8         key_size[0x1];
12697 	u8         reserved_at_82[0x2];
12698 	u8         key2_invalid[0x1];
12699 	u8         reserved_at_85[0x3];
12700 	u8         pd[0x18];
12701 
12702 	u8         key_purpose[0x5];
12703 	u8         reserved_at_a5[0x13];
12704 	u8         kek_id[0x8];
12705 
12706 	u8         reserved_at_c0[0x40];
12707 
12708 	u8         key1[0x8][0x20];
12709 
12710 	u8         key2[0x8][0x20];
12711 
12712 	u8         reserved_at_300[0x40];
12713 
12714 	u8         const1[0x1];
12715 	u8         reserved_at_341[0x1f];
12716 
12717 	u8         reserved_at_360[0x20];
12718 
12719 	u8         auth_tag[0x80];
12720 };
12721 
12722 struct mlx5_ifc_encryption_key_obj_bits {
12723 	u8         modify_field_select[0x40];
12724 
12725 	u8         state[0x8];
12726 	u8         sw_wrapped[0x1];
12727 	u8         reserved_at_49[0xb];
12728 	u8         key_size[0x4];
12729 	u8         reserved_at_58[0x4];
12730 	u8         key_purpose[0x4];
12731 
12732 	u8         reserved_at_60[0x8];
12733 	u8         pd[0x18];
12734 
12735 	u8         reserved_at_80[0x100];
12736 
12737 	u8         opaque[0x40];
12738 
12739 	u8         reserved_at_1c0[0x40];
12740 
12741 	u8         key[8][0x80];
12742 
12743 	u8         sw_wrapped_dek[8][0x80];
12744 
12745 	u8         reserved_at_a00[0x600];
12746 };
12747 
12748 struct mlx5_ifc_create_encryption_key_in_bits {
12749 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12750 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12751 };
12752 
12753 struct mlx5_ifc_modify_encryption_key_in_bits {
12754 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12755 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12756 };
12757 
12758 enum {
12759 	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
12760 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
12761 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
12762 	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
12763 };
12764 
12765 struct mlx5_ifc_flow_meter_parameters_bits {
12766 	u8         valid[0x1];
12767 	u8         bucket_overflow[0x1];
12768 	u8         start_color[0x2];
12769 	u8         both_buckets_on_green[0x1];
12770 	u8         reserved_at_5[0x1];
12771 	u8         meter_mode[0x2];
12772 	u8         reserved_at_8[0x18];
12773 
12774 	u8         reserved_at_20[0x20];
12775 
12776 	u8         reserved_at_40[0x3];
12777 	u8         cbs_exponent[0x5];
12778 	u8         cbs_mantissa[0x8];
12779 	u8         reserved_at_50[0x3];
12780 	u8         cir_exponent[0x5];
12781 	u8         cir_mantissa[0x8];
12782 
12783 	u8         reserved_at_60[0x20];
12784 
12785 	u8         reserved_at_80[0x3];
12786 	u8         ebs_exponent[0x5];
12787 	u8         ebs_mantissa[0x8];
12788 	u8         reserved_at_90[0x3];
12789 	u8         eir_exponent[0x5];
12790 	u8         eir_mantissa[0x8];
12791 
12792 	u8         reserved_at_a0[0x60];
12793 };
12794 
12795 struct mlx5_ifc_flow_meter_aso_obj_bits {
12796 	u8         modify_field_select[0x40];
12797 
12798 	u8         reserved_at_40[0x40];
12799 
12800 	u8         reserved_at_80[0x8];
12801 	u8         meter_aso_access_pd[0x18];
12802 
12803 	u8         reserved_at_a0[0x160];
12804 
12805 	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12806 };
12807 
12808 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12809 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12810 	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12811 };
12812 
12813 struct mlx5_ifc_int_kek_obj_bits {
12814 	u8         modify_field_select[0x40];
12815 
12816 	u8         state[0x8];
12817 	u8         auto_gen[0x1];
12818 	u8         reserved_at_49[0xb];
12819 	u8         key_size[0x4];
12820 	u8         reserved_at_58[0x8];
12821 
12822 	u8         reserved_at_60[0x8];
12823 	u8         pd[0x18];
12824 
12825 	u8         reserved_at_80[0x180];
12826 	u8         key[8][0x80];
12827 
12828 	u8         reserved_at_600[0x200];
12829 };
12830 
12831 struct mlx5_ifc_create_int_kek_obj_in_bits {
12832 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12833 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12834 };
12835 
12836 struct mlx5_ifc_create_int_kek_obj_out_bits {
12837 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12838 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12839 };
12840 
12841 struct mlx5_ifc_sampler_obj_bits {
12842 	u8         modify_field_select[0x40];
12843 
12844 	u8         table_type[0x8];
12845 	u8         level[0x8];
12846 	u8         reserved_at_50[0xf];
12847 	u8         ignore_flow_level[0x1];
12848 
12849 	u8         sample_ratio[0x20];
12850 
12851 	u8         reserved_at_80[0x8];
12852 	u8         sample_table_id[0x18];
12853 
12854 	u8         reserved_at_a0[0x8];
12855 	u8         default_table_id[0x18];
12856 
12857 	u8         sw_steering_icm_address_rx[0x40];
12858 	u8         sw_steering_icm_address_tx[0x40];
12859 
12860 	u8         reserved_at_140[0xa0];
12861 };
12862 
12863 struct mlx5_ifc_create_sampler_obj_in_bits {
12864 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12865 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12866 };
12867 
12868 struct mlx5_ifc_query_sampler_obj_out_bits {
12869 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12870 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12871 };
12872 
12873 enum {
12874 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12875 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12876 };
12877 
12878 enum {
12879 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12880 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12881 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12882 };
12883 
12884 struct mlx5_ifc_tls_static_params_bits {
12885 	u8         const_2[0x2];
12886 	u8         tls_version[0x4];
12887 	u8         const_1[0x2];
12888 	u8         reserved_at_8[0x14];
12889 	u8         encryption_standard[0x4];
12890 
12891 	u8         reserved_at_20[0x20];
12892 
12893 	u8         initial_record_number[0x40];
12894 
12895 	u8         resync_tcp_sn[0x20];
12896 
12897 	u8         gcm_iv[0x20];
12898 
12899 	u8         implicit_iv[0x40];
12900 
12901 	u8         reserved_at_100[0x8];
12902 	u8         dek_index[0x18];
12903 
12904 	u8         reserved_at_120[0xe0];
12905 };
12906 
12907 struct mlx5_ifc_tls_progress_params_bits {
12908 	u8         next_record_tcp_sn[0x20];
12909 
12910 	u8         hw_resync_tcp_sn[0x20];
12911 
12912 	u8         record_tracker_state[0x2];
12913 	u8         auth_state[0x2];
12914 	u8         reserved_at_44[0x4];
12915 	u8         hw_offset_record_number[0x18];
12916 };
12917 
12918 enum {
12919 	MLX5_MTT_PERM_READ	= 1 << 0,
12920 	MLX5_MTT_PERM_WRITE	= 1 << 1,
12921 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12922 };
12923 
12924 enum {
12925 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12926 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12927 };
12928 
12929 struct mlx5_ifc_suspend_vhca_in_bits {
12930 	u8         opcode[0x10];
12931 	u8         uid[0x10];
12932 
12933 	u8         reserved_at_20[0x10];
12934 	u8         op_mod[0x10];
12935 
12936 	u8         reserved_at_40[0x10];
12937 	u8         vhca_id[0x10];
12938 
12939 	u8         reserved_at_60[0x20];
12940 };
12941 
12942 struct mlx5_ifc_suspend_vhca_out_bits {
12943 	u8         status[0x8];
12944 	u8         reserved_at_8[0x18];
12945 
12946 	u8         syndrome[0x20];
12947 
12948 	u8         reserved_at_40[0x40];
12949 };
12950 
12951 enum {
12952 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12953 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12954 };
12955 
12956 struct mlx5_ifc_resume_vhca_in_bits {
12957 	u8         opcode[0x10];
12958 	u8         uid[0x10];
12959 
12960 	u8         reserved_at_20[0x10];
12961 	u8         op_mod[0x10];
12962 
12963 	u8         reserved_at_40[0x10];
12964 	u8         vhca_id[0x10];
12965 
12966 	u8         reserved_at_60[0x20];
12967 };
12968 
12969 struct mlx5_ifc_resume_vhca_out_bits {
12970 	u8         status[0x8];
12971 	u8         reserved_at_8[0x18];
12972 
12973 	u8         syndrome[0x20];
12974 
12975 	u8         reserved_at_40[0x40];
12976 };
12977 
12978 struct mlx5_ifc_query_vhca_migration_state_in_bits {
12979 	u8         opcode[0x10];
12980 	u8         uid[0x10];
12981 
12982 	u8         reserved_at_20[0x10];
12983 	u8         op_mod[0x10];
12984 
12985 	u8         incremental[0x1];
12986 	u8         chunk[0x1];
12987 	u8         reserved_at_42[0xe];
12988 	u8         vhca_id[0x10];
12989 
12990 	u8         reserved_at_60[0x20];
12991 };
12992 
12993 struct mlx5_ifc_query_vhca_migration_state_out_bits {
12994 	u8         status[0x8];
12995 	u8         reserved_at_8[0x18];
12996 
12997 	u8         syndrome[0x20];
12998 
12999 	u8         reserved_at_40[0x40];
13000 
13001 	u8         required_umem_size[0x20];
13002 
13003 	u8         reserved_at_a0[0x20];
13004 
13005 	u8         remaining_total_size[0x40];
13006 
13007 	u8         reserved_at_100[0x100];
13008 };
13009 
13010 struct mlx5_ifc_save_vhca_state_in_bits {
13011 	u8         opcode[0x10];
13012 	u8         uid[0x10];
13013 
13014 	u8         reserved_at_20[0x10];
13015 	u8         op_mod[0x10];
13016 
13017 	u8         incremental[0x1];
13018 	u8         set_track[0x1];
13019 	u8         reserved_at_42[0xe];
13020 	u8         vhca_id[0x10];
13021 
13022 	u8         reserved_at_60[0x20];
13023 
13024 	u8         va[0x40];
13025 
13026 	u8         mkey[0x20];
13027 
13028 	u8         size[0x20];
13029 };
13030 
13031 struct mlx5_ifc_save_vhca_state_out_bits {
13032 	u8         status[0x8];
13033 	u8         reserved_at_8[0x18];
13034 
13035 	u8         syndrome[0x20];
13036 
13037 	u8         actual_image_size[0x20];
13038 
13039 	u8         next_required_umem_size[0x20];
13040 };
13041 
13042 struct mlx5_ifc_load_vhca_state_in_bits {
13043 	u8         opcode[0x10];
13044 	u8         uid[0x10];
13045 
13046 	u8         reserved_at_20[0x10];
13047 	u8         op_mod[0x10];
13048 
13049 	u8         reserved_at_40[0x10];
13050 	u8         vhca_id[0x10];
13051 
13052 	u8         reserved_at_60[0x20];
13053 
13054 	u8         va[0x40];
13055 
13056 	u8         mkey[0x20];
13057 
13058 	u8         size[0x20];
13059 };
13060 
13061 struct mlx5_ifc_load_vhca_state_out_bits {
13062 	u8         status[0x8];
13063 	u8         reserved_at_8[0x18];
13064 
13065 	u8         syndrome[0x20];
13066 
13067 	u8         reserved_at_40[0x40];
13068 };
13069 
13070 struct mlx5_ifc_adv_virtualization_cap_bits {
13071 	u8         reserved_at_0[0x3];
13072 	u8         pg_track_log_max_num[0x5];
13073 	u8         pg_track_max_num_range[0x8];
13074 	u8         pg_track_log_min_addr_space[0x8];
13075 	u8         pg_track_log_max_addr_space[0x8];
13076 
13077 	u8         reserved_at_20[0x3];
13078 	u8         pg_track_log_min_msg_size[0x5];
13079 	u8         reserved_at_28[0x3];
13080 	u8         pg_track_log_max_msg_size[0x5];
13081 	u8         reserved_at_30[0x3];
13082 	u8         pg_track_log_min_page_size[0x5];
13083 	u8         reserved_at_38[0x3];
13084 	u8         pg_track_log_max_page_size[0x5];
13085 
13086 	u8         reserved_at_40[0x7c0];
13087 };
13088 
13089 struct mlx5_ifc_page_track_report_entry_bits {
13090 	u8         dirty_address_high[0x20];
13091 
13092 	u8         dirty_address_low[0x20];
13093 };
13094 
13095 enum {
13096 	MLX5_PAGE_TRACK_STATE_TRACKING,
13097 	MLX5_PAGE_TRACK_STATE_REPORTING,
13098 	MLX5_PAGE_TRACK_STATE_ERROR,
13099 };
13100 
13101 struct mlx5_ifc_page_track_range_bits {
13102 	u8         start_address[0x40];
13103 
13104 	u8         length[0x40];
13105 };
13106 
13107 struct mlx5_ifc_page_track_bits {
13108 	u8         modify_field_select[0x40];
13109 
13110 	u8         reserved_at_40[0x10];
13111 	u8         vhca_id[0x10];
13112 
13113 	u8         reserved_at_60[0x20];
13114 
13115 	u8         state[0x4];
13116 	u8         track_type[0x4];
13117 	u8         log_addr_space_size[0x8];
13118 	u8         reserved_at_90[0x3];
13119 	u8         log_page_size[0x5];
13120 	u8         reserved_at_98[0x3];
13121 	u8         log_msg_size[0x5];
13122 
13123 	u8         reserved_at_a0[0x8];
13124 	u8         reporting_qpn[0x18];
13125 
13126 	u8         reserved_at_c0[0x18];
13127 	u8         num_ranges[0x8];
13128 
13129 	u8         reserved_at_e0[0x20];
13130 
13131 	u8         range_start_address[0x40];
13132 
13133 	u8         length[0x40];
13134 
13135 	struct     mlx5_ifc_page_track_range_bits track_range[0];
13136 };
13137 
13138 struct mlx5_ifc_create_page_track_obj_in_bits {
13139 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13140 	struct mlx5_ifc_page_track_bits obj_context;
13141 };
13142 
13143 struct mlx5_ifc_modify_page_track_obj_in_bits {
13144 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13145 	struct mlx5_ifc_page_track_bits obj_context;
13146 };
13147 
13148 struct mlx5_ifc_query_page_track_obj_out_bits {
13149 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13150 	struct mlx5_ifc_page_track_bits obj_context;
13151 };
13152 
13153 struct mlx5_ifc_msecq_reg_bits {
13154 	u8         reserved_at_0[0x20];
13155 
13156 	u8         reserved_at_20[0x12];
13157 	u8         network_option[0x2];
13158 	u8         local_ssm_code[0x4];
13159 	u8         local_enhanced_ssm_code[0x8];
13160 
13161 	u8         local_clock_identity[0x40];
13162 
13163 	u8         reserved_at_80[0x180];
13164 };
13165 
13166 enum {
13167 	MLX5_MSEES_FIELD_SELECT_ENABLE			= BIT(0),
13168 	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS		= BIT(1),
13169 	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE	= BIT(2),
13170 };
13171 
13172 enum mlx5_msees_admin_status {
13173 	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING		= 0x0,
13174 	MLX5_MSEES_ADMIN_STATUS_TRACK			= 0x1,
13175 };
13176 
13177 enum mlx5_msees_oper_status {
13178 	MLX5_MSEES_OPER_STATUS_FREE_RUNNING		= 0x0,
13179 	MLX5_MSEES_OPER_STATUS_SELF_TRACK		= 0x1,
13180 	MLX5_MSEES_OPER_STATUS_OTHER_TRACK		= 0x2,
13181 	MLX5_MSEES_OPER_STATUS_HOLDOVER			= 0x3,
13182 	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER		= 0x4,
13183 	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING	= 0x5,
13184 };
13185 
13186 enum mlx5_msees_failure_reason {
13187 	MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR		= 0x0,
13188 	MLX5_MSEES_FAILURE_REASON_PORT_DOWN			= 0x1,
13189 	MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF	= 0x2,
13190 	MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR	= 0x3,
13191 	MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES		= 0x4,
13192 };
13193 
13194 struct mlx5_ifc_msees_reg_bits {
13195 	u8         reserved_at_0[0x8];
13196 	u8         local_port[0x8];
13197 	u8         pnat[0x2];
13198 	u8         lp_msb[0x2];
13199 	u8         reserved_at_14[0xc];
13200 
13201 	u8         field_select[0x20];
13202 
13203 	u8         admin_status[0x4];
13204 	u8         oper_status[0x4];
13205 	u8         ho_acq[0x1];
13206 	u8         reserved_at_49[0xc];
13207 	u8         admin_freq_measure[0x1];
13208 	u8         oper_freq_measure[0x1];
13209 	u8         failure_reason[0x9];
13210 
13211 	u8         frequency_diff[0x20];
13212 
13213 	u8         reserved_at_80[0x180];
13214 };
13215 
13216 struct mlx5_ifc_mrtcq_reg_bits {
13217 	u8         reserved_at_0[0x40];
13218 
13219 	u8         rt_clock_identity[0x40];
13220 
13221 	u8         reserved_at_80[0x180];
13222 };
13223 
13224 #endif /* MLX5_IFC_H */
13225