Searched refs:num_uclk_states (Results 1 – 2 of 2) sorted by relevance
2146 unsigned int num_uclk_states; in dcn30_update_bw_bounding_box() local2192 num_uclk_states = bw_params->clk_table.num_entries; in dcn30_update_bw_bounding_box()2195 for (i = 0; i < num_uclk_states; i++) { in dcn30_update_bw_bounding_box()2207 for (j = 0; j < num_uclk_states; j++) { in dcn30_update_bw_bounding_box()2219 if (j == num_uclk_states - 1) { in dcn30_update_bw_bounding_box()2230 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()2235 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2239 j = num_uclk_states; in dcn30_update_bw_bounding_box()2249 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
3126 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn32_update_bw_bounding_box_fpu() local3169 num_uclk_states = bw_params->clk_table.num_entries; in dcn32_update_bw_bounding_box_fpu()3172 for (i = 0; i < num_uclk_states; i++) { in dcn32_update_bw_bounding_box_fpu()3182 for (j = 0; j < num_uclk_states; j++) { in dcn32_update_bw_bounding_box_fpu()3194 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()3199 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu()3203 j = num_uclk_states; in dcn32_update_bw_bounding_box_fpu()3213 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn32_update_bw_bounding_box_fpu()