| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_rm.c | 443 int num_dsc = 0; in _dpu_rm_dsc_alloc() local
449 num_dsc < top->num_dsc; dsc_idx++) { in _dpu_rm_dsc_alloc()
465 num_dsc++; in _dpu_rm_dsc_alloc()
469 if (num_dsc < top->num_dsc) { in _dpu_rm_dsc_alloc()
471 num_dsc, top->num_dsc); in _dpu_rm_dsc_alloc()
483 int num_dsc = 0; in _dpu_rm_dsc_alloc_pair() local
489 num_dsc < top->num_dsc; dsc_idx += 2) { in _dpu_rm_dsc_alloc_pair()
521 num_dsc += 2; in _dpu_rm_dsc_alloc_pair()
525 if (num_dsc < top->num_dsc) { in _dpu_rm_dsc_alloc_pair()
527 num_dsc, top->num_dsc); in _dpu_rm_dsc_alloc_pair()
[all …]
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| H A D | dpu_encoder.c | 550 int i, intf_count = 0, num_dsc = 0; in dpu_encoder_use_dsc_merge() local
558 num_dsc = 2; in dpu_encoder_use_dsc_merge()
560 return (num_dsc > 0) && (num_dsc > intf_count); in dpu_encoder_use_dsc_merge()
619 topology.num_dsc = 2; in dpu_encoder_get_topology()
1103 int num_lm, num_ctl, num_pp, num_dsc; in dpu_encoder_virt_atomic_mode_set() local
1142 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, in dpu_encoder_virt_atomic_mode_set()
1145 for (i = 0; i < num_dsc; i++) { in dpu_encoder_virt_atomic_mode_set()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4.c | 58 .num_dsc = 4,
84 ip_caps->num_dsc = ip_params->num_dsc;
108 ip_params->num_dsc = ip_caps->num_dsc;
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| H A D | dml_top_soc_parameter_types.h | 166 unsigned int num_dsc; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/ |
| H A D | dcn4_soc_bb.h | 338 .num_dsc = 4,
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| H A D | dcn3_soc_bb.h | 376 .num_dsc = 4,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 76 .num_dsc = 3,
221 .num_dsc = 3,
320 .num_dsc = 3,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 665 .num_dsc = 6,
703 .num_dsc = 5,
1094 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1338 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1352 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1366 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
2722 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | resource.h | 55 int num_dsc; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 44 .num_dsc = 5,
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 855 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { in dcn35_init_pipes()
1214 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1282 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) in dcn35_hw_block_power_down()
1335 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { in dcn35_hw_block_power_up()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 132 .num_dsc = 5,
1007 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1431 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 130 .num_dsc = 2,
952 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
1364 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_translation_helper.c | 91 out->num_dsc = 4; in dml2_init_ip_params()
128 out->num_dsc = 4; in dml2_init_ip_params()
225 out->num_dsc = 4; in dml2_init_ip_params()
614 out->num_dsc = in_ip_params->num_dsc; in dml2_translate_ip_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 43 .num_dsc = 2,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 272 unsigned int num_dsc; member
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| /linux/drivers/gpu/drm/msm/ |
| H A D | msm_drv.h | 82 * @num_dsc: number of Display Stream Compression (DSC) blocks used
89 u32 num_dsc; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 651 .num_dsc = 3,
1056 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1655 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 581 .num_dsc = 3,
665 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
1656 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 57 .num_dsc = 4,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 46 .num_dsc = 3,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 821 .num_dsc = 3,
1382 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1956 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 839 .num_dsc = 4,
1443 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
2058 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 661 .num_dsc = 4,
1434 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn351_resource_destruct()
2059 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn351_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 681 .num_dsc = 4,
1455 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn35_resource_destruct()
2082 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn35_resource_construct()
|