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Searched refs:num_dsc (Results 1 – 25 of 33) sorted by relevance

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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder.c625 int i, intf_count = 0, num_dsc = 0; in dpu_encoder_use_dsc_merge() local
633 num_dsc++; in dpu_encoder_use_dsc_merge()
635 return (num_dsc > 0) && (num_dsc > intf_count); in dpu_encoder_use_dsc_merge()
690 topology->num_dsc = 2; in dpu_encoder_update_topology()
692 topology->num_dsc = 1; in dpu_encoder_update_topology()
1164 int num_ctl, num_pp, num_dsc, num_pp_per_intf; in dpu_encoder_virt_atomic_mode_set() local
1223 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, in dpu_encoder_virt_atomic_mode_set()
1226 for (i = 0; i < num_dsc; i++) { in dpu_encoder_virt_atomic_mode_set()
2029 int num_dsc = 0; in dpu_encoder_prep_dsc() local
2039 num_dsc++; in dpu_encoder_prep_dsc()
[all …]
H A Ddpu_crtc.c1411 else if (topology.num_dsc == 2) in dpu_crtc_get_topology()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/
H A Ddml_top_soc_parameter_types.h179 unsigned int num_dsc; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c76 .num_dsc = 3,
221 .num_dsc = 3,
320 .num_dsc = 3,
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c665 .num_dsc = 6,
703 .num_dsc = 5,
1094 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1339 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1353 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1367 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
2695 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c132 .num_dsc = 2,
954 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
1369 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c135 .num_dsc = 5,
1010 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1437 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h272 unsigned int num_dsc; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c581 .num_dsc = 3,
667 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
1657 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c651 .num_dsc = 3,
1056 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1655 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c798 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { in dcn35_init_pipes()
1201 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { in dcn35_hw_block_power_down()
1269 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) in dcn35_hw_block_power_up()
1322 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { in dcn35_root_clock_control()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c821 .num_dsc = 3,
1382 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1959 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c839 .num_dsc = 4,
1445 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
2067 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c826 .num_dsc = 3,
1387 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct()
2092 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c827 .num_dsc = 3,
1386 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
2143 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c668 .num_dsc = 4,
1443 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn36_resource_destruct()
2092 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn36_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c681 .num_dsc = 4,
1456 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn35_resource_destruct()
2113 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn35_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c661 .num_dsc = 4,
1436 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn351_resource_destruct()
2085 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn351_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c655 .num_dsc = 4,
1373 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct()
1947 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c40 .num_dsc = 4,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c61 .num_dsc = 4,
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c667 .num_dsc = 4,
1428 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn401_resource_destruct()
2188 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn401_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c680 .num_dsc = 6,
1085 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
2535 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c659 .num_dsc = 4,
1392 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct()
2450 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c570 .num_dsc = 0,

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