1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef NPC_H 9 #define NPC_H 10 11 #define NPC_KEX_CHAN_MASK 0xFFFULL 12 13 #define SET_KEX_LD(intf, lid, ltype, ld, cfg) \ 14 rvu_write64(rvu, blkaddr, \ 15 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg) 16 17 #define SET_KEX_LDFLAGS(intf, ld, flags, cfg) \ 18 rvu_write64(rvu, blkaddr, \ 19 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg) 20 21 enum NPC_LID_E { 22 NPC_LID_LA = 0, 23 NPC_LID_LB, 24 NPC_LID_LC, 25 NPC_LID_LD, 26 NPC_LID_LE, 27 NPC_LID_LF, 28 NPC_LID_LG, 29 NPC_LID_LH, 30 }; 31 32 #define NPC_LT_NA 0 33 34 enum npc_kpu_la_ltype { 35 NPC_LT_LA_8023 = 1, 36 NPC_LT_LA_ETHER, 37 NPC_LT_LA_IH_NIX_ETHER, 38 NPC_LT_LA_HIGIG2_ETHER = 7, 39 NPC_LT_LA_IH_NIX_HIGIG2_ETHER, 40 NPC_LT_LA_CUSTOM_L2_90B_ETHER, 41 NPC_LT_LA_CPT_HDR, 42 NPC_LT_LA_CUSTOM_L2_24B_ETHER, 43 NPC_LT_LA_CUSTOM_PRE_L2_ETHER, 44 NPC_LT_LA_FP_ETHER, 45 NPC_LT_LA_CUSTOM0 = 0xE, 46 NPC_LT_LA_CUSTOM1 = 0xF, 47 }; 48 49 enum npc_kpu_lb_ltype { 50 NPC_LT_LB_ETAG = 1, 51 NPC_LT_LB_CTAG, 52 NPC_LT_LB_STAG_QINQ, 53 NPC_LT_LB_BTAG, 54 NPC_LT_LB_PPPOE, 55 NPC_LT_LB_DSA, 56 NPC_LT_LB_DSA_VLAN, 57 NPC_LT_LB_EDSA, 58 NPC_LT_LB_EDSA_VLAN, 59 NPC_LT_LB_EXDSA, 60 NPC_LT_LB_EXDSA_VLAN, 61 NPC_LT_LB_FDSA, 62 NPC_LT_LB_VLAN_EXDSA, 63 NPC_LT_LB_CUSTOM0 = 0xE, 64 NPC_LT_LB_CUSTOM1 = 0xF, 65 }; 66 67 /* Don't modify ltypes up to IP6_EXT, otherwise length and checksum of IP 68 * headers may not be checked correctly. IPv4 ltypes and IPv6 ltypes must 69 * differ only at bit 0 so mask 0xE can be used to detect extended headers. 70 */ 71 enum npc_kpu_lc_ltype { 72 NPC_LT_LC_PTP = 1, 73 NPC_LT_LC_IP, 74 NPC_LT_LC_IP_OPT, 75 NPC_LT_LC_IP6, 76 NPC_LT_LC_IP6_EXT, 77 NPC_LT_LC_ARP, 78 NPC_LT_LC_RARP, 79 NPC_LT_LC_MPLS, 80 NPC_LT_LC_NSH, 81 NPC_LT_LC_FCOE, 82 NPC_LT_LC_NGIO, 83 NPC_LT_LC_CUSTOM0 = 0xE, 84 NPC_LT_LC_CUSTOM1 = 0xF, 85 }; 86 87 /* Don't modify Ltypes upto SCTP, otherwise it will 88 * effect flow tag calculation and thus RSS. 89 */ 90 enum npc_kpu_ld_ltype { 91 NPC_LT_LD_TCP = 1, 92 NPC_LT_LD_UDP, 93 NPC_LT_LD_SCTP = 4, 94 NPC_LT_LD_ICMP6, 95 NPC_LT_LD_CUSTOM0, 96 NPC_LT_LD_CUSTOM1, 97 NPC_LT_LD_IGMP = 8, 98 NPC_LT_LD_AH, 99 NPC_LT_LD_GRE, 100 NPC_LT_LD_NVGRE, 101 NPC_LT_LD_NSH, 102 NPC_LT_LD_TU_MPLS_IN_NSH, 103 NPC_LT_LD_TU_MPLS_IN_IP, 104 NPC_LT_LD_ICMP, 105 }; 106 107 enum npc_kpu_le_ltype { 108 NPC_LT_LE_VXLAN = 1, 109 NPC_LT_LE_GENEVE, 110 NPC_LT_LE_ESP, 111 NPC_LT_LE_GTPU = 4, 112 NPC_LT_LE_VXLANGPE, 113 NPC_LT_LE_GTPC, 114 NPC_LT_LE_NSH, 115 NPC_LT_LE_TU_MPLS_IN_GRE, 116 NPC_LT_LE_TU_NSH_IN_GRE, 117 NPC_LT_LE_TU_MPLS_IN_UDP, 118 NPC_LT_LE_ROCEV2, 119 NPC_LT_LE_CUSTOM0 = 0xE, 120 NPC_LT_LE_CUSTOM1 = 0xF, 121 }; 122 123 enum npc_kpu_lf_ltype { 124 NPC_LT_LF_TU_ETHER = 1, 125 NPC_LT_LF_TU_PPP, 126 NPC_LT_LF_TU_MPLS_IN_VXLANGPE, 127 NPC_LT_LF_TU_NSH_IN_VXLANGPE, 128 NPC_LT_LF_TU_MPLS_IN_NSH, 129 NPC_LT_LF_TU_3RD_NSH, 130 NPC_LT_LF_CUSTOM0 = 0xE, 131 NPC_LT_LF_CUSTOM1 = 0xF, 132 }; 133 134 enum npc_kpu_lg_ltype { 135 NPC_LT_LG_TU_IP = 1, 136 NPC_LT_LG_TU_IP6, 137 NPC_LT_LG_TU_ARP, 138 NPC_LT_LG_TU_ETHER_IN_NSH, 139 NPC_LT_LG_CUSTOM0 = 0xE, 140 NPC_LT_LG_CUSTOM1 = 0xF, 141 }; 142 143 /* Don't modify Ltypes upto SCTP, otherwise it will 144 * effect flow tag calculation and thus RSS. 145 */ 146 enum npc_kpu_lh_ltype { 147 NPC_LT_LH_TU_TCP = 1, 148 NPC_LT_LH_TU_UDP, 149 NPC_LT_LH_TU_SCTP = 4, 150 NPC_LT_LH_TU_ICMP6, 151 NPC_LT_LH_CUSTOM0, 152 NPC_LT_LH_CUSTOM1, 153 NPC_LT_LH_TU_IGMP = 8, 154 NPC_LT_LH_TU_ESP, 155 NPC_LT_LH_TU_AH, 156 NPC_LT_LH_TU_ICMP = 0xF, 157 }; 158 159 /* NPC port kind defines how the incoming or outgoing packets 160 * are processed. NPC accepts packets from up to 64 pkinds. 161 * Software assigns pkind for each incoming port such as CGX 162 * Ethernet interfaces, LBK interfaces, etc. 163 */ 164 #define NPC_UNRESERVED_PKIND_COUNT NPC_RX_SKIP_SIZE_PKIND 165 166 enum npc_pkind_type { 167 NPC_RX_LBK_PKIND = 0ULL, 168 NPC_RX_SKIP_SIZE_PKIND = 46ULL, 169 NPC_RX_CPT_SKIP_SIZE_PKIND = 50ULL, 170 NPC_RX_CPT_HDR_PTP_PKIND = 54ULL, 171 NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL, 172 NPC_RX_VLAN_EXDSA_PKIND = 56ULL, 173 NPC_RX_CHLEN24B_PKIND = 57ULL, 174 NPC_RX_CPT_HDR_PKIND, 175 NPC_RX_CHLEN90B_PKIND, 176 NPC_TX_HIGIG_PKIND, 177 NPC_RX_HIGIG_PKIND, 178 NPC_RX_EDSA_PKIND, 179 NPC_TX_DEF_PKIND, /* NIX-TX PKIND */ 180 }; 181 182 enum npc_interface_type { 183 NPC_INTF_MODE_DEF, 184 }; 185 186 /* list of known and supported fields in packet header and 187 * fields present in key structure. 188 */ 189 enum key_fields { 190 NPC_DMAC, 191 NPC_SMAC, 192 NPC_ETYPE, 193 NPC_VLAN_ETYPE_CTAG, /* 0x8100 */ 194 NPC_VLAN_ETYPE_STAG, /* 0x88A8 */ 195 NPC_OUTER_VID, 196 NPC_INNER_VID, 197 NPC_TOS, 198 NPC_IPFRAG_IPV4, 199 NPC_SIP_IPV4, 200 NPC_DIP_IPV4, 201 NPC_IPFRAG_IPV6, 202 NPC_SIP_IPV6, 203 NPC_DIP_IPV6, 204 NPC_IPPROTO_TCP, 205 NPC_IPPROTO_UDP, 206 NPC_IPPROTO_SCTP, 207 NPC_IPPROTO_AH, 208 NPC_IPPROTO_ESP, 209 NPC_IPPROTO_ICMP, 210 NPC_IPPROTO_ICMP6, 211 NPC_SPORT_TCP, 212 NPC_DPORT_TCP, 213 NPC_SPORT_UDP, 214 NPC_DPORT_UDP, 215 NPC_SPORT_SCTP, 216 NPC_DPORT_SCTP, 217 NPC_IPSEC_SPI, 218 NPC_MPLS1_LBTCBOS, 219 NPC_MPLS1_TTL, 220 NPC_MPLS2_LBTCBOS, 221 NPC_MPLS2_TTL, 222 NPC_MPLS3_LBTCBOS, 223 NPC_MPLS3_TTL, 224 NPC_MPLS4_LBTCBOS, 225 NPC_MPLS4_TTL, 226 NPC_TYPE_ICMP, 227 NPC_CODE_ICMP, 228 NPC_TCP_FLAGS, 229 NPC_HEADER_FIELDS_MAX, 230 NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */ 231 NPC_PF_FUNC, /* Valid when Tx */ 232 NPC_ERRLEV, 233 NPC_ERRCODE, 234 NPC_LXMB, 235 NPC_EXACT_RESULT, 236 NPC_LA, 237 NPC_LB, 238 NPC_LC, 239 NPC_LD, 240 NPC_LE, 241 NPC_LF, 242 NPC_LG, 243 NPC_LH, 244 /* Ethertype for untagged frame */ 245 NPC_ETYPE_ETHER, 246 /* Ethertype for single tagged frame */ 247 NPC_ETYPE_TAG1, 248 /* Ethertype for double tagged frame */ 249 NPC_ETYPE_TAG2, 250 /* outer vlan tci for single tagged frame */ 251 NPC_VLAN_TAG1, 252 /* outer vlan tci for double tagged frame */ 253 NPC_VLAN_TAG2, 254 /* inner vlan tci for double tagged frame */ 255 NPC_VLAN_TAG3, 256 /* other header fields programmed to extract but not of our interest */ 257 NPC_UNKNOWN, 258 NPC_KEY_FIELDS_MAX, 259 }; 260 261 struct npc_kpu_profile_cam { 262 u8 state; 263 u8 state_mask; 264 u16 dp0; 265 u16 dp0_mask; 266 u16 dp1; 267 u16 dp1_mask; 268 u16 dp2; 269 u16 dp2_mask; 270 } __packed; 271 272 struct npc_kpu_profile_cam2 { 273 u8 state; 274 u8 state_mask; 275 u16 dp0; 276 u16 dp0_mask; 277 u16 dp1; 278 u16 dp1_mask; 279 u16 dp2; 280 u16 dp2_mask; 281 u8 ptype; 282 u8 ptype_mask; 283 } __packed; 284 285 struct npc_kpu_profile_action { 286 u8 errlev; 287 u8 errcode; 288 u8 dp0_offset; 289 u8 dp1_offset; 290 u8 dp2_offset; 291 u8 bypass_count; 292 u8 parse_done; 293 u8 next_state; 294 u8 ptr_advance; 295 u8 cap_ena; 296 u8 lid; 297 u8 ltype; 298 u8 flags; 299 u8 offset; 300 u8 mask; 301 u8 right; 302 u8 shift; 303 } __packed; 304 305 struct npc_kpu_profile { 306 int cam_entries; 307 int action_entries; 308 struct npc_kpu_profile_cam *cam; 309 struct npc_kpu_profile_action *action; 310 int cam_entries2; 311 int action_entries2; 312 struct npc_kpu_profile_action *action2; 313 struct npc_kpu_profile_cam2 *cam2; 314 }; 315 316 /* NPC KPU register formats */ 317 struct npc_kpu_cam { 318 #if defined(__BIG_ENDIAN_BITFIELD) 319 u64 rsvd_63_56 : 8; 320 u64 state : 8; 321 u64 dp2_data : 16; 322 u64 dp1_data : 16; 323 u64 dp0_data : 16; 324 #else 325 u64 dp0_data : 16; 326 u64 dp1_data : 16; 327 u64 dp2_data : 16; 328 u64 state : 8; 329 u64 rsvd_63_56 : 8; 330 #endif 331 }; 332 333 struct npc_kpu_action0 { 334 #if defined(__BIG_ENDIAN_BITFIELD) 335 u64 rsvd_63_57 : 7; 336 u64 byp_count : 3; 337 u64 capture_ena : 1; 338 u64 parse_done : 1; 339 u64 next_state : 8; 340 u64 rsvd_43 : 1; 341 u64 capture_lid : 3; 342 u64 capture_ltype : 4; 343 u64 capture_flags : 8; 344 u64 ptr_advance : 8; 345 u64 var_len_offset : 8; 346 u64 var_len_mask : 8; 347 u64 var_len_right : 1; 348 u64 var_len_shift : 3; 349 #else 350 u64 var_len_shift : 3; 351 u64 var_len_right : 1; 352 u64 var_len_mask : 8; 353 u64 var_len_offset : 8; 354 u64 ptr_advance : 8; 355 u64 capture_flags : 8; 356 u64 capture_ltype : 4; 357 u64 capture_lid : 3; 358 u64 rsvd_43 : 1; 359 u64 next_state : 8; 360 u64 parse_done : 1; 361 u64 capture_ena : 1; 362 u64 byp_count : 3; 363 u64 rsvd_63_57 : 7; 364 #endif 365 }; 366 367 struct npc_kpu_action1 { 368 #if defined(__BIG_ENDIAN_BITFIELD) 369 u64 rsvd_63_36 : 28; 370 u64 errlev : 4; 371 u64 errcode : 8; 372 u64 dp2_offset : 8; 373 u64 dp1_offset : 8; 374 u64 dp0_offset : 8; 375 #else 376 u64 dp0_offset : 8; 377 u64 dp1_offset : 8; 378 u64 dp2_offset : 8; 379 u64 errcode : 8; 380 u64 errlev : 4; 381 u64 rsvd_63_36 : 28; 382 #endif 383 }; 384 385 struct npc_kpu_pkind_cpi_def { 386 #if defined(__BIG_ENDIAN_BITFIELD) 387 u64 ena : 1; 388 u64 rsvd_62_59 : 4; 389 u64 lid : 3; 390 u64 ltype_match : 4; 391 u64 ltype_mask : 4; 392 u64 flags_match : 8; 393 u64 flags_mask : 8; 394 u64 add_offset : 8; 395 u64 add_mask : 8; 396 u64 rsvd_15 : 1; 397 u64 add_shift : 3; 398 u64 rsvd_11_10 : 2; 399 u64 cpi_base : 10; 400 #else 401 u64 cpi_base : 10; 402 u64 rsvd_11_10 : 2; 403 u64 add_shift : 3; 404 u64 rsvd_15 : 1; 405 u64 add_mask : 8; 406 u64 add_offset : 8; 407 u64 flags_mask : 8; 408 u64 flags_match : 8; 409 u64 ltype_mask : 4; 410 u64 ltype_match : 4; 411 u64 lid : 3; 412 u64 rsvd_62_59 : 4; 413 u64 ena : 1; 414 #endif 415 }; 416 417 struct nix_rx_action { 418 #if defined(__BIG_ENDIAN_BITFIELD) 419 u64 rsvd_63_61 :3; 420 u64 flow_key_alg :5; 421 u64 match_id :16; 422 u64 index :20; 423 u64 pf_func :16; 424 u64 op :4; 425 #else 426 u64 op :4; 427 u64 pf_func :16; 428 u64 index :20; 429 u64 match_id :16; 430 u64 flow_key_alg :5; 431 u64 rsvd_63_61 :3; 432 #endif 433 }; 434 435 /* NPC_AF_INTFX_KEX_CFG field masks */ 436 #define NPC_EXACT_NIBBLE_START 40 437 #define NPC_EXACT_NIBBLE_END 43 438 #define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40) 439 440 /* NPC_EXACT_KEX_S nibble definitions for each field */ 441 #define NPC_EXACT_NIBBLE_HIT BIT_ULL(40) 442 #define NPC_EXACT_NIBBLE_OPC BIT_ULL(40) 443 #define NPC_EXACT_NIBBLE_WAY BIT_ULL(40) 444 #define NPC_EXACT_NIBBLE_INDEX GENMASK_ULL(43, 41) 445 446 #define NPC_EXACT_RESULT_HIT BIT_ULL(0) 447 #define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1) 448 #define NPC_EXACT_RESULT_WAY GENMASK_ULL(4, 3) 449 #define NPC_EXACT_RESULT_IDX GENMASK_ULL(15, 5) 450 451 /* NPC_AF_INTFX_KEX_CFG field masks */ 452 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0) 453 #define NPC_TOTAL_NIBBLE 31 454 455 /* NPC_PARSE_KEX_S nibble definitions for each field */ 456 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0) 457 #define NPC_PARSE_NIBBLE_ERRLEV BIT_ULL(3) 458 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4) 459 #define NPC_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6) 460 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7) 461 #define NPC_PARSE_NIBBLE_LA_LTYPE BIT_ULL(9) 462 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10) 463 #define NPC_PARSE_NIBBLE_LB_LTYPE BIT_ULL(12) 464 #define NPC_PARSE_NIBBLE_LC_FLAGS GENMASK_ULL(14, 13) 465 #define NPC_PARSE_NIBBLE_LC_LTYPE BIT_ULL(15) 466 #define NPC_PARSE_NIBBLE_LD_FLAGS GENMASK_ULL(17, 16) 467 #define NPC_PARSE_NIBBLE_LD_LTYPE BIT_ULL(18) 468 #define NPC_PARSE_NIBBLE_LE_FLAGS GENMASK_ULL(20, 19) 469 #define NPC_PARSE_NIBBLE_LE_LTYPE BIT_ULL(21) 470 #define NPC_PARSE_NIBBLE_LF_FLAGS GENMASK_ULL(23, 22) 471 #define NPC_PARSE_NIBBLE_LF_LTYPE BIT_ULL(24) 472 #define NPC_PARSE_NIBBLE_LG_FLAGS GENMASK_ULL(26, 25) 473 #define NPC_PARSE_NIBBLE_LG_LTYPE BIT_ULL(27) 474 #define NPC_PARSE_NIBBLE_LH_FLAGS GENMASK_ULL(29, 28) 475 #define NPC_PARSE_NIBBLE_LH_LTYPE BIT_ULL(30) 476 477 struct nix_tx_action { 478 #if defined(__BIG_ENDIAN_BITFIELD) 479 u64 rsvd_63_48 :16; 480 u64 match_id :16; 481 u64 index :20; 482 u64 rsvd_11_8 :8; 483 u64 op :4; 484 #else 485 u64 op :4; 486 u64 rsvd_11_8 :8; 487 u64 index :20; 488 u64 match_id :16; 489 u64 rsvd_63_48 :16; 490 #endif 491 }; 492 493 /* NIX Receive Vtag Action Structure */ 494 #define RX_VTAG0_VALID_BIT BIT_ULL(15) 495 #define RX_VTAG0_TYPE_MASK GENMASK_ULL(14, 12) 496 #define RX_VTAG0_LID_MASK GENMASK_ULL(10, 8) 497 #define RX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 498 #define RX_VTAG1_VALID_BIT BIT_ULL(47) 499 #define RX_VTAG1_TYPE_MASK GENMASK_ULL(46, 44) 500 #define RX_VTAG1_LID_MASK GENMASK_ULL(42, 40) 501 #define RX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32) 502 503 /* NIX Transmit Vtag Action Structure */ 504 #define TX_VTAG0_DEF_MASK GENMASK_ULL(25, 16) 505 #define TX_VTAG0_OP_MASK GENMASK_ULL(13, 12) 506 #define TX_VTAG0_LID_MASK GENMASK_ULL(10, 8) 507 #define TX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 508 #define TX_VTAG1_DEF_MASK GENMASK_ULL(57, 48) 509 #define TX_VTAG1_OP_MASK GENMASK_ULL(45, 44) 510 #define TX_VTAG1_LID_MASK GENMASK_ULL(42, 40) 511 #define TX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32) 512 513 /* NPC MCAM reserved entry index per nixlf */ 514 #define NIXLF_UCAST_ENTRY 0 515 #define NIXLF_BCAST_ENTRY 1 516 #define NIXLF_ALLMULTI_ENTRY 2 517 #define NIXLF_PROMISC_ENTRY 3 518 519 struct npc_coalesced_kpu_prfl { 520 #define NPC_SIGN 0x00666f727063706e 521 #define NPC_PRFL_NAME "npc_prfls_array" 522 #define NPC_NAME_LEN 32 523 __le64 signature; /* "npcprof\0" (8 bytes/ASCII characters) */ 524 u8 name[NPC_NAME_LEN]; /* KPU Profile name */ 525 u64 version; /* KPU firmware/profile version */ 526 u8 num_prfl; /* No of NPC profiles. */ 527 u16 prfl_sz[]; 528 }; 529 530 struct npc_mcam_kex { 531 /* MKEX Profle Header */ 532 u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */ 533 u8 name[MKEX_NAME_LEN]; /* MKEX Profile name */ 534 u64 cpu_model; /* Format as profiled by CPU hardware */ 535 u64 kpu_version; /* KPU firmware/profile version */ 536 u64 reserved; /* Reserved for extension */ 537 538 /* MKEX Profle Data */ 539 u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */ 540 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 541 u64 kex_ld_flags[NPC_MAX_LD]; 542 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 543 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 544 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 545 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 546 } __packed; 547 548 struct npc_kpu_fwdata { 549 int entries; 550 /* What follows is: 551 * struct npc_kpu_profile_cam[entries]; 552 * struct npc_kpu_profile_action[entries]; 553 */ 554 u8 data[]; 555 } __packed; 556 557 struct npc_lt_def { 558 u8 ltype_mask; 559 u8 ltype_match; 560 u8 lid; 561 } __packed; 562 563 struct npc_lt_def_ipsec { 564 u8 ltype_mask; 565 u8 ltype_match; 566 u8 lid; 567 u8 spi_offset; 568 u8 spi_nz; 569 } __packed; 570 571 struct npc_lt_def_apad { 572 u8 ltype_mask; 573 u8 ltype_match; 574 u8 lid; 575 u8 valid; 576 } __packed; 577 578 struct npc_lt_def_color { 579 u8 ltype_mask; 580 u8 ltype_match; 581 u8 lid; 582 u8 noffset; 583 u8 offset; 584 } __packed; 585 586 struct npc_lt_def_et { 587 u8 ltype_mask; 588 u8 ltype_match; 589 u8 lid; 590 u8 valid; 591 u8 offset; 592 } __packed; 593 594 struct npc_lt_def_cfg { 595 struct npc_lt_def rx_ol2; 596 struct npc_lt_def rx_oip4; 597 struct npc_lt_def rx_iip4; 598 struct npc_lt_def rx_oip6; 599 struct npc_lt_def rx_iip6; 600 struct npc_lt_def rx_otcp; 601 struct npc_lt_def rx_itcp; 602 struct npc_lt_def rx_oudp; 603 struct npc_lt_def rx_iudp; 604 struct npc_lt_def rx_osctp; 605 struct npc_lt_def rx_isctp; 606 struct npc_lt_def_ipsec rx_ipsec[2]; 607 struct npc_lt_def pck_ol2; 608 struct npc_lt_def pck_oip4; 609 struct npc_lt_def pck_oip6; 610 struct npc_lt_def pck_iip4; 611 struct npc_lt_def_apad rx_apad0; 612 struct npc_lt_def_apad rx_apad1; 613 struct npc_lt_def_color ovlan; 614 struct npc_lt_def_color ivlan; 615 struct npc_lt_def_color rx_gen0_color; 616 struct npc_lt_def_color rx_gen1_color; 617 struct npc_lt_def_et rx_et[2]; 618 } __packed; 619 620 /* Loadable KPU profile firmware data */ 621 struct npc_kpu_profile_fwdata { 622 #define KPU_SIGN 0x00666f727075706b 623 #define KPU_NAME_LEN 32 624 /** Maximum number of custom KPU entries supported by the built-in profile. */ 625 #define KPU_MAX_CST_ENT 6 626 /* KPU Profle Header */ 627 __le64 signature; /* "kpuprof\0" (8 bytes/ASCII characters) */ 628 u8 name[KPU_NAME_LEN]; /* KPU Profile name */ 629 __le64 version; /* KPU profile version */ 630 u8 kpus; 631 u8 reserved[7]; 632 633 /* Default MKEX profile to be used with this KPU profile. May be 634 * overridden with mkex_profile module parameter. Format is same as for 635 * the MKEX profile to streamline processing. 636 */ 637 struct npc_mcam_kex mkex; 638 /* LTYPE values for specific HW offloaded protocols. */ 639 struct npc_lt_def_cfg lt_def; 640 /* Dynamically sized data: 641 * Custom KPU CAM and ACTION configuration entries. 642 * struct npc_kpu_fwdata kpu[kpus]; 643 */ 644 u8 data[]; 645 } __packed; 646 647 struct rvu_npc_mcam_rule { 648 struct flow_msg packet; 649 struct flow_msg mask; 650 u8 intf; 651 union { 652 struct nix_tx_action tx_action; 653 struct nix_rx_action rx_action; 654 }; 655 u64 vtag_action; 656 struct list_head list; 657 u64 features; 658 u16 owner; 659 u16 entry; 660 u16 cntr; 661 bool has_cntr; 662 u8 default_rule; 663 bool enable; 664 bool vfvlan_cfg; 665 u16 chan; 666 u16 chan_mask; 667 u8 lxmb; 668 u8 hw_prio; 669 }; 670 671 #endif /* NPC_H */ 672