1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include <linux/export.h>
8 #include <linux/module.h>
9 #include <linux/slab.h>
10 #include <linux/remoteproc.h>
11 #include <linux/firmware.h>
12 #include <linux/of.h>
13
14 #include "core.h"
15 #include "dp_tx.h"
16 #include "dp_rx.h"
17 #include "debug.h"
18 #include "hif.h"
19 #include "wow.h"
20 #include "fw.h"
21
22 unsigned int ath11k_debug_mask;
23 EXPORT_SYMBOL(ath11k_debug_mask);
24 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
25 MODULE_PARM_DESC(debug_mask, "Debugging mask");
26
27 static unsigned int ath11k_crypto_mode;
28 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
29 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
30
31 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
32 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
33 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
34 MODULE_PARM_DESC(frame_mode,
35 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
36
37 bool ath11k_ftm_mode;
38 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
39 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
40
41 static const struct ath11k_hw_params ath11k_hw_params[] = {
42 {
43 .hw_rev = ATH11K_HW_IPQ8074,
44 .name = "ipq8074 hw2.0",
45 .fw = {
46 .dir = "IPQ8074/hw2.0",
47 .board_size = 256 * 1024,
48 .cal_offset = 128 * 1024,
49 },
50 .max_radios = 3,
51 .bdf_addr = 0x4B0C0000,
52 .hw_ops = &ipq8074_ops,
53 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
54 .internal_sleep_clock = false,
55 .regs = &ipq8074_regs,
56 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
57 .host_ce_config = ath11k_host_ce_config_ipq8074,
58 .ce_count = 12,
59 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
60 .target_ce_count = 11,
61 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
62 .svc_to_ce_map_len = 21,
63 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
64 .single_pdev_only = false,
65 .rxdma1_enable = true,
66 .num_rxdma_per_pdev = 1,
67 .rx_mac_buf_ring = false,
68 .vdev_start_delay = false,
69 .htt_peer_map_v2 = true,
70
71 .spectral = {
72 .fft_sz = 2,
73 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
74 * so added pad size as 2 bytes to compensate the BIN size
75 */
76 .fft_pad_sz = 2,
77 .summary_pad_sz = 0,
78 .fft_hdr_len = 16,
79 .max_fft_bins = 512,
80 .fragment_160mhz = true,
81 },
82
83 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
84 BIT(NL80211_IFTYPE_AP) |
85 BIT(NL80211_IFTYPE_MESH_POINT),
86 .supports_monitor = true,
87 .full_monitor_mode = false,
88 .supports_shadow_regs = false,
89 .idle_ps = false,
90 .supports_sta_ps = false,
91 .coldboot_cal_mm = true,
92 .coldboot_cal_ftm = true,
93 .cbcal_restart_fw = true,
94 .fw_mem_mode = 0,
95 .num_vdevs = 16 + 1,
96 .num_peers = 512,
97 .supports_suspend = false,
98 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
99 .supports_regdb = false,
100 .fix_l1ss = true,
101 .credit_flow = false,
102 .hal_params = &ath11k_hw_hal_params_ipq8074,
103 .supports_dynamic_smps_6ghz = false,
104 .alloc_cacheable_memory = true,
105 .supports_rssi_stats = false,
106 .fw_wmi_diag_event = false,
107 .current_cc_support = false,
108 .dbr_debug_support = true,
109 .global_reset = false,
110 .bios_sar_capa = NULL,
111 .m3_fw_support = false,
112 .fixed_bdf_addr = true,
113 .fixed_mem_region = true,
114 .static_window_map = false,
115 .hybrid_bus_type = false,
116 .fixed_fw_mem = false,
117 .support_off_channel_tx = false,
118 .supports_multi_bssid = false,
119
120 .sram_dump = {},
121
122 .tcl_ring_retry = true,
123 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
124 .smp2p_wow_exit = false,
125 .support_dual_stations = false,
126 .pdev_suspend = false,
127 .cfr_support = true,
128 .cfr_num_stream_bufs = 255,
129 .cfr_stream_buf_size = 8200,
130 },
131 {
132 .hw_rev = ATH11K_HW_IPQ6018_HW10,
133 .name = "ipq6018 hw1.0",
134 .fw = {
135 .dir = "IPQ6018/hw1.0",
136 .board_size = 256 * 1024,
137 .cal_offset = 128 * 1024,
138 },
139 .max_radios = 2,
140 .bdf_addr = 0x4ABC0000,
141 .hw_ops = &ipq6018_ops,
142 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
143 .internal_sleep_clock = false,
144 .regs = &ipq8074_regs,
145 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
146 .host_ce_config = ath11k_host_ce_config_ipq8074,
147 .ce_count = 12,
148 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
149 .target_ce_count = 11,
150 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
151 .svc_to_ce_map_len = 19,
152 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
153 .single_pdev_only = false,
154 .rxdma1_enable = true,
155 .num_rxdma_per_pdev = 1,
156 .rx_mac_buf_ring = false,
157 .vdev_start_delay = false,
158 .htt_peer_map_v2 = true,
159
160 .spectral = {
161 .fft_sz = 4,
162 .fft_pad_sz = 0,
163 .summary_pad_sz = 0,
164 .fft_hdr_len = 16,
165 .max_fft_bins = 512,
166 .fragment_160mhz = true,
167 },
168
169 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
170 BIT(NL80211_IFTYPE_AP) |
171 BIT(NL80211_IFTYPE_MESH_POINT),
172 .supports_monitor = true,
173 .full_monitor_mode = false,
174 .supports_shadow_regs = false,
175 .idle_ps = false,
176 .supports_sta_ps = false,
177 .coldboot_cal_mm = true,
178 .coldboot_cal_ftm = true,
179 .cbcal_restart_fw = true,
180 .fw_mem_mode = 0,
181 .num_vdevs = 16 + 1,
182 .num_peers = 512,
183 .supports_suspend = false,
184 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
185 .supports_regdb = false,
186 .fix_l1ss = true,
187 .credit_flow = false,
188 .hal_params = &ath11k_hw_hal_params_ipq8074,
189 .supports_dynamic_smps_6ghz = false,
190 .alloc_cacheable_memory = true,
191 .supports_rssi_stats = false,
192 .fw_wmi_diag_event = false,
193 .current_cc_support = false,
194 .dbr_debug_support = true,
195 .global_reset = false,
196 .bios_sar_capa = NULL,
197 .m3_fw_support = false,
198 .fixed_bdf_addr = true,
199 .fixed_mem_region = true,
200 .static_window_map = false,
201 .hybrid_bus_type = false,
202 .fixed_fw_mem = false,
203 .support_off_channel_tx = false,
204 .supports_multi_bssid = false,
205
206 .sram_dump = {},
207
208 .tcl_ring_retry = true,
209 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
210 .smp2p_wow_exit = false,
211 .support_fw_mac_sequence = false,
212 .support_dual_stations = false,
213 .pdev_suspend = false,
214 .cfr_support = false,
215 .cfr_num_stream_bufs = 0,
216 .cfr_stream_buf_size = 0,
217 },
218 {
219 .name = "qca6390 hw2.0",
220 .hw_rev = ATH11K_HW_QCA6390_HW20,
221 .fw = {
222 .dir = "QCA6390/hw2.0",
223 .board_size = 256 * 1024,
224 .cal_offset = 128 * 1024,
225 },
226 .max_radios = 3,
227 .bdf_addr = 0x4B0C0000,
228 .hw_ops = &qca6390_ops,
229 .ring_mask = &ath11k_hw_ring_mask_qca6390,
230 .internal_sleep_clock = true,
231 .regs = &qca6390_regs,
232 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
233 .host_ce_config = ath11k_host_ce_config_qca6390,
234 .ce_count = 9,
235 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
236 .target_ce_count = 9,
237 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
238 .svc_to_ce_map_len = 14,
239 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
240 .single_pdev_only = true,
241 .rxdma1_enable = false,
242 .num_rxdma_per_pdev = 2,
243 .rx_mac_buf_ring = true,
244 .vdev_start_delay = true,
245 .htt_peer_map_v2 = false,
246
247 .spectral = {
248 .fft_sz = 0,
249 .fft_pad_sz = 0,
250 .summary_pad_sz = 0,
251 .fft_hdr_len = 0,
252 .max_fft_bins = 0,
253 .fragment_160mhz = false,
254 },
255
256 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
257 BIT(NL80211_IFTYPE_AP) |
258 BIT(NL80211_IFTYPE_P2P_DEVICE) |
259 BIT(NL80211_IFTYPE_P2P_CLIENT) |
260 BIT(NL80211_IFTYPE_P2P_GO),
261 .supports_monitor = false,
262 .full_monitor_mode = false,
263 .supports_shadow_regs = true,
264 .idle_ps = true,
265 .supports_sta_ps = true,
266 .coldboot_cal_mm = false,
267 .coldboot_cal_ftm = false,
268 .cbcal_restart_fw = false,
269 .fw_mem_mode = 0,
270 .num_vdevs = 4,
271 .num_peers = 512,
272 .supports_suspend = true,
273 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
274 .supports_regdb = false,
275 .fix_l1ss = true,
276 .credit_flow = true,
277 .hal_params = &ath11k_hw_hal_params_qca6390,
278 .supports_dynamic_smps_6ghz = false,
279 .alloc_cacheable_memory = false,
280 .supports_rssi_stats = true,
281 .fw_wmi_diag_event = true,
282 .current_cc_support = true,
283 .dbr_debug_support = false,
284 .global_reset = true,
285 .bios_sar_capa = NULL,
286 .m3_fw_support = true,
287 .fixed_bdf_addr = false,
288 .fixed_mem_region = false,
289 .static_window_map = false,
290 .hybrid_bus_type = false,
291 .fixed_fw_mem = false,
292 .support_off_channel_tx = true,
293 .supports_multi_bssid = true,
294
295 .sram_dump = {
296 .start = 0x01400000,
297 .end = 0x0171ffff,
298 },
299
300 .tcl_ring_retry = true,
301 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
302 .smp2p_wow_exit = false,
303 .support_fw_mac_sequence = true,
304 .support_dual_stations = true,
305 .pdev_suspend = false,
306 .cfr_support = false,
307 .cfr_num_stream_bufs = 0,
308 .cfr_stream_buf_size = 0,
309 },
310 {
311 .name = "qcn9074 hw1.0",
312 .hw_rev = ATH11K_HW_QCN9074_HW10,
313 .fw = {
314 .dir = "QCN9074/hw1.0",
315 .board_size = 256 * 1024,
316 .cal_offset = 128 * 1024,
317 },
318 .max_radios = 1,
319 .single_pdev_only = false,
320 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
321 .hw_ops = &qcn9074_ops,
322 .ring_mask = &ath11k_hw_ring_mask_qcn9074,
323 .internal_sleep_clock = false,
324 .regs = &qcn9074_regs,
325 .host_ce_config = ath11k_host_ce_config_qcn9074,
326 .ce_count = 6,
327 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
328 .target_ce_count = 9,
329 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
330 .svc_to_ce_map_len = 18,
331 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
332 .rxdma1_enable = true,
333 .num_rxdma_per_pdev = 1,
334 .rx_mac_buf_ring = false,
335 .vdev_start_delay = false,
336 .htt_peer_map_v2 = true,
337
338 .spectral = {
339 .fft_sz = 2,
340 .fft_pad_sz = 0,
341 .summary_pad_sz = 16,
342 .fft_hdr_len = 24,
343 .max_fft_bins = 1024,
344 .fragment_160mhz = false,
345 },
346
347 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
348 BIT(NL80211_IFTYPE_AP) |
349 BIT(NL80211_IFTYPE_MESH_POINT),
350 .supports_monitor = true,
351 .full_monitor_mode = true,
352 .supports_shadow_regs = false,
353 .idle_ps = false,
354 .supports_sta_ps = false,
355 .coldboot_cal_mm = false,
356 .coldboot_cal_ftm = true,
357 .cbcal_restart_fw = true,
358 .fw_mem_mode = 2,
359 .num_vdevs = 8,
360 .num_peers = 128,
361 .supports_suspend = false,
362 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
363 .supports_regdb = false,
364 .fix_l1ss = true,
365 .credit_flow = false,
366 .hal_params = &ath11k_hw_hal_params_ipq8074,
367 .supports_dynamic_smps_6ghz = true,
368 .alloc_cacheable_memory = true,
369 .supports_rssi_stats = false,
370 .fw_wmi_diag_event = false,
371 .current_cc_support = false,
372 .dbr_debug_support = true,
373 .global_reset = false,
374 .bios_sar_capa = NULL,
375 .m3_fw_support = true,
376 .fixed_bdf_addr = false,
377 .fixed_mem_region = false,
378 .static_window_map = true,
379 .hybrid_bus_type = false,
380 .fixed_fw_mem = false,
381 .support_off_channel_tx = false,
382 .supports_multi_bssid = false,
383
384 .sram_dump = {},
385
386 .tcl_ring_retry = true,
387 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
388 .smp2p_wow_exit = false,
389 .support_fw_mac_sequence = false,
390 .support_dual_stations = false,
391 .pdev_suspend = false,
392 .cfr_support = false,
393 .cfr_num_stream_bufs = 0,
394 .cfr_stream_buf_size = 0,
395 },
396 {
397 .name = "wcn6855 hw2.0",
398 .hw_rev = ATH11K_HW_WCN6855_HW20,
399 .fw = {
400 .dir = "WCN6855/hw2.0",
401 .board_size = 256 * 1024,
402 .cal_offset = 128 * 1024,
403 },
404 .max_radios = 3,
405 .bdf_addr = 0x4B0C0000,
406 .hw_ops = &wcn6855_ops,
407 .ring_mask = &ath11k_hw_ring_mask_qca6390,
408 .internal_sleep_clock = true,
409 .regs = &wcn6855_regs,
410 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
411 .host_ce_config = ath11k_host_ce_config_qca6390,
412 .ce_count = 9,
413 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
414 .target_ce_count = 9,
415 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
416 .svc_to_ce_map_len = 14,
417 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
418 .single_pdev_only = true,
419 .rxdma1_enable = false,
420 .num_rxdma_per_pdev = 2,
421 .rx_mac_buf_ring = true,
422 .vdev_start_delay = true,
423 .htt_peer_map_v2 = false,
424
425 .spectral = {
426 .fft_sz = 0,
427 .fft_pad_sz = 0,
428 .summary_pad_sz = 0,
429 .fft_hdr_len = 0,
430 .max_fft_bins = 0,
431 .fragment_160mhz = false,
432 },
433
434 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
435 BIT(NL80211_IFTYPE_AP) |
436 BIT(NL80211_IFTYPE_P2P_DEVICE) |
437 BIT(NL80211_IFTYPE_P2P_CLIENT) |
438 BIT(NL80211_IFTYPE_P2P_GO),
439 .supports_monitor = false,
440 .full_monitor_mode = false,
441 .supports_shadow_regs = true,
442 .idle_ps = true,
443 .supports_sta_ps = true,
444 .coldboot_cal_mm = false,
445 .coldboot_cal_ftm = false,
446 .cbcal_restart_fw = false,
447 .fw_mem_mode = 0,
448 .num_vdevs = 4,
449 .num_peers = 512,
450 .supports_suspend = true,
451 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
452 .supports_regdb = true,
453 .fix_l1ss = false,
454 .credit_flow = true,
455 .hal_params = &ath11k_hw_hal_params_qca6390,
456 .supports_dynamic_smps_6ghz = false,
457 .alloc_cacheable_memory = false,
458 .supports_rssi_stats = true,
459 .fw_wmi_diag_event = true,
460 .current_cc_support = true,
461 .dbr_debug_support = false,
462 .global_reset = true,
463 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
464 .m3_fw_support = true,
465 .fixed_bdf_addr = false,
466 .fixed_mem_region = false,
467 .static_window_map = false,
468 .hybrid_bus_type = false,
469 .fixed_fw_mem = false,
470 .support_off_channel_tx = true,
471 .supports_multi_bssid = true,
472
473 .sram_dump = {
474 .start = 0x01400000,
475 .end = 0x0177ffff,
476 },
477
478 .tcl_ring_retry = true,
479 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
480 .smp2p_wow_exit = false,
481 .support_fw_mac_sequence = true,
482 .support_dual_stations = true,
483 .pdev_suspend = false,
484 .cfr_support = false,
485 .cfr_num_stream_bufs = 0,
486 .cfr_stream_buf_size = 0,
487 },
488 {
489 .name = "wcn6855 hw2.1",
490 .hw_rev = ATH11K_HW_WCN6855_HW21,
491 .fw = {
492 .dir = "WCN6855/hw2.1",
493 .board_size = 256 * 1024,
494 .cal_offset = 128 * 1024,
495 },
496 .max_radios = 3,
497 .bdf_addr = 0x4B0C0000,
498 .hw_ops = &wcn6855_ops,
499 .ring_mask = &ath11k_hw_ring_mask_qca6390,
500 .internal_sleep_clock = true,
501 .regs = &wcn6855_regs,
502 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
503 .host_ce_config = ath11k_host_ce_config_qca6390,
504 .ce_count = 9,
505 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
506 .target_ce_count = 9,
507 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
508 .svc_to_ce_map_len = 14,
509 .single_pdev_only = true,
510 .rxdma1_enable = false,
511 .num_rxdma_per_pdev = 2,
512 .rx_mac_buf_ring = true,
513 .vdev_start_delay = true,
514 .htt_peer_map_v2 = false,
515
516 .spectral = {
517 .fft_sz = 0,
518 .fft_pad_sz = 0,
519 .summary_pad_sz = 0,
520 .fft_hdr_len = 0,
521 .max_fft_bins = 0,
522 .fragment_160mhz = false,
523 },
524
525 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
526 BIT(NL80211_IFTYPE_AP) |
527 BIT(NL80211_IFTYPE_P2P_DEVICE) |
528 BIT(NL80211_IFTYPE_P2P_CLIENT) |
529 BIT(NL80211_IFTYPE_P2P_GO),
530 .supports_monitor = false,
531 .supports_shadow_regs = true,
532 .idle_ps = true,
533 .supports_sta_ps = true,
534 .coldboot_cal_mm = false,
535 .coldboot_cal_ftm = false,
536 .cbcal_restart_fw = false,
537 .fw_mem_mode = 0,
538 .num_vdevs = 4,
539 .num_peers = 512,
540 .supports_suspend = true,
541 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
542 .supports_regdb = true,
543 .fix_l1ss = false,
544 .credit_flow = true,
545 .hal_params = &ath11k_hw_hal_params_qca6390,
546 .supports_dynamic_smps_6ghz = false,
547 .alloc_cacheable_memory = false,
548 .supports_rssi_stats = true,
549 .fw_wmi_diag_event = true,
550 .current_cc_support = true,
551 .dbr_debug_support = false,
552 .global_reset = true,
553 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
554 .m3_fw_support = true,
555 .fixed_bdf_addr = false,
556 .fixed_mem_region = false,
557 .static_window_map = false,
558 .hybrid_bus_type = false,
559 .fixed_fw_mem = false,
560 .support_off_channel_tx = true,
561 .supports_multi_bssid = true,
562
563 .sram_dump = {
564 .start = 0x01400000,
565 .end = 0x0177ffff,
566 },
567
568 .tcl_ring_retry = true,
569 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
570 .smp2p_wow_exit = false,
571 .support_fw_mac_sequence = true,
572 .support_dual_stations = true,
573 .pdev_suspend = false,
574 .cfr_support = true,
575 .cfr_num_stream_bufs = 255,
576 .cfr_stream_buf_size = 8200,
577 },
578 {
579 .name = "wcn6750 hw1.0",
580 .hw_rev = ATH11K_HW_WCN6750_HW10,
581 .fw = {
582 .dir = "WCN6750/hw1.0",
583 .board_size = 256 * 1024,
584 .cal_offset = 128 * 1024,
585 },
586 .max_radios = 1,
587 .bdf_addr = 0x4B0C0000,
588 .hw_ops = &wcn6750_ops,
589 .ring_mask = &ath11k_hw_ring_mask_wcn6750,
590 .internal_sleep_clock = false,
591 .regs = &wcn6750_regs,
592 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
593 .host_ce_config = ath11k_host_ce_config_qca6390,
594 .ce_count = 9,
595 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
596 .target_ce_count = 9,
597 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
598 .svc_to_ce_map_len = 14,
599 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
600 .single_pdev_only = true,
601 .rxdma1_enable = false,
602 .num_rxdma_per_pdev = 1,
603 .rx_mac_buf_ring = true,
604 .vdev_start_delay = true,
605 .htt_peer_map_v2 = false,
606
607 .spectral = {
608 .fft_sz = 0,
609 .fft_pad_sz = 0,
610 .summary_pad_sz = 0,
611 .fft_hdr_len = 0,
612 .max_fft_bins = 0,
613 .fragment_160mhz = false,
614 },
615
616 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
617 BIT(NL80211_IFTYPE_AP),
618 .supports_monitor = false,
619 .supports_shadow_regs = true,
620 .idle_ps = true,
621 .supports_sta_ps = true,
622 .coldboot_cal_mm = true,
623 .coldboot_cal_ftm = true,
624 .cbcal_restart_fw = false,
625 .fw_mem_mode = 0,
626 .num_vdevs = 3,
627 .num_peers = 512,
628 .supports_suspend = false,
629 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
630 .supports_regdb = true,
631 .fix_l1ss = false,
632 .credit_flow = true,
633 .hal_params = &ath11k_hw_hal_params_wcn6750,
634 .supports_dynamic_smps_6ghz = false,
635 .alloc_cacheable_memory = false,
636 .supports_rssi_stats = true,
637 .fw_wmi_diag_event = true,
638 .current_cc_support = true,
639 .dbr_debug_support = false,
640 .global_reset = false,
641 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
642 .m3_fw_support = false,
643 .fixed_bdf_addr = false,
644 .fixed_mem_region = false,
645 .static_window_map = true,
646 .hybrid_bus_type = true,
647 .fixed_fw_mem = true,
648 .support_off_channel_tx = true,
649 .supports_multi_bssid = true,
650
651 .sram_dump = {},
652
653 .tcl_ring_retry = false,
654 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
655 .smp2p_wow_exit = true,
656 .support_fw_mac_sequence = true,
657 .support_dual_stations = false,
658 .pdev_suspend = true,
659 .cfr_support = false,
660 .cfr_num_stream_bufs = 0,
661 .cfr_stream_buf_size = 0,
662 },
663 {
664 .hw_rev = ATH11K_HW_IPQ5018_HW10,
665 .name = "ipq5018 hw1.0",
666 .fw = {
667 .dir = "IPQ5018/hw1.0",
668 .board_size = 256 * 1024,
669 .cal_offset = 128 * 1024,
670 },
671 .max_radios = MAX_RADIOS_5018,
672 .bdf_addr = 0x4BA00000,
673 /* hal_desc_sz and hw ops are similar to qcn9074 */
674 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
675 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
676 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
677 .credit_flow = false,
678 .spectral = {
679 .fft_sz = 2,
680 .fft_pad_sz = 0,
681 .summary_pad_sz = 16,
682 .fft_hdr_len = 24,
683 .max_fft_bins = 1024,
684 },
685 .internal_sleep_clock = false,
686 .regs = &ipq5018_regs,
687 .hw_ops = &ipq5018_ops,
688 .host_ce_config = ath11k_host_ce_config_qcn9074,
689 .ce_count = CE_CNT_5018,
690 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
691 .target_ce_count = TARGET_CE_CNT_5018,
692 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
693 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
694 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
695 .ce_remap = &ath11k_ce_remap_ipq5018,
696 .rxdma1_enable = true,
697 .num_rxdma_per_pdev = RXDMA_PER_PDEV_5018,
698 .rx_mac_buf_ring = false,
699 .vdev_start_delay = false,
700 .htt_peer_map_v2 = true,
701 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
702 BIT(NL80211_IFTYPE_AP) |
703 BIT(NL80211_IFTYPE_MESH_POINT),
704 .supports_monitor = false,
705 .supports_sta_ps = false,
706 .supports_shadow_regs = false,
707 .fw_mem_mode = 0,
708 .num_vdevs = 16 + 1,
709 .num_peers = 512,
710 .supports_regdb = false,
711 .idle_ps = false,
712 .supports_suspend = false,
713 .hal_params = &ath11k_hw_hal_params_ipq5018,
714 .single_pdev_only = false,
715 .coldboot_cal_mm = true,
716 .coldboot_cal_ftm = true,
717 .cbcal_restart_fw = true,
718 .fix_l1ss = true,
719 .supports_dynamic_smps_6ghz = false,
720 .alloc_cacheable_memory = true,
721 .supports_rssi_stats = false,
722 .fw_wmi_diag_event = false,
723 .current_cc_support = false,
724 .dbr_debug_support = true,
725 .global_reset = false,
726 .bios_sar_capa = NULL,
727 .m3_fw_support = false,
728 .fixed_bdf_addr = true,
729 .fixed_mem_region = true,
730 .static_window_map = false,
731 .hybrid_bus_type = false,
732 .fixed_fw_mem = false,
733 .support_off_channel_tx = false,
734 .supports_multi_bssid = false,
735
736 .sram_dump = {},
737
738 .tcl_ring_retry = true,
739 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
740 .smp2p_wow_exit = false,
741 .support_fw_mac_sequence = false,
742 .support_dual_stations = false,
743 .pdev_suspend = false,
744 .cfr_support = false,
745 .cfr_num_stream_bufs = 0,
746 .cfr_stream_buf_size = 0,
747 },
748 {
749 .name = "qca2066 hw2.1",
750 .hw_rev = ATH11K_HW_QCA2066_HW21,
751 .fw = {
752 .dir = "QCA2066/hw2.1",
753 .board_size = 256 * 1024,
754 .cal_offset = 128 * 1024,
755 },
756 .max_radios = 3,
757 .bdf_addr = 0x4B0C0000,
758 .hw_ops = &wcn6855_ops,
759 .ring_mask = &ath11k_hw_ring_mask_qca6390,
760 .internal_sleep_clock = true,
761 .regs = &wcn6855_regs,
762 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
763 .host_ce_config = ath11k_host_ce_config_qca6390,
764 .ce_count = 9,
765 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
766 .target_ce_count = 9,
767 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
768 .svc_to_ce_map_len = 14,
769 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
770 .single_pdev_only = true,
771 .rxdma1_enable = false,
772 .num_rxdma_per_pdev = 2,
773 .rx_mac_buf_ring = true,
774 .vdev_start_delay = true,
775 .htt_peer_map_v2 = false,
776
777 .spectral = {
778 .fft_sz = 0,
779 .fft_pad_sz = 0,
780 .summary_pad_sz = 0,
781 .fft_hdr_len = 0,
782 .max_fft_bins = 0,
783 .fragment_160mhz = false,
784 },
785
786 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
787 BIT(NL80211_IFTYPE_AP) |
788 BIT(NL80211_IFTYPE_P2P_DEVICE) |
789 BIT(NL80211_IFTYPE_P2P_CLIENT) |
790 BIT(NL80211_IFTYPE_P2P_GO),
791 .supports_monitor = false,
792 .full_monitor_mode = false,
793 .supports_shadow_regs = true,
794 .idle_ps = true,
795 .supports_sta_ps = true,
796 .coldboot_cal_mm = false,
797 .coldboot_cal_ftm = false,
798 .cbcal_restart_fw = false,
799 .fw_mem_mode = 0,
800 .num_vdevs = 4,
801 .num_peers = 512,
802 .supports_suspend = true,
803 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
804 .supports_regdb = true,
805 .fix_l1ss = false,
806 .credit_flow = true,
807 .hal_params = &ath11k_hw_hal_params_qca6390,
808 .supports_dynamic_smps_6ghz = false,
809 .alloc_cacheable_memory = false,
810 .supports_rssi_stats = true,
811 .fw_wmi_diag_event = true,
812 .current_cc_support = true,
813 .dbr_debug_support = false,
814 .global_reset = true,
815 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
816 .m3_fw_support = true,
817 .fixed_bdf_addr = false,
818 .fixed_mem_region = false,
819 .static_window_map = false,
820 .hybrid_bus_type = false,
821 .fixed_fw_mem = false,
822 .support_off_channel_tx = true,
823 .supports_multi_bssid = true,
824
825 .sram_dump = {
826 .start = 0x01400000,
827 .end = 0x0177ffff,
828 },
829
830 .tcl_ring_retry = true,
831 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
832 .smp2p_wow_exit = false,
833 .support_fw_mac_sequence = true,
834 .support_dual_stations = true,
835 .cfr_support = false,
836 .cfr_num_stream_bufs = 0,
837 .cfr_stream_buf_size = 0,
838 },
839 {
840 .name = "qca6698aq hw2.1",
841 .hw_rev = ATH11K_HW_QCA6698AQ_HW21,
842 .fw = {
843 .dir = "QCA6698AQ/hw2.1",
844 .board_size = 256 * 1024,
845 .cal_offset = 128 * 1024,
846 },
847 .max_radios = 3,
848 .bdf_addr = 0x4B0C0000,
849 .hw_ops = &wcn6855_ops,
850 .ring_mask = &ath11k_hw_ring_mask_qca6390,
851 .internal_sleep_clock = true,
852 .regs = &wcn6855_regs,
853 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
854 .host_ce_config = ath11k_host_ce_config_qca6390,
855 .ce_count = 9,
856 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
857 .target_ce_count = 9,
858 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
859 .svc_to_ce_map_len = 14,
860 .single_pdev_only = true,
861 .rxdma1_enable = false,
862 .num_rxdma_per_pdev = 2,
863 .rx_mac_buf_ring = true,
864 .vdev_start_delay = true,
865 .htt_peer_map_v2 = false,
866
867 .spectral = {
868 .fft_sz = 0,
869 .fft_pad_sz = 0,
870 .summary_pad_sz = 0,
871 .fft_hdr_len = 0,
872 .max_fft_bins = 0,
873 .fragment_160mhz = false,
874 },
875
876 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
877 BIT(NL80211_IFTYPE_AP) |
878 BIT(NL80211_IFTYPE_P2P_DEVICE) |
879 BIT(NL80211_IFTYPE_P2P_CLIENT) |
880 BIT(NL80211_IFTYPE_P2P_GO),
881 .supports_monitor = false,
882 .supports_shadow_regs = true,
883 .idle_ps = true,
884 .supports_sta_ps = true,
885 .coldboot_cal_mm = false,
886 .coldboot_cal_ftm = false,
887 .cbcal_restart_fw = false,
888 .fw_mem_mode = 0,
889 .num_vdevs = 4,
890 .num_peers = 512,
891 .supports_suspend = true,
892 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
893 .supports_regdb = true,
894 .fix_l1ss = false,
895 .credit_flow = true,
896 .hal_params = &ath11k_hw_hal_params_qca6390,
897 .supports_dynamic_smps_6ghz = false,
898 .alloc_cacheable_memory = false,
899 .supports_rssi_stats = true,
900 .fw_wmi_diag_event = true,
901 .current_cc_support = true,
902 .dbr_debug_support = false,
903 .global_reset = true,
904 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
905 .m3_fw_support = true,
906 .fixed_bdf_addr = false,
907 .fixed_mem_region = false,
908 .static_window_map = false,
909 .hybrid_bus_type = false,
910 .fixed_fw_mem = false,
911 .support_off_channel_tx = true,
912 .supports_multi_bssid = true,
913
914 .sram_dump = {
915 .start = 0x01400000,
916 .end = 0x0177ffff,
917 },
918
919 .tcl_ring_retry = true,
920 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
921 .smp2p_wow_exit = false,
922 .support_fw_mac_sequence = true,
923 .support_dual_stations = true,
924 .pdev_suspend = false,
925 .cfr_support = true,
926 .cfr_num_stream_bufs = 255,
927 .cfr_stream_buf_size = 8200,
928 },
929 };
930
931 static const struct dmi_system_id ath11k_pm_quirk_table[] = {
932 {
933 .driver_data = (void *)ATH11K_PM_WOW,
934 .matches = { /* X13 G4 AMD #1 */
935 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
936 DMI_MATCH(DMI_PRODUCT_NAME, "21J3"),
937 },
938 },
939 {
940 .driver_data = (void *)ATH11K_PM_WOW,
941 .matches = { /* X13 G4 AMD #2 */
942 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
943 DMI_MATCH(DMI_PRODUCT_NAME, "21J4"),
944 },
945 },
946 {
947 .driver_data = (void *)ATH11K_PM_WOW,
948 .matches = { /* T14 G4 AMD #1 */
949 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
950 DMI_MATCH(DMI_PRODUCT_NAME, "21K3"),
951 },
952 },
953 {
954 .driver_data = (void *)ATH11K_PM_WOW,
955 .matches = { /* T14 G4 AMD #2 */
956 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
957 DMI_MATCH(DMI_PRODUCT_NAME, "21K4"),
958 },
959 },
960 {
961 .driver_data = (void *)ATH11K_PM_WOW,
962 .matches = { /* P14s G4 AMD #1 */
963 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
964 DMI_MATCH(DMI_PRODUCT_NAME, "21K5"),
965 },
966 },
967 {
968 .driver_data = (void *)ATH11K_PM_WOW,
969 .matches = { /* P14s G4 AMD #2 */
970 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
971 DMI_MATCH(DMI_PRODUCT_NAME, "21K6"),
972 },
973 },
974 {
975 .driver_data = (void *)ATH11K_PM_WOW,
976 .matches = { /* T16 G2 AMD #1 */
977 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
978 DMI_MATCH(DMI_PRODUCT_NAME, "21K7"),
979 },
980 },
981 {
982 .driver_data = (void *)ATH11K_PM_WOW,
983 .matches = { /* T16 G2 AMD #2 */
984 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
985 DMI_MATCH(DMI_PRODUCT_NAME, "21K8"),
986 },
987 },
988 {
989 .driver_data = (void *)ATH11K_PM_WOW,
990 .matches = { /* P16s G2 AMD #1 */
991 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
992 DMI_MATCH(DMI_PRODUCT_NAME, "21K9"),
993 },
994 },
995 {
996 .driver_data = (void *)ATH11K_PM_WOW,
997 .matches = { /* P16s G2 AMD #2 */
998 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
999 DMI_MATCH(DMI_PRODUCT_NAME, "21KA"),
1000 },
1001 },
1002 {
1003 .driver_data = (void *)ATH11K_PM_WOW,
1004 .matches = { /* T14s G4 AMD #1 */
1005 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
1006 DMI_MATCH(DMI_PRODUCT_NAME, "21F8"),
1007 },
1008 },
1009 {
1010 .driver_data = (void *)ATH11K_PM_WOW,
1011 .matches = { /* T14s G4 AMD #2 */
1012 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
1013 DMI_MATCH(DMI_PRODUCT_NAME, "21F9"),
1014 },
1015 },
1016 {
1017 .driver_data = (void *)ATH11K_PM_WOW,
1018 .matches = { /* Z13 G1 */
1019 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
1020 DMI_MATCH(DMI_PRODUCT_NAME, "21D2"),
1021 },
1022 },
1023 {
1024 .driver_data = (void *)ATH11K_PM_WOW,
1025 .matches = { /* Z13 G1 */
1026 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
1027 DMI_MATCH(DMI_PRODUCT_NAME, "21D3"),
1028 },
1029 },
1030 {
1031 .driver_data = (void *)ATH11K_PM_WOW,
1032 .matches = { /* Z16 G1 */
1033 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
1034 DMI_MATCH(DMI_PRODUCT_NAME, "21D4"),
1035 },
1036 },
1037 {
1038 .driver_data = (void *)ATH11K_PM_WOW,
1039 .matches = { /* Z16 G1 */
1040 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
1041 DMI_MATCH(DMI_PRODUCT_NAME, "21D5"),
1042 },
1043 },
1044 {}
1045 };
1046
1047 static const struct __ath11k_core_usecase_firmware_table {
1048 u32 hw_rev;
1049 const char *compatible;
1050 const char *firmware_name;
1051 } ath11k_core_usecase_firmware_table[] = {
1052 { ATH11K_HW_WCN6855_HW21, "qcom,hamoa-iot-evk", "nfa765"},
1053 { ATH11K_HW_WCN6855_HW21, "qcom,lemans-evk", "nfa765"},
1054 { ATH11K_HW_WCN6855_HW21, "qcom,monaco-evk", "nfa765"},
1055 { ATH11K_HW_WCN6855_HW21, "qcom,purwa-iot-evk", "nfa765"},
1056 { ATH11K_HW_WCN6855_HW21, "qcom,qcs6490-rb3gen2", "nfa765"},
1057 { /* Sentinel */ }
1058 };
1059
ath11k_core_get_usecase_firmware(struct ath11k_base * ab)1060 const char *ath11k_core_get_usecase_firmware(struct ath11k_base *ab)
1061 {
1062 const struct __ath11k_core_usecase_firmware_table *entry = NULL;
1063
1064 entry = ath11k_core_usecase_firmware_table;
1065 while (entry->compatible) {
1066 if (ab->hw_rev == entry->hw_rev &&
1067 of_machine_is_compatible(entry->compatible))
1068 return entry->firmware_name;
1069 entry++;
1070 }
1071
1072 return NULL;
1073 }
1074 EXPORT_SYMBOL(ath11k_core_get_usecase_firmware);
1075
ath11k_fw_stats_pdevs_free(struct list_head * head)1076 void ath11k_fw_stats_pdevs_free(struct list_head *head)
1077 {
1078 struct ath11k_fw_stats_pdev *i, *tmp;
1079
1080 list_for_each_entry_safe(i, tmp, head, list) {
1081 list_del(&i->list);
1082 kfree(i);
1083 }
1084 }
1085
ath11k_fw_stats_vdevs_free(struct list_head * head)1086 void ath11k_fw_stats_vdevs_free(struct list_head *head)
1087 {
1088 struct ath11k_fw_stats_vdev *i, *tmp;
1089
1090 list_for_each_entry_safe(i, tmp, head, list) {
1091 list_del(&i->list);
1092 kfree(i);
1093 }
1094 }
1095
ath11k_fw_stats_bcn_free(struct list_head * head)1096 void ath11k_fw_stats_bcn_free(struct list_head *head)
1097 {
1098 struct ath11k_fw_stats_bcn *i, *tmp;
1099
1100 list_for_each_entry_safe(i, tmp, head, list) {
1101 list_del(&i->list);
1102 kfree(i);
1103 }
1104 }
1105
ath11k_fw_stats_init(struct ath11k * ar)1106 void ath11k_fw_stats_init(struct ath11k *ar)
1107 {
1108 INIT_LIST_HEAD(&ar->fw_stats.pdevs);
1109 INIT_LIST_HEAD(&ar->fw_stats.vdevs);
1110 INIT_LIST_HEAD(&ar->fw_stats.bcn);
1111
1112 init_completion(&ar->fw_stats_complete);
1113 init_completion(&ar->fw_stats_done);
1114 }
1115
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)1116 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
1117 {
1118 ath11k_fw_stats_pdevs_free(&stats->pdevs);
1119 ath11k_fw_stats_vdevs_free(&stats->vdevs);
1120 ath11k_fw_stats_bcn_free(&stats->bcn);
1121 }
1122
ath11k_core_coldboot_cal_support(struct ath11k_base * ab)1123 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
1124 {
1125 if (!ath11k_cold_boot_cal)
1126 return false;
1127
1128 if (ath11k_ftm_mode)
1129 return ab->hw_params.coldboot_cal_ftm;
1130
1131 else
1132 return ab->hw_params.coldboot_cal_mm;
1133 }
1134
1135 /* Check if we need to continue with suspend/resume operation.
1136 * Return:
1137 * a negative value: error happens and don't continue.
1138 * 0: no error but don't continue.
1139 * positive value: no error and do continue.
1140 */
ath11k_core_continue_suspend_resume(struct ath11k_base * ab)1141 static int ath11k_core_continue_suspend_resume(struct ath11k_base *ab)
1142 {
1143 struct ath11k *ar;
1144
1145 if (!ab->hw_params.supports_suspend)
1146 return -EOPNOTSUPP;
1147
1148 /* so far single_pdev_only chips have supports_suspend as true
1149 * so pass 0 as a dummy pdev_id here.
1150 */
1151 ar = ab->pdevs[0].ar;
1152 if (!ar || ar->state != ATH11K_STATE_OFF)
1153 return 0;
1154
1155 return 1;
1156 }
1157
ath11k_core_suspend_wow(struct ath11k_base * ab)1158 static int ath11k_core_suspend_wow(struct ath11k_base *ab)
1159 {
1160 int ret;
1161
1162 ret = ath11k_dp_rx_pktlog_stop(ab, true);
1163 if (ret) {
1164 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
1165 ret);
1166 return ret;
1167 }
1168
1169 /* So far only single_pdev_only devices can reach here,
1170 * so it is valid to handle the first, and the only, pdev.
1171 */
1172 ret = ath11k_mac_wait_tx_complete(ab->pdevs[0].ar);
1173 if (ret) {
1174 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
1175 return ret;
1176 }
1177
1178 ret = ath11k_wow_enable(ab);
1179 if (ret) {
1180 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
1181 return ret;
1182 }
1183
1184 ret = ath11k_dp_rx_pktlog_stop(ab, false);
1185 if (ret) {
1186 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
1187 ret);
1188 return ret;
1189 }
1190
1191 ath11k_ce_stop_shadow_timers(ab);
1192 ath11k_dp_stop_shadow_timers(ab);
1193
1194 ath11k_hif_irq_disable(ab);
1195 ath11k_hif_ce_irq_disable(ab);
1196
1197 ret = ath11k_hif_suspend(ab);
1198 if (ret) {
1199 ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
1200 return ret;
1201 }
1202
1203 return 0;
1204 }
1205
ath11k_core_suspend_default(struct ath11k_base * ab)1206 static int ath11k_core_suspend_default(struct ath11k_base *ab)
1207 {
1208 int ret;
1209
1210 ret = ath11k_dp_rx_pktlog_stop(ab, true);
1211 if (ret) {
1212 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
1213 ret);
1214 return ret;
1215 }
1216
1217 /* So far only single_pdev_only devices can reach here,
1218 * so it is valid to handle the first, and the only, pdev.
1219 */
1220 ret = ath11k_mac_wait_tx_complete(ab->pdevs[0].ar);
1221 if (ret) {
1222 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
1223 return ret;
1224 }
1225
1226 ret = ath11k_dp_rx_pktlog_stop(ab, false);
1227 if (ret) {
1228 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
1229 ret);
1230 return ret;
1231 }
1232
1233 ath11k_ce_stop_shadow_timers(ab);
1234 ath11k_dp_stop_shadow_timers(ab);
1235
1236 /* PM framework skips suspend_late/resume_early callbacks
1237 * if other devices report errors in their suspend callbacks.
1238 * However ath11k_core_resume() would still be called because
1239 * here we return success thus kernel put us on dpm_suspended_list.
1240 * Since we won't go through a power down/up cycle, there is
1241 * no chance to call complete(&ab->restart_completed) in
1242 * ath11k_core_restart(), making ath11k_core_resume() timeout.
1243 * So call it here to avoid this issue. This also works in case
1244 * no error happens thus suspend_late/resume_early get called,
1245 * because it will be reinitialized in ath11k_core_resume_early().
1246 */
1247 complete(&ab->restart_completed);
1248
1249 return 0;
1250 }
1251
ath11k_core_suspend(struct ath11k_base * ab)1252 int ath11k_core_suspend(struct ath11k_base *ab)
1253 {
1254 int ret;
1255
1256 ret = ath11k_core_continue_suspend_resume(ab);
1257 if (ret <= 0)
1258 return ret;
1259
1260 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1261 return ath11k_core_suspend_wow(ab);
1262
1263 return ath11k_core_suspend_default(ab);
1264 }
1265 EXPORT_SYMBOL(ath11k_core_suspend);
1266
ath11k_core_suspend_late(struct ath11k_base * ab)1267 int ath11k_core_suspend_late(struct ath11k_base *ab)
1268 {
1269 int ret;
1270
1271 ret = ath11k_core_continue_suspend_resume(ab);
1272 if (ret <= 0)
1273 return ret;
1274
1275 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1276 return 0;
1277
1278 ath11k_hif_irq_disable(ab);
1279 ath11k_hif_ce_irq_disable(ab);
1280
1281 ath11k_hif_power_down(ab, true);
1282
1283 return 0;
1284 }
1285 EXPORT_SYMBOL(ath11k_core_suspend_late);
1286
ath11k_core_resume_early(struct ath11k_base * ab)1287 int ath11k_core_resume_early(struct ath11k_base *ab)
1288 {
1289 int ret;
1290
1291 ret = ath11k_core_continue_suspend_resume(ab);
1292 if (ret <= 0)
1293 return ret;
1294
1295 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1296 return 0;
1297
1298 reinit_completion(&ab->restart_completed);
1299 ret = ath11k_hif_power_up(ab);
1300 if (ret)
1301 ath11k_warn(ab, "failed to power up hif during resume: %d\n", ret);
1302
1303 return ret;
1304 }
1305 EXPORT_SYMBOL(ath11k_core_resume_early);
1306
ath11k_core_resume_default(struct ath11k_base * ab)1307 static int ath11k_core_resume_default(struct ath11k_base *ab)
1308 {
1309 struct ath11k *ar;
1310 long time_left;
1311 int ret;
1312
1313 time_left = wait_for_completion_timeout(&ab->restart_completed,
1314 ATH11K_RESET_TIMEOUT_HZ);
1315 if (time_left == 0) {
1316 ath11k_warn(ab, "timeout while waiting for restart complete");
1317 return -ETIMEDOUT;
1318 }
1319
1320 /* So far only single_pdev_only devices can reach here,
1321 * so it is valid to handle the first, and the only, pdev.
1322 */
1323 ar = ab->pdevs[0].ar;
1324 if (ab->hw_params.current_cc_support &&
1325 ar->alpha2[0] != 0 && ar->alpha2[1] != 0) {
1326 ret = ath11k_reg_set_cc(ar);
1327 if (ret) {
1328 ath11k_warn(ab, "failed to set country code during resume: %d\n",
1329 ret);
1330 return ret;
1331 }
1332 }
1333
1334 ret = ath11k_dp_rx_pktlog_start(ab);
1335 if (ret)
1336 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
1337 ret);
1338
1339 return ret;
1340 }
1341
ath11k_core_resume_wow(struct ath11k_base * ab)1342 static int ath11k_core_resume_wow(struct ath11k_base *ab)
1343 {
1344 int ret;
1345
1346 ret = ath11k_hif_resume(ab);
1347 if (ret) {
1348 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
1349 return ret;
1350 }
1351
1352 ath11k_hif_ce_irq_enable(ab);
1353 ath11k_hif_irq_enable(ab);
1354
1355 ret = ath11k_dp_rx_pktlog_start(ab);
1356 if (ret) {
1357 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
1358 ret);
1359 return ret;
1360 }
1361
1362 ret = ath11k_wow_wakeup(ab);
1363 if (ret) {
1364 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
1365 return ret;
1366 }
1367
1368 return 0;
1369 }
1370
ath11k_core_resume(struct ath11k_base * ab)1371 int ath11k_core_resume(struct ath11k_base *ab)
1372 {
1373 int ret;
1374
1375 ret = ath11k_core_continue_suspend_resume(ab);
1376 if (ret <= 0)
1377 return ret;
1378
1379 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1380 return ath11k_core_resume_wow(ab);
1381
1382 return ath11k_core_resume_default(ab);
1383 }
1384 EXPORT_SYMBOL(ath11k_core_resume);
1385
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)1386 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
1387 {
1388 struct ath11k_base *ab = data;
1389 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
1390 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
1391 ssize_t copied;
1392 size_t len;
1393 int i;
1394
1395 if (ab->qmi.target.bdf_ext[0] != '\0')
1396 return;
1397
1398 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
1399 return;
1400
1401 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
1402 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1403 "wrong smbios bdf ext type length (%d).\n",
1404 hdr->length);
1405 return;
1406 }
1407
1408 spin_lock_bh(&ab->base_lock);
1409
1410 switch (smbios->country_code_flag) {
1411 case ATH11K_SMBIOS_CC_ISO:
1412 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
1413 ab->new_alpha2[1] = smbios->cc_code & 0xff;
1414 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
1415 ab->new_alpha2[0], ab->new_alpha2[1]);
1416 break;
1417 case ATH11K_SMBIOS_CC_WW:
1418 ab->new_alpha2[0] = '0';
1419 ab->new_alpha2[1] = '0';
1420 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
1421 break;
1422 default:
1423 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
1424 smbios->country_code_flag);
1425 break;
1426 }
1427
1428 spin_unlock_bh(&ab->base_lock);
1429
1430 if (!smbios->bdf_enabled) {
1431 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
1432 return;
1433 }
1434
1435 /* Only one string exists (per spec) */
1436 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
1437 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1438 "bdf variant magic does not match.\n");
1439 return;
1440 }
1441
1442 len = min_t(size_t,
1443 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
1444 for (i = 0; i < len; i++) {
1445 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
1446 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1447 "bdf variant name contains non ascii chars.\n");
1448 return;
1449 }
1450 }
1451
1452 /* Copy extension name without magic prefix */
1453 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
1454 sizeof(ab->qmi.target.bdf_ext));
1455 if (copied < 0) {
1456 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1457 "bdf variant string is longer than the buffer can accommodate\n");
1458 return;
1459 }
1460
1461 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1462 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1463 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
1464 }
1465
ath11k_core_check_smbios(struct ath11k_base * ab)1466 int ath11k_core_check_smbios(struct ath11k_base *ab)
1467 {
1468 ab->qmi.target.bdf_ext[0] = '\0';
1469 dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
1470
1471 if (ab->qmi.target.bdf_ext[0] == '\0')
1472 return -ENODATA;
1473
1474 return 0;
1475 }
1476
ath11k_core_check_dt(struct ath11k_base * ab)1477 int ath11k_core_check_dt(struct ath11k_base *ab)
1478 {
1479 size_t max_len = sizeof(ab->qmi.target.bdf_ext);
1480 const char *variant = NULL;
1481 struct device_node *node;
1482
1483 node = ab->dev->of_node;
1484 if (!node)
1485 return -ENOENT;
1486
1487 of_property_read_string(node, "qcom,calibration-variant",
1488 &variant);
1489 if (!variant)
1490 of_property_read_string(node, "qcom,ath11k-calibration-variant",
1491 &variant);
1492 if (!variant)
1493 return -ENODATA;
1494
1495 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
1496 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1497 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1498 variant);
1499
1500 return 0;
1501 }
1502
1503 enum ath11k_bdf_name_type {
1504 ATH11K_BDF_NAME_FULL,
1505 ATH11K_BDF_NAME_BUS_NAME,
1506 ATH11K_BDF_NAME_CHIP_ID,
1507 };
1508
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,enum ath11k_bdf_name_type name_type)1509 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1510 size_t name_len, bool with_variant,
1511 enum ath11k_bdf_name_type name_type)
1512 {
1513 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
1514 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = {};
1515
1516 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
1517 scnprintf(variant, sizeof(variant), ",variant=%s",
1518 ab->qmi.target.bdf_ext);
1519
1520 switch (ab->id.bdf_search) {
1521 case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
1522 switch (name_type) {
1523 case ATH11K_BDF_NAME_FULL:
1524 scnprintf(name, name_len,
1525 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1526 ath11k_bus_str(ab->hif.bus),
1527 ab->id.vendor, ab->id.device,
1528 ab->id.subsystem_vendor,
1529 ab->id.subsystem_device,
1530 ab->qmi.target.chip_id,
1531 ab->qmi.target.board_id,
1532 variant);
1533 break;
1534 case ATH11K_BDF_NAME_BUS_NAME:
1535 scnprintf(name, name_len,
1536 "bus=%s",
1537 ath11k_bus_str(ab->hif.bus));
1538 break;
1539 case ATH11K_BDF_NAME_CHIP_ID:
1540 scnprintf(name, name_len,
1541 "bus=%s,qmi-chip-id=%d",
1542 ath11k_bus_str(ab->hif.bus),
1543 ab->qmi.target.chip_id);
1544 break;
1545 }
1546 break;
1547 default:
1548 scnprintf(name, name_len,
1549 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1550 ath11k_bus_str(ab->hif.bus),
1551 ab->qmi.target.chip_id,
1552 ab->qmi.target.board_id, variant);
1553 break;
1554 }
1555
1556 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1557
1558 return 0;
1559 }
1560
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)1561 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1562 size_t name_len)
1563 {
1564 return __ath11k_core_create_board_name(ab, name, name_len, true,
1565 ATH11K_BDF_NAME_FULL);
1566 }
1567
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)1568 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
1569 size_t name_len)
1570 {
1571 return __ath11k_core_create_board_name(ab, name, name_len, false,
1572 ATH11K_BDF_NAME_FULL);
1573 }
1574
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)1575 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
1576 size_t name_len)
1577 {
1578 return __ath11k_core_create_board_name(ab, name, name_len, false,
1579 ATH11K_BDF_NAME_BUS_NAME);
1580 }
1581
ath11k_core_create_chip_id_board_name(struct ath11k_base * ab,char * name,size_t name_len)1582 static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name,
1583 size_t name_len)
1584 {
1585 return __ath11k_core_create_board_name(ab, name, name_len, false,
1586 ATH11K_BDF_NAME_CHIP_ID);
1587 }
1588
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)1589 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1590 const char *file)
1591 {
1592 const struct firmware *fw;
1593 char path[100];
1594 int ret;
1595
1596 if (file == NULL)
1597 return ERR_PTR(-ENOENT);
1598
1599 ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
1600
1601 ret = firmware_request_nowarn(&fw, path, ab->dev);
1602 if (ret)
1603 return ERR_PTR(ret);
1604
1605 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1606 path, fw->size);
1607
1608 return fw;
1609 }
1610
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1611 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1612 {
1613 if (!IS_ERR(bd->fw))
1614 release_firmware(bd->fw);
1615
1616 memset(bd, 0, sizeof(*bd));
1617 }
1618
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)1619 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1620 struct ath11k_board_data *bd,
1621 const void *buf, size_t buf_len,
1622 const char *boardname,
1623 int ie_id,
1624 int name_id,
1625 int data_id)
1626 {
1627 const struct ath11k_fw_ie *hdr;
1628 bool name_match_found;
1629 int ret, board_ie_id;
1630 size_t board_ie_len;
1631 const void *board_ie_data;
1632
1633 name_match_found = false;
1634
1635 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1636 while (buf_len > sizeof(struct ath11k_fw_ie)) {
1637 hdr = buf;
1638 board_ie_id = le32_to_cpu(hdr->id);
1639 board_ie_len = le32_to_cpu(hdr->len);
1640 board_ie_data = hdr->data;
1641
1642 buf_len -= sizeof(*hdr);
1643 buf += sizeof(*hdr);
1644
1645 if (buf_len < ALIGN(board_ie_len, 4)) {
1646 ath11k_err(ab, "invalid %s length: %zu < %zu\n",
1647 ath11k_bd_ie_type_str(ie_id),
1648 buf_len, ALIGN(board_ie_len, 4));
1649 ret = -EINVAL;
1650 goto out;
1651 }
1652
1653 if (board_ie_id == name_id) {
1654 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
1655 board_ie_data, board_ie_len);
1656
1657 if (board_ie_len != strlen(boardname))
1658 goto next;
1659
1660 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1661 if (ret)
1662 goto next;
1663
1664 name_match_found = true;
1665 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1666 "found match %s for name '%s'",
1667 ath11k_bd_ie_type_str(ie_id),
1668 boardname);
1669 } else if (board_ie_id == data_id) {
1670 if (!name_match_found)
1671 /* no match found */
1672 goto next;
1673
1674 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1675 "found %s for '%s'",
1676 ath11k_bd_ie_type_str(ie_id),
1677 boardname);
1678
1679 bd->data = board_ie_data;
1680 bd->len = board_ie_len;
1681
1682 ret = 0;
1683 goto out;
1684 } else {
1685 ath11k_warn(ab, "unknown %s id found: %d\n",
1686 ath11k_bd_ie_type_str(ie_id),
1687 board_ie_id);
1688 }
1689 next:
1690 /* jump over the padding */
1691 board_ie_len = ALIGN(board_ie_len, 4);
1692
1693 buf_len -= board_ie_len;
1694 buf += board_ie_len;
1695 }
1696
1697 /* no match found */
1698 ret = -ENOENT;
1699
1700 out:
1701 return ret;
1702 }
1703
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1704 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1705 struct ath11k_board_data *bd,
1706 const char *boardname,
1707 int ie_id_match,
1708 int name_id,
1709 int data_id)
1710 {
1711 size_t len, magic_len;
1712 const u8 *data;
1713 char *filename, filepath[100];
1714 size_t ie_len;
1715 struct ath11k_fw_ie *hdr;
1716 int ret, ie_id;
1717
1718 filename = ATH11K_BOARD_API2_FILE;
1719
1720 if (!bd->fw)
1721 bd->fw = ath11k_core_firmware_request(ab, filename);
1722
1723 if (IS_ERR(bd->fw))
1724 return PTR_ERR(bd->fw);
1725
1726 data = bd->fw->data;
1727 len = bd->fw->size;
1728
1729 ath11k_core_create_firmware_path(ab, filename,
1730 filepath, sizeof(filepath));
1731
1732 /* magic has extra null byte padded */
1733 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1734 if (len < magic_len) {
1735 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1736 filepath, len);
1737 ret = -EINVAL;
1738 goto err;
1739 }
1740
1741 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1742 ath11k_err(ab, "found invalid board magic\n");
1743 ret = -EINVAL;
1744 goto err;
1745 }
1746
1747 /* magic is padded to 4 bytes */
1748 magic_len = ALIGN(magic_len, 4);
1749 if (len < magic_len) {
1750 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1751 filepath, len);
1752 ret = -EINVAL;
1753 goto err;
1754 }
1755
1756 data += magic_len;
1757 len -= magic_len;
1758
1759 while (len > sizeof(struct ath11k_fw_ie)) {
1760 hdr = (struct ath11k_fw_ie *)data;
1761 ie_id = le32_to_cpu(hdr->id);
1762 ie_len = le32_to_cpu(hdr->len);
1763
1764 len -= sizeof(*hdr);
1765 data = hdr->data;
1766
1767 if (len < ALIGN(ie_len, 4)) {
1768 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1769 ie_id, ie_len, len);
1770 ret = -EINVAL;
1771 goto err;
1772 }
1773
1774 if (ie_id == ie_id_match) {
1775 ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1776 ie_len,
1777 boardname,
1778 ie_id_match,
1779 name_id,
1780 data_id);
1781 if (ret == -ENOENT)
1782 /* no match found, continue */
1783 goto next;
1784 else if (ret)
1785 /* there was an error, bail out */
1786 goto err;
1787 /* either found or error, so stop searching */
1788 goto out;
1789 }
1790 next:
1791 /* jump over the padding */
1792 ie_len = ALIGN(ie_len, 4);
1793
1794 len -= ie_len;
1795 data += ie_len;
1796 }
1797
1798 out:
1799 if (!bd->data || !bd->len) {
1800 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1801 "failed to fetch %s for %s from %s\n",
1802 ath11k_bd_ie_type_str(ie_id_match),
1803 boardname, filepath);
1804 ret = -ENODATA;
1805 goto err;
1806 }
1807
1808 return 0;
1809
1810 err:
1811 ath11k_core_free_bdf(ab, bd);
1812 return ret;
1813 }
1814
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1815 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1816 struct ath11k_board_data *bd,
1817 const char *name)
1818 {
1819 bd->fw = ath11k_core_firmware_request(ab, name);
1820
1821 if (IS_ERR(bd->fw))
1822 return PTR_ERR(bd->fw);
1823
1824 bd->data = bd->fw->data;
1825 bd->len = bd->fw->size;
1826
1827 return 0;
1828 }
1829
1830 #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1831 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1832 {
1833 char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL;
1834 char *filename, filepath[100];
1835 int bd_api;
1836 int ret = 0;
1837
1838 filename = ATH11K_BOARD_API2_FILE;
1839 boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1840 if (!boardname) {
1841 ret = -ENOMEM;
1842 goto exit;
1843 }
1844
1845 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1846 if (ret) {
1847 ath11k_err(ab, "failed to create board name: %d", ret);
1848 goto exit;
1849 }
1850
1851 bd_api = 2;
1852 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1853 ATH11K_BD_IE_BOARD,
1854 ATH11K_BD_IE_BOARD_NAME,
1855 ATH11K_BD_IE_BOARD_DATA);
1856 if (!ret)
1857 goto exit;
1858
1859 fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1860 if (!fallback_boardname) {
1861 ret = -ENOMEM;
1862 goto exit;
1863 }
1864
1865 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1866 BOARD_NAME_SIZE);
1867 if (ret) {
1868 ath11k_err(ab, "failed to create fallback board name: %d", ret);
1869 goto exit;
1870 }
1871
1872 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1873 ATH11K_BD_IE_BOARD,
1874 ATH11K_BD_IE_BOARD_NAME,
1875 ATH11K_BD_IE_BOARD_DATA);
1876 if (!ret)
1877 goto exit;
1878
1879 chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1880 if (!chip_id_boardname) {
1881 ret = -ENOMEM;
1882 goto exit;
1883 }
1884
1885 ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname,
1886 BOARD_NAME_SIZE);
1887 if (ret) {
1888 ath11k_err(ab, "failed to create chip id board name: %d", ret);
1889 goto exit;
1890 }
1891
1892 ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname,
1893 ATH11K_BD_IE_BOARD,
1894 ATH11K_BD_IE_BOARD_NAME,
1895 ATH11K_BD_IE_BOARD_DATA);
1896
1897 if (!ret)
1898 goto exit;
1899
1900 bd_api = 1;
1901 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1902 if (ret) {
1903 ath11k_core_create_firmware_path(ab, filename,
1904 filepath, sizeof(filepath));
1905 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1906 boardname, filepath);
1907 if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1908 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1909 fallback_boardname, filepath);
1910
1911 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1912 chip_id_boardname, filepath);
1913
1914 ath11k_err(ab, "failed to fetch board.bin from %s\n",
1915 ab->hw_params.fw.dir);
1916 }
1917
1918 exit:
1919 kfree(boardname);
1920 kfree(fallback_boardname);
1921 kfree(chip_id_boardname);
1922
1923 if (!ret)
1924 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api);
1925
1926 return ret;
1927 }
1928
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1929 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1930 {
1931 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1932 int ret;
1933
1934 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1935 if (ret) {
1936 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1937 "failed to create board name for regdb: %d", ret);
1938 goto exit;
1939 }
1940
1941 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1942 ATH11K_BD_IE_REGDB,
1943 ATH11K_BD_IE_REGDB_NAME,
1944 ATH11K_BD_IE_REGDB_DATA);
1945 if (!ret)
1946 goto exit;
1947
1948 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
1949 BOARD_NAME_SIZE);
1950 if (ret) {
1951 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1952 "failed to create default board name for regdb: %d", ret);
1953 goto exit;
1954 }
1955
1956 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
1957 ATH11K_BD_IE_REGDB,
1958 ATH11K_BD_IE_REGDB_NAME,
1959 ATH11K_BD_IE_REGDB_DATA);
1960 if (!ret)
1961 goto exit;
1962
1963 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1964 if (ret)
1965 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1966 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1967
1968 exit:
1969 if (!ret)
1970 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1971
1972 return ret;
1973 }
1974
ath11k_core_stop(struct ath11k_base * ab)1975 static void ath11k_core_stop(struct ath11k_base *ab)
1976 {
1977 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1978 ath11k_qmi_firmware_stop(ab);
1979
1980 ath11k_hif_stop(ab);
1981 ath11k_wmi_detach(ab);
1982 ath11k_dp_pdev_reo_cleanup(ab);
1983
1984 /* De-Init of components as needed */
1985 }
1986
ath11k_core_soc_create(struct ath11k_base * ab)1987 static int ath11k_core_soc_create(struct ath11k_base *ab)
1988 {
1989 int ret;
1990
1991 if (ath11k_ftm_mode) {
1992 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
1993 ath11k_info(ab, "Booting in factory test mode\n");
1994 }
1995
1996 ret = ath11k_qmi_init_service(ab);
1997 if (ret) {
1998 ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1999 return ret;
2000 }
2001
2002 ret = ath11k_debugfs_soc_create(ab);
2003 if (ret) {
2004 ath11k_err(ab, "failed to create ath11k debugfs\n");
2005 goto err_qmi_deinit;
2006 }
2007
2008 ret = ath11k_hif_power_up(ab);
2009 if (ret) {
2010 ath11k_err(ab, "failed to power up :%d\n", ret);
2011 goto err_debugfs_reg;
2012 }
2013
2014 return 0;
2015
2016 err_debugfs_reg:
2017 ath11k_debugfs_soc_destroy(ab);
2018 err_qmi_deinit:
2019 ath11k_qmi_deinit_service(ab);
2020 return ret;
2021 }
2022
ath11k_core_soc_destroy(struct ath11k_base * ab)2023 static void ath11k_core_soc_destroy(struct ath11k_base *ab)
2024 {
2025 ath11k_debugfs_soc_destroy(ab);
2026 ath11k_dp_free(ab);
2027 ath11k_reg_free(ab);
2028 ath11k_qmi_deinit_service(ab);
2029 }
2030
ath11k_core_pdev_create(struct ath11k_base * ab)2031 static int ath11k_core_pdev_create(struct ath11k_base *ab)
2032 {
2033 int ret;
2034
2035 ret = ath11k_debugfs_pdev_create(ab);
2036 if (ret) {
2037 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
2038 return ret;
2039 }
2040
2041 ret = ath11k_dp_pdev_alloc(ab);
2042 if (ret) {
2043 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
2044 goto err_pdev_debug;
2045 }
2046
2047 ret = ath11k_mac_register(ab);
2048 if (ret) {
2049 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
2050 goto err_dp_pdev_free;
2051 }
2052
2053 ret = ath11k_thermal_register(ab);
2054 if (ret) {
2055 ath11k_err(ab, "could not register thermal device: %d\n",
2056 ret);
2057 goto err_mac_unregister;
2058 }
2059
2060 ret = ath11k_spectral_init(ab);
2061 if (ret) {
2062 ath11k_err(ab, "failed to init spectral %d\n", ret);
2063 goto err_thermal_unregister;
2064 }
2065
2066 ret = ath11k_cfr_init(ab);
2067 if (ret) {
2068 ath11k_err(ab, "failed to init cfr %d\n", ret);
2069 goto err_spectral_unregister;
2070 }
2071
2072 return 0;
2073
2074 err_spectral_unregister:
2075 ath11k_spectral_deinit(ab);
2076 err_thermal_unregister:
2077 ath11k_thermal_unregister(ab);
2078 err_mac_unregister:
2079 ath11k_mac_unregister(ab);
2080 err_dp_pdev_free:
2081 ath11k_dp_pdev_free(ab);
2082 err_pdev_debug:
2083 ath11k_debugfs_pdev_destroy(ab);
2084
2085 return ret;
2086 }
2087
ath11k_core_pdev_suspend_target(struct ath11k_base * ab)2088 static void ath11k_core_pdev_suspend_target(struct ath11k_base *ab)
2089 {
2090 struct ath11k *ar;
2091 struct ath11k_pdev *pdev;
2092 unsigned long time_left;
2093 int ret;
2094 int i;
2095
2096 if (!ab->hw_params.pdev_suspend)
2097 return;
2098
2099 for (i = 0; i < ab->num_radios; i++) {
2100 pdev = &ab->pdevs[i];
2101 ar = pdev->ar;
2102
2103 reinit_completion(&ab->htc_suspend);
2104
2105 ret = ath11k_wmi_pdev_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
2106 pdev->pdev_id);
2107 if (ret) {
2108 ath11k_warn(ab, "could not suspend target :%d\n", ret);
2109 /* pointless to try other pdevs */
2110 return;
2111 }
2112
2113 time_left = wait_for_completion_timeout(&ab->htc_suspend, 3 * HZ);
2114
2115 if (!time_left) {
2116 ath11k_warn(ab, "suspend timed out - target pause event never came\n");
2117 /* pointless to try other pdevs */
2118 return;
2119 }
2120 }
2121 }
2122
ath11k_core_pdev_destroy(struct ath11k_base * ab)2123 static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
2124 {
2125 ath11k_cfr_deinit(ab);
2126 ath11k_spectral_deinit(ab);
2127 ath11k_thermal_unregister(ab);
2128 ath11k_mac_unregister(ab);
2129 ath11k_core_pdev_suspend_target(ab);
2130 ath11k_hif_irq_disable(ab);
2131 ath11k_dp_pdev_free(ab);
2132 ath11k_debugfs_pdev_destroy(ab);
2133 }
2134
ath11k_core_start(struct ath11k_base * ab)2135 static int ath11k_core_start(struct ath11k_base *ab)
2136 {
2137 int ret;
2138
2139 ret = ath11k_wmi_attach(ab);
2140 if (ret) {
2141 ath11k_err(ab, "failed to attach wmi: %d\n", ret);
2142 return ret;
2143 }
2144
2145 ret = ath11k_htc_init(ab);
2146 if (ret) {
2147 ath11k_err(ab, "failed to init htc: %d\n", ret);
2148 goto err_wmi_detach;
2149 }
2150
2151 ret = ath11k_hif_start(ab);
2152 if (ret) {
2153 ath11k_err(ab, "failed to start HIF: %d\n", ret);
2154 goto err_wmi_detach;
2155 }
2156
2157 ret = ath11k_htc_wait_target(&ab->htc);
2158 if (ret) {
2159 ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
2160 goto err_hif_stop;
2161 }
2162
2163 ret = ath11k_dp_htt_connect(&ab->dp);
2164 if (ret) {
2165 ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
2166 goto err_hif_stop;
2167 }
2168
2169 ret = ath11k_wmi_connect(ab);
2170 if (ret) {
2171 ath11k_err(ab, "failed to connect wmi: %d\n", ret);
2172 goto err_hif_stop;
2173 }
2174
2175 ret = ath11k_htc_start(&ab->htc);
2176 if (ret) {
2177 ath11k_err(ab, "failed to start HTC: %d\n", ret);
2178 goto err_hif_stop;
2179 }
2180
2181 ret = ath11k_wmi_wait_for_service_ready(ab);
2182 if (ret) {
2183 ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
2184 ret);
2185 goto err_hif_stop;
2186 }
2187
2188 ret = ath11k_mac_allocate(ab);
2189 if (ret) {
2190 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
2191 ret);
2192 goto err_hif_stop;
2193 }
2194
2195 ath11k_dp_pdev_pre_alloc(ab);
2196
2197 ret = ath11k_dp_pdev_reo_setup(ab);
2198 if (ret) {
2199 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
2200 goto err_mac_destroy;
2201 }
2202
2203 ret = ath11k_wmi_cmd_init(ab);
2204 if (ret) {
2205 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
2206 goto err_reo_cleanup;
2207 }
2208
2209 ret = ath11k_wmi_wait_for_unified_ready(ab);
2210 if (ret) {
2211 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
2212 ret);
2213 goto err_reo_cleanup;
2214 }
2215
2216 /* put hardware to DBS mode */
2217 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxdma_per_pdev > 1) {
2218 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
2219 if (ret) {
2220 ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
2221 goto err_hif_stop;
2222 }
2223 }
2224
2225 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
2226 if (ret) {
2227 ath11k_err(ab, "failed to send htt version request message: %d\n",
2228 ret);
2229 goto err_reo_cleanup;
2230 }
2231
2232 return 0;
2233
2234 err_reo_cleanup:
2235 ath11k_dp_pdev_reo_cleanup(ab);
2236 err_mac_destroy:
2237 ath11k_mac_destroy(ab);
2238 err_hif_stop:
2239 ath11k_hif_stop(ab);
2240 err_wmi_detach:
2241 ath11k_wmi_detach(ab);
2242
2243 return ret;
2244 }
2245
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)2246 static int ath11k_core_start_firmware(struct ath11k_base *ab,
2247 enum ath11k_firmware_mode mode)
2248 {
2249 int ret;
2250
2251 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
2252 &ab->qmi.ce_cfg.shadow_reg_v2_len);
2253
2254 ret = ath11k_qmi_firmware_start(ab, mode);
2255 if (ret) {
2256 ath11k_err(ab, "failed to send firmware start: %d\n", ret);
2257 return ret;
2258 }
2259
2260 return ret;
2261 }
2262
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)2263 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
2264 {
2265 int ret;
2266
2267 switch (ath11k_crypto_mode) {
2268 case ATH11K_CRYPT_MODE_SW:
2269 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
2270 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
2271 break;
2272 case ATH11K_CRYPT_MODE_HW:
2273 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
2274 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
2275 break;
2276 default:
2277 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
2278 return -EINVAL;
2279 }
2280
2281 ret = ath11k_core_start_firmware(ab, ab->fw_mode);
2282 if (ret) {
2283 ath11k_err(ab, "failed to start firmware: %d\n", ret);
2284 return ret;
2285 }
2286
2287 ret = ath11k_ce_init_pipes(ab);
2288 if (ret) {
2289 ath11k_err(ab, "failed to initialize CE: %d\n", ret);
2290 goto err_firmware_stop;
2291 }
2292
2293 ret = ath11k_dp_alloc(ab);
2294 if (ret) {
2295 ath11k_err(ab, "failed to init DP: %d\n", ret);
2296 goto err_firmware_stop;
2297 }
2298
2299 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
2300 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
2301
2302 mutex_lock(&ab->core_lock);
2303 ret = ath11k_core_start(ab);
2304 if (ret) {
2305 ath11k_err(ab, "failed to start core: %d\n", ret);
2306 goto err_dp_free;
2307 }
2308
2309 ret = ath11k_core_pdev_create(ab);
2310 if (ret) {
2311 ath11k_err(ab, "failed to create pdev core: %d\n", ret);
2312 goto err_core_stop;
2313 }
2314 ath11k_hif_irq_enable(ab);
2315 mutex_unlock(&ab->core_lock);
2316
2317 return 0;
2318
2319 err_core_stop:
2320 ath11k_core_stop(ab);
2321 ath11k_mac_destroy(ab);
2322 err_dp_free:
2323 ath11k_dp_free(ab);
2324 mutex_unlock(&ab->core_lock);
2325 err_firmware_stop:
2326 ath11k_qmi_firmware_stop(ab);
2327
2328 return ret;
2329 }
2330
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)2331 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
2332 {
2333 int ret;
2334
2335 mutex_lock(&ab->core_lock);
2336 ath11k_thermal_unregister(ab);
2337 ath11k_dp_pdev_free(ab);
2338 ath11k_cfr_deinit(ab);
2339 ath11k_spectral_deinit(ab);
2340 ath11k_ce_cleanup_pipes(ab);
2341 ath11k_wmi_detach(ab);
2342 ath11k_dp_pdev_reo_cleanup(ab);
2343 mutex_unlock(&ab->core_lock);
2344
2345 ath11k_dp_free(ab);
2346 ath11k_hal_srng_clear(ab);
2347
2348 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
2349
2350 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
2351
2352 ret = ath11k_core_qmi_firmware_ready(ab);
2353 if (ret)
2354 goto err_hal_srng_deinit;
2355
2356 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
2357
2358 return 0;
2359
2360 err_hal_srng_deinit:
2361 ath11k_hal_srng_deinit(ab);
2362 return ret;
2363 }
2364
ath11k_core_halt(struct ath11k * ar)2365 void ath11k_core_halt(struct ath11k *ar)
2366 {
2367 struct ath11k_base *ab = ar->ab;
2368 struct list_head *pos, *n;
2369
2370 lockdep_assert_held(&ar->conf_mutex);
2371
2372 ar->num_created_vdevs = 0;
2373 ar->allocated_vdev_map = 0;
2374
2375 ath11k_mac_scan_finish(ar);
2376 ath11k_mac_peer_cleanup_all(ar);
2377 cancel_delayed_work_sync(&ar->scan.timeout);
2378 cancel_work_sync(&ar->channel_update_work);
2379 cancel_work_sync(&ar->regd_update_work);
2380 cancel_work_sync(&ab->update_11d_work);
2381
2382 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
2383 synchronize_rcu();
2384
2385 spin_lock_bh(&ar->data_lock);
2386 list_for_each_safe(pos, n, &ar->arvifs)
2387 list_del_init(pos);
2388 spin_unlock_bh(&ar->data_lock);
2389
2390 idr_init(&ar->txmgmt_idr);
2391 }
2392
ath11k_update_11d(struct work_struct * work)2393 static void ath11k_update_11d(struct work_struct *work)
2394 {
2395 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
2396 struct ath11k *ar;
2397 struct ath11k_pdev *pdev;
2398 int ret, i;
2399
2400 for (i = 0; i < ab->num_radios; i++) {
2401 pdev = &ab->pdevs[i];
2402 ar = pdev->ar;
2403
2404 spin_lock_bh(&ab->base_lock);
2405 memcpy(&ar->alpha2, &ab->new_alpha2, 2);
2406 spin_unlock_bh(&ab->base_lock);
2407
2408 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c for pdev %d\n",
2409 ar->alpha2[0], ar->alpha2[1], i);
2410
2411 ret = ath11k_reg_set_cc(ar);
2412 if (ret)
2413 ath11k_warn(ar->ab,
2414 "pdev id %d failed set current country code: %d\n",
2415 i, ret);
2416 }
2417 }
2418
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)2419 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
2420 {
2421 struct ath11k *ar;
2422 struct ath11k_pdev *pdev;
2423 int i;
2424
2425 spin_lock_bh(&ab->base_lock);
2426 ab->stats.fw_crash_counter++;
2427 spin_unlock_bh(&ab->base_lock);
2428
2429 for (i = 0; i < ab->num_radios; i++) {
2430 pdev = &ab->pdevs[i];
2431 ar = pdev->ar;
2432 if (!ar || ar->state == ATH11K_STATE_OFF ||
2433 ar->state == ATH11K_STATE_FTM)
2434 continue;
2435
2436 ieee80211_stop_queues(ar->hw);
2437 ath11k_mac_drain_tx(ar);
2438 ar->state_11d = ATH11K_11D_IDLE;
2439 complete(&ar->completed_11d_scan);
2440 complete(&ar->scan.started);
2441 complete_all(&ar->scan.completed);
2442 complete(&ar->scan.on_channel);
2443 complete(&ar->peer_assoc_done);
2444 complete(&ar->peer_delete_done);
2445 complete(&ar->install_key_done);
2446 complete(&ar->vdev_setup_done);
2447 complete(&ar->vdev_delete_done);
2448 complete(&ar->bss_survey_done);
2449 complete(&ar->thermal.wmi_sync);
2450
2451 wake_up(&ar->dp.tx_empty_waitq);
2452 idr_for_each(&ar->txmgmt_idr,
2453 ath11k_mac_tx_mgmt_pending_free, ar);
2454 idr_destroy(&ar->txmgmt_idr);
2455 wake_up(&ar->txmgmt_empty_waitq);
2456
2457 ar->monitor_vdev_id = -1;
2458 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags);
2459 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
2460 }
2461
2462 wake_up(&ab->wmi_ab.tx_credits_wq);
2463 wake_up(&ab->peer_mapping_wq);
2464
2465 reinit_completion(&ab->driver_recovery);
2466 }
2467
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)2468 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
2469 {
2470 struct ath11k *ar;
2471 struct ath11k_pdev *pdev;
2472 int i;
2473
2474 for (i = 0; i < ab->num_radios; i++) {
2475 pdev = &ab->pdevs[i];
2476 ar = pdev->ar;
2477 if (!ar || ar->state == ATH11K_STATE_OFF)
2478 continue;
2479
2480 mutex_lock(&ar->conf_mutex);
2481
2482 switch (ar->state) {
2483 case ATH11K_STATE_ON:
2484 ar->state = ATH11K_STATE_RESTARTING;
2485 ath11k_core_halt(ar);
2486 ieee80211_restart_hw(ar->hw);
2487 break;
2488 case ATH11K_STATE_OFF:
2489 ath11k_warn(ab,
2490 "cannot restart radio %d that hasn't been started\n",
2491 i);
2492 break;
2493 case ATH11K_STATE_RESTARTING:
2494 break;
2495 case ATH11K_STATE_RESTARTED:
2496 ar->state = ATH11K_STATE_WEDGED;
2497 fallthrough;
2498 case ATH11K_STATE_WEDGED:
2499 ath11k_warn(ab,
2500 "device is wedged, will not restart radio %d\n", i);
2501 break;
2502 case ATH11K_STATE_FTM:
2503 ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
2504 "fw mode reset done radio %d\n", i);
2505 break;
2506 }
2507
2508 mutex_unlock(&ar->conf_mutex);
2509 }
2510 complete(&ab->driver_recovery);
2511 }
2512
ath11k_core_restart(struct work_struct * work)2513 static void ath11k_core_restart(struct work_struct *work)
2514 {
2515 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
2516 int ret;
2517
2518 ret = ath11k_core_reconfigure_on_crash(ab);
2519 if (ret) {
2520 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
2521 return;
2522 }
2523
2524 if (ab->is_reset)
2525 complete_all(&ab->reconfigure_complete);
2526
2527 if (!ab->is_reset)
2528 ath11k_core_post_reconfigure_recovery(ab);
2529
2530 complete(&ab->restart_completed);
2531 }
2532
ath11k_core_reset(struct work_struct * work)2533 static void ath11k_core_reset(struct work_struct *work)
2534 {
2535 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
2536 int reset_count, fail_cont_count;
2537 long time_left;
2538
2539 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
2540 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
2541 return;
2542 }
2543
2544 /* Sometimes the recovery will fail and then the next all recovery fail,
2545 * this is to avoid infinite recovery since it can not recovery success.
2546 */
2547 fail_cont_count = atomic_read(&ab->fail_cont_count);
2548
2549 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
2550 return;
2551
2552 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
2553 time_before(jiffies, ab->reset_fail_timeout))
2554 return;
2555
2556 reset_count = atomic_inc_return(&ab->reset_count);
2557
2558 if (reset_count > 1) {
2559 /* Sometimes it happened another reset worker before the previous one
2560 * completed, then the second reset worker will destroy the previous one,
2561 * thus below is to avoid that.
2562 */
2563 ath11k_warn(ab, "already resetting count %d\n", reset_count);
2564
2565 reinit_completion(&ab->reset_complete);
2566 time_left = wait_for_completion_timeout(&ab->reset_complete,
2567 ATH11K_RESET_TIMEOUT_HZ);
2568
2569 if (time_left) {
2570 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
2571 atomic_dec(&ab->reset_count);
2572 return;
2573 }
2574
2575 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
2576 /* Record the continuous recovery fail count when recovery failed*/
2577 atomic_inc(&ab->fail_cont_count);
2578 }
2579
2580 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
2581
2582 ab->is_reset = true;
2583 atomic_set(&ab->recovery_count, 0);
2584 reinit_completion(&ab->recovery_start);
2585 atomic_set(&ab->recovery_start_count, 0);
2586
2587 ath11k_coredump_collect(ab);
2588 ath11k_core_pre_reconfigure_recovery(ab);
2589
2590 reinit_completion(&ab->reconfigure_complete);
2591 ath11k_core_post_reconfigure_recovery(ab);
2592
2593 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
2594
2595 time_left = wait_for_completion_timeout(&ab->recovery_start,
2596 ATH11K_RECOVER_START_TIMEOUT_HZ);
2597
2598 ath11k_hif_irq_disable(ab);
2599 ath11k_hif_ce_irq_disable(ab);
2600
2601 ath11k_hif_power_down(ab, false);
2602 ath11k_hif_power_up(ab);
2603
2604 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
2605 }
2606
ath11k_init_hw_params(struct ath11k_base * ab)2607 static int ath11k_init_hw_params(struct ath11k_base *ab)
2608 {
2609 const struct ath11k_hw_params *hw_params = NULL;
2610 int i;
2611
2612 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
2613 hw_params = &ath11k_hw_params[i];
2614
2615 if (hw_params->hw_rev == ab->hw_rev)
2616 break;
2617 }
2618
2619 if (i == ARRAY_SIZE(ath11k_hw_params)) {
2620 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
2621 return -EINVAL;
2622 }
2623
2624 ab->hw_params = *hw_params;
2625
2626 ath11k_info(ab, "%s\n", ab->hw_params.name);
2627
2628 return 0;
2629 }
2630
ath11k_core_pre_init(struct ath11k_base * ab)2631 int ath11k_core_pre_init(struct ath11k_base *ab)
2632 {
2633 int ret;
2634
2635 ret = ath11k_init_hw_params(ab);
2636 if (ret) {
2637 ath11k_err(ab, "failed to get hw params: %d\n", ret);
2638 return ret;
2639 }
2640
2641 ret = ath11k_fw_pre_init(ab);
2642 if (ret) {
2643 ath11k_err(ab, "failed to pre init firmware: %d", ret);
2644 return ret;
2645 }
2646
2647 return 0;
2648 }
2649 EXPORT_SYMBOL(ath11k_core_pre_init);
2650
ath11k_core_pm_notify(struct notifier_block * nb,unsigned long action,void * nouse)2651 static int ath11k_core_pm_notify(struct notifier_block *nb,
2652 unsigned long action, void *nouse)
2653 {
2654 struct ath11k_base *ab = container_of(nb, struct ath11k_base,
2655 pm_nb);
2656
2657 switch (action) {
2658 case PM_SUSPEND_PREPARE:
2659 ab->actual_pm_policy = ab->pm_policy;
2660 break;
2661 case PM_HIBERNATION_PREPARE:
2662 ab->actual_pm_policy = ATH11K_PM_DEFAULT;
2663 break;
2664 default:
2665 break;
2666 }
2667
2668 return NOTIFY_OK;
2669 }
2670
ath11k_core_pm_notifier_register(struct ath11k_base * ab)2671 static int ath11k_core_pm_notifier_register(struct ath11k_base *ab)
2672 {
2673 ab->pm_nb.notifier_call = ath11k_core_pm_notify;
2674 return register_pm_notifier(&ab->pm_nb);
2675 }
2676
ath11k_core_pm_notifier_unregister(struct ath11k_base * ab)2677 void ath11k_core_pm_notifier_unregister(struct ath11k_base *ab)
2678 {
2679 int ret;
2680
2681 ret = unregister_pm_notifier(&ab->pm_nb);
2682 if (ret)
2683 /* just warn here, there is nothing can be done in fail case */
2684 ath11k_warn(ab, "failed to unregister PM notifier %d\n", ret);
2685 }
2686 EXPORT_SYMBOL(ath11k_core_pm_notifier_unregister);
2687
ath11k_core_init(struct ath11k_base * ab)2688 int ath11k_core_init(struct ath11k_base *ab)
2689 {
2690 const struct dmi_system_id *dmi_id;
2691 int ret;
2692
2693 dmi_id = dmi_first_match(ath11k_pm_quirk_table);
2694 if (dmi_id)
2695 ab->pm_policy = (kernel_ulong_t)dmi_id->driver_data;
2696 else
2697 ab->pm_policy = ATH11K_PM_DEFAULT;
2698
2699 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pm policy %u\n", ab->pm_policy);
2700
2701 ret = ath11k_core_pm_notifier_register(ab);
2702 if (ret) {
2703 ath11k_err(ab, "failed to register PM notifier: %d\n", ret);
2704 return ret;
2705 }
2706
2707 ret = ath11k_core_soc_create(ab);
2708 if (ret) {
2709 ath11k_err(ab, "failed to create soc core: %d\n", ret);
2710 goto err_unregister_pm_notifier;
2711 }
2712
2713 return 0;
2714
2715 err_unregister_pm_notifier:
2716 ath11k_core_pm_notifier_unregister(ab);
2717
2718 return ret;
2719 }
2720 EXPORT_SYMBOL(ath11k_core_init);
2721
ath11k_core_deinit(struct ath11k_base * ab)2722 void ath11k_core_deinit(struct ath11k_base *ab)
2723 {
2724 mutex_lock(&ab->core_lock);
2725
2726 ath11k_core_pdev_destroy(ab);
2727 ath11k_core_stop(ab);
2728
2729 mutex_unlock(&ab->core_lock);
2730
2731 ath11k_hif_power_down(ab, false);
2732 ath11k_mac_destroy(ab);
2733 ath11k_core_soc_destroy(ab);
2734 ath11k_core_pm_notifier_unregister(ab);
2735 }
2736 EXPORT_SYMBOL(ath11k_core_deinit);
2737
ath11k_core_free(struct ath11k_base * ab)2738 void ath11k_core_free(struct ath11k_base *ab)
2739 {
2740 destroy_workqueue(ab->workqueue_aux);
2741 destroy_workqueue(ab->workqueue);
2742
2743 kfree(ab);
2744 }
2745 EXPORT_SYMBOL(ath11k_core_free);
2746
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)2747 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
2748 enum ath11k_bus bus)
2749 {
2750 struct ath11k_base *ab;
2751
2752 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2753 if (!ab)
2754 return NULL;
2755
2756 init_completion(&ab->driver_recovery);
2757
2758 ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2759 if (!ab->workqueue)
2760 goto err_sc_free;
2761
2762 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
2763 if (!ab->workqueue_aux)
2764 goto err_free_wq;
2765
2766 mutex_init(&ab->core_lock);
2767 mutex_init(&ab->tbl_mtx_lock);
2768 spin_lock_init(&ab->base_lock);
2769 mutex_init(&ab->vdev_id_11d_lock);
2770 init_completion(&ab->reset_complete);
2771 init_completion(&ab->reconfigure_complete);
2772 init_completion(&ab->recovery_start);
2773
2774 INIT_LIST_HEAD(&ab->peers);
2775 init_waitqueue_head(&ab->peer_mapping_wq);
2776 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2777 init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2778 INIT_WORK(&ab->restart_work, ath11k_core_restart);
2779 INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
2780 INIT_WORK(&ab->reset_work, ath11k_core_reset);
2781 INIT_WORK(&ab->dump_work, ath11k_coredump_upload);
2782 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2783 init_completion(&ab->htc_suspend);
2784 init_completion(&ab->wow.wakeup_completed);
2785 init_completion(&ab->restart_completed);
2786
2787 ab->dev = dev;
2788 ab->hif.bus = bus;
2789
2790 return ab;
2791
2792 err_free_wq:
2793 destroy_workqueue(ab->workqueue);
2794 err_sc_free:
2795 kfree(ab);
2796 return NULL;
2797 }
2798 EXPORT_SYMBOL(ath11k_core_alloc);
2799
2800 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2801 MODULE_LICENSE("Dual BSD/GPL");
2802