| /linux/drivers/clk/mediatek/ |
| H A D | clk-mux.c | 35 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); in mtk_clk_mux_enable_setclr() local
38 if (mux->lock) in mtk_clk_mux_enable_setclr()
39 spin_lock_irqsave(mux->lock, flags); in mtk_clk_mux_enable_setclr()
41 __acquire(mux->lock); in mtk_clk_mux_enable_setclr()
43 regmap_write(mux->regmap, mux->data->clr_ofs, in mtk_clk_mux_enable_setclr()
44 BIT(mux->data->gate_shift)); in mtk_clk_mux_enable_setclr()
51 if (mux->reparent && mux->data->upd_shift >= 0) { in mtk_clk_mux_enable_setclr()
52 regmap_write(mux->regmap, mux->data->upd_ofs, in mtk_clk_mux_enable_setclr()
53 BIT(mux->data->upd_shift)); in mtk_clk_mux_enable_setclr()
54 mux->reparent = false; in mtk_clk_mux_enable_setclr()
[all …]
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| H A D | clk-cpumux.c | 33 struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw); in clk_cpumux_get_parent() local
36 regmap_read(mux->regmap, mux->reg, &val); in clk_cpumux_get_parent()
38 val >>= mux->shift; in clk_cpumux_get_parent()
39 val &= mux->mask; in clk_cpumux_get_parent()
46 struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw); in clk_cpumux_set_parent() local
49 val = index << mux->shift; in clk_cpumux_set_parent()
50 mask = mux->mask << mux->shift; in clk_cpumux_set_parent()
52 return regmap_update_bits(mux->regmap, mux->reg, mask, val); in clk_cpumux_set_parent()
62 mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux, in mtk_clk_register_cpumux() argument
73 init.name = mux->name; in mtk_clk_register_cpumux()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_ring_mux.c | 43 static inline struct amdgpu_mux_entry *amdgpu_ring_mux_sw_entry(struct amdgpu_ring_mux *mux, in amdgpu_ring_mux_sw_entry() argument
46 return ring->entry_index < mux->ring_entry_size ? in amdgpu_ring_mux_sw_entry()
47 &mux->ring_entry[ring->entry_index] : NULL; in amdgpu_ring_mux_sw_entry()
51 static void amdgpu_ring_mux_copy_pkt_from_sw_ring(struct amdgpu_ring_mux *mux, in amdgpu_ring_mux_copy_pkt_from_sw_ring() argument
56 struct amdgpu_ring *real_ring = mux->real_ring; in amdgpu_ring_mux_copy_pkt_from_sw_ring()
76 static void amdgpu_mux_resubmit_chunks(struct amdgpu_ring_mux *mux) in amdgpu_mux_resubmit_chunks() argument
84 if (!mux->s_resubmit) in amdgpu_mux_resubmit_chunks()
87 for (i = 0; i < mux->num_ring_entries; i++) { in amdgpu_mux_resubmit_chunks()
88 if (mux->ring_entry[i].ring->hw_prio <= AMDGPU_RING_PRIO_DEFAULT) { in amdgpu_mux_resubmit_chunks()
89 e = &mux->ring_entry[i]; in amdgpu_mux_resubmit_chunks()
[all …]
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| /linux/drivers/clk/ti/ |
| H A D | mux.c | 23 struct clk_omap_mux *mux = to_clk_omap_mux(hw); in ti_clk_mux_get_parent() local
34 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
35 val &= mux->mask; in ti_clk_mux_get_parent()
37 if (mux->table) { in ti_clk_mux_get_parent()
41 if (mux->table[i] == val) in ti_clk_mux_get_parent()
46 if (val && (mux->flags & CLK_MUX_INDEX_BIT)) in ti_clk_mux_get_parent()
49 if (val && (mux->flags & CLK_MUX_INDEX_ONE)) in ti_clk_mux_get_parent()
60 struct clk_omap_mux *mux = to_clk_omap_mux(hw); in ti_clk_mux_set_parent() local
63 if (mux->table) { in ti_clk_mux_set_parent()
64 index = mux->table[index]; in ti_clk_mux_set_parent()
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| /linux/drivers/iio/multiplexer/ |
| H A D | iio-mux.c | 29 struct mux { struct
39 static int iio_mux_select(struct mux *mux, int idx) in iio_mux_select() argument
41 struct mux_child *child = &mux->child[idx]; in iio_mux_select()
42 struct iio_chan_spec const *chan = &mux->chan[idx]; in iio_mux_select()
46 ret = mux_control_select_delay(mux->control, chan->channel, in iio_mux_select()
47 mux->delay_us); in iio_mux_select()
49 mux->cached_state = -1; in iio_mux_select()
53 if (mux->cached_state == chan->channel) in iio_mux_select()
66 ret = iio_write_channel_ext_info(mux->parent, attr, in iio_mux_select()
71 mux_control_deselect(mux->control); in iio_mux_select()
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| /linux/drivers/clk/ |
| H A D | clk-mux.c | 27 static inline u32 clk_mux_readl(struct clk_mux *mux) in clk_mux_readl() argument
29 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_readl()
30 return ioread32be(mux->reg); in clk_mux_readl()
32 return readl(mux->reg); in clk_mux_readl()
35 static inline void clk_mux_writel(struct clk_mux *mux, u32 val) in clk_mux_writel() argument
37 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_writel()
38 iowrite32be(val, mux->reg); in clk_mux_writel()
40 writel(val, mux->reg); in clk_mux_writel()
90 struct clk_mux *mux = to_clk_mux(hw); in clk_mux_get_parent() local
93 val = clk_mux_readl(mux) >> mux->shift; in clk_mux_get_parent()
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| /linux/arch/arm/boot/dts/nuvoton/ |
| H A D | nuvoton-wpcm450.dtsi | 172 smb3_pins: mux-smb3 {
177 smb4_pins: mux-smb4 {
182 smb5_pins: mux-smb5 {
187 scs1_pins: mux-scs1 {
192 scs2_pins: mux-scs2 {
197 scs3_pins: mux-scs3 {
202 smb0_pins: mux-smb0 {
207 smb1_pins: mux-smb1 {
212 smb2_pins: mux-smb2 {
217 bsp_pins: mux-bsp {
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| /linux/drivers/clk/qcom/ |
| H A D | clk-krait.c | 23 static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) in __krait_mux_set_sel() argument
30 regval = krait_get_l2_indirect_reg(mux->offset); in __krait_mux_set_sel()
33 if (mux->disable_sec_src_gating) { in __krait_mux_set_sel()
35 krait_set_l2_indirect_reg(mux->offset, regval); in __krait_mux_set_sel()
38 regval &= ~(mux->mask << mux->shift); in __krait_mux_set_sel()
39 regval |= (sel & mux->mask) << mux->shift; in __krait_mux_set_sel()
40 if (mux->lpl) { in __krait_mux_set_sel()
41 regval &= ~(mux->mask << (mux->shift + LPL_SHIFT)); in __krait_mux_set_sel()
42 regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); in __krait_mux_set_sel()
44 krait_set_l2_indirect_reg(mux->offset, regval); in __krait_mux_set_sel()
[all …]
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| H A D | krait-cc.c | 48 struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk, in krait_notifier_cb() local
52 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); in krait_notifier_cb()
53 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
54 mux->reparent = false; in krait_notifier_cb()
61 if (!mux->reparent) in krait_notifier_cb()
62 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
63 mux->old_index); in krait_notifier_cb()
70 struct krait_mux_clk *mux) in krait_notifier_register() argument
74 mux->clk_nb.notifier_call = krait_notifier_cb; in krait_notifier_register()
75 ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb); in krait_notifier_register()
[all …]
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| H A D | clk-regmap-mux.c | 20 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); in mux_get_parent() local
22 unsigned int mask = GENMASK(mux->width - 1, 0); in mux_get_parent()
25 regmap_read(clkr->regmap, mux->reg, &val); in mux_get_parent()
27 val >>= mux->shift; in mux_get_parent()
30 if (mux->parent_map) in mux_get_parent()
31 return qcom_find_cfg_index(hw, mux->parent_map, val); in mux_get_parent()
38 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); in mux_set_parent() local
40 unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); in mux_set_parent()
43 if (mux->parent_map) in mux_set_parent()
44 index = mux->parent_map[index].cfg; in mux_set_parent()
[all …]
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| /linux/net/kcm/ |
| H A D | kcmsock.c | 59 struct kcm_mux *mux = psock->mux; in kcm_abort_tx_psock() local
63 spin_lock_bh(&mux->lock); in kcm_abort_tx_psock()
66 spin_unlock_bh(&mux->lock); in kcm_abort_tx_psock()
87 spin_unlock_bh(&mux->lock); in kcm_abort_tx_psock()
94 static void kcm_update_rx_mux_stats(struct kcm_mux *mux, in kcm_update_rx_mux_stats() argument
97 STRP_STATS_ADD(mux->stats.rx_bytes, in kcm_update_rx_mux_stats()
100 mux->stats.rx_msgs += in kcm_update_rx_mux_stats()
106 static void kcm_update_tx_mux_stats(struct kcm_mux *mux, in kcm_update_tx_mux_stats() argument
109 KCM_STATS_ADD(mux->stats.tx_bytes, in kcm_update_tx_mux_stats()
111 mux->stats.tx_msgs += in kcm_update_tx_mux_stats()
[all …]
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| /linux/drivers/clk/uniphier/ |
| H A D | clk-uniphier-mux.c | 25 struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw); in uniphier_clk_mux_set_parent() local
27 return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], in uniphier_clk_mux_set_parent()
28 mux->vals[index]); in uniphier_clk_mux_set_parent()
33 struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw); in uniphier_clk_mux_get_parent() local
39 ret = regmap_read(mux->regmap, mux->reg, &val); in uniphier_clk_mux_get_parent()
44 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_mux_get_parent()
61 struct uniphier_clk_mux *mux; in uniphier_clk_register_mux() local
65 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); in uniphier_clk_register_mux()
66 if (!mux) in uniphier_clk_register_mux()
75 mux->regmap = regmap; in uniphier_clk_register_mux()
[all …]
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-cv18xx-ip.c | 396 struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw); in mux_enable() local
398 return cv1800_clk_setbit(&mux->common, &mux->gate); in mux_enable()
403 struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw); in mux_disable() local
405 cv1800_clk_clearbit(&mux->common, &mux->gate); in mux_disable()
410 struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw); in mux_is_enabled() local
412 return cv1800_clk_checkbit(&mux->common, &mux->gate); in mux_is_enabled()
418 struct cv1800_clk_mux *mux = data; in mux_round_rate() local
420 return div_helper_round_rate(&mux->div, &mux->common.hw, parent, in mux_round_rate()
427 struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw); in mux_determine_rate() local
429 return mux_helper_determine_rate(&mux->common, req, in mux_determine_rate()
[all …]
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| /linux/drivers/dma/ |
| H A D | lpc32xx-dmamux.c | 80 struct lpc32xx_dmamux *mux = route_data; in lpc32xx_dmamux_release() local
83 mux->signal, mux->muxval ? mux->name_sel1 : mux->name_sel1); in lpc32xx_dmamux_release()
87 mux->busy = false; in lpc32xx_dmamux_release()
97 struct lpc32xx_dmamux *mux = NULL; in lpc32xx_dmamux_reserve() local
107 mux = &lpc32xx_muxes[i]; in lpc32xx_dmamux_reserve()
111 if (!mux) { in lpc32xx_dmamux_reserve()
131 if (mux->busy) { in lpc32xx_dmamux_reserve()
134 mux->signal, mux->muxval ? mux->name_sel1 : mux->name_sel1); in lpc32xx_dmamux_reserve()
139 mux->busy = true; in lpc32xx_dmamux_reserve()
140 mux->muxval = dma_spec->args[2] ? BIT(mux->bit) : 0; in lpc32xx_dmamux_reserve()
[all …]
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| /linux/Documentation/devicetree/bindings/mux/ |
| H A D | adi,adg792a.txt | 5 - #mux-control-cells : <0> if parallel (the three muxes are bound together
6 with a single mux controller controlling all three muxes), or <1> if
7 not (one mux controller for each mux).
8 * Standard mux-controller bindings as described in mux-controller.yaml
18 - idle-state : if present, array of states that the mux controllers will have
27 * Three independent mux controllers (of which one is used).
28 * Mux 0 is disconnected when idle, mux 1 idles in the previously
29 * selected state and mux 2 idles with signal B.
32 mux: mux-controller@50 {
35 #mux-control-cells = <1>;
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| /linux/drivers/clk/imx/ |
| H A D | clk-fixup-mux.c | 23 struct clk_mux mux; member
30 struct clk_mux *mux = to_clk_mux(hw); in to_clk_fixup_mux() local
32 return container_of(mux, struct clk_fixup_mux, mux); in to_clk_fixup_mux()
39 return fixup_mux->ops->get_parent(&fixup_mux->mux.hw); in clk_fixup_mux_get_parent()
45 struct clk_mux *mux = to_clk_mux(hw); in clk_fixup_mux_set_parent() local
49 spin_lock_irqsave(mux->lock, flags); in clk_fixup_mux_set_parent()
51 val = readl(mux->reg); in clk_fixup_mux_set_parent()
52 val &= ~(mux->mask << mux->shift); in clk_fixup_mux_set_parent()
53 val |= index << mux->shift; in clk_fixup_mux_set_parent()
55 writel(val, mux->reg); in clk_fixup_mux_set_parent()
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| H A D | clk-composite-93.c | 156 struct clk_mux *mux = to_clk_mux(hw); in imx93_clk_composite_mux_set_parent() local
157 u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); in imx93_clk_composite_mux_set_parent()
162 if (mux->lock) in imx93_clk_composite_mux_set_parent()
163 spin_lock_irqsave(mux->lock, flags); in imx93_clk_composite_mux_set_parent()
165 reg = readl(mux->reg); in imx93_clk_composite_mux_set_parent()
166 reg &= ~(mux->mask << mux->shift); in imx93_clk_composite_mux_set_parent()
167 val = val << mux->shift; in imx93_clk_composite_mux_set_parent()
169 writel(reg, mux->reg); in imx93_clk_composite_mux_set_parent()
171 ret = imx93_clk_composite_wait_ready(hw, mux->reg); in imx93_clk_composite_mux_set_parent()
173 if (mux->lock) in imx93_clk_composite_mux_set_parent()
[all …]
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| /linux/Documentation/i2c/ |
| H A D | i2c-topology.rst | 10 1. A mux may be needed on the bus to prevent address collisions.
25 I2C transfers, and all adapters with a parent are part of an "i2c-mux"
28 Depending of the particular mux driver, something happens when there is
29 an I2C transfer on one of its child adapters. The mux driver can
30 obviously operate a mux, but it can also do arbitration with an external
31 bus master or open a gate. The mux driver has two operations for this,
40 mux-locked or parent-locked muxes.
52 stages of the transaction. This has the benefit that the mux driver
61 .--------. | mux- |-----| dev D1 |
63 '--------' | | mux M1 |--. .--------.
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| /linux/drivers/clk/sprd/ |
| H A D | mux.c | 15 const struct sprd_mux_ssel *mux) in sprd_mux_helper_get_parent() argument
23 parent = reg >> mux->shift; in sprd_mux_helper_get_parent()
24 parent &= (1 << mux->width) - 1; in sprd_mux_helper_get_parent()
26 if (!mux->table) in sprd_mux_helper_get_parent()
32 if (parent >= mux->table[i] && parent < mux->table[i + 1]) in sprd_mux_helper_get_parent()
43 return sprd_mux_helper_get_parent(&cm->common, &cm->mux); in sprd_mux_get_parent()
47 const struct sprd_mux_ssel *mux, in sprd_mux_helper_set_parent() argument
52 if (mux->table) in sprd_mux_helper_set_parent()
53 index = mux->table[index]; in sprd_mux_helper_set_parent()
56 reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift); in sprd_mux_helper_set_parent()
[all …]
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| /linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-gxbb.dtsi | 98 reg-names = "mux", "pull", "gpio";
105 mux {
113 mux {
122 mux {
130 mux {
139 mux {
147 mux {
156 mux {
164 mux {
172 mux {
[all …]
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| H A D | meson-gxl.dtsi | 156 reg-names = "mux", "pull", "gpio";
163 mux {
171 mux {
180 mux {
188 mux {
196 mux {
205 mux {
213 mux {
222 mux {
230 mux {
[all …]
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| H A D | amlogic-c3.dtsi | 177 reg-names = "mux", "gpio";
184 mux {
194 mux {
204 mux {
214 mux {
224 mux {
234 mux {
244 mux {
254 mux {
264 mux {
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| /linux/drivers/clk/tegra/ |
| H A D | clk-super.c | 36 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); in clk_super_get_parent() local
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
47 super_state_to_src_shift(mux, SUPER_STATE_IDLE) : in clk_super_get_parent()
48 super_state_to_src_shift(mux, SUPER_STATE_RUN); in clk_super_get_parent()
50 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
57 (source == mux->pllx_index)) in clk_super_get_parent()
58 source = mux->div2_index; in clk_super_get_parent()
65 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); in clk_super_set_parent() local
71 if (mux->lock) in clk_super_set_parent()
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| /linux/arch/arm/boot/dts/microchip/ |
| H A D | at91-natte.dtsi | 11 mux: mux-controller { label
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
24 mux-controls = <&mux>;
31 batv-mux {
32 compatible = "io-channel-mux";
35 mux-controls = <&mux>;
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-muxgrf.c | 23 struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw); in rockchip_muxgrf_get_parent() local
24 unsigned int mask = GENMASK(mux->width - 1, 0); in rockchip_muxgrf_get_parent()
27 regmap_read(mux->regmap, mux->reg, &val); in rockchip_muxgrf_get_parent()
29 val >>= mux->shift; in rockchip_muxgrf_get_parent()
37 struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw); in rockchip_muxgrf_set_parent() local
38 unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); in rockchip_muxgrf_set_parent()
42 val <<= mux->shift; in rockchip_muxgrf_set_parent()
44 if (mux->flags & CLK_MUX_HIWORD_MASK) in rockchip_muxgrf_set_parent()
45 return regmap_write(mux->regmap, mux->reg, val | (mask << 16)); in rockchip_muxgrf_set_parent()
47 return regmap_update_bits(mux->regmap, mux->reg, mask, val); in rockchip_muxgrf_set_parent()
|