Lines Matching refs:mux
36 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); in clk_super_get_parent() local
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
47 super_state_to_src_shift(mux, SUPER_STATE_IDLE) : in clk_super_get_parent()
48 super_state_to_src_shift(mux, SUPER_STATE_RUN); in clk_super_get_parent()
50 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
57 (source == mux->pllx_index)) in clk_super_get_parent()
58 source = mux->div2_index; in clk_super_get_parent()
65 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); in clk_super_set_parent() local
71 if (mux->lock) in clk_super_set_parent()
72 spin_lock_irqsave(mux->lock, flags); in clk_super_set_parent()
74 val = readl_relaxed(mux->reg); in clk_super_set_parent()
79 super_state_to_src_shift(mux, SUPER_STATE_IDLE) : in clk_super_set_parent()
80 super_state_to_src_shift(mux, SUPER_STATE_RUN); in clk_super_set_parent()
87 if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) || in clk_super_set_parent()
88 (index == mux->pllx_index))) { in clk_super_set_parent()
90 if ((parent_index == mux->div2_index) || in clk_super_set_parent()
91 (parent_index == mux->pllx_index)) { in clk_super_set_parent()
97 writel_relaxed(val, mux->reg); in clk_super_set_parent()
100 if (index == mux->div2_index) in clk_super_set_parent()
101 index = mux->pllx_index; in clk_super_set_parent()
105 if ((mux->flags & TEGRA210_CPU_CLK) && in clk_super_set_parent()
109 val &= ~((super_state_to_src_mask(mux)) << shift); in clk_super_set_parent()
110 val |= (index & (super_state_to_src_mask(mux))) << shift; in clk_super_set_parent()
112 writel_relaxed(val, mux->reg); in clk_super_set_parent()
116 if ((mux->flags & TEGRA210_CPU_CLK) && in clk_super_set_parent()
121 if (mux->lock) in clk_super_set_parent()
122 spin_unlock_irqrestore(mux->lock, flags); in clk_super_set_parent()