/linux/drivers/clk/ |
H A D | clk-multiplier.c | 15 static inline u32 clk_mult_readl(struct clk_multiplier *mult) in clk_mult_readl() argument 17 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_readl() 18 return ioread32be(mult->reg); in clk_mult_readl() 20 return readl(mult->reg); in clk_mult_readl() 23 static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val) in clk_mult_writel() argument 25 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_writel() 26 iowrite32be(val, mult->reg); in clk_mult_writel() 28 writel(val, mult->reg); in clk_mult_writel() 31 static unsigned long __get_mult(struct clk_multiplier *mult, in __get_mult() argument 35 if (mult->flags & CLK_MULTIPLIER_ROUND_CLOSEST) in __get_mult() [all …]
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H A D | clk-fixed-factor.c | 28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate() 41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate() 45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate() 95 unsigned long flags, unsigned int mult, unsigned int div, in __clk_hw_register_fixed_factor() argument 116 fix->mult = mult; in __clk_hw_register_fixed_factor() 165 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_index() argument 170 flags, mult, div, 0, 0, true); in devm_clk_hw_register_fixed_factor_index() 189 unsigned long flags, unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_parent_hw() argument 194 &pdata, flags, mult, div, 0, 0, true); in devm_clk_hw_register_fixed_factor_parent_hw() 200 unsigned long flags, unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor_parent_hw() argument [all …]
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H A D | clk-eyeq.c | 95 unsigned int mult; member 138 static void eqc_pll_downshift_factors(unsigned long *mult, unsigned long *div) in eqc_pll_downshift_factors() argument 144 static_assert(sizeof_field(struct clk_fixed_factor, mult) == sizeof(unsigned int)); in eqc_pll_downshift_factors() 148 if (*mult <= UINT_MAX && *div <= UINT_MAX) in eqc_pll_downshift_factors() 156 biggest = max(*mult, *div); in eqc_pll_downshift_factors() 159 *mult >>= shift; in eqc_pll_downshift_factors() 163 static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult, in eqc_pll_parse_registers() argument 169 *mult = 1; in eqc_pll_parse_registers() 178 *mult = FIELD_GET(PCSR0_INTIN, r0); in eqc_pll_parse_registers() 186 *mult = *mult * (1ULL << 20) + FIELD_GET(PCSR1_FRAC_IN, r1); in eqc_pll_parse_registers() [all …]
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/linux/drivers/clk/sunxi-ng/ |
H A D | ccu_mult.c | 14 unsigned long mult, min, max; member 18 struct _ccu_mult *mult) in ccu_mult_find_best() argument 23 if (_mult < mult->min) in ccu_mult_find_best() 24 _mult = mult->min; in ccu_mult_find_best() 26 if (_mult > mult->max) in ccu_mult_find_best() 27 _mult = mult->max; in ccu_mult_find_best() 29 mult->mult = _mult; in ccu_mult_find_best() 41 _cm.min = cm->mult.min; in ccu_mult_round_rate() 43 if (cm->mult.max) in ccu_mult_round_rate() 44 _cm.max = cm->mult.max; in ccu_mult_round_rate() [all …]
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/linux/drivers/clk/renesas/ |
H A D | rcar-gen3-cpg.c | 56 unsigned int mult; in cpg_pll_clk_recalc_rate() local 60 mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; in cpg_pll_clk_recalc_rate() 62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate() 69 unsigned int min_mult, max_mult, mult; in cpg_pll_clk_determine_rate() local 78 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate() 79 mult = clamp(mult, min_mult, max_mult); in cpg_pll_clk_determine_rate() 81 req->rate = prate * mult; in cpg_pll_clk_determine_rate() 89 unsigned int mult, i; in cpg_pll_clk_set_rate() local 92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); in cpg_pll_clk_set_rate() 93 mult = clamp(mult, 1U, 128U); in cpg_pll_clk_set_rate() [all …]
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H A D | rcar-gen2-cpg.c | 57 unsigned int mult; in cpg_z_clk_recalc_rate() local 61 mult = 32 - val; in cpg_z_clk_recalc_rate() 63 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate() 70 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local 77 mult = div64_ul(req->rate * 32ULL, prate); in cpg_z_clk_determine_rate() 78 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate() 80 req->rate = div_u64((u64)prate * mult, 32); in cpg_z_clk_determine_rate() 88 unsigned int mult; in cpg_z_clk_set_rate() local 92 mult = div64_ul(rate * 32ULL, parent_rate); in cpg_z_clk_set_rate() 93 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate() [all …]
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H A D | clk-sh73a0.c | 78 unsigned int mult = 1; in sh73a0_cpg_register_clock() local 109 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock() 113 mult *= 2; in sh73a0_cpg_register_clock() 121 mult = readl(dsi_reg); in sh73a0_cpg_register_clock() 122 if (!(mult & 0x8000)) in sh73a0_cpg_register_clock() 123 mult = 1; in sh73a0_cpg_register_clock() 125 mult = (mult & 0x3f) + 1; in sh73a0_cpg_register_clock() 151 mult, div); in sh73a0_cpg_register_clock()
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H A D | rcar-gen4-cpg.c | 282 unsigned int mult; in cpg_z_clk_recalc_rate() local 286 mult = 32 - (val >> __ffs(zclk->mask)); in cpg_z_clk_recalc_rate() 288 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, in cpg_z_clk_recalc_rate() 296 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local 316 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); in cpg_z_clk_determine_rate() 317 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate() 319 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); in cpg_z_clk_determine_rate() 327 unsigned int mult; in cpg_z_clk_set_rate() local 330 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, in cpg_z_clk_set_rate() 332 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate() [all …]
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H A D | clk-rz.c | 51 unsigned mult; in rz_cpg_register_clock() local 58 mult = cpg_mode ? (32 / 4) : 30; in rz_cpg_register_clock() 60 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1); in rz_cpg_register_clock() 78 mult = frqcr_tab[val]; in rz_cpg_register_clock() 79 return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3); in rz_cpg_register_clock()
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H A D | clk-r8a73a4.c | 64 unsigned int mult = 1; in r8a73a4_cpg_register_clock() local 95 mult = ((value >> 24) & 0x7f) + 1; in r8a73a4_cpg_register_clock() 103 mult = ((value >> 24) & 0x7f) + 1; in r8a73a4_cpg_register_clock() 148 mult = ((value >> 24) & 0x7f) + 1; in r8a73a4_cpg_register_clock() 158 mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f); in r8a73a4_cpg_register_clock() 177 mult, div); in r8a73a4_cpg_register_clock()
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/linux/drivers/clk/imx/ |
H A D | clk-pllv4.c | 82 u32 mult, mfn, mfd; in clk_pllv4_recalc_rate() local 85 mult = readl_relaxed(pll->base + pll->cfg_offset); in clk_pllv4_recalc_rate() 86 mult &= BM_PLL_MULT; in clk_pllv4_recalc_rate() 87 mult >>= BP_PLL_MULT; in clk_pllv4_recalc_rate() 95 return (parent_rate * mult) + (u32)temp64; in clk_pllv4_recalc_rate() 107 u32 mult; in clk_pllv4_round_rate() local 112 mult = temp64; in clk_pllv4_round_rate() 113 if (mult >= pllv4_mult_range[1] && in clk_pllv4_round_rate() 114 mult <= pllv4_mult_range[0]) { in clk_pllv4_round_rate() 115 round_rate = parent_rate * mult; in clk_pllv4_round_rate() [all …]
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/linux/drivers/clk/mvebu/ |
H A D | orion.c | 60 int *mult, int *div) in mv88f5181_get_clk_ratio() argument 65 *mult = 1; in mv88f5181_get_clk_ratio() 68 *mult = 1; in mv88f5181_get_clk_ratio() 71 *mult = 0; in mv88f5181_get_clk_ratio() 128 int *mult, int *div) in mv88f5182_get_clk_ratio() argument 133 *mult = 1; in mv88f5182_get_clk_ratio() 136 *mult = 1; in mv88f5182_get_clk_ratio() 139 *mult = 0; in mv88f5182_get_clk_ratio() 185 int *mult, int *div) in mv88f5281_get_clk_ratio() argument 190 *mult = 1; in mv88f5281_get_clk_ratio() [all …]
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H A D | mv98dx3236.c | 118 void __iomem *sar, int id, int *mult, int *div) in mv98dx3236_get_clk_ratio() argument 126 *mult = mv98dx4251_cpu_ddr_ratios[opt][0]; in mv98dx3236_get_clk_ratio() 129 *mult = mv98dx3236_cpu_ddr_ratios[opt][0]; in mv98dx3236_get_clk_ratio() 135 *mult = mv98dx4251_cpu_mpll_ratios[opt][0]; in mv98dx3236_get_clk_ratio() 138 *mult = mv98dx3236_cpu_mpll_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
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/linux/drivers/clk/sunxi/ |
H A D | clk-sun4i-pll3.c | 24 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local 48 mult = kzalloc(sizeof(*mult), GFP_KERNEL); in sun4i_a10_pll3_setup() 49 if (!mult) in sun4i_a10_pll3_setup() 52 mult->reg = reg; in sun4i_a10_pll3_setup() 53 mult->shift = SUN4I_A10_PLL3_DIV_SHIFT; in sun4i_a10_pll3_setup() 54 mult->width = SUN4I_A10_PLL3_DIV_WIDTH; in sun4i_a10_pll3_setup() 55 mult->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup() 60 &mult->hw, &clk_multiplier_ops, in sun4i_a10_pll3_setup() 80 kfree(mult); in sun4i_a10_pll3_setup()
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H A D | clk-a10-pll2.c | 44 struct clk_multiplier *mult; in sun4i_pll2_setup() local 83 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); in sun4i_pll2_setup() 84 if (!mult) in sun4i_pll2_setup() 87 mult->reg = reg; in sun4i_pll2_setup() 88 mult->shift = SUN4I_PLL2_N_SHIFT; in sun4i_pll2_setup() 89 mult->width = 7; in sun4i_pll2_setup() 90 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | in sun4i_pll2_setup() 92 mult->lock = &sun4i_a10_pll2_lock; in sun4i_pll2_setup() 98 &mult->hw, &clk_multiplier_ops, in sun4i_pll2_setup() 168 kfree(mult); in sun4i_pll2_setup()
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/linux/drivers/iio/common/inv_sensors/ |
H A D | inv_sensors_timestamp.c | 52 ts->mult = chip->init_period / chip->clock_period; in inv_sensors_timestamp_init() 63 uint32_t mult; in inv_sensors_timestamp_update_odr() local 69 mult = period / ts->chip.clock_period; in inv_sensors_timestamp_update_odr() 70 if (mult != ts->mult) in inv_sensors_timestamp_update_odr() 71 ts->new_mult = mult; in inv_sensors_timestamp_update_odr() 86 period_min = ts->min_period * ts->mult; in inv_validate_period() 87 period_max = ts->max_period * ts->mult; in inv_validate_period() 103 new_chip_period = period / ts->mult; in inv_update_chip_period() 105 ts->period = ts->mult * ts->chip_period.val; in inv_update_chip_period() 112 const int64_t period_min = ts->min_period * ts->mult; in inv_align_timestamp_it() [all …]
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/linux/arch/arm/mach-omap2/ |
H A D | clkt2xxx_dpllcore.c | 113 u32 cur_rate, low, mult, div, valid_rate, done_rate; in omap2_reprogram_dpllcore() local 119 mult = omap2xxx_cm_get_core_clk_src(); in omap2_reprogram_dpllcore() 121 if ((rate == (cur_rate / 2)) && (mult == 2)) { in omap2_reprogram_dpllcore() 123 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { in omap2_reprogram_dpllcore() 130 if (mult == 1) in omap2_reprogram_dpllcore() 148 mult = ((rate / 2) / 1000000); in omap2_reprogram_dpllcore() 152 mult = (rate / 1000000); in omap2_reprogram_dpllcore() 156 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); in omap2_reprogram_dpllcore()
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/linux/sound/core/ |
H A D | pcm_timer.c | 21 unsigned long rate, mult, fsize, l, post; in snd_pcm_timer_resolution_change() local 24 mult = 1000000000; in snd_pcm_timer_resolution_change() 28 l = gcd(mult, rate); in snd_pcm_timer_resolution_change() 29 mult /= l; in snd_pcm_timer_resolution_change() 38 while ((mult * fsize) / fsize != mult) { in snd_pcm_timer_resolution_change() 39 mult /= 2; in snd_pcm_timer_resolution_change() 49 runtime->timer_resolution = (mult * fsize / rate) * post; in snd_pcm_timer_resolution_change()
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap36xx-omap3430es2plus-clocks.dtsi | 51 clock-mult = <1>; 83 clock-mult = <1>; 107 clock-mult = <1>; 115 clock-mult = <1>; 123 clock-mult = <1>; 131 clock-mult = <1>; 139 clock-mult = <1>; 147 clock-mult = <1>; 155 clock-mult = <1>; 163 clock-mult = <1>; [all …]
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H A D | am33xx-clocks.dtsi | 22 clock-mult = <1>; 31 clock-mult = <1>; 40 clock-mult = <1>; 49 clock-mult = <1>; 58 clock-mult = <1>; 67 clock-mult = <1>; 76 clock-mult = <1>; 85 clock-mult = <1>; 94 clock-mult = <1>; 103 clock-mult = <1>; [all …]
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/linux/sound/soc/codecs/ |
H A D | es8311.c | 328 unsigned int mult; member 383 unsigned int mult = coeff->mult; in es8311_cmp_adj_mclk_coeff() local 394 mult = coeff->mclk / mclk_freq; in es8311_cmp_adj_mclk_coeff() 395 if (mult == 2 || mult == 4 || mult == 8) { in es8311_cmp_adj_mclk_coeff() 396 mult *= coeff->mult; in es8311_cmp_adj_mclk_coeff() 397 if (mult <= 8) in es8311_cmp_adj_mclk_coeff() 406 out_coeff->mult = mult; in es8311_cmp_adj_mclk_coeff() 562 unsigned int mult; in es8311_hw_params() local 564 switch (coeff.mult) { in es8311_hw_params() 566 mult = 0; in es8311_hw_params() [all …]
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/linux/drivers/thermal/broadcom/ |
H A D | brcmstb_thermal.c | 107 unsigned int mult; member 124 int mult = priv->temp_params->mult; in avs_tmon_code_to_temp() local 126 return (offset - (int)((code & AVS_TMON_TEMP_MASK) * mult)); in avs_tmon_code_to_temp() 139 int mult = priv->temp_params->mult; in avs_tmon_temp_to_code() local 148 return (u32)(DIV_ROUND_UP(offset - temp, mult)); in avs_tmon_temp_to_code() 150 return (u32)((offset - temp) / mult); in avs_tmon_temp_to_code() 295 .mult = 557, 306 .mult = 487,
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/linux/drivers/net/ethernet/pensando/ionic/ |
H A D | ionic_phc.c | 311 ctx->cmd.lif_setphc.mult = cpu_to_le32(phc->cc.mult); in ionic_setphc_cmd() 342 phc->cc.mult = adj; in ionic_phc_adjfine() 524 u64 delay, diff, mult; in ionic_lif_alloc_phc() local 544 phc->cc.mult = le32_to_cpu(ionic->ident.dev.hwstamp_mult); in ionic_lif_alloc_phc() 547 if (!phc->cc.mult) { in ionic_lif_alloc_phc() 550 phc->cc.mult); in ionic_lif_alloc_phc() 557 phc->cc.mask, phc->cc.mult, phc->cc.shift); in ionic_lif_alloc_phc() 567 diff = U64_MAX / phc->cc.mult / 2; in ionic_lif_alloc_phc() 571 diff = DIV_ROUND_UP(diff, phc->cc.mult); in ionic_lif_alloc_phc() 602 mult = U64_MAX / 2 / max(diff / 2, SCALED_PPM); in ionic_lif_alloc_phc() [all …]
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/linux/drivers/clk/davinci/ |
H A D | pll.c | 119 u32 mult; in davinci_pll_recalc_rate() local 121 mult = readl(pll->base + PLLM) & pll->pllm_mask; in davinci_pll_recalc_rate() 122 rate *= mult + 1; in davinci_pll_recalc_rate() 135 u32 mult; in davinci_pll_determine_rate() local 142 mult = rate / parent_rate; in davinci_pll_determine_rate() 143 best_rate = parent_rate * mult; in davinci_pll_determine_rate() 150 if (mult < pll->pllm_min || mult > pll->pllm_max) in davinci_pll_determine_rate() 161 for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { in davinci_pll_determine_rate() 162 parent_rate = clk_hw_round_rate(parent, rate / mult); in davinci_pll_determine_rate() 163 r = parent_rate * mult; in davinci_pll_determine_rate() [all …]
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/linux/drivers/cpufreq/ |
H A D | longhaul.c | 108 static unsigned int calc_speed(int mult) in calc_speed() argument 111 khz = (mult/10)*fsb; in calc_speed() 112 if (mult%10) in calc_speed() 250 int speed, mult; in longhaul_setstate() local 260 mult = mults[mults_index & 0x1f]; in longhaul_setstate() 261 if (mult == -1) in longhaul_setstate() 264 speed = calc_speed(mult); in longhaul_setstate() 276 fsb, mult/10, mult%10, print_speed(speed/1000)); in longhaul_setstate() 407 static int guess_fsb(int mult) in guess_fsb() argument 415 f_max = ((speeds[i] * mult) + 50) / 100; in guess_fsb() [all …]
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