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Searched refs:mul_mask (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/clk/at91/
H A Dclk-pll.c21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
90 ((pll->mul & layout->mul_mask) << layout->mul_shift)); in clk_pll_prepare()
362 .mul_mask = 0x7FF,
368 .mul_mask = 0xFF,
374 .mul_mask = 0x3F,
380 .mul_mask = 0x7F,
H A Dsam9x7.c148 .mul_mask = GENMASK(31, 24),
157 .mul_mask = GENMASK(31, 24),
H A Dpmc.h59 u32 mul_mask; member
H A Dsam9x60.c56 .mul_mask = GENMASK(31, 24),
H A Dclk-sam9x60-pll.c99 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; in sam9x60_frac_pll_set()
269 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; in sam9x60_frac_pll_set_rate_chg()
H A Dsama7g5.c69 .mul_mask = GENMASK(31, 24),
H A Dsama7d65.c74 .mul_mask = GENMASK(31, 24),
/linux/drivers/clk/actions/
H A Dowl-pll.c28 return mul & mul_mask(pll_hw); in owl_pll_calculate_mul()
100 val &= mul_mask(pll_hw); in owl_pll_recalc_rate()
112 val &= mul_mask(pll_hw); in owl_pll_recalc_rate()
184 reg &= ~mul_mask(pll_hw); in owl_pll_set_rate()
H A Dowl-pll.h99 #define mul_mask(m) ((1 << ((m)->width)) - 1) macro
/linux/drivers/clk/
H A Dclk-k230.c70 .mul_mask = _mul_mask, \
97 .mul_mask = _mul_mask, \
186 u32 mul_mask; member
2021 & rate_self->mul_mask; in k230_clk_get_rate_mul()
2054 & rate_self->mul_mask; in k230_clk_get_rate_mul_div()
2230 mul_reg &= ~(rate_self->mul_mask << rate_self->mul_shift); in k230_clk_set_rate_mul()
2231 mul_reg |= ((mul - 1) & rate_self->mul_mask) << (rate_self->mul_shift); in k230_clk_set_rate_mul()
2298 mul_reg &= ~(rate_self->mul_mask << rate_self->mul_shift); in k230_clk_set_rate_mul_div()
2299 mul_reg |= ((mul - 1) & rate_self->mul_mask) << (rate_self->mul_shift); in k230_clk_set_rate_mul_div()