Searched refs:mpllb (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_cx0_phy.c | 774 .mpllb = { 0x50a8, /* mpllb cfg0 */
799 .mpllb = { 0x308c, /* mpllb cfg0 */
824 .mpllb = { 0x108c, /* mpllb cfg0 */
849 .mpllb = { 0x10d2, /* mpllb cfg0 */
899 .mpllb = { 0x015f, /* mpllb cfg0 */
963 .mpllb = { 0x50e1,
988 .mpllb = { 0x50fd,
1013 .mpllb = { 0x30a8,
1038 .mpllb = { 0x30e1,
1063 .mpllb = { 0x10af,
[all …]
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| H A D | intel_dpll_mgr.h | 257 u16 mpllb[11]; member
278 struct intel_mpllb_state mpllb; member
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| H A D | intel_snps_phy.c | 1814 crtc_state->dpll_hw_state.mpllb = *tables[i]; in intel_mpllb_calc_state()
1826 const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb; in intel_mpllb_enable()
2004 const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb; in intel_mpllb_state_verify()
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| H A D | intel_ddi.c | 4043 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4044 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
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