| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| H A D | dcn20_mpc.c | 509 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc2_init_mpcc() argument
511 mpcc->mpcc_id = mpcc_inst; in mpc2_init_mpcc()
545 int mpcc_inst, in mpc2_read_mpcc_state() argument
550 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc2_read_mpcc_state()
551 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc2_read_mpcc_state()
552 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); in mpc2_read_mpcc_state()
553 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, in mpc2_read_mpcc_state()
557 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, in mpc2_read_mpcc_state()
561 REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_inst], in mpc2_read_mpcc_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_mpc.c | 62 static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc201_init_mpcc() argument
64 mpcc->mpcc_id = mpcc_inst; in mpc201_init_mpcc()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | pg_cntl.h | 45 void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on);
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| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 348 unsigned int mpcc_inst, bool power_on) in pg_cntl35_mpcc_pg_control() argument
353 if (mpcc_inst < MAX_PIPES) in pg_cntl35_mpcc_pg_control()
354 pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on; in pg_cntl35_mpcc_pg_control()
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| H A D | dcn35_pg_cntl.h | 179 unsigned int mpcc_inst, bool power_on);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 90 unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; in dcn401_program_gamut_remap()
3088 hwss_add_opp_set_mpcc_disconnect_pending(seq_state, opp, pipe_ctx->plane_res.mpcc_inst, true); in dcn401_plane_atomic_disconnect_sequence()
3198 int mpcc_inst = -1; in dcn401_program_all_writeback_pipes_in_tree_sequence() local
3209 mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn401_program_all_writeback_pipes_in_tree_sequence()
3214 if (mpcc_inst == -1) { in dcn401_program_all_writeback_pipes_in_tree_sequence()
3230 dcn401_enable_writeback_sequence(dc, wb_info, context, mpcc_inst, seq_state); in dcn401_program_all_writeback_pipes_in_tree_sequence()
3243 int mpcc_inst, in dcn401_enable_writeback_sequence() argument
3268 hwss_add_mpc_set_dwb_mux(seq_state, dc->res_pool->mpc, wb_info->dwb_pipe_inst, mpcc_inst); in dcn401_enable_writeback_sequence()
3835 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) in get_hubp_by_inst() argument
3840 if (res_pool->hubps[i]->inst == mpcc_inst) in get_hubp_by_inst()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 315 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
323 res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_init_hw()
411 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_plane_atomic_disconnect()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2162 int mpcc_inst; in hwss_wait_for_outstanding_hw_updates() local
2183 mpcc_inst = hubp->inst; in hwss_wait_for_outstanding_hw_updates()
2187 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) { in hwss_wait_for_outstanding_hw_updates()
2188 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); in hwss_wait_for_outstanding_hw_updates()
2189 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; in hwss_wait_for_outstanding_hw_updates()
2525 int mpcc_inst = params->opp_set_mpcc_disconnect_pending_params.mpcc_inst; in hwss_opp_set_mpcc_disconnect_pending() local
2528 opp->mpcc_disconnect_pending[mpcc_inst] = pending; in hwss_opp_set_mpcc_disconnect_pending()
3184 struct output_pixel_processor *opp, int mpcc_inst, bool pending) in hwss_add_opp_set_mpcc_disconnect_pending() argument
3189 …->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.mpcc_inst = mpcc_inst; in hwss_add_opp_set_mpcc_disconnect_pending()
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| H A D | dc_resource.c | 2618 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_split_pipe()
3794 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst; in acquire_resource_from_hw_enabled_state()
3799 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); in acquire_resource_from_hw_enabled_state()
3802 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = in acquire_resource_from_hw_enabled_state()
3806 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = in acquire_resource_from_hw_enabled_state()
3938 pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in acquire_otg_master_pipe_for_stream()
5560 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 420 int mpcc_inst; member
1720 struct output_pixel_processor *opp, int mpcc_inst, bool pending);
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 1966 int mpcc_inst);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 3200 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn20_fpga_init_hw()
3210 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn20_fpga_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 3604 uint8_t mpcc_inst; member
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