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Searched refs:mpcc_inst (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.c509 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc2_init_mpcc() argument
511 mpcc->mpcc_id = mpcc_inst; in mpc2_init_mpcc()
545 int mpcc_inst, in mpc2_read_mpcc_state() argument
550 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc2_read_mpcc_state()
551 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc2_read_mpcc_state()
552 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); in mpc2_read_mpcc_state()
553 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, in mpc2_read_mpcc_state()
557 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, in mpc2_read_mpcc_state()
561 REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_inst], in mpc2_read_mpcc_state()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c62 static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc201_init_mpcc() argument
64 mpcc->mpcc_id = mpcc_inst; in mpc201_init_mpcc()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c440 ASSERT(wb_info->mpcc_inst >= 0); in dcn30_set_writeback()
441 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
447 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
462 wb_info->mpcc_inst); in dcn30_update_writeback()
540 wb_info->mpcc_inst); in dcn30_enable_writeback()
604 wb_info.mpcc_inst = -1; in dcn30_program_all_writeback_pipes_in_tree()
612 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
617 if (wb_info.mpcc_inst == -1) { in dcn30_program_all_writeback_pipes_in_tree()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dpg_cntl.h45 void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on);
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.c348 unsigned int mpcc_inst, bool power_on) in pg_cntl35_mpcc_pg_control() argument
353 if (mpcc_inst < MAX_PIPES) in pg_cntl35_mpcc_pg_control()
354 pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on; in pg_cntl35_mpcc_pg_control()
H A Ddcn35_pg_cntl.h179 unsigned int mpcc_inst, bool power_on);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c91 unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; in dcn401_program_gamut_remap()
3099 hwss_add_opp_set_mpcc_disconnect_pending(seq_state, opp, pipe_ctx->plane_res.mpcc_inst, true); in dcn401_plane_atomic_disconnect_sequence()
3209 int mpcc_inst = -1; in dcn401_program_all_writeback_pipes_in_tree_sequence() local
3220 mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn401_program_all_writeback_pipes_in_tree_sequence()
3225 if (mpcc_inst == -1) { in dcn401_program_all_writeback_pipes_in_tree_sequence()
3241 dcn401_enable_writeback_sequence(dc, wb_info, context, mpcc_inst, seq_state); in dcn401_program_all_writeback_pipes_in_tree_sequence()
3254 int mpcc_inst, in dcn401_enable_writeback_sequence() argument
3279 hwss_add_mpc_set_dwb_mux(seq_state, dc->res_pool->mpc, wb_info->dwb_pipe_inst, mpcc_inst); in dcn401_enable_writeback_sequence()
3846 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) in get_hubp_by_inst() argument
3851 if (res_pool->hubps[i]->inst == mpcc_inst) in get_hubp_by_inst()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c318 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
326 res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_init_hw()
414 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_plane_atomic_disconnect()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_psr.c341 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c1464 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_plane_atomic_disconnect()
1675 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn10_init_pipes()
1682 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_init_pipes()
3546 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) in get_hubp_by_inst() argument
3551 if (res_pool->hubps[i]->inst == mpcc_inst) in get_hubp_by_inst()
3564 int mpcc_inst; in dcn10_wait_for_mpcc_disconnect() local
3573 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { in dcn10_wait_for_mpcc_disconnect()
3574 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { in dcn10_wait_for_mpcc_disconnect()
3575 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
3579 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c2164 int mpcc_inst; in hwss_wait_for_outstanding_hw_updates() local
2185 mpcc_inst = hubp->inst; in hwss_wait_for_outstanding_hw_updates()
2189 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) { in hwss_wait_for_outstanding_hw_updates()
2190 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); in hwss_wait_for_outstanding_hw_updates()
2191 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; in hwss_wait_for_outstanding_hw_updates()
2527 int mpcc_inst = params->opp_set_mpcc_disconnect_pending_params.mpcc_inst; in hwss_opp_set_mpcc_disconnect_pending() local
2530 opp->mpcc_disconnect_pending[mpcc_inst] = pending; in hwss_opp_set_mpcc_disconnect_pending()
3186 struct output_pixel_processor *opp, int mpcc_inst, bool pending) in hwss_add_opp_set_mpcc_disconnect_pending() argument
3191 …->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.mpcc_inst = mpcc_inst; in hwss_add_opp_set_mpcc_disconnect_pending()
H A Ddc_resource.c2618 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_split_pipe()
3794 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst; in acquire_resource_from_hw_enabled_state()
3799 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); in acquire_resource_from_hw_enabled_state()
3802 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = in acquire_resource_from_hw_enabled_state()
3806 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = in acquire_resource_from_hw_enabled_state()
3938 pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in acquire_otg_master_pipe_for_stream()
5560 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_stream.h106 int mpcc_inst; member
H A Ddc.h1989 int mpcc_inst);
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h384 uint8_t mpcc_inst; member
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c727 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn35_init_pipes()
734 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn35_init_pipes()
958 update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false; in dcn35_calc_blocks_to_gate()
1050 update_state->pg_pipe_res_update[j][new_pipe->plane_res.mpcc_inst] = true; in dcn35_calc_blocks_to_ungate()
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h420 int mpcc_inst; member
1733 struct output_pixel_processor *opp, int mpcc_inst, bool pending);
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1496 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1552 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in dcn20_split_stream_for_mpc()
2168 sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst; in dcn20_acquire_free_pipe_for_layer()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c2764 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2823 free_pipe->plane_res.mpcc_inst = in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2856 free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst; in dcn32_acquire_free_pipe_as_secondary_opp_head()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c1025 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn201_acquire_free_pipe_for_layer()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c1106 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_free_pipe_for_layer()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c3194 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn20_fpga_init_hw()
3204 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn20_fpga_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c541 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in split_stream_across_pipes()
/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h3656 uint8_t mpcc_inst; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1537 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()