Searched refs:mpcc_id (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/ |
| H A D | dcn50_hwseq.c | 420 int mpcc_id; in dcn50_update_mpcc_sequence() local
460 mpcc_id = hubp->inst; in dcn50_update_mpcc_sequence()
467 hwss_add_mpc_update_blending(seq_state, mpc, blnd_cfg, mpcc_id); in dcn50_update_mpcc_sequence()
470 hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id); in dcn50_update_mpcc_sequence()
475 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); in dcn50_update_mpcc_sequence()
483 hwss_add_mpc_assert_idle_mpcc(seq_state, mpc, mpcc_id); in dcn50_update_mpcc_sequence()
487 …s_add_mpc_insert_plane(seq_state, mpc, mpc_tree_params, blnd_cfg, NULL, NULL, hubp->inst, mpcc_id); in dcn50_update_mpcc_sequence()
490 hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id); in dcn50_update_mpcc_sequence()
494 hubp->mpcc_id = mpcc_id; in dcn50_update_mpcc_sequence()
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| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| H A D | dcn20_mpc.h | 280 int mpcc_id);
306 int mpcc_id,
310 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
311 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 261 int mpcc_id, const struct dc_stream_state *stream) in dcn30_set_mpc_shaper_3dlut() argument
289 if (mpcc_id_projected != mpcc_id) in dcn30_set_mpc_shaper_3dlut()
294 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, in dcn30_set_mpc_shaper_3dlut()
311 mpc->funcs->release_rmu(mpc, mpcc_id); in dcn30_set_mpc_shaper_3dlut()
362 int mpcc_id = params->mpcc_id; in dcn30_program_gamut_remap() local
396 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust); in dcn30_program_gamut_remap()
403 int mpcc_id = otf_params->mpcc_id; in dcn30_set_output_transfer_func() local
413 ret = dcn30_set_mpc_shaper_3dlut(dpp, mpc, mpcc_id, stream); in dcn30_set_output_transfer_func()
430 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); in dcn30_set_output_transfer_func()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_mpc.c | 64 mpcc->mpcc_id = mpcc_inst; in mpc201_init_mpcc()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.c | 153 hubp201->base.mpcc_id = 0xf; in dcn201_hubp_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1768 int mpcc_id, in dcn32_acquire_post_bldn_3dlut() argument
1778 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { in dcn32_acquire_post_bldn_3dlut()
1779 *lut = pool->mpc_lut[mpcc_id]; in dcn32_acquire_post_bldn_3dlut()
1780 *shaper = pool->mpc_shaper[mpcc_id]; in dcn32_acquire_post_bldn_3dlut()
1781 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; in dcn32_acquire_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1592 int mpcc_id, in dcn30_acquire_post_bldn_3dlut() argument
1613 state->bits.mpc_rmu0_mux = mpcc_id; in dcn30_acquire_post_bldn_3dlut()
1615 state->bits.mpc_rmu1_mux = mpcc_id; in dcn30_acquire_post_bldn_3dlut()
1617 state->bits.mpc_rmu2_mux = mpcc_id; in dcn30_acquire_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 838 .mpcc_id = pipes->plane_res.mpcc_inst, in dc_stream_set_gamut_remap()
1379 dc->hwss.update_visual_confirm_color(dc, pipe, pipe->plane_res.hubp->mpcc_id); in dc_stream_adjust_vmin_vmax()
2647 int mpcc_id = 0; in dc_acquire_release_mpc_3dlut() local
2655 mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; in dc_acquire_release_mpc_3dlut()
2664 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper); in dc_acquire_release_mpc_3dlut()
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