| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 319 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
430 int mpcc_id, dpp_id; in dcn201_update_mpcc() local
485 mpcc_id = dpp_id; in dcn201_update_mpcc()
489 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); in dcn201_update_mpcc()
490 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); in dcn201_update_mpcc()
511 dc->res_pool->mpc, mpcc_id); in dcn201_update_mpcc()
514 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); in dcn201_update_mpcc()
521 mpcc_id); in dcn201_update_mpcc()
525 hubp->mpcc_id = mpcc_id; in dcn201_update_mpcc()
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| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| H A D | dcn20_mpc.h | 280 int mpcc_id);
306 int mpcc_id,
310 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
311 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 871 …block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_r… in hwss_build_fast_sequence()
877 …block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_re… in hwss_build_fast_sequence()
1011 params->update_visual_confirm_params.mpcc_id); in hwss_execute_sequence()
1481 int mpcc_id) in hwss_add_mpc_update_visual_confirm() argument
1486 seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.mpcc_id = mpcc_id; in hwss_add_mpc_update_visual_confirm()
1497 int mpcc_id, in hwss_add_mpc_power_on_mpc_mem_pwr() argument
1502 seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = mpcc_id; in hwss_add_mpc_power_on_mpc_mem_pwr()
1993 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id; in hwss_power_on_mpc_mem_pwr() local
1997 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on); in hwss_power_on_mpc_mem_pwr()
2679 int mpcc_id = params->mpc_set_dwb_mux_params.mpcc_id; in hwss_mpc_set_dwb_mux() local
[all …]
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| H A D | dc_stream.c | 523 pipe_ctx->plane_res.hubp->mpcc_id); in dc_stream_program_cursor_position()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 95 unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; in dcn401_program_gamut_remap() local
111 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust); in dcn401_program_gamut_remap()
117 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust); in dcn401_program_gamut_remap()
133 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust); in dcn401_program_gamut_remap()
394 int mpcc_id = hubp->inst; in dcn401_set_mcm_luts() local
404 mpc->funcs->get_lut_mode(mpc, MCM_LUT_1DLUT, mpcc_id, &lut_enable, &lut_bank_a); in dcn401_set_mcm_luts()
406 mpc->funcs->get_lut_mode(mpc, MCM_LUT_SHAPER, mpcc_id, &lut_enable, &lut_bank_a); in dcn401_set_mcm_luts()
409 mpc->funcs->get_lut_mode(mpc, MCM_LUT_3DLUT, mpcc_id, &lut_enable, &lut_bank_a); in dcn401_set_mcm_luts()
418 mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); in dcn401_set_mcm_luts()
442 …pc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut_enable, lut_bank_a, CM_LUT_SIZE_NONE, mpcc_id); in dcn401_set_mcm_luts()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_mpc.c | 64 mpcc->mpcc_id = mpcc_inst; in mpc201_init_mpcc()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.c | 153 hubp201->base.mpcc_id = 0xf; in dcn201_hubp_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1633 int mpcc_id, in dcn32_acquire_post_bldn_3dlut() argument
1643 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { in dcn32_acquire_post_bldn_3dlut()
1644 *lut = pool->mpc_lut[mpcc_id]; in dcn32_acquire_post_bldn_3dlut()
1645 *shaper = pool->mpc_shaper[mpcc_id]; in dcn32_acquire_post_bldn_3dlut()
1646 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; in dcn32_acquire_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1465 int mpcc_id, in dcn30_acquire_post_bldn_3dlut() argument
1486 state->bits.mpc_rmu0_mux = mpcc_id; in dcn30_acquire_post_bldn_3dlut()
1488 state->bits.mpc_rmu1_mux = mpcc_id; in dcn30_acquire_post_bldn_3dlut()
1490 state->bits.mpc_rmu2_mux = mpcc_id; in dcn30_acquire_post_bldn_3dlut()
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