| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn32/ |
| H A D | dcn32_mpc.c | 49 int mpcc_id; in mpc32_mpc_init() local
55 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) { in mpc32_mpc_init()
56 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
57 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
58 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
62 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) in mpc32_mpc_init()
63 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
70 uint32_t mpcc_id, in mpc32_power_on_blnd_lut() argument
75 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, MPCC_MCM_1DLUT_MEM_PWR_DIS, power_on); in mpc32_power_on_blnd_lut()
79 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0); in mpc32_power_on_blnd_lut()
[all …]
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| H A D | dcn32_mpc.h | 315 int mpcc_id);
319 uint32_t mpcc_id);
323 uint32_t mpcc_id);
335 uint32_t mpcc_id,
339 uint32_t mpcc_id,
344 uint32_t mpcc_id,
348 uint32_t mpcc_id,
352 uint32_t mpcc_id,
358 uint32_t mpcc_id);
362 uint32_t mpcc_id);
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn401/ |
| H A D | dcn401_mpc.c | 43 static void mpc401_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp_idx) in mpc401_update_3dlut_fast_load_select() argument
47 REG_SET(MPCC_MCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, MPCC_MCM_3DLUT_FL_SEL, hubp_idx); in mpc401_update_3dlut_fast_load_select()
50 static void mpc401_get_3dlut_fast_load_status(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_… in mpc401_get_3dlut_fast_load_status() argument
54 REG_GET_3(MPCC_MCM_3DLUT_FAST_LOAD_STATUS[mpcc_id], in mpc401_get_3dlut_fast_load_status()
60 …pc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id) in mpc401_set_movable_cm_location() argument
66 REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id], in mpc401_set_movable_cm_location()
70 REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id], in mpc401_set_movable_cm_location()
80 int mpcc_id) in get3dlut_config() argument
86 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], in get3dlut_config()
89 REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], in get3dlut_config()
[all …]
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| H A D | dcn401_mpc.h | 207 …c401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id);
209 bool lut_bank_a, int mpcc_id);
216 int mpcc_id);
222 int mpcc_id);
227 int mpcc_id);
231 int mpcc_id,
236 int mpcc_id,
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| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn10/ |
| H A D | dcn10_mpc.c | 42 int mpcc_id) in mpc1_set_bg_color() argument
45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_set_bg_color()
68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
79 int mpcc_id) in mpc1_update_blending() argument
82 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_update_blending()
84 REG_UPDATE_5(MPCC_CONTROL[mpcc_id], in mpc1_update_blending()
97 int mpcc_id) in mpc1_update_stereo_mix() argument
101 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id], in mpc1_update_stereo_mix()
[all …]
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| H A D | dcn10_mpc.h | 148 int mpcc_id);
160 unsigned int mpcc_id);
174 int mpcc_id);
178 int mpcc_id);
182 int mpcc_id);
190 int mpcc_id);
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| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| H A D | dcn20_mpc.c | 51 int mpcc_id) in mpc2_update_blending() argument
55 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc2_update_blending()
57 REG_UPDATE_7(MPCC_CONTROL[mpcc_id], in mpc2_update_blending()
66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
273 struct mpc *mpc, int mpcc_id, in mpc20_power_on_ogam_lut() argument
278 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
284 struct mpc *mpc, int mpcc_id, in mpc20_configure_ogam_lut() argument
289 REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], in mpc20_configure_ogam_lut()
[all …]
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| H A D | dcn20_mpc.h | 280 int mpcc_id);
306 int mpcc_id,
310 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
311 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
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| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/ |
| H A D | dcn30_mpc.c | 62 void mpc3_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) in mpc3_mpc_init_single_inst() argument
66 mpc1_mpc_init_single_inst(mpc, mpcc_id); in mpc3_mpc_init_single_inst()
71 if (mpcc_id < MAX_OPP && REG(MUX[mpcc_id])) in mpc3_mpc_init_single_inst()
73 REG_UPDATE_2(MUX[mpcc_id], MPC_OUT_RATE_CONTROL_DISABLE, in mpc3_mpc_init_single_inst()
95 int mpcc_id) in mpc3_set_dwb_mux() argument
100 MPC_DWB0_MUX, mpcc_id); in mpc3_set_dwb_mux()
113 enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) in mpc3_get_ogam_current() argument
123 REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id], MPCC_OGAM_MODE_CURRENT, &state_mode, in mpc3_get_ogam_current()
152 struct mpc *mpc, int mpcc_id, in mpc3_power_on_ogam_lut() argument
163 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], in mpc3_power_on_ogam_lut()
[all …]
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| H A D | dcn30_mpc.h | 1015 unsigned int mpcc_id);
1028 int mpcc_id, int rmu_idx);
1054 int mpcc_id,
1063 int mpcc_id,
1067 int mpcc_id,
1078 int mpcc_id);
1089 struct mpc *mpc, int mpcc_id,
1096 int mpcc_id);
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | mpc.h | 231 int mpcc_id; member
359 int mpcc_id);
407 unsigned int mpcc_id);
427 int mpcc_id);
480 int mpcc_id);
566 void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id);
684 int mpcc_id,
704 int mpcc_id,
724 int mpcc_id);
801 int mpcc_id,
[all …]
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| H A D | hubp.h | 109 int mpcc_id; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 316 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
427 int mpcc_id, dpp_id; in dcn201_update_mpcc() local
482 mpcc_id = dpp_id; in dcn201_update_mpcc()
486 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); in dcn201_update_mpcc()
487 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); in dcn201_update_mpcc()
508 dc->res_pool->mpc, mpcc_id); in dcn201_update_mpcc()
511 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); in dcn201_update_mpcc()
518 mpcc_id); in dcn201_update_mpcc()
522 hubp->mpcc_id = mpcc_id; in dcn201_update_mpcc()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 247 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut() local
275 if (mpcc_id_projected != mpcc_id) in dcn30_set_mpc_shaper_3dlut()
280 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, in dcn30_set_mpc_shaper_3dlut()
297 mpc->funcs->release_rmu(mpc, mpcc_id); in dcn30_set_mpc_shaper_3dlut()
348 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_program_gamut_remap() local
377 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust); in dcn30_program_gamut_remap()
384 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func() local
409 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); in dcn30_set_output_transfer_func()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 115 int mpcc_id; member
120 int mpcc_id; member
432 int mpcc_id);
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.h | 86 int mpcc_id,
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn31/ |
| H A D | dcn31_hubp.c | 116 hubp2->base.mpcc_id = 0xf; in hubp31_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_mpc.c | 64 mpcc->mpcc_id = mpcc_inst; in mpc201_init_mpcc()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.c | 151 hubp201->base.mpcc_id = 0xf; in dcn201_hubp_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn32/ |
| H A D | dcn32_hubp.c | 222 hubp2->base.mpcc_id = 0xf; in hubp32_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn35/ |
| H A D | dcn35_hubp.c | 236 hubp2->base.mpcc_id = 0xf; in hubp35_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 1458 hubp->mpcc_id = dpp->inst; in dcn10_init_pipes()
1490 int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id; in dcn10_init_pipes()
2665 int mpcc_id) in dcn10_update_visual_confirm_color() argument
2671 mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id); in dcn10_update_visual_confirm_color()
2680 int mpcc_id; in dcn10_update_mpcc() local
2719 mpcc_id = hubp->inst; in dcn10_update_mpcc()
2723 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); in dcn10_update_mpcc()
2724 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); in dcn10_update_mpcc()
2729 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); in dcn10_update_mpcc()
2736 dc->res_pool->mpc, mpcc_id); in dcn10_update_mpcc()
[all …]
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| H A D | dcn10_hwseq.h | 208 int mpcc_id);
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| H A D | dcn30_hubp.c | 532 hubp2->base.mpcc_id = 0xf; in hubp3_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| H A D | dcn10_hubp.c | 65 hubp->mpcc_id = 0xf; in hubp1_set_blank()
1394 hubp1->base.mpcc_id = 0xf; in dcn10_hubp_construct()
|