Home
last modified time | relevance | path

Searched refs:mmUVD_VCPU_CACHE_OFFSET0 (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h88 #define mmUVD_VCPU_CACHE_OFFSET0 0x3D36 macro
H A Duvd_4_2_d.h60 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
H A Duvd_3_1_d.h62 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
H A Duvd_5_0_d.h66 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
H A Duvd_6_0_d.h82 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
H A Duvd_7_0_offset.h178 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_5.c475 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
483 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_5_mc_resume()
530 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
537 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
549 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_mc_resume_dpg_mode()
1303 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); in vcn_v2_5_sriov_start()
1315 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_sriov_start()
H A Dvcn_v3_0.c502 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
510 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v3_0_mc_resume()
556 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
563 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
575 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_mc_resume_dpg_mode()
1389 mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_start_sriov()
1400 mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_start_sriov()
H A Dvcn_v2_0.c387 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_0_mc_resume()
395 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_0_mc_resume()
444 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
451 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
463 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_0_mc_resume_dpg_mode()
1953 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_0_start_sriov()
H A Duvd_v7_0.c690 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in uvd_v7_0_mc_resume()
698 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, in uvd_v7_0_mc_resume()
832 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); in uvd_v7_0_sriov_start()
840 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in uvd_v7_0_sriov_start()
H A Dvcn_v1_0.c357 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v1_0_mc_resume_spg_mode()
365 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume_spg_mode()
426 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, in vcn_v1_0_mc_resume_dpg_mode()
435 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume_dpg_mode()
H A Duvd_v3_1.c248 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); in uvd_v3_1_mc_resume()
H A Duvd_v4_2.c581 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); in uvd_v4_2_mc_resume()
H A Duvd_v5_0.c293 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v5_0_mc_resume()
H A Duvd_v6_0.c617 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v6_0_mc_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h364 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
H A Dvcn_2_5_offset.h685 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
H A Dvcn_2_0_0_offset.h614 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
H A Dvcn_3_0_0_offset.h1061 #define mmUVD_VCPU_CACHE_OFFSET0 … macro