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Searched refs:mmUVD_RBC_RB_WPTR_CNTL (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h74 #define mmUVD_RBC_RB_WPTR_CNTL 0x3DA6 macro
H A Duvd_4_2_d.h73 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 macro
H A Duvd_3_1_d.h75 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 macro
H A Duvd_5_0_d.h79 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 macro
H A Duvd_6_0_d.h95 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 macro
H A Duvd_7_0_offset.h202 #define mmUVD_RBC_RB_WPTR_CNTL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h388 #define mmUVD_RBC_RB_WPTR_CNTL … macro
H A Dvcn_2_5_offset.h797 #define mmUVD_RBC_RB_WPTR_CNTL … macro
H A Dvcn_2_0_0_offset.h684 #define mmUVD_RBC_RB_WPTR_CNTL … macro
H A Dvcn_3_0_0_offset.h1183 #define mmUVD_RBC_RB_WPTR_CNTL … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c380 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v4_2_start()
H A Duvd_v3_1.c417 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v3_1_start()
H A Duvd_v5_0.c432 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v5_0_start()
H A Duvd_v6_0.c847 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v6_0_start()
H A Duvd_v7_0.c1094 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v7_0_start()