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Searched refs:mmUVD_RBC_RB_WPTR (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h73 #define mmUVD_RBC_RB_WPTR 0x3DA5 macro
H A Duvd_4_2_d.h72 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
H A Duvd_3_1_d.h74 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
H A Duvd_5_0_d.h78 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
H A Duvd_6_0_d.h94 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
H A Duvd_7_0_offset.h200 #define mmUVD_RBC_RB_WPTR … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c76 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v4_2_ring_get_wptr()
90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_ring_set_wptr()
390 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_start()
H A Duvd_v3_1.c62 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v3_1_ring_get_wptr()
76 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v3_1_ring_set_wptr()
427 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v3_1_start()
H A Duvd_v5_0.c74 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v5_0_ring_get_wptr()
88 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_ring_set_wptr()
447 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_start()
H A Dvcn_v1_0.c979 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_start_spg_mode()
1137 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_start_dpg_mode()
1226 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v1_0_stop_dpg_mode()
1302 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_pause_dpg_mode()
1363 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_pause_dpg_mode()
1441 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); in vcn_v1_0_dec_ring_get_wptr()
1459 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_dec_ring_set_wptr()
H A Dvcn_v2_0.c964 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_start_dpg_mode()
1122 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_start()
1164 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v2_0_stop_dpg_mode()
1300 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_pause_dpg_mode()
1389 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); in vcn_v2_0_dec_ring_get_wptr()
1411 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_dec_ring_set_wptr()
H A Dvcn_v3_0.c1122 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start_dpg_mode()
1298 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start()
1555 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v3_0_stop_dpg_mode()
1703 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); in vcn_v3_0_pause_dpg_mode()
1752 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v3_0_dec_ring_get_wptr()
1779 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_dec_ring_set_wptr()
H A Dvcn_v2_5.c1000 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start_dpg_mode()
1178 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start()
1415 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v2_5_stop_dpg_mode()
1599 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v2_5_dec_ring_get_wptr()
1617 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_dec_ring_set_wptr()
H A Duvd_v6_0.c111 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v6_0_ring_get_wptr()
142 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_ring_set_wptr()
862 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
H A Duvd_v7_0.c106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); in uvd_v7_0_ring_get_wptr()
140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
1110 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, in uvd_v7_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h386 #define mmUVD_RBC_RB_WPTR … macro
H A Dvcn_2_5_offset.h791 #define mmUVD_RBC_RB_WPTR … macro
H A Dvcn_2_0_0_offset.h682 #define mmUVD_RBC_RB_WPTR … macro
H A Dvcn_3_0_0_offset.h1175 #define mmUVD_RBC_RB_WPTR … macro