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Searched refs:mmUVD_LMI_CTRL2 (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v5_0.c340 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start()
382 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start()
466 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_stop()
477 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_stop()
H A Duvd_v7_0.c874 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_sriov_start()
931 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_sriov_start()
987 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), in uvd_v7_0_start()
1038 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, in uvd_v7_0_start()
1150 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_stop()
1164 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, in uvd_v7_0_stop()
H A Duvd_v3_1.c372 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v3_1_start()
477 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v3_1_stop()
H A Duvd_v4_2.c334 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start()
439 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v4_2_stop()
H A Dvcn_v2_0.c917 UVD, 0, mmUVD_LMI_CTRL2), in vcn_v2_0_start_dpg_mode()
1044 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v2_0_start()
1201 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); in vcn_v2_0_stop()
1203 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); in vcn_v2_0_stop()
H A Dvcn_v2_5.c942 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
1103 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
1455 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v2_5_stop()
1457 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v2_5_stop()
H A Dvcn_v3_0.c1062 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1177 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v3_0_start()
1596 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v3_0_stop()
1598 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v3_0_stop()
H A Dvcn_v1_0.c902 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v1_0_start_spg_mode()
1080 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2, in vcn_v1_0_start_dpg_mode()
1174 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), in vcn_v1_0_stop_spg_mode()
H A Duvd_v6_0.c897 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v6_0_stop()
908 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v6_0_stop()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h48 #define mmUVD_LMI_CTRL2 0x3D3D macro
H A Duvd_4_2_d.h46 #define mmUVD_LMI_CTRL2 0x3d3d macro
H A Duvd_3_1_d.h46 #define mmUVD_LMI_CTRL2 0x3d3d macro
H A Duvd_5_0_d.h52 #define mmUVD_LMI_CTRL2 0x3d3d macro
H A Duvd_6_0_d.h68 #define mmUVD_LMI_CTRL2 0x3d3d macro
H A Duvd_7_0_offset.h150 #define mmUVD_LMI_CTRL2 … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h328 #define mmUVD_LMI_CTRL2 … macro
H A Dvcn_2_5_offset.h955 #define mmUVD_LMI_CTRL2 … macro
H A Dvcn_2_0_0_offset.h536 #define mmUVD_LMI_CTRL2 … macro
H A Dvcn_3_0_0_offset.h1469 #define mmUVD_LMI_CTRL2 … macro