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Searched refs:mmUVD_JRBC_STATUS (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v3_0.c170 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) in jpeg_v3_0_hw_fini()
453 ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & in jpeg_v3_0_is_idle()
464 return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, in jpeg_v3_0_wait_for_idle()
H A Djpeg_v2_5.c221 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)) in jpeg_v2_5_hw_fini()
494 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) & in jpeg_v2_5_is_idle()
511 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, in jpeg_v2_5_wait_for_idle()
H A Djpeg_v2_0.c156 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) in jpeg_v2_0_hw_fini()
662 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & in jpeg_v2_0_is_idle()
672 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, in jpeg_v2_0_wait_for_idle()
H A Djpeg_v1_0.c349 …PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); in jpeg_v1_0_decode_ring_emit_ib()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h286 #define mmUVD_JRBC_STATUS … macro
H A Dvcn_2_5_offset.h151 #define mmUVD_JRBC_STATUS … macro
H A Dvcn_2_0_0_offset.h136 #define mmUVD_JRBC_STATUS … macro
H A Dvcn_3_0_0_offset.h349 #define mmUVD_JRBC_STATUS … macro