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Searched refs:mmUVD_JRBC_RB_RPTR (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v1_0.c121 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v1_0_decode_ring_set_patch_ring()
144 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v1_0_decode_ring_get_rptr()
541 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v1_0_start()
H A Djpeg_v3_0.c360 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v3_0_start()
409 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v3_0_dec_ring_get_rptr()
H A Djpeg_v2_5.c358 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v2_5_start()
410 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); in jpeg_v2_5_dec_ring_get_rptr()
H A Djpeg_v2_0.c341 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v2_0_start()
391 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v2_0_dec_ring_get_rptr()
H A Dvcn_v1_0.c1224 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1357 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); in vcn_v1_0_pause_dpg_mode()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_offset.h104 #define mmUVD_JRBC_RB_RPTR … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h228 #define mmUVD_JRBC_RB_RPTR … macro
H A Dvcn_2_5_offset.h153 #define mmUVD_JRBC_RB_RPTR … macro
H A Dvcn_2_0_0_offset.h138 #define mmUVD_JRBC_RB_RPTR … macro
H A Dvcn_3_0_0_offset.h351 #define mmUVD_JRBC_RB_RPTR … macro